[PATCH] mv643xx_eth: Remove needless mask of extended intr register
[linux-2.6/zen-sources.git] / drivers / net / mv643xx_eth.c
blob40ae36b20c9dea2811491e93e4de9ceb9d0c3ef5
1 /*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/tcp.h>
36 #include <linux/udp.h>
37 #include <linux/etherdevice.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
46 #include <asm/io.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
54 * The first part is the high level driver of the gigE ethernet ports.
57 /* Constants */
58 #define VLAN_HLEN 4
59 #define FCS_LEN 4
60 #define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61 #define HW_IP_ALIGN 2 /* hw aligns IP header */
62 #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
63 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
65 #define INT_UNMASK_ALL 0x0007ffff
66 #define INT_UNMASK_ALL_EXT 0x0011ffff
67 #define INT_MASK_ALL 0x00000000
68 #define INT_MASK_ALL_EXT 0x00000000
69 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
72 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74 #else
75 #define MAX_DESCS_PER_SKB 1
76 #endif
78 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79 #define PHY_WAIT_MICRO_SECONDS 10
81 /* Static function declarations */
82 static int eth_port_link_is_up(unsigned int eth_port_num);
83 static void eth_port_uc_addr_get(struct net_device *dev,
84 unsigned char *MacAddr);
85 static void eth_port_set_multicast_list(struct net_device *);
86 static int mv643xx_eth_open(struct net_device *);
87 static int mv643xx_eth_stop(struct net_device *);
88 static int mv643xx_eth_change_mtu(struct net_device *, int);
89 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
90 static void eth_port_init_mac_tables(unsigned int eth_port_num);
91 #ifdef MV643XX_NAPI
92 static int mv643xx_poll(struct net_device *dev, int *budget);
93 #endif
94 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
95 static int ethernet_phy_detect(unsigned int eth_port_num);
96 static struct ethtool_ops mv643xx_ethtool_ops;
98 static char mv643xx_driver_name[] = "mv643xx_eth";
99 static char mv643xx_driver_version[] = "1.0";
101 static void __iomem *mv643xx_eth_shared_base;
103 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
104 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
106 static inline u32 mv_read(int offset)
108 void __iomem *reg_base;
110 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
112 return readl(reg_base + offset);
115 static inline void mv_write(int offset, u32 data)
117 void __iomem *reg_base;
119 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
120 writel(data, reg_base + offset);
124 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
126 * Input : pointer to ethernet interface network device structure
127 * new mtu size
128 * Output : 0 upon success, -EINVAL upon failure
130 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
132 if ((new_mtu > 9500) || (new_mtu < 64))
133 return -EINVAL;
135 dev->mtu = new_mtu;
137 * Stop then re-open the interface. This will allocate RX skb's with
138 * the new MTU.
139 * There is a possible danger that the open will not successed, due
140 * to memory is full, which might fail the open function.
142 if (netif_running(dev)) {
143 mv643xx_eth_stop(dev);
144 if (mv643xx_eth_open(dev))
145 printk(KERN_ERR
146 "%s: Fatal error on opening device\n",
147 dev->name);
150 return 0;
154 * mv643xx_eth_rx_task
156 * Fills / refills RX queue on a certain gigabit ethernet port
158 * Input : pointer to ethernet interface network device structure
159 * Output : N/A
161 static void mv643xx_eth_rx_task(void *data)
163 struct net_device *dev = (struct net_device *)data;
164 struct mv643xx_private *mp = netdev_priv(dev);
165 struct pkt_info pkt_info;
166 struct sk_buff *skb;
167 int unaligned;
169 if (test_and_set_bit(0, &mp->rx_task_busy))
170 panic("%s: Error in test_set_bit / clear_bit", dev->name);
172 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
173 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
174 if (!skb)
175 break;
176 mp->rx_ring_skbs++;
177 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
178 if (unaligned)
179 skb_reserve(skb, DMA_ALIGN - unaligned);
180 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
181 pkt_info.byte_cnt = RX_SKB_SIZE;
182 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
183 DMA_FROM_DEVICE);
184 pkt_info.return_info = skb;
185 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
186 printk(KERN_ERR
187 "%s: Error allocating RX Ring\n", dev->name);
188 break;
190 skb_reserve(skb, HW_IP_ALIGN);
192 clear_bit(0, &mp->rx_task_busy);
194 * If RX ring is empty of SKB, set a timer to try allocating
195 * again in a later time .
197 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
198 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
199 /* After 100mSec */
200 mp->timeout.expires = jiffies + (HZ / 10);
201 add_timer(&mp->timeout);
202 mp->rx_timer_flag = 1;
204 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
205 else {
206 /* Return interrupts */
207 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
208 INT_UNMASK_ALL);
210 #endif
214 * mv643xx_eth_rx_task_timer_wrapper
216 * Timer routine to wake up RX queue filling task. This function is
217 * used only in case the RX queue is empty, and all alloc_skb has
218 * failed (due to out of memory event).
220 * Input : pointer to ethernet interface network device structure
221 * Output : N/A
223 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
225 struct net_device *dev = (struct net_device *)data;
226 struct mv643xx_private *mp = netdev_priv(dev);
228 mp->rx_timer_flag = 0;
229 mv643xx_eth_rx_task((void *)data);
233 * mv643xx_eth_update_mac_address
235 * Update the MAC address of the port in the address table
237 * Input : pointer to ethernet interface network device structure
238 * Output : N/A
240 static void mv643xx_eth_update_mac_address(struct net_device *dev)
242 struct mv643xx_private *mp = netdev_priv(dev);
243 unsigned int port_num = mp->port_num;
245 eth_port_init_mac_tables(port_num);
246 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
247 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
251 * mv643xx_eth_set_rx_mode
253 * Change from promiscuos to regular rx mode
255 * Input : pointer to ethernet interface network device structure
256 * Output : N/A
258 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
260 struct mv643xx_private *mp = netdev_priv(dev);
262 if (dev->flags & IFF_PROMISC)
263 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
264 else
265 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
267 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
269 eth_port_set_multicast_list(dev);
273 * mv643xx_eth_set_mac_address
275 * Change the interface's mac address.
276 * No special hardware thing should be done because interface is always
277 * put in promiscuous mode.
279 * Input : pointer to ethernet interface network device structure and
280 * a pointer to the designated entry to be added to the cache.
281 * Output : zero upon success, negative upon failure
283 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
285 int i;
287 for (i = 0; i < 6; i++)
288 /* +2 is for the offset of the HW addr type */
289 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
290 mv643xx_eth_update_mac_address(dev);
291 return 0;
295 * mv643xx_eth_tx_timeout
297 * Called upon a timeout on transmitting a packet
299 * Input : pointer to ethernet interface network device structure.
300 * Output : N/A
302 static void mv643xx_eth_tx_timeout(struct net_device *dev)
304 struct mv643xx_private *mp = netdev_priv(dev);
306 printk(KERN_INFO "%s: TX timeout ", dev->name);
308 /* Do the reset outside of interrupt context */
309 schedule_work(&mp->tx_timeout_task);
313 * mv643xx_eth_tx_timeout_task
315 * Actual routine to reset the adapter when a timeout on Tx has occurred
317 static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
319 struct mv643xx_private *mp = netdev_priv(dev);
321 netif_device_detach(dev);
322 eth_port_reset(mp->port_num);
323 eth_port_start(mp);
324 netif_device_attach(dev);
328 * mv643xx_eth_free_tx_queue
330 * Input : dev - a pointer to the required interface
332 * Output : 0 if was able to release skb , nonzero otherwise
334 static int mv643xx_eth_free_tx_queue(struct net_device *dev,
335 unsigned int eth_int_cause_ext)
337 struct mv643xx_private *mp = netdev_priv(dev);
338 struct net_device_stats *stats = &mp->stats;
339 struct pkt_info pkt_info;
340 int released = 1;
342 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
343 return released;
345 /* Check only queue 0 */
346 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
347 if (pkt_info.cmd_sts & BIT0) {
348 printk("%s: Error in TX\n", dev->name);
349 stats->tx_errors++;
352 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
353 dma_unmap_single(NULL, pkt_info.buf_ptr,
354 pkt_info.byte_cnt,
355 DMA_TO_DEVICE);
356 else
357 dma_unmap_page(NULL, pkt_info.buf_ptr,
358 pkt_info.byte_cnt,
359 DMA_TO_DEVICE);
361 if (pkt_info.return_info) {
362 dev_kfree_skb_irq(pkt_info.return_info);
363 released = 0;
367 return released;
371 * mv643xx_eth_receive
373 * This function is forward packets that are received from the port's
374 * queues toward kernel core or FastRoute them to another interface.
376 * Input : dev - a pointer to the required interface
377 * max - maximum number to receive (0 means unlimted)
379 * Output : number of served packets
381 #ifdef MV643XX_NAPI
382 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
383 #else
384 static int mv643xx_eth_receive_queue(struct net_device *dev)
385 #endif
387 struct mv643xx_private *mp = netdev_priv(dev);
388 struct net_device_stats *stats = &mp->stats;
389 unsigned int received_packets = 0;
390 struct sk_buff *skb;
391 struct pkt_info pkt_info;
393 #ifdef MV643XX_NAPI
394 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
395 #else
396 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
397 #endif
398 mp->rx_ring_skbs--;
399 received_packets++;
401 /* Update statistics. Note byte count includes 4 byte CRC count */
402 stats->rx_packets++;
403 stats->rx_bytes += pkt_info.byte_cnt;
404 skb = pkt_info.return_info;
406 * In case received a packet without first / last bits on OR
407 * the error summary bit is on, the packets needs to be dropeed.
409 if (((pkt_info.cmd_sts
410 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
411 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
412 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
413 stats->rx_dropped++;
414 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
415 ETH_RX_LAST_DESC)) !=
416 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
417 if (net_ratelimit())
418 printk(KERN_ERR
419 "%s: Received packet spread "
420 "on multiple descriptors\n",
421 dev->name);
423 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
424 stats->rx_errors++;
426 dev_kfree_skb_irq(skb);
427 } else {
429 * The -4 is for the CRC in the trailer of the
430 * received packet
432 skb_put(skb, pkt_info.byte_cnt - 4);
433 skb->dev = dev;
435 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
436 skb->ip_summed = CHECKSUM_UNNECESSARY;
437 skb->csum = htons(
438 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
440 skb->protocol = eth_type_trans(skb, dev);
441 #ifdef MV643XX_NAPI
442 netif_receive_skb(skb);
443 #else
444 netif_rx(skb);
445 #endif
449 return received_packets;
453 * mv643xx_eth_int_handler
455 * Main interrupt handler for the gigbit ethernet ports
457 * Input : irq - irq number (not used)
458 * dev_id - a pointer to the required interface's data structure
459 * regs - not used
460 * Output : N/A
463 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
464 struct pt_regs *regs)
466 struct net_device *dev = (struct net_device *)dev_id;
467 struct mv643xx_private *mp = netdev_priv(dev);
468 u32 eth_int_cause, eth_int_cause_ext = 0;
469 unsigned int port_num = mp->port_num;
471 /* Read interrupt cause registers */
472 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
473 INT_UNMASK_ALL;
475 if (eth_int_cause & BIT1)
476 eth_int_cause_ext = mv_read(
477 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
478 INT_UNMASK_ALL_EXT;
480 #ifdef MV643XX_NAPI
481 if (!(eth_int_cause & 0x0007fffd)) {
482 /* Dont ack the Rx interrupt */
483 #endif
485 * Clear specific ethernet port intrerrupt registers by
486 * acknowleding relevant bits.
488 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
489 ~eth_int_cause);
490 if (eth_int_cause_ext != 0x0)
491 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
492 (port_num), ~eth_int_cause_ext);
494 /* UDP change : We may need this */
495 if ((eth_int_cause_ext & 0x0000ffff) &&
496 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
497 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
498 netif_wake_queue(dev);
499 #ifdef MV643XX_NAPI
500 } else {
501 if (netif_rx_schedule_prep(dev)) {
502 /* Mask all the interrupts */
503 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
504 INT_MASK_ALL);
505 /* wait for previous write to complete */
506 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
507 __netif_rx_schedule(dev);
509 #else
510 if (eth_int_cause & (BIT2 | BIT11))
511 mv643xx_eth_receive_queue(dev, 0);
514 * After forwarded received packets to upper layer, add a task
515 * in an interrupts enabled context that refills the RX ring
516 * with skb's.
518 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
519 /* Mask all interrupts on ethernet port */
520 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
521 INT_MASK_ALL);
522 /* wait for previous write to take effect */
523 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
525 queue_task(&mp->rx_task, &tq_immediate);
526 mark_bh(IMMEDIATE_BH);
527 #else
528 mp->rx_task.func(dev);
529 #endif
530 #endif
532 /* PHY status changed */
533 if (eth_int_cause_ext & (BIT16 | BIT20)) {
534 if (eth_port_link_is_up(port_num)) {
535 netif_carrier_on(dev);
536 netif_wake_queue(dev);
537 /* Start TX queue */
538 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
539 (port_num), 1);
540 } else {
541 netif_carrier_off(dev);
542 netif_stop_queue(dev);
547 * If no real interrupt occured, exit.
548 * This can happen when using gigE interrupt coalescing mechanism.
550 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
551 return IRQ_NONE;
553 return IRQ_HANDLED;
556 #ifdef MV643XX_COAL
559 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
561 * DESCRIPTION:
562 * This routine sets the RX coalescing interrupt mechanism parameter.
563 * This parameter is a timeout counter, that counts in 64 t_clk
564 * chunks ; that when timeout event occurs a maskable interrupt
565 * occurs.
566 * The parameter is calculated using the tClk of the MV-643xx chip
567 * , and the required delay of the interrupt in usec.
569 * INPUT:
570 * unsigned int eth_port_num Ethernet port number
571 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
572 * unsigned int delay Delay in usec
574 * OUTPUT:
575 * Interrupt coalescing mechanism value is set in MV-643xx chip.
577 * RETURN:
578 * The interrupt coalescing value set in the gigE port.
581 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
582 unsigned int t_clk, unsigned int delay)
584 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
586 /* Set RX Coalescing mechanism */
587 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
588 ((coal & 0x3fff) << 8) |
589 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
590 & 0xffc000ff));
592 return coal;
594 #endif
597 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
599 * DESCRIPTION:
600 * This routine sets the TX coalescing interrupt mechanism parameter.
601 * This parameter is a timeout counter, that counts in 64 t_clk
602 * chunks ; that when timeout event occurs a maskable interrupt
603 * occurs.
604 * The parameter is calculated using the t_cLK frequency of the
605 * MV-643xx chip and the required delay in the interrupt in uSec
607 * INPUT:
608 * unsigned int eth_port_num Ethernet port number
609 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
610 * unsigned int delay Delay in uSeconds
612 * OUTPUT:
613 * Interrupt coalescing mechanism value is set in MV-643xx chip.
615 * RETURN:
616 * The interrupt coalescing value set in the gigE port.
619 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
620 unsigned int t_clk, unsigned int delay)
622 unsigned int coal;
623 coal = ((t_clk / 1000000) * delay) / 64;
624 /* Set TX Coalescing mechanism */
625 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
626 coal << 4);
627 return coal;
631 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
633 * DESCRIPTION:
634 * This function prepares a Rx chained list of descriptors and packet
635 * buffers in a form of a ring. The routine must be called after port
636 * initialization routine and before port start routine.
637 * The Ethernet SDMA engine uses CPU bus addresses to access the various
638 * devices in the system (i.e. DRAM). This function uses the ethernet
639 * struct 'virtual to physical' routine (set by the user) to set the ring
640 * with physical addresses.
642 * INPUT:
643 * struct mv643xx_private *mp Ethernet Port Control srtuct.
645 * OUTPUT:
646 * The routine updates the Ethernet port control struct with information
647 * regarding the Rx descriptors and buffers.
649 * RETURN:
650 * None.
652 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
654 volatile struct eth_rx_desc *p_rx_desc;
655 int rx_desc_num = mp->rx_ring_size;
656 int i;
658 /* initialize the next_desc_ptr links in the Rx descriptors ring */
659 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
660 for (i = 0; i < rx_desc_num; i++) {
661 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
662 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
665 /* Save Rx desc pointer to driver struct. */
666 mp->rx_curr_desc_q = 0;
667 mp->rx_used_desc_q = 0;
669 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
671 /* Add the queue to the list of RX queues of this port */
672 mp->port_rx_queue_command |= 1;
676 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
678 * DESCRIPTION:
679 * This function prepares a Tx chained list of descriptors and packet
680 * buffers in a form of a ring. The routine must be called after port
681 * initialization routine and before port start routine.
682 * The Ethernet SDMA engine uses CPU bus addresses to access the various
683 * devices in the system (i.e. DRAM). This function uses the ethernet
684 * struct 'virtual to physical' routine (set by the user) to set the ring
685 * with physical addresses.
687 * INPUT:
688 * struct mv643xx_private *mp Ethernet Port Control srtuct.
690 * OUTPUT:
691 * The routine updates the Ethernet port control struct with information
692 * regarding the Tx descriptors and buffers.
694 * RETURN:
695 * None.
697 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
699 int tx_desc_num = mp->tx_ring_size;
700 struct eth_tx_desc *p_tx_desc;
701 int i;
703 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
704 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
705 for (i = 0; i < tx_desc_num; i++) {
706 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
707 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
710 mp->tx_curr_desc_q = 0;
711 mp->tx_used_desc_q = 0;
712 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
713 mp->tx_first_desc_q = 0;
714 #endif
716 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
718 /* Add the queue to the list of Tx queues of this port */
719 mp->port_tx_queue_command |= 1;
723 * mv643xx_eth_open
725 * This function is called when openning the network device. The function
726 * should initialize all the hardware, initialize cyclic Rx/Tx
727 * descriptors chain and buffers and allocate an IRQ to the network
728 * device.
730 * Input : a pointer to the network device structure
732 * Output : zero of success , nonzero if fails.
735 static int mv643xx_eth_open(struct net_device *dev)
737 struct mv643xx_private *mp = netdev_priv(dev);
738 unsigned int port_num = mp->port_num;
739 unsigned int size;
740 int err;
742 err = request_irq(dev->irq, mv643xx_eth_int_handler,
743 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
744 if (err) {
745 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
746 port_num);
747 return -EAGAIN;
750 /* Stop RX Queues */
751 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
753 /* Set the MAC Address */
754 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
756 eth_port_init(mp);
758 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
760 memset(&mp->timeout, 0, sizeof(struct timer_list));
761 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
762 mp->timeout.data = (unsigned long)dev;
764 mp->rx_task_busy = 0;
765 mp->rx_timer_flag = 0;
767 /* Allocate RX and TX skb rings */
768 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
769 GFP_KERNEL);
770 if (!mp->rx_skb) {
771 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
772 err = -ENOMEM;
773 goto out_free_irq;
775 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
776 GFP_KERNEL);
777 if (!mp->tx_skb) {
778 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
779 err = -ENOMEM;
780 goto out_free_rx_skb;
783 /* Allocate TX ring */
784 mp->tx_ring_skbs = 0;
785 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
786 mp->tx_desc_area_size = size;
788 if (mp->tx_sram_size) {
789 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
790 mp->tx_sram_size);
791 mp->tx_desc_dma = mp->tx_sram_addr;
792 } else
793 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
794 &mp->tx_desc_dma,
795 GFP_KERNEL);
797 if (!mp->p_tx_desc_area) {
798 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
799 dev->name, size);
800 err = -ENOMEM;
801 goto out_free_tx_skb;
803 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
804 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
806 ether_init_tx_desc_ring(mp);
808 /* Allocate RX ring */
809 mp->rx_ring_skbs = 0;
810 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
811 mp->rx_desc_area_size = size;
813 if (mp->rx_sram_size) {
814 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
815 mp->rx_sram_size);
816 mp->rx_desc_dma = mp->rx_sram_addr;
817 } else
818 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
819 &mp->rx_desc_dma,
820 GFP_KERNEL);
822 if (!mp->p_rx_desc_area) {
823 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
824 dev->name, size);
825 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
826 dev->name);
827 if (mp->rx_sram_size)
828 iounmap(mp->p_tx_desc_area);
829 else
830 dma_free_coherent(NULL, mp->tx_desc_area_size,
831 mp->p_tx_desc_area, mp->tx_desc_dma);
832 err = -ENOMEM;
833 goto out_free_tx_skb;
835 memset((void *)mp->p_rx_desc_area, 0, size);
837 ether_init_rx_desc_ring(mp);
839 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
841 eth_port_start(mp);
843 /* Interrupt Coalescing */
845 #ifdef MV643XX_COAL
846 mp->rx_int_coal =
847 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
848 #endif
850 mp->tx_int_coal =
851 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
853 /* Clear any pending ethernet port interrupts */
854 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
855 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
857 /* Unmask phy and link status changes interrupts */
858 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
859 INT_UNMASK_ALL_EXT);
861 /* Unmask RX buffer and TX end interrupt */
862 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
863 return 0;
865 out_free_tx_skb:
866 kfree(mp->tx_skb);
867 out_free_rx_skb:
868 kfree(mp->rx_skb);
869 out_free_irq:
870 free_irq(dev->irq, dev);
872 return err;
875 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
877 struct mv643xx_private *mp = netdev_priv(dev);
878 unsigned int port_num = mp->port_num;
879 unsigned int curr;
880 struct sk_buff *skb;
882 /* Stop Tx Queues */
883 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
885 /* Free outstanding skb's on TX rings */
886 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
887 skb = mp->tx_skb[curr];
888 if (skb) {
889 mp->tx_ring_skbs -= skb_shinfo(skb)->nr_frags;
890 dev_kfree_skb(skb);
891 mp->tx_ring_skbs--;
894 if (mp->tx_ring_skbs)
895 printk("%s: Error on Tx descriptor free - could not free %d"
896 " descriptors\n", dev->name, mp->tx_ring_skbs);
898 /* Free TX ring */
899 if (mp->tx_sram_size)
900 iounmap(mp->p_tx_desc_area);
901 else
902 dma_free_coherent(NULL, mp->tx_desc_area_size,
903 mp->p_tx_desc_area, mp->tx_desc_dma);
906 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
908 struct mv643xx_private *mp = netdev_priv(dev);
909 unsigned int port_num = mp->port_num;
910 int curr;
912 /* Stop RX Queues */
913 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
915 /* Free preallocated skb's on RX rings */
916 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
917 if (mp->rx_skb[curr]) {
918 dev_kfree_skb(mp->rx_skb[curr]);
919 mp->rx_ring_skbs--;
923 if (mp->rx_ring_skbs)
924 printk(KERN_ERR
925 "%s: Error in freeing Rx Ring. %d skb's still"
926 " stuck in RX Ring - ignoring them\n", dev->name,
927 mp->rx_ring_skbs);
928 /* Free RX ring */
929 if (mp->rx_sram_size)
930 iounmap(mp->p_rx_desc_area);
931 else
932 dma_free_coherent(NULL, mp->rx_desc_area_size,
933 mp->p_rx_desc_area, mp->rx_desc_dma);
937 * mv643xx_eth_stop
939 * This function is used when closing the network device.
940 * It updates the hardware,
941 * release all memory that holds buffers and descriptors and release the IRQ.
942 * Input : a pointer to the device structure
943 * Output : zero if success , nonzero if fails
946 static int mv643xx_eth_stop(struct net_device *dev)
948 struct mv643xx_private *mp = netdev_priv(dev);
949 unsigned int port_num = mp->port_num;
951 /* Mask all interrupts on ethernet port */
952 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
953 /* wait for previous write to complete */
954 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
956 #ifdef MV643XX_NAPI
957 netif_poll_disable(dev);
958 #endif
959 netif_carrier_off(dev);
960 netif_stop_queue(dev);
962 eth_port_reset(mp->port_num);
964 mv643xx_eth_free_tx_rings(dev);
965 mv643xx_eth_free_rx_rings(dev);
967 #ifdef MV643XX_NAPI
968 netif_poll_enable(dev);
969 #endif
971 free_irq(dev->irq, dev);
973 return 0;
976 #ifdef MV643XX_NAPI
977 static void mv643xx_tx(struct net_device *dev)
979 struct mv643xx_private *mp = netdev_priv(dev);
980 struct pkt_info pkt_info;
982 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
983 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
984 dma_unmap_single(NULL, pkt_info.buf_ptr,
985 pkt_info.byte_cnt,
986 DMA_TO_DEVICE);
987 else
988 dma_unmap_page(NULL, pkt_info.buf_ptr,
989 pkt_info.byte_cnt,
990 DMA_TO_DEVICE);
992 if (pkt_info.return_info)
993 dev_kfree_skb_irq(pkt_info.return_info);
996 if (netif_queue_stopped(dev) &&
997 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
998 netif_wake_queue(dev);
1002 * mv643xx_poll
1004 * This function is used in case of NAPI
1006 static int mv643xx_poll(struct net_device *dev, int *budget)
1008 struct mv643xx_private *mp = netdev_priv(dev);
1009 int done = 1, orig_budget, work_done;
1010 unsigned int port_num = mp->port_num;
1012 #ifdef MV643XX_TX_FAST_REFILL
1013 if (++mp->tx_clean_threshold > 5) {
1014 mv643xx_tx(dev);
1015 mp->tx_clean_threshold = 0;
1017 #endif
1019 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1020 != (u32) mp->rx_used_desc_q) {
1021 orig_budget = *budget;
1022 if (orig_budget > dev->quota)
1023 orig_budget = dev->quota;
1024 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1025 mp->rx_task.func(dev);
1026 *budget -= work_done;
1027 dev->quota -= work_done;
1028 if (work_done >= orig_budget)
1029 done = 0;
1032 if (done) {
1033 netif_rx_complete(dev);
1034 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1035 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1036 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1037 INT_UNMASK_ALL);
1040 return done ? 0 : 1;
1042 #endif
1044 /* Hardware can't handle unaligned fragments smaller than 9 bytes.
1045 * This helper function detects that case.
1048 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1050 unsigned int frag;
1051 skb_frag_t *fragp;
1053 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1054 fragp = &skb_shinfo(skb)->frags[frag];
1055 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1056 return 1;
1059 return 0;
1064 * mv643xx_eth_start_xmit
1066 * This function is queues a packet in the Tx descriptor for
1067 * required port.
1069 * Input : skb - a pointer to socket buffer
1070 * dev - a pointer to the required port
1072 * Output : zero upon success
1074 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1076 struct mv643xx_private *mp = netdev_priv(dev);
1077 struct net_device_stats *stats = &mp->stats;
1078 ETH_FUNC_RET_STATUS status;
1079 unsigned long flags;
1080 struct pkt_info pkt_info;
1082 if (netif_queue_stopped(dev)) {
1083 printk(KERN_ERR
1084 "%s: Tried sending packet when interface is stopped\n",
1085 dev->name);
1086 return 1;
1089 /* This is a hard error, log it. */
1090 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1091 (skb_shinfo(skb)->nr_frags + 1)) {
1092 netif_stop_queue(dev);
1093 printk(KERN_ERR
1094 "%s: Bug in mv643xx_eth - Trying to transmit when"
1095 " queue full !\n", dev->name);
1096 return 1;
1099 /* Paranoid check - this shouldn't happen */
1100 if (skb == NULL) {
1101 stats->tx_dropped++;
1102 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1103 return 1;
1106 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1107 if (has_tiny_unaligned_frags(skb)) {
1108 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1109 stats->tx_dropped++;
1110 printk(KERN_DEBUG "%s: failed to linearize tiny "
1111 "unaligned fragment\n", dev->name);
1112 return 1;
1116 spin_lock_irqsave(&mp->lock, flags);
1118 if (!skb_shinfo(skb)->nr_frags) {
1119 if (skb->ip_summed != CHECKSUM_HW) {
1120 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1121 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1122 ETH_TX_FIRST_DESC |
1123 ETH_TX_LAST_DESC |
1124 5 << ETH_TX_IHL_SHIFT;
1125 pkt_info.l4i_chk = 0;
1126 } else {
1127 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1128 ETH_TX_FIRST_DESC |
1129 ETH_TX_LAST_DESC |
1130 ETH_GEN_TCP_UDP_CHECKSUM |
1131 ETH_GEN_IP_V_4_CHECKSUM |
1132 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1133 /* CPU already calculated pseudo header checksum. */
1134 if ((skb->protocol == ETH_P_IP) &&
1135 (skb->nh.iph->protocol == IPPROTO_UDP) ) {
1136 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1137 pkt_info.l4i_chk = skb->h.uh->check;
1138 } else if ((skb->protocol == ETH_P_IP) &&
1139 (skb->nh.iph->protocol == IPPROTO_TCP))
1140 pkt_info.l4i_chk = skb->h.th->check;
1141 else {
1142 printk(KERN_ERR
1143 "%s: chksum proto != IPv4 TCP or UDP\n",
1144 dev->name);
1145 spin_unlock_irqrestore(&mp->lock, flags);
1146 return 1;
1149 pkt_info.byte_cnt = skb->len;
1150 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1151 DMA_TO_DEVICE);
1152 pkt_info.return_info = skb;
1153 status = eth_port_send(mp, &pkt_info);
1154 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1155 printk(KERN_ERR "%s: Error on transmitting packet\n",
1156 dev->name);
1157 stats->tx_bytes += pkt_info.byte_cnt;
1158 } else {
1159 unsigned int frag;
1161 /* first frag which is skb header */
1162 pkt_info.byte_cnt = skb_headlen(skb);
1163 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1164 skb_headlen(skb),
1165 DMA_TO_DEVICE);
1166 pkt_info.l4i_chk = 0;
1167 pkt_info.return_info = 0;
1169 if (skb->ip_summed != CHECKSUM_HW)
1170 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1171 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1172 5 << ETH_TX_IHL_SHIFT;
1173 else {
1174 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1175 ETH_GEN_TCP_UDP_CHECKSUM |
1176 ETH_GEN_IP_V_4_CHECKSUM |
1177 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1178 /* CPU already calculated pseudo header checksum. */
1179 if ((skb->protocol == ETH_P_IP) &&
1180 (skb->nh.iph->protocol == IPPROTO_UDP)) {
1181 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1182 pkt_info.l4i_chk = skb->h.uh->check;
1183 } else if ((skb->protocol == ETH_P_IP) &&
1184 (skb->nh.iph->protocol == IPPROTO_TCP))
1185 pkt_info.l4i_chk = skb->h.th->check;
1186 else {
1187 printk(KERN_ERR
1188 "%s: chksum proto != IPv4 TCP or UDP\n",
1189 dev->name);
1190 spin_unlock_irqrestore(&mp->lock, flags);
1191 return 1;
1195 status = eth_port_send(mp, &pkt_info);
1196 if (status != ETH_OK) {
1197 if ((status == ETH_ERROR))
1198 printk(KERN_ERR
1199 "%s: Error on transmitting packet\n",
1200 dev->name);
1201 if (status == ETH_QUEUE_FULL)
1202 printk("Error on Queue Full \n");
1203 if (status == ETH_QUEUE_LAST_RESOURCE)
1204 printk("Tx resource error \n");
1206 stats->tx_bytes += pkt_info.byte_cnt;
1208 /* Check for the remaining frags */
1209 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1210 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1211 pkt_info.l4i_chk = 0x0000;
1212 pkt_info.cmd_sts = 0x00000000;
1214 /* Last Frag enables interrupt and frees the skb */
1215 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1216 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1217 ETH_TX_LAST_DESC;
1218 pkt_info.return_info = skb;
1219 } else {
1220 pkt_info.return_info = 0;
1222 pkt_info.l4i_chk = 0;
1223 pkt_info.byte_cnt = this_frag->size;
1225 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1226 this_frag->page_offset,
1227 this_frag->size,
1228 DMA_TO_DEVICE);
1230 status = eth_port_send(mp, &pkt_info);
1232 if (status != ETH_OK) {
1233 if ((status == ETH_ERROR))
1234 printk(KERN_ERR "%s: Error on "
1235 "transmitting packet\n",
1236 dev->name);
1238 if (status == ETH_QUEUE_LAST_RESOURCE)
1239 printk("Tx resource error \n");
1241 if (status == ETH_QUEUE_FULL)
1242 printk("Queue is full \n");
1244 stats->tx_bytes += pkt_info.byte_cnt;
1247 #else
1248 spin_lock_irqsave(&mp->lock, flags);
1250 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1251 ETH_TX_LAST_DESC;
1252 pkt_info.l4i_chk = 0;
1253 pkt_info.byte_cnt = skb->len;
1254 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1255 DMA_TO_DEVICE);
1256 pkt_info.return_info = skb;
1257 status = eth_port_send(mp, &pkt_info);
1258 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1259 printk(KERN_ERR "%s: Error on transmitting packet\n",
1260 dev->name);
1261 stats->tx_bytes += pkt_info.byte_cnt;
1262 #endif
1264 /* Check if TX queue can handle another skb. If not, then
1265 * signal higher layers to stop requesting TX
1267 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1269 * Stop getting skb's from upper layers.
1270 * Getting skb's from upper layers will be enabled again after
1271 * packets are released.
1273 netif_stop_queue(dev);
1275 /* Update statistics and start of transmittion time */
1276 stats->tx_packets++;
1277 dev->trans_start = jiffies;
1279 spin_unlock_irqrestore(&mp->lock, flags);
1281 return 0; /* success */
1285 * mv643xx_eth_get_stats
1287 * Returns a pointer to the interface statistics.
1289 * Input : dev - a pointer to the required interface
1291 * Output : a pointer to the interface's statistics
1294 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1296 struct mv643xx_private *mp = netdev_priv(dev);
1298 return &mp->stats;
1301 #ifdef CONFIG_NET_POLL_CONTROLLER
1302 static void mv643xx_netpoll(struct net_device *netdev)
1304 struct mv643xx_private *mp = netdev_priv(netdev);
1305 int port_num = mp->port_num;
1307 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1308 /* wait for previous write to complete */
1309 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1311 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1313 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
1315 #endif
1318 * mv643xx_eth_probe
1320 * First function called after registering the network device.
1321 * It's purpose is to initialize the device as an ethernet device,
1322 * fill the ethernet device structure with pointers * to functions,
1323 * and set the MAC address of the interface
1325 * Input : struct device *
1326 * Output : -ENOMEM if failed , 0 if success
1328 static int mv643xx_eth_probe(struct platform_device *pdev)
1330 struct mv643xx_eth_platform_data *pd;
1331 int port_num = pdev->id;
1332 struct mv643xx_private *mp;
1333 struct net_device *dev;
1334 u8 *p;
1335 struct resource *res;
1336 int err;
1338 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1339 if (!dev)
1340 return -ENOMEM;
1342 platform_set_drvdata(pdev, dev);
1344 mp = netdev_priv(dev);
1346 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1347 BUG_ON(!res);
1348 dev->irq = res->start;
1350 mp->port_num = port_num;
1352 dev->open = mv643xx_eth_open;
1353 dev->stop = mv643xx_eth_stop;
1354 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1355 dev->get_stats = mv643xx_eth_get_stats;
1356 dev->set_mac_address = mv643xx_eth_set_mac_address;
1357 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1359 /* No need to Tx Timeout */
1360 dev->tx_timeout = mv643xx_eth_tx_timeout;
1361 #ifdef MV643XX_NAPI
1362 dev->poll = mv643xx_poll;
1363 dev->weight = 64;
1364 #endif
1366 #ifdef CONFIG_NET_POLL_CONTROLLER
1367 dev->poll_controller = mv643xx_netpoll;
1368 #endif
1370 dev->watchdog_timeo = 2 * HZ;
1371 dev->tx_queue_len = mp->tx_ring_size;
1372 dev->base_addr = 0;
1373 dev->change_mtu = mv643xx_eth_change_mtu;
1374 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1376 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1377 #ifdef MAX_SKB_FRAGS
1379 * Zero copy can only work if we use Discovery II memory. Else, we will
1380 * have to map the buffers to ISA memory which is only 16 MB
1382 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1383 #endif
1384 #endif
1386 /* Configure the timeout task */
1387 INIT_WORK(&mp->tx_timeout_task,
1388 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1390 spin_lock_init(&mp->lock);
1392 /* set default config values */
1393 eth_port_uc_addr_get(dev, dev->dev_addr);
1394 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1395 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1396 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1397 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1398 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1399 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1401 pd = pdev->dev.platform_data;
1402 if (pd) {
1403 if (pd->mac_addr != NULL)
1404 memcpy(dev->dev_addr, pd->mac_addr, 6);
1406 if (pd->phy_addr || pd->force_phy_addr)
1407 ethernet_phy_set(port_num, pd->phy_addr);
1409 if (pd->port_config || pd->force_port_config)
1410 mp->port_config = pd->port_config;
1412 if (pd->port_config_extend || pd->force_port_config_extend)
1413 mp->port_config_extend = pd->port_config_extend;
1415 if (pd->port_sdma_config || pd->force_port_sdma_config)
1416 mp->port_sdma_config = pd->port_sdma_config;
1418 if (pd->port_serial_control || pd->force_port_serial_control)
1419 mp->port_serial_control = pd->port_serial_control;
1421 if (pd->rx_queue_size)
1422 mp->rx_ring_size = pd->rx_queue_size;
1424 if (pd->tx_queue_size)
1425 mp->tx_ring_size = pd->tx_queue_size;
1427 if (pd->tx_sram_size) {
1428 mp->tx_sram_size = pd->tx_sram_size;
1429 mp->tx_sram_addr = pd->tx_sram_addr;
1432 if (pd->rx_sram_size) {
1433 mp->rx_sram_size = pd->rx_sram_size;
1434 mp->rx_sram_addr = pd->rx_sram_addr;
1438 err = ethernet_phy_detect(port_num);
1439 if (err) {
1440 pr_debug("MV643xx ethernet port %d: "
1441 "No PHY detected at addr %d\n",
1442 port_num, ethernet_phy_get(port_num));
1443 return err;
1446 err = register_netdev(dev);
1447 if (err)
1448 goto out;
1450 p = dev->dev_addr;
1451 printk(KERN_NOTICE
1452 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1453 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1455 if (dev->features & NETIF_F_SG)
1456 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1458 if (dev->features & NETIF_F_IP_CSUM)
1459 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1460 dev->name);
1462 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1463 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1464 #endif
1466 #ifdef MV643XX_COAL
1467 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1468 dev->name);
1469 #endif
1471 #ifdef MV643XX_NAPI
1472 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1473 #endif
1475 if (mp->tx_sram_size > 0)
1476 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1478 return 0;
1480 out:
1481 free_netdev(dev);
1483 return err;
1486 static int mv643xx_eth_remove(struct platform_device *pdev)
1488 struct net_device *dev = platform_get_drvdata(pdev);
1490 unregister_netdev(dev);
1491 flush_scheduled_work();
1493 free_netdev(dev);
1494 platform_set_drvdata(pdev, NULL);
1495 return 0;
1498 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1500 struct resource *res;
1502 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1504 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1505 if (res == NULL)
1506 return -ENODEV;
1508 mv643xx_eth_shared_base = ioremap(res->start,
1509 MV643XX_ETH_SHARED_REGS_SIZE);
1510 if (mv643xx_eth_shared_base == NULL)
1511 return -ENOMEM;
1513 return 0;
1517 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1519 iounmap(mv643xx_eth_shared_base);
1520 mv643xx_eth_shared_base = NULL;
1522 return 0;
1525 static struct platform_driver mv643xx_eth_driver = {
1526 .probe = mv643xx_eth_probe,
1527 .remove = mv643xx_eth_remove,
1528 .driver = {
1529 .name = MV643XX_ETH_NAME,
1533 static struct platform_driver mv643xx_eth_shared_driver = {
1534 .probe = mv643xx_eth_shared_probe,
1535 .remove = mv643xx_eth_shared_remove,
1536 .driver = {
1537 .name = MV643XX_ETH_SHARED_NAME,
1542 * mv643xx_init_module
1544 * Registers the network drivers into the Linux kernel
1546 * Input : N/A
1548 * Output : N/A
1550 static int __init mv643xx_init_module(void)
1552 int rc;
1554 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1555 if (!rc) {
1556 rc = platform_driver_register(&mv643xx_eth_driver);
1557 if (rc)
1558 platform_driver_unregister(&mv643xx_eth_shared_driver);
1560 return rc;
1564 * mv643xx_cleanup_module
1566 * Registers the network drivers into the Linux kernel
1568 * Input : N/A
1570 * Output : N/A
1572 static void __exit mv643xx_cleanup_module(void)
1574 platform_driver_unregister(&mv643xx_eth_driver);
1575 platform_driver_unregister(&mv643xx_eth_shared_driver);
1578 module_init(mv643xx_init_module);
1579 module_exit(mv643xx_cleanup_module);
1581 MODULE_LICENSE("GPL");
1582 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1583 " and Dale Farnsworth");
1584 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1587 * The second part is the low level driver of the gigE ethernet ports.
1591 * Marvell's Gigabit Ethernet controller low level driver
1593 * DESCRIPTION:
1594 * This file introduce low level API to Marvell's Gigabit Ethernet
1595 * controller. This Gigabit Ethernet Controller driver API controls
1596 * 1) Operations (i.e. port init, start, reset etc').
1597 * 2) Data flow (i.e. port send, receive etc').
1598 * Each Gigabit Ethernet port is controlled via
1599 * struct mv643xx_private.
1600 * This struct includes user configuration information as well as
1601 * driver internal data needed for its operations.
1603 * Supported Features:
1604 * - This low level driver is OS independent. Allocating memory for
1605 * the descriptor rings and buffers are not within the scope of
1606 * this driver.
1607 * - The user is free from Rx/Tx queue managing.
1608 * - This low level driver introduce functionality API that enable
1609 * the to operate Marvell's Gigabit Ethernet Controller in a
1610 * convenient way.
1611 * - Simple Gigabit Ethernet port operation API.
1612 * - Simple Gigabit Ethernet port data flow API.
1613 * - Data flow and operation API support per queue functionality.
1614 * - Support cached descriptors for better performance.
1615 * - Enable access to all four DRAM banks and internal SRAM memory
1616 * spaces.
1617 * - PHY access and control API.
1618 * - Port control register configuration API.
1619 * - Full control over Unicast and Multicast MAC configurations.
1621 * Operation flow:
1623 * Initialization phase
1624 * This phase complete the initialization of the the
1625 * mv643xx_private struct.
1626 * User information regarding port configuration has to be set
1627 * prior to calling the port initialization routine.
1629 * In this phase any port Tx/Rx activity is halted, MIB counters
1630 * are cleared, PHY address is set according to user parameter and
1631 * access to DRAM and internal SRAM memory spaces.
1633 * Driver ring initialization
1634 * Allocating memory for the descriptor rings and buffers is not
1635 * within the scope of this driver. Thus, the user is required to
1636 * allocate memory for the descriptors ring and buffers. Those
1637 * memory parameters are used by the Rx and Tx ring initialization
1638 * routines in order to curve the descriptor linked list in a form
1639 * of a ring.
1640 * Note: Pay special attention to alignment issues when using
1641 * cached descriptors/buffers. In this phase the driver store
1642 * information in the mv643xx_private struct regarding each queue
1643 * ring.
1645 * Driver start
1646 * This phase prepares the Ethernet port for Rx and Tx activity.
1647 * It uses the information stored in the mv643xx_private struct to
1648 * initialize the various port registers.
1650 * Data flow:
1651 * All packet references to/from the driver are done using
1652 * struct pkt_info.
1653 * This struct is a unified struct used with Rx and Tx operations.
1654 * This way the user is not required to be familiar with neither
1655 * Tx nor Rx descriptors structures.
1656 * The driver's descriptors rings are management by indexes.
1657 * Those indexes controls the ring resources and used to indicate
1658 * a SW resource error:
1659 * 'current'
1660 * This index points to the current available resource for use. For
1661 * example in Rx process this index will point to the descriptor
1662 * that will be passed to the user upon calling the receive
1663 * routine. In Tx process, this index will point to the descriptor
1664 * that will be assigned with the user packet info and transmitted.
1665 * 'used'
1666 * This index points to the descriptor that need to restore its
1667 * resources. For example in Rx process, using the Rx buffer return
1668 * API will attach the buffer returned in packet info to the
1669 * descriptor pointed by 'used'. In Tx process, using the Tx
1670 * descriptor return will merely return the user packet info with
1671 * the command status of the transmitted buffer pointed by the
1672 * 'used' index. Nevertheless, it is essential to use this routine
1673 * to update the 'used' index.
1674 * 'first'
1675 * This index supports Tx Scatter-Gather. It points to the first
1676 * descriptor of a packet assembled of multiple buffers. For
1677 * example when in middle of Such packet we have a Tx resource
1678 * error the 'curr' index get the value of 'first' to indicate
1679 * that the ring returned to its state before trying to transmit
1680 * this packet.
1682 * Receive operation:
1683 * The eth_port_receive API set the packet information struct,
1684 * passed by the caller, with received information from the
1685 * 'current' SDMA descriptor.
1686 * It is the user responsibility to return this resource back
1687 * to the Rx descriptor ring to enable the reuse of this source.
1688 * Return Rx resource is done using the eth_rx_return_buff API.
1690 * Transmit operation:
1691 * The eth_port_send API supports Scatter-Gather which enables to
1692 * send a packet spanned over multiple buffers. This means that
1693 * for each packet info structure given by the user and put into
1694 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1695 * bit will be set in the packet info command status field. This
1696 * API also consider restriction regarding buffer alignments and
1697 * sizes.
1698 * The user must return a Tx resource after ensuring the buffer
1699 * has been transmitted to enable the Tx ring indexes to update.
1701 * BOARD LAYOUT
1702 * This device is on-board. No jumper diagram is necessary.
1704 * EXTERNAL INTERFACE
1706 * Prior to calling the initialization routine eth_port_init() the user
1707 * must set the following fields under mv643xx_private struct:
1708 * port_num User Ethernet port number.
1709 * port_mac_addr[6] User defined port MAC address.
1710 * port_config User port configuration value.
1711 * port_config_extend User port config extend value.
1712 * port_sdma_config User port SDMA config value.
1713 * port_serial_control User port serial control value.
1715 * This driver data flow is done using the struct pkt_info which
1716 * is a unified struct for Rx and Tx operations:
1718 * byte_cnt Tx/Rx descriptor buffer byte count.
1719 * l4i_chk CPU provided TCP Checksum. For Tx operation
1720 * only.
1721 * cmd_sts Tx/Rx descriptor command status.
1722 * buf_ptr Tx/Rx descriptor buffer pointer.
1723 * return_info Tx/Rx user resource return information.
1726 /* defines */
1727 /* SDMA command macros */
1728 #define ETH_ENABLE_TX_QUEUE(eth_port) \
1729 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1731 /* locals */
1733 /* PHY routines */
1734 static int ethernet_phy_get(unsigned int eth_port_num);
1735 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1737 /* Ethernet Port routines */
1738 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1739 int option);
1742 * eth_port_init - Initialize the Ethernet port driver
1744 * DESCRIPTION:
1745 * This function prepares the ethernet port to start its activity:
1746 * 1) Completes the ethernet port driver struct initialization toward port
1747 * start routine.
1748 * 2) Resets the device to a quiescent state in case of warm reboot.
1749 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1750 * 4) Clean MAC tables. The reset status of those tables is unknown.
1751 * 5) Set PHY address.
1752 * Note: Call this routine prior to eth_port_start routine and after
1753 * setting user values in the user fields of Ethernet port control
1754 * struct.
1756 * INPUT:
1757 * struct mv643xx_private *mp Ethernet port control struct
1759 * OUTPUT:
1760 * See description.
1762 * RETURN:
1763 * None.
1765 static void eth_port_init(struct mv643xx_private *mp)
1767 mp->port_rx_queue_command = 0;
1768 mp->port_tx_queue_command = 0;
1770 mp->rx_resource_err = 0;
1771 mp->tx_resource_err = 0;
1773 eth_port_reset(mp->port_num);
1775 eth_port_init_mac_tables(mp->port_num);
1777 ethernet_phy_reset(mp->port_num);
1781 * eth_port_start - Start the Ethernet port activity.
1783 * DESCRIPTION:
1784 * This routine prepares the Ethernet port for Rx and Tx activity:
1785 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1786 * has been initialized a descriptor's ring (using
1787 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1788 * 2. Initialize and enable the Ethernet configuration port by writing to
1789 * the port's configuration and command registers.
1790 * 3. Initialize and enable the SDMA by writing to the SDMA's
1791 * configuration and command registers. After completing these steps,
1792 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1794 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1795 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1796 * and ether_init_rx_desc_ring for Rx queues).
1798 * INPUT:
1799 * struct mv643xx_private *mp Ethernet port control struct
1801 * OUTPUT:
1802 * Ethernet port is ready to receive and transmit.
1804 * RETURN:
1805 * None.
1807 static void eth_port_start(struct mv643xx_private *mp)
1809 unsigned int port_num = mp->port_num;
1810 int tx_curr_desc, rx_curr_desc;
1812 /* Assignment of Tx CTRP of given queue */
1813 tx_curr_desc = mp->tx_curr_desc_q;
1814 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1815 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1817 /* Assignment of Rx CRDP of given queue */
1818 rx_curr_desc = mp->rx_curr_desc_q;
1819 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1820 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1822 /* Add the assigned Ethernet address to the port's address table */
1823 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1825 /* Assign port configuration and command. */
1826 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1828 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1829 mp->port_config_extend);
1832 /* Increase the Rx side buffer size if supporting GigE */
1833 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1834 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1835 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1836 else
1837 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1838 mp->port_serial_control);
1840 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1841 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1842 MV643XX_ETH_SERIAL_PORT_ENABLE);
1844 /* Assign port SDMA configuration */
1845 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1846 mp->port_sdma_config);
1848 /* Enable port Rx. */
1849 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1850 mp->port_rx_queue_command);
1852 /* Disable port bandwidth limits by clearing MTU register */
1853 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1857 * eth_port_uc_addr_set - This function Set the port Unicast address.
1859 * DESCRIPTION:
1860 * This function Set the port Ethernet MAC address.
1862 * INPUT:
1863 * unsigned int eth_port_num Port number.
1864 * char * p_addr Address to be set
1866 * OUTPUT:
1867 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1868 * To set the unicast table with the proper information.
1870 * RETURN:
1871 * N/A.
1874 static void eth_port_uc_addr_set(unsigned int eth_port_num,
1875 unsigned char *p_addr)
1877 unsigned int mac_h;
1878 unsigned int mac_l;
1880 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1881 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1882 (p_addr[3] << 0);
1884 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1885 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1887 /* Accept frames of this address */
1888 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1890 return;
1894 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1895 * (MAC address) from the ethernet hw registers.
1897 * DESCRIPTION:
1898 * This function retrieves the port Ethernet MAC address.
1900 * INPUT:
1901 * unsigned int eth_port_num Port number.
1902 * char *MacAddr pointer where the MAC address is stored
1904 * OUTPUT:
1905 * Copy the MAC address to the location pointed to by MacAddr
1907 * RETURN:
1908 * N/A.
1911 static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1913 struct mv643xx_private *mp = netdev_priv(dev);
1914 unsigned int mac_h;
1915 unsigned int mac_l;
1917 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1918 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1920 p_addr[0] = (mac_h >> 24) & 0xff;
1921 p_addr[1] = (mac_h >> 16) & 0xff;
1922 p_addr[2] = (mac_h >> 8) & 0xff;
1923 p_addr[3] = mac_h & 0xff;
1924 p_addr[4] = (mac_l >> 8) & 0xff;
1925 p_addr[5] = mac_l & 0xff;
1929 * eth_port_uc_addr - This function Set the port unicast address table
1931 * DESCRIPTION:
1932 * This function locates the proper entry in the Unicast table for the
1933 * specified MAC nibble and sets its properties according to function
1934 * parameters.
1936 * INPUT:
1937 * unsigned int eth_port_num Port number.
1938 * unsigned char uc_nibble Unicast MAC Address last nibble.
1939 * int option 0 = Add, 1 = remove address.
1941 * OUTPUT:
1942 * This function add/removes MAC addresses from the port unicast address
1943 * table.
1945 * RETURN:
1946 * true is output succeeded.
1947 * false if option parameter is invalid.
1950 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1951 int option)
1953 unsigned int unicast_reg;
1954 unsigned int tbl_offset;
1955 unsigned int reg_offset;
1957 /* Locate the Unicast table entry */
1958 uc_nibble = (0xf & uc_nibble);
1959 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1960 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1962 switch (option) {
1963 case REJECT_MAC_ADDR:
1964 /* Clear accepts frame bit at given unicast DA table entry */
1965 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1966 (eth_port_num) + tbl_offset));
1968 unicast_reg &= (0x0E << (8 * reg_offset));
1970 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1971 (eth_port_num) + tbl_offset), unicast_reg);
1972 break;
1974 case ACCEPT_MAC_ADDR:
1975 /* Set accepts frame bit at unicast DA filter table entry */
1976 unicast_reg =
1977 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1978 (eth_port_num) + tbl_offset));
1980 unicast_reg |= (0x01 << (8 * reg_offset));
1982 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1983 (eth_port_num) + tbl_offset), unicast_reg);
1985 break;
1987 default:
1988 return 0;
1991 return 1;
1995 * The entries in each table are indexed by a hash of a packet's MAC
1996 * address. One bit in each entry determines whether the packet is
1997 * accepted. There are 4 entries (each 8 bits wide) in each register
1998 * of the table. The bits in each entry are defined as follows:
1999 * 0 Accept=1, Drop=0
2000 * 3-1 Queue (ETH_Q0=0)
2001 * 7-4 Reserved = 0;
2003 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2005 unsigned int table_reg;
2006 unsigned int tbl_offset;
2007 unsigned int reg_offset;
2009 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2010 reg_offset = entry % 4; /* Entry offset within the register */
2012 /* Set "accepts frame bit" at specified table entry */
2013 table_reg = mv_read(table + tbl_offset);
2014 table_reg |= 0x01 << (8 * reg_offset);
2015 mv_write(table + tbl_offset, table_reg);
2019 * eth_port_mc_addr - Multicast address settings.
2021 * The MV device supports multicast using two tables:
2022 * 1) Special Multicast Table for MAC addresses of the form
2023 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2024 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2025 * Table entries in the DA-Filter table.
2026 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2027 * is used as an index to the Other Multicast Table entries in the
2028 * DA-Filter table. This function calculates the CRC-8bit value.
2029 * In either case, eth_port_set_filter_table_entry() is then called
2030 * to set to set the actual table entry.
2032 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2034 unsigned int mac_h;
2035 unsigned int mac_l;
2036 unsigned char crc_result = 0;
2037 int table;
2038 int mac_array[48];
2039 int crc[8];
2040 int i;
2042 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2043 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2044 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2045 (eth_port_num);
2046 eth_port_set_filter_table_entry(table, p_addr[5]);
2047 return;
2050 /* Calculate CRC-8 out of the given address */
2051 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2052 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2053 (p_addr[4] << 8) | (p_addr[5] << 0);
2055 for (i = 0; i < 32; i++)
2056 mac_array[i] = (mac_l >> i) & 0x1;
2057 for (i = 32; i < 48; i++)
2058 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2060 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2061 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2062 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2063 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2064 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2066 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2067 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2068 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2069 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2070 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2071 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2072 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2074 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2075 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2076 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2077 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2078 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2079 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2081 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2082 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2083 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2084 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2085 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2086 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2088 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2089 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2090 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2091 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2092 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2093 mac_array[3] ^ mac_array[2];
2095 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2096 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2097 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2098 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2099 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2100 mac_array[4] ^ mac_array[3];
2102 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2103 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2104 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2105 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2106 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2107 mac_array[4];
2109 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2110 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2111 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2112 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2113 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2115 for (i = 0; i < 8; i++)
2116 crc_result = crc_result | (crc[i] << i);
2118 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2119 eth_port_set_filter_table_entry(table, crc_result);
2123 * Set the entire multicast list based on dev->mc_list.
2125 static void eth_port_set_multicast_list(struct net_device *dev)
2128 struct dev_mc_list *mc_list;
2129 int i;
2130 int table_index;
2131 struct mv643xx_private *mp = netdev_priv(dev);
2132 unsigned int eth_port_num = mp->port_num;
2134 /* If the device is in promiscuous mode or in all multicast mode,
2135 * we will fully populate both multicast tables with accept.
2136 * This is guaranteed to yield a match on all multicast addresses...
2138 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2139 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2140 /* Set all entries in DA filter special multicast
2141 * table (Ex_dFSMT)
2142 * Set for ETH_Q0 for now
2143 * Bits
2144 * 0 Accept=1, Drop=0
2145 * 3-1 Queue ETH_Q0=0
2146 * 7-4 Reserved = 0;
2148 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2150 /* Set all entries in DA filter other multicast
2151 * table (Ex_dFOMT)
2152 * Set for ETH_Q0 for now
2153 * Bits
2154 * 0 Accept=1, Drop=0
2155 * 3-1 Queue ETH_Q0=0
2156 * 7-4 Reserved = 0;
2158 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2160 return;
2163 /* We will clear out multicast tables every time we get the list.
2164 * Then add the entire new list...
2166 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2167 /* Clear DA filter special multicast table (Ex_dFSMT) */
2168 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2169 (eth_port_num) + table_index, 0);
2171 /* Clear DA filter other multicast table (Ex_dFOMT) */
2172 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2173 (eth_port_num) + table_index, 0);
2176 /* Get pointer to net_device multicast list and add each one... */
2177 for (i = 0, mc_list = dev->mc_list;
2178 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2179 i++, mc_list = mc_list->next)
2180 if (mc_list->dmi_addrlen == 6)
2181 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2185 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2187 * DESCRIPTION:
2188 * Go through all the DA filter tables (Unicast, Special Multicast &
2189 * Other Multicast) and set each entry to 0.
2191 * INPUT:
2192 * unsigned int eth_port_num Ethernet Port number.
2194 * OUTPUT:
2195 * Multicast and Unicast packets are rejected.
2197 * RETURN:
2198 * None.
2200 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2202 int table_index;
2204 /* Clear DA filter unicast table (Ex_dFUT) */
2205 for (table_index = 0; table_index <= 0xC; table_index += 4)
2206 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2207 (eth_port_num) + table_index), 0);
2209 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2210 /* Clear DA filter special multicast table (Ex_dFSMT) */
2211 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2212 (eth_port_num) + table_index, 0);
2213 /* Clear DA filter other multicast table (Ex_dFOMT) */
2214 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2215 (eth_port_num) + table_index, 0);
2220 * eth_clear_mib_counters - Clear all MIB counters
2222 * DESCRIPTION:
2223 * This function clears all MIB counters of a specific ethernet port.
2224 * A read from the MIB counter will reset the counter.
2226 * INPUT:
2227 * unsigned int eth_port_num Ethernet Port number.
2229 * OUTPUT:
2230 * After reading all MIB counters, the counters resets.
2232 * RETURN:
2233 * MIB counter value.
2236 static void eth_clear_mib_counters(unsigned int eth_port_num)
2238 int i;
2240 /* Perform dummy reads from MIB counters */
2241 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2242 i += 4)
2243 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2246 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2248 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2251 static void eth_update_mib_counters(struct mv643xx_private *mp)
2253 struct mv643xx_mib_counters *p = &mp->mib_counters;
2254 int offset;
2256 p->good_octets_received +=
2257 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2258 p->good_octets_received +=
2259 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2261 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2262 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2263 offset += 4)
2264 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2266 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2267 p->good_octets_sent +=
2268 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2270 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2271 offset <= ETH_MIB_LATE_COLLISION;
2272 offset += 4)
2273 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2277 * ethernet_phy_detect - Detect whether a phy is present
2279 * DESCRIPTION:
2280 * This function tests whether there is a PHY present on
2281 * the specified port.
2283 * INPUT:
2284 * unsigned int eth_port_num Ethernet Port number.
2286 * OUTPUT:
2287 * None
2289 * RETURN:
2290 * 0 on success
2291 * -ENODEV on failure
2294 static int ethernet_phy_detect(unsigned int port_num)
2296 unsigned int phy_reg_data0;
2297 int auto_neg;
2299 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2300 auto_neg = phy_reg_data0 & 0x1000;
2301 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2302 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2304 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2305 if ((phy_reg_data0 & 0x1000) == auto_neg)
2306 return -ENODEV; /* change didn't take */
2308 phy_reg_data0 ^= 0x1000;
2309 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2310 return 0;
2314 * ethernet_phy_get - Get the ethernet port PHY address.
2316 * DESCRIPTION:
2317 * This routine returns the given ethernet port PHY address.
2319 * INPUT:
2320 * unsigned int eth_port_num Ethernet Port number.
2322 * OUTPUT:
2323 * None.
2325 * RETURN:
2326 * PHY address.
2329 static int ethernet_phy_get(unsigned int eth_port_num)
2331 unsigned int reg_data;
2333 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2335 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2339 * ethernet_phy_set - Set the ethernet port PHY address.
2341 * DESCRIPTION:
2342 * This routine sets the given ethernet port PHY address.
2344 * INPUT:
2345 * unsigned int eth_port_num Ethernet Port number.
2346 * int phy_addr PHY address.
2348 * OUTPUT:
2349 * None.
2351 * RETURN:
2352 * None.
2355 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2357 u32 reg_data;
2358 int addr_shift = 5 * eth_port_num;
2360 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2361 reg_data &= ~(0x1f << addr_shift);
2362 reg_data |= (phy_addr & 0x1f) << addr_shift;
2363 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2367 * ethernet_phy_reset - Reset Ethernet port PHY.
2369 * DESCRIPTION:
2370 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2372 * INPUT:
2373 * unsigned int eth_port_num Ethernet Port number.
2375 * OUTPUT:
2376 * The PHY is reset.
2378 * RETURN:
2379 * None.
2382 static void ethernet_phy_reset(unsigned int eth_port_num)
2384 unsigned int phy_reg_data;
2386 /* Reset the PHY */
2387 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2388 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2389 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2393 * eth_port_reset - Reset Ethernet port
2395 * DESCRIPTION:
2396 * This routine resets the chip by aborting any SDMA engine activity and
2397 * clearing the MIB counters. The Receiver and the Transmit unit are in
2398 * idle state after this command is performed and the port is disabled.
2400 * INPUT:
2401 * unsigned int eth_port_num Ethernet Port number.
2403 * OUTPUT:
2404 * Channel activity is halted.
2406 * RETURN:
2407 * None.
2410 static void eth_port_reset(unsigned int port_num)
2412 unsigned int reg_data;
2414 /* Stop Tx port activity. Check port Tx activity. */
2415 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2417 if (reg_data & 0xFF) {
2418 /* Issue stop command for active channels only */
2419 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2420 (reg_data << 8));
2422 /* Wait for all Tx activity to terminate. */
2423 /* Check port cause register that all Tx queues are stopped */
2424 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2425 & 0xFF)
2426 udelay(10);
2429 /* Stop Rx port activity. Check port Rx activity. */
2430 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2432 if (reg_data & 0xFF) {
2433 /* Issue stop command for active channels only */
2434 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2435 (reg_data << 8));
2437 /* Wait for all Rx activity to terminate. */
2438 /* Check port cause register that all Rx queues are stopped */
2439 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2440 & 0xFF)
2441 udelay(10);
2444 /* Clear all MIB counters */
2445 eth_clear_mib_counters(port_num);
2447 /* Reset the Enable bit in the Configuration Register */
2448 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2449 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2450 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2454 static int eth_port_autoneg_supported(unsigned int eth_port_num)
2456 unsigned int phy_reg_data0;
2458 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2460 return phy_reg_data0 & 0x1000;
2463 static int eth_port_link_is_up(unsigned int eth_port_num)
2465 unsigned int phy_reg_data1;
2467 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2469 if (eth_port_autoneg_supported(eth_port_num)) {
2470 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2471 return 1;
2472 } else if (phy_reg_data1 & 0x4) /* link up */
2473 return 1;
2475 return 0;
2479 * eth_port_read_smi_reg - Read PHY registers
2481 * DESCRIPTION:
2482 * This routine utilize the SMI interface to interact with the PHY in
2483 * order to perform PHY register read.
2485 * INPUT:
2486 * unsigned int port_num Ethernet Port number.
2487 * unsigned int phy_reg PHY register address offset.
2488 * unsigned int *value Register value buffer.
2490 * OUTPUT:
2491 * Write the value of a specified PHY register into given buffer.
2493 * RETURN:
2494 * false if the PHY is busy or read data is not in valid state.
2495 * true otherwise.
2498 static void eth_port_read_smi_reg(unsigned int port_num,
2499 unsigned int phy_reg, unsigned int *value)
2501 int phy_addr = ethernet_phy_get(port_num);
2502 unsigned long flags;
2503 int i;
2505 /* the SMI register is a shared resource */
2506 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2508 /* wait for the SMI register to become available */
2509 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2510 if (i == PHY_WAIT_ITERATIONS) {
2511 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2512 goto out;
2514 udelay(PHY_WAIT_MICRO_SECONDS);
2517 mv_write(MV643XX_ETH_SMI_REG,
2518 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2520 /* now wait for the data to be valid */
2521 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2522 if (i == PHY_WAIT_ITERATIONS) {
2523 printk("mv643xx PHY read timeout, port %d\n", port_num);
2524 goto out;
2526 udelay(PHY_WAIT_MICRO_SECONDS);
2529 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2530 out:
2531 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2535 * eth_port_write_smi_reg - Write to PHY registers
2537 * DESCRIPTION:
2538 * This routine utilize the SMI interface to interact with the PHY in
2539 * order to perform writes to PHY registers.
2541 * INPUT:
2542 * unsigned int eth_port_num Ethernet Port number.
2543 * unsigned int phy_reg PHY register address offset.
2544 * unsigned int value Register value.
2546 * OUTPUT:
2547 * Write the given value to the specified PHY register.
2549 * RETURN:
2550 * false if the PHY is busy.
2551 * true otherwise.
2554 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2555 unsigned int phy_reg, unsigned int value)
2557 int phy_addr;
2558 int i;
2559 unsigned long flags;
2561 phy_addr = ethernet_phy_get(eth_port_num);
2563 /* the SMI register is a shared resource */
2564 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2566 /* wait for the SMI register to become available */
2567 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2568 if (i == PHY_WAIT_ITERATIONS) {
2569 printk("mv643xx PHY busy timeout, port %d\n",
2570 eth_port_num);
2571 goto out;
2573 udelay(PHY_WAIT_MICRO_SECONDS);
2576 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2577 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2578 out:
2579 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2583 * eth_port_send - Send an Ethernet packet
2585 * DESCRIPTION:
2586 * This routine send a given packet described by p_pktinfo parameter. It
2587 * supports transmitting of a packet spaned over multiple buffers. The
2588 * routine updates 'curr' and 'first' indexes according to the packet
2589 * segment passed to the routine. In case the packet segment is first,
2590 * the 'first' index is update. In any case, the 'curr' index is updated.
2591 * If the routine get into Tx resource error it assigns 'curr' index as
2592 * 'first'. This way the function can abort Tx process of multiple
2593 * descriptors per packet.
2595 * INPUT:
2596 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2597 * struct pkt_info *p_pkt_info User packet buffer.
2599 * OUTPUT:
2600 * Tx ring 'curr' and 'first' indexes are updated.
2602 * RETURN:
2603 * ETH_QUEUE_FULL in case of Tx resource error.
2604 * ETH_ERROR in case the routine can not access Tx desc ring.
2605 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2606 * ETH_OK otherwise.
2609 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2611 * Modified to include the first descriptor pointer in case of SG
2613 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2614 struct pkt_info *p_pkt_info)
2616 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2617 struct eth_tx_desc *current_descriptor;
2618 struct eth_tx_desc *first_descriptor;
2619 u32 command;
2620 unsigned long flags;
2622 /* Do not process Tx ring in case of Tx ring resource error */
2623 if (mp->tx_resource_err)
2624 return ETH_QUEUE_FULL;
2627 * The hardware requires that each buffer that is <= 8 bytes
2628 * in length must be aligned on an 8 byte boundary.
2630 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2631 printk(KERN_ERR
2632 "mv643xx_eth port %d: packet size <= 8 problem\n",
2633 mp->port_num);
2634 return ETH_ERROR;
2637 spin_lock_irqsave(&mp->lock, flags);
2639 mp->tx_ring_skbs++;
2640 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2642 /* Get the Tx Desc ring indexes */
2643 tx_desc_curr = mp->tx_curr_desc_q;
2644 tx_desc_used = mp->tx_used_desc_q;
2646 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2648 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2650 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2651 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2652 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2653 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2655 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2656 ETH_BUFFER_OWNED_BY_DMA;
2657 if (command & ETH_TX_FIRST_DESC) {
2658 tx_first_desc = tx_desc_curr;
2659 mp->tx_first_desc_q = tx_first_desc;
2660 first_descriptor = current_descriptor;
2661 mp->tx_first_command = command;
2662 } else {
2663 tx_first_desc = mp->tx_first_desc_q;
2664 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2665 BUG_ON(first_descriptor == NULL);
2666 current_descriptor->cmd_sts = command;
2669 if (command & ETH_TX_LAST_DESC) {
2670 wmb();
2671 first_descriptor->cmd_sts = mp->tx_first_command;
2673 wmb();
2674 ETH_ENABLE_TX_QUEUE(mp->port_num);
2677 * Finish Tx packet. Update first desc in case of Tx resource
2678 * error */
2679 tx_first_desc = tx_next_desc;
2680 mp->tx_first_desc_q = tx_first_desc;
2683 /* Check for ring index overlap in the Tx desc ring */
2684 if (tx_next_desc == tx_desc_used) {
2685 mp->tx_resource_err = 1;
2686 mp->tx_curr_desc_q = tx_first_desc;
2688 spin_unlock_irqrestore(&mp->lock, flags);
2690 return ETH_QUEUE_LAST_RESOURCE;
2693 mp->tx_curr_desc_q = tx_next_desc;
2695 spin_unlock_irqrestore(&mp->lock, flags);
2697 return ETH_OK;
2699 #else
2700 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2701 struct pkt_info *p_pkt_info)
2703 int tx_desc_curr;
2704 int tx_desc_used;
2705 struct eth_tx_desc *current_descriptor;
2706 unsigned int command_status;
2707 unsigned long flags;
2709 /* Do not process Tx ring in case of Tx ring resource error */
2710 if (mp->tx_resource_err)
2711 return ETH_QUEUE_FULL;
2713 spin_lock_irqsave(&mp->lock, flags);
2715 mp->tx_ring_skbs++;
2716 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2718 /* Get the Tx Desc ring indexes */
2719 tx_desc_curr = mp->tx_curr_desc_q;
2720 tx_desc_used = mp->tx_used_desc_q;
2721 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2723 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2724 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2725 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2726 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2728 /* Set last desc with DMA ownership and interrupt enable. */
2729 wmb();
2730 current_descriptor->cmd_sts = command_status |
2731 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2733 wmb();
2734 ETH_ENABLE_TX_QUEUE(mp->port_num);
2736 /* Finish Tx packet. Update first desc in case of Tx resource error */
2737 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2739 /* Update the current descriptor */
2740 mp->tx_curr_desc_q = tx_desc_curr;
2742 /* Check for ring index overlap in the Tx desc ring */
2743 if (tx_desc_curr == tx_desc_used) {
2744 mp->tx_resource_err = 1;
2746 spin_unlock_irqrestore(&mp->lock, flags);
2747 return ETH_QUEUE_LAST_RESOURCE;
2750 spin_unlock_irqrestore(&mp->lock, flags);
2751 return ETH_OK;
2753 #endif
2756 * eth_tx_return_desc - Free all used Tx descriptors
2758 * DESCRIPTION:
2759 * This routine returns the transmitted packet information to the caller.
2760 * It uses the 'first' index to support Tx desc return in case a transmit
2761 * of a packet spanned over multiple buffer still in process.
2762 * In case the Tx queue was in "resource error" condition, where there are
2763 * no available Tx resources, the function resets the resource error flag.
2765 * INPUT:
2766 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2767 * struct pkt_info *p_pkt_info User packet buffer.
2769 * OUTPUT:
2770 * Tx ring 'first' and 'used' indexes are updated.
2772 * RETURN:
2773 * ETH_OK on success
2774 * ETH_ERROR otherwise.
2777 static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2778 struct pkt_info *p_pkt_info)
2780 int tx_desc_used;
2781 int tx_busy_desc;
2782 struct eth_tx_desc *p_tx_desc_used;
2783 unsigned int command_status;
2784 unsigned long flags;
2785 int err = ETH_OK;
2787 spin_lock_irqsave(&mp->lock, flags);
2789 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2790 tx_busy_desc = mp->tx_first_desc_q;
2791 #else
2792 tx_busy_desc = mp->tx_curr_desc_q;
2793 #endif
2795 /* Get the Tx Desc ring indexes */
2796 tx_desc_used = mp->tx_used_desc_q;
2798 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2800 /* Sanity check */
2801 if (p_tx_desc_used == NULL) {
2802 err = ETH_ERROR;
2803 goto out;
2806 /* Stop release. About to overlap the current available Tx descriptor */
2807 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err) {
2808 err = ETH_ERROR;
2809 goto out;
2812 command_status = p_tx_desc_used->cmd_sts;
2814 /* Still transmitting... */
2815 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2816 err = ETH_ERROR;
2817 goto out;
2820 /* Pass the packet information to the caller */
2821 p_pkt_info->cmd_sts = command_status;
2822 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2823 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2824 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
2825 mp->tx_skb[tx_desc_used] = NULL;
2827 /* Update the next descriptor to release. */
2828 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2830 /* Any Tx return cancels the Tx resource error status */
2831 mp->tx_resource_err = 0;
2833 BUG_ON(mp->tx_ring_skbs == 0);
2834 mp->tx_ring_skbs--;
2836 out:
2837 spin_unlock_irqrestore(&mp->lock, flags);
2839 return err;
2843 * eth_port_receive - Get received information from Rx ring.
2845 * DESCRIPTION:
2846 * This routine returns the received data to the caller. There is no
2847 * data copying during routine operation. All information is returned
2848 * using pointer to packet information struct passed from the caller.
2849 * If the routine exhausts Rx ring resources then the resource error flag
2850 * is set.
2852 * INPUT:
2853 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2854 * struct pkt_info *p_pkt_info User packet buffer.
2856 * OUTPUT:
2857 * Rx ring current and used indexes are updated.
2859 * RETURN:
2860 * ETH_ERROR in case the routine can not access Rx desc ring.
2861 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2862 * ETH_END_OF_JOB if there is no received data.
2863 * ETH_OK otherwise.
2865 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2866 struct pkt_info *p_pkt_info)
2868 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2869 volatile struct eth_rx_desc *p_rx_desc;
2870 unsigned int command_status;
2871 unsigned long flags;
2873 /* Do not process Rx ring in case of Rx ring resource error */
2874 if (mp->rx_resource_err)
2875 return ETH_QUEUE_FULL;
2877 spin_lock_irqsave(&mp->lock, flags);
2879 /* Get the Rx Desc ring 'curr and 'used' indexes */
2880 rx_curr_desc = mp->rx_curr_desc_q;
2881 rx_used_desc = mp->rx_used_desc_q;
2883 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2885 /* The following parameters are used to save readings from memory */
2886 command_status = p_rx_desc->cmd_sts;
2887 rmb();
2889 /* Nothing to receive... */
2890 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2891 spin_unlock_irqrestore(&mp->lock, flags);
2892 return ETH_END_OF_JOB;
2895 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2896 p_pkt_info->cmd_sts = command_status;
2897 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2898 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2899 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2901 /* Clean the return info field to indicate that the packet has been */
2902 /* moved to the upper layers */
2903 mp->rx_skb[rx_curr_desc] = NULL;
2905 /* Update current index in data structure */
2906 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2907 mp->rx_curr_desc_q = rx_next_curr_desc;
2909 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2910 if (rx_next_curr_desc == rx_used_desc)
2911 mp->rx_resource_err = 1;
2913 spin_unlock_irqrestore(&mp->lock, flags);
2915 return ETH_OK;
2919 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2921 * DESCRIPTION:
2922 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2923 * next 'used' descriptor and attached the returned buffer to it.
2924 * In case the Rx ring was in "resource error" condition, where there are
2925 * no available Rx resources, the function resets the resource error flag.
2927 * INPUT:
2928 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2929 * struct pkt_info *p_pkt_info Information on returned buffer.
2931 * OUTPUT:
2932 * New available Rx resource in Rx descriptor ring.
2934 * RETURN:
2935 * ETH_ERROR in case the routine can not access Rx desc ring.
2936 * ETH_OK otherwise.
2938 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2939 struct pkt_info *p_pkt_info)
2941 int used_rx_desc; /* Where to return Rx resource */
2942 volatile struct eth_rx_desc *p_used_rx_desc;
2943 unsigned long flags;
2945 spin_lock_irqsave(&mp->lock, flags);
2947 /* Get 'used' Rx descriptor */
2948 used_rx_desc = mp->rx_used_desc_q;
2949 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2951 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2952 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2953 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2955 /* Flush the write pipe */
2957 /* Return the descriptor to DMA ownership */
2958 wmb();
2959 p_used_rx_desc->cmd_sts =
2960 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2961 wmb();
2963 /* Move the used descriptor pointer to the next descriptor */
2964 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2966 /* Any Rx return cancels the Rx resource error status */
2967 mp->rx_resource_err = 0;
2969 spin_unlock_irqrestore(&mp->lock, flags);
2971 return ETH_OK;
2974 /************* Begin ethtool support *************************/
2976 struct mv643xx_stats {
2977 char stat_string[ETH_GSTRING_LEN];
2978 int sizeof_stat;
2979 int stat_offset;
2982 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2983 offsetof(struct mv643xx_private, m)
2985 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2986 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2987 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2988 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2989 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2990 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2991 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2992 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2993 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2994 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2995 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2996 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2997 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2998 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2999 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3000 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3001 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3002 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3003 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3004 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3005 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3006 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3007 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3008 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3009 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3010 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3011 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3012 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3013 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3014 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3015 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3016 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3017 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3018 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3019 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3020 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3021 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3022 { "collision", MV643XX_STAT(mib_counters.collision) },
3023 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3026 #define MV643XX_STATS_LEN \
3027 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3029 static int
3030 mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
3032 struct mv643xx_private *mp = netdev->priv;
3033 int port_num = mp->port_num;
3034 int autoneg = eth_port_autoneg_supported(port_num);
3035 int mode_10_bit;
3036 int auto_duplex;
3037 int half_duplex = 0;
3038 int full_duplex = 0;
3039 int auto_speed;
3040 int speed_10 = 0;
3041 int speed_100 = 0;
3042 int speed_1000 = 0;
3044 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
3045 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
3047 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
3049 if (mode_10_bit) {
3050 ecmd->supported = SUPPORTED_10baseT_Half;
3051 } else {
3052 ecmd->supported = (SUPPORTED_10baseT_Half |
3053 SUPPORTED_10baseT_Full |
3054 SUPPORTED_100baseT_Half |
3055 SUPPORTED_100baseT_Full |
3056 SUPPORTED_1000baseT_Full |
3057 (autoneg ? SUPPORTED_Autoneg : 0) |
3058 SUPPORTED_TP);
3060 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3061 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3063 ecmd->advertising = ADVERTISED_TP;
3065 if (autoneg) {
3066 ecmd->advertising |= ADVERTISED_Autoneg;
3068 if (auto_duplex) {
3069 half_duplex = 1;
3070 full_duplex = 1;
3071 } else {
3072 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3073 full_duplex = 1;
3074 else
3075 half_duplex = 1;
3078 if (auto_speed) {
3079 speed_10 = 1;
3080 speed_100 = 1;
3081 speed_1000 = 1;
3082 } else {
3083 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3084 speed_1000 = 1;
3085 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3086 speed_100 = 1;
3087 else
3088 speed_10 = 1;
3091 if (speed_10 & half_duplex)
3092 ecmd->advertising |= ADVERTISED_10baseT_Half;
3093 if (speed_10 & full_duplex)
3094 ecmd->advertising |= ADVERTISED_10baseT_Full;
3095 if (speed_100 & half_duplex)
3096 ecmd->advertising |= ADVERTISED_100baseT_Half;
3097 if (speed_100 & full_duplex)
3098 ecmd->advertising |= ADVERTISED_100baseT_Full;
3099 if (speed_1000)
3100 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3104 ecmd->port = PORT_TP;
3105 ecmd->phy_address = ethernet_phy_get(port_num);
3107 ecmd->transceiver = XCVR_EXTERNAL;
3109 if (netif_carrier_ok(netdev)) {
3110 if (mode_10_bit)
3111 ecmd->speed = SPEED_10;
3112 else {
3113 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3114 ecmd->speed = SPEED_1000;
3115 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3116 ecmd->speed = SPEED_100;
3117 else
3118 ecmd->speed = SPEED_10;
3121 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3122 ecmd->duplex = DUPLEX_FULL;
3123 else
3124 ecmd->duplex = DUPLEX_HALF;
3125 } else {
3126 ecmd->speed = -1;
3127 ecmd->duplex = -1;
3130 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3131 return 0;
3134 static void
3135 mv643xx_get_drvinfo(struct net_device *netdev,
3136 struct ethtool_drvinfo *drvinfo)
3138 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3139 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3140 strncpy(drvinfo->fw_version, "N/A", 32);
3141 strncpy(drvinfo->bus_info, "mv643xx", 32);
3142 drvinfo->n_stats = MV643XX_STATS_LEN;
3145 static int
3146 mv643xx_get_stats_count(struct net_device *netdev)
3148 return MV643XX_STATS_LEN;
3151 static void
3152 mv643xx_get_ethtool_stats(struct net_device *netdev,
3153 struct ethtool_stats *stats, uint64_t *data)
3155 struct mv643xx_private *mp = netdev->priv;
3156 int i;
3158 eth_update_mib_counters(mp);
3160 for(i = 0; i < MV643XX_STATS_LEN; i++) {
3161 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3162 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3163 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3167 static void
3168 mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
3170 int i;
3172 switch(stringset) {
3173 case ETH_SS_STATS:
3174 for (i=0; i < MV643XX_STATS_LEN; i++) {
3175 memcpy(data + i * ETH_GSTRING_LEN,
3176 mv643xx_gstrings_stats[i].stat_string,
3177 ETH_GSTRING_LEN);
3179 break;
3183 static struct ethtool_ops mv643xx_ethtool_ops = {
3184 .get_settings = mv643xx_get_settings,
3185 .get_drvinfo = mv643xx_get_drvinfo,
3186 .get_link = ethtool_op_get_link,
3187 .get_sg = ethtool_op_get_sg,
3188 .set_sg = ethtool_op_set_sg,
3189 .get_strings = mv643xx_get_strings,
3190 .get_stats_count = mv643xx_get_stats_count,
3191 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3194 /************* End ethtool support *************************/