arch/x86_64/kernel/i8259.c

   1 #include <linux/linkage.h>
   2 #include <linux/config.h>
   3 #include <linux/errno.h>
   4 #include <linux/signal.h>
   5 #include <linux/sched.h>
   6 #include <linux/ioport.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/timex.h>
   9 #include <linux/slab.h>
  10 #include <linux/random.h>
  11 #include <linux/smp_lock.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/sysdev.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/acpi.h>
  18 #include <asm/atomic.h>
  19 #include <asm/system.h>
  20 #include <asm/io.h>
  21 #include <asm/irq.h>
  22 #include <asm/hw_irq.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/delay.h>
  25 #include <asm/desc.h>
  26 #include <asm/apic.h>
  27
  28 #include <linux/irq.h>
  29
  30 /*
  31  * Common place to define all x86 IRQ vectors
  32  *
  33  * This builds up the IRQ handler stubs using some ugly macros in irq.h
  34  *
  35  * These macros create the low-level assembly IRQ routines that save
  36  * register context and call do_IRQ(). do_IRQ() then does all the
  37  * operations that are needed to keep the AT (or SMP IOAPIC)
  38  * interrupt-controller happy.
  39  */
  40
  41 #define BI(x,y) \
  42         BUILD_IRQ(x##y)
  43
  44 #define BUILD_16_IRQS(x) \
  45         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  46         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  47         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  48         BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  49
  50 #define BUILD_14_IRQS(x) \
  51         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  52         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  53         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  54         BI(x,c) BI(x,d)
  55
  56 /*
  57  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  58  * (these are usually mapped to vectors 0x20-0x2f)
  59  */
  60 BUILD_16_IRQS(0x0)
  61
  62 #ifdef CONFIG_X86_LOCAL_APIC
  63 /*
  64  * The IO-APIC gives us many more interrupt sources. Most of these
  65  * are unused but an SMP system is supposed to have enough memory ...
  66  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  67  * across the spectrum, so we really want to be prepared to get all
  68  * of these. Plus, more powerful systems might have more than 64
  69  * IO-APIC registers.
  70  *
  71  * (these are usually mapped into the 0x30-0xff vector range)
  72  */
  73                    BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  74 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  75 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  76 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
  77
  78 #ifdef CONFIG_PCI_MSI
  79         BUILD_14_IRQS(0xe)
  80 #endif
  81
  82 #endif
  83
  84 #undef BUILD_16_IRQS
  85 #undef BUILD_14_IRQS
  86 #undef BI
  87
  88
  89 #define IRQ(x,y) \
  90         IRQ##x##y##_interrupt
  91
  92 #define IRQLIST_16(x) \
  93         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  94         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  95         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  96         IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
  97
  98 #define IRQLIST_14(x) \
  99         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
 100         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
 101         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
 102         IRQ(x,c), IRQ(x,d)
 103
 104 void (*interrupt[NR_IRQS])(void) = {
 105         IRQLIST_16(0x0),
 106
 107 #ifdef CONFIG_X86_IO_APIC
 108                          IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
 109         IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
 110         IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
 111         IRQLIST_16(0xc), IRQLIST_16(0xd)
 112
 113 #ifdef CONFIG_PCI_MSI
 114         , IRQLIST_14(0xe)
 115 #endif
 116
 117 #endif
 118 };
 119
 120 #undef IRQ
 121 #undef IRQLIST_16
 122 #undef IRQLIST_14
 123
 124 /*
 125  * This is the 'legacy' 8259A Programmable Interrupt Controller,
 126  * present in the majority of PC/AT boxes.
 127  * plus some generic x86 specific things if generic specifics makes
 128  * any sense at all.
 129  * this file should become arch/i386/kernel/irq.c when the old irq.c
 130  * moves to arch independent land
 131  */
 132
 133 DEFINE_SPINLOCK(i8259A_lock);
 134
 135 static void end_8259A_irq (unsigned int irq)
 136 {
 137         if (irq > 256) {
 138                 char var;
 139                 printk("return %p stack %p ti %p\n", __builtin_return_address(0), &var, current->thread_info);
 140
 141                 BUG();
 142         }
 143
 144         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
 145             irq_desc[irq].action)
 146                 enable_8259A_irq(irq);
 147 }
 148
 149 #define shutdown_8259A_irq      disable_8259A_irq
 150
 151 static void mask_and_ack_8259A(unsigned int);
 152
 153 static unsigned int startup_8259A_irq(unsigned int irq)
 154 {
 155         enable_8259A_irq(irq);
 156         return 0; /* never anything pending */
 157 }
 158
 159 static struct hw_interrupt_type i8259A_irq_type = {
 160         .typename = "XT-PIC",
 161         .startup = startup_8259A_irq,
 162         .shutdown = shutdown_8259A_irq,
 163         .enable = enable_8259A_irq,
 164         .disable = disable_8259A_irq,
 165         .ack = mask_and_ack_8259A,
 166         .end = end_8259A_irq,
 167 };
 168
 169 /*
 170  * 8259A PIC functions to handle ISA devices:
 171  */
 172
 173 /*
 174  * This contains the irq mask for both 8259A irq controllers,
 175  */
 176 static unsigned int cached_irq_mask = 0xffff;
 177
 178 #define __byte(x,y)     (((unsigned char *)&(y))[x])
 179 #define cached_21       (__byte(0,cached_irq_mask))
 180 #define cached_A1       (__byte(1,cached_irq_mask))
 181
 182 /*
 183  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 184  * boards the timer interrupt is not really connected to any IO-APIC pin,
 185  * it's fed to the master 8259A's IR0 line only.
 186  *
 187  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 188  * this 'mixed mode' IRQ handling costs nothing because it's only used
 189  * at IRQ setup time.
 190  */
 191 unsigned long io_apic_irqs;
 192
 193 void disable_8259A_irq(unsigned int irq)
 194 {
 195         unsigned int mask = 1 << irq;
 196         unsigned long flags;
 197
 198         spin_lock_irqsave(&i8259A_lock, flags);
 199         cached_irq_mask |= mask;
 200         if (irq & 8)
 201                 outb(cached_A1,0xA1);
 202         else
 203                 outb(cached_21,0x21);
 204         spin_unlock_irqrestore(&i8259A_lock, flags);
 205 }
 206
 207 void enable_8259A_irq(unsigned int irq)
 208 {
 209         unsigned int mask = ~(1 << irq);
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&i8259A_lock, flags);
 213         cached_irq_mask &= mask;
 214         if (irq & 8)
 215                 outb(cached_A1,0xA1);
 216         else
 217                 outb(cached_21,0x21);
 218         spin_unlock_irqrestore(&i8259A_lock, flags);
 219 }
 220
 221 int i8259A_irq_pending(unsigned int irq)
 222 {
 223         unsigned int mask = 1<<irq;
 224         unsigned long flags;
 225         int ret;
 226
 227         spin_lock_irqsave(&i8259A_lock, flags);
 228         if (irq < 8)
 229                 ret = inb(0x20) & mask;
 230         else
 231                 ret = inb(0xA0) & (mask >> 8);
 232         spin_unlock_irqrestore(&i8259A_lock, flags);
 233
 234         return ret;
 235 }
 236
 237 void make_8259A_irq(unsigned int irq)
 238 {
 239         disable_irq_nosync(irq);
 240         io_apic_irqs &= ~(1<<irq);
 241         irq_desc[irq].handler = &i8259A_irq_type;
 242         enable_irq(irq);
 243 }
 244
 245 /*
 246  * This function assumes to be called rarely. Switching between
 247  * 8259A registers is slow.
 248  * This has to be protected by the irq controller spinlock
 249  * before being called.
 250  */
 251 static inline int i8259A_irq_real(unsigned int irq)
 252 {
 253         int value;
 254         int irqmask = 1<<irq;
 255
 256         if (irq < 8) {
 257                 outb(0x0B,0x20);                /* ISR register */
 258                 value = inb(0x20) & irqmask;
 259                 outb(0x0A,0x20);                /* back to the IRR register */
 260                 return value;
 261         }
 262         outb(0x0B,0xA0);                /* ISR register */
 263         value = inb(0xA0) & (irqmask >> 8);
 264         outb(0x0A,0xA0);                /* back to the IRR register */
 265         return value;
 266 }
 267
 268 /*
 269  * Careful! The 8259A is a fragile beast, it pretty
 270  * much _has_ to be done exactly like this (mask it
 271  * first, _then_ send the EOI, and the order of EOI
 272  * to the two 8259s is important!
 273  */
 274 static void mask_and_ack_8259A(unsigned int irq)
 275 {
 276         unsigned int irqmask = 1 << irq;
 277         unsigned long flags;
 278
 279         spin_lock_irqsave(&i8259A_lock, flags);
 280         /*
 281          * Lightweight spurious IRQ detection. We do not want
 282          * to overdo spurious IRQ handling - it's usually a sign
 283          * of hardware problems, so we only do the checks we can
 284          * do without slowing down good hardware unnecesserily.
 285          *
 286          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 287          * usually resulting from the 8259A-1|2 PICs) occur
 288          * even if the IRQ is masked in the 8259A. Thus we
 289          * can check spurious 8259A IRQs without doing the
 290          * quite slow i8259A_irq_real() call for every IRQ.
 291          * This does not cover 100% of spurious interrupts,
 292          * but should be enough to warn the user that there
 293          * is something bad going on ...
 294          */
 295         if (cached_irq_mask & irqmask)
 296                 goto spurious_8259A_irq;
 297         cached_irq_mask |= irqmask;
 298
 299 handle_real_irq:
 300         if (irq & 8) {
 301                 inb(0xA1);              /* DUMMY - (do we need this?) */
 302                 outb(cached_A1,0xA1);
 303                 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
 304                 outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
 305         } else {
 306                 inb(0x21);              /* DUMMY - (do we need this?) */
 307                 outb(cached_21,0x21);
 308                 outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
 309         }
 310         spin_unlock_irqrestore(&i8259A_lock, flags);
 311         return;
 312
 313 spurious_8259A_irq:
 314         /*
 315          * this is the slow path - should happen rarely.
 316          */
 317         if (i8259A_irq_real(irq))
 318                 /*
 319                  * oops, the IRQ _is_ in service according to the
 320                  * 8259A - not spurious, go handle it.
 321                  */
 322                 goto handle_real_irq;
 323
 324         {
 325                 static int spurious_irq_mask;
 326                 /*
 327                  * At this point we can be sure the IRQ is spurious,
 328                  * lets ACK and report it. [once per IRQ]
 329                  */
 330                 if (!(spurious_irq_mask & irqmask)) {
 331                         printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
 332                         spurious_irq_mask |= irqmask;
 333                 }
 334                 atomic_inc(&irq_err_count);
 335                 /*
 336                  * Theoretically we do not have to handle this IRQ,
 337                  * but in Linux this does not cause problems and is
 338                  * simpler for us.
 339                  */
 340                 goto handle_real_irq;
 341         }
 342 }
 343
 344 void init_8259A(int auto_eoi)
 345 {
 346         unsigned long flags;
 347
 348         spin_lock_irqsave(&i8259A_lock, flags);
 349
 350         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 351         outb(0xff, 0xA1);       /* mask all of 8259A-2 */
 352
 353         /*
 354          * outb_p - this has to work on a wide range of PC hardware.
 355          */
 356         outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
 357         outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
 358         outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
 359         if (auto_eoi)
 360                 outb_p(0x03, 0x21);     /* master does Auto EOI */
 361         else
 362                 outb_p(0x01, 0x21);     /* master expects normal EOI */
 363
 364         outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
 365         outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
 366         outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
 367         outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
 368                                     is to be investigated) */
 369
 370         if (auto_eoi)
 371                 /*
 372                  * in AEOI mode we just have to mask the interrupt
 373                  * when acking.
 374                  */
 375                 i8259A_irq_type.ack = disable_8259A_irq;
 376         else
 377                 i8259A_irq_type.ack = mask_and_ack_8259A;
 378
 379         udelay(100);            /* wait for 8259A to initialize */
 380
 381         outb(cached_21, 0x21);  /* restore master IRQ mask */
 382         outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
 383
 384         spin_unlock_irqrestore(&i8259A_lock, flags);
 385 }
 386
 387 static char irq_trigger[2];
 388 /**
 389  * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 390  */
 391 static void restore_ELCR(char *trigger)
 392 {
 393         outb(trigger[0], 0x4d0);
 394         outb(trigger[1], 0x4d1);
 395 }
 396
 397 static void save_ELCR(char *trigger)
 398 {
 399         /* IRQ 0,1,2,8,13 are marked as reserved */
 400         trigger[0] = inb(0x4d0) & 0xF8;
 401         trigger[1] = inb(0x4d1) & 0xDE;
 402 }
 403
 404 static int i8259A_resume(struct sys_device *dev)
 405 {
 406         init_8259A(0);
 407         restore_ELCR(irq_trigger);
 408         return 0;
 409 }
 410
 411 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
 412 {
 413         save_ELCR(irq_trigger);
 414         return 0;
 415 }
 416
 417 static struct sysdev_class i8259_sysdev_class = {
 418         set_kset_name("i8259"),
 419         .suspend = i8259A_suspend,
 420         .resume = i8259A_resume,
 421 };
 422
 423 static struct sys_device device_i8259A = {
 424         .id     = 0,
 425         .cls    = &i8259_sysdev_class,
 426 };
 427
 428 static int __init i8259A_init_sysfs(void)
 429 {
 430         int error = sysdev_class_register(&i8259_sysdev_class);
 431         if (!error)
 432                 error = sysdev_register(&device_i8259A);
 433         return error;
 434 }
 435
 436 device_initcall(i8259A_init_sysfs);
 437
 438 /*
 439  * IRQ2 is cascade interrupt to second interrupt controller
 440  */
 441
 442 static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 443
 444 void __init init_ISA_irqs (void)
 445 {
 446         int i;
 447
 448 #ifdef CONFIG_X86_LOCAL_APIC
 449         init_bsp_APIC();
 450 #endif
 451         init_8259A(0);
 452
 453         for (i = 0; i < NR_IRQS; i++) {
 454                 irq_desc[i].status = IRQ_DISABLED;
 455                 irq_desc[i].action = NULL;
 456                 irq_desc[i].depth = 1;
 457
 458                 if (i < 16) {
 459                         /*
 460                          * 16 old-style INTA-cycle interrupts:
 461                          */
 462                         irq_desc[i].handler = &i8259A_irq_type;
 463                 } else {
 464                         /*
 465                          * 'high' PCI IRQs filled in on demand
 466                          */
 467                         irq_desc[i].handler = &no_irq_type;
 468                 }
 469         }
 470 }
 471
 472 void apic_timer_interrupt(void);
 473 void spurious_interrupt(void);
 474 void error_interrupt(void);
 475 void reschedule_interrupt(void);
 476 void call_function_interrupt(void);
 477 void invalidate_interrupt(void);
 478 void thermal_interrupt(void);
 479 void i8254_timer_resume(void);
 480
 481 static void setup_timer(void)
 482 {
 483         outb_p(0x34,0x43);              /* binary, mode 2, LSB/MSB, ch 0 */
 484         udelay(10);
 485         outb_p(LATCH & 0xff , 0x40);    /* LSB */
 486         udelay(10);
 487         outb(LATCH >> 8 , 0x40);        /* MSB */
 488 }
 489
 490 static int timer_resume(struct sys_device *dev)
 491 {
 492         setup_timer();
 493         return 0;
 494 }
 495
 496 void i8254_timer_resume(void)
 497 {
 498         setup_timer();
 499 }
 500
 501 static struct sysdev_class timer_sysclass = {
 502         set_kset_name("timer"),
 503         .resume         = timer_resume,
 504 };
 505
 506 static struct sys_device device_timer = {
 507         .id             = 0,
 508         .cls            = &timer_sysclass,
 509 };
 510
 511 static int __init init_timer_sysfs(void)
 512 {
 513         int error = sysdev_class_register(&timer_sysclass);
 514         if (!error)
 515                 error = sysdev_register(&device_timer);
 516         return error;
 517 }
 518
 519 device_initcall(init_timer_sysfs);
 520
 521 void __init init_IRQ(void)
 522 {
 523         int i;
 524
 525         init_ISA_irqs();
 526         /*
 527          * Cover the whole vector space, no vector can escape
 528          * us. (some of these will be overridden and become
 529          * 'special' SMP interrupts)
 530          */
 531         for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
 532                 int vector = FIRST_EXTERNAL_VECTOR + i;
 533                 if (i >= NR_IRQS)
 534                         break;
 535                 if (vector != IA32_SYSCALL_VECTOR && vector != KDB_VECTOR) {
 536                         set_intr_gate(vector, interrupt[i]);
 537         }
 538         }
 539
 540 #ifdef CONFIG_SMP
 541         /*
 542          * IRQ0 must be given a fixed assignment and initialized,
 543          * because it's used before the IO-APIC is set up.
 544          */
 545         set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
 546
 547         /*
 548          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 549          * IPI, driven by wakeup.
 550          */
 551         set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 552
 553         /* IPI for invalidation */
 554         set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
 555
 556         /* IPI for generic function call */
 557         set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 558 #endif
 559         set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 560
 561 #ifdef CONFIG_X86_LOCAL_APIC
 562         /* self generated IPI for local APIC timer */
 563         set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 564
 565         /* IPI vectors for APIC spurious and error interrupts */
 566         set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 567         set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 568 #endif
 569
 570         /*
 571          * Set the clock to HZ Hz, we already have a valid
 572          * vector now:
 573          */
 574         setup_timer();
 575
 576         if (!acpi_ioapic)
 577                 setup_irq(2, &irq2);
 578 }