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tgafb: fix an out-of-range shift in mono imageblit
[linux-2.6/zen-sources.git] / drivers / video / tgafb.c
blob5539f4d9cb7438a668c431eba8b76d175e1eeab8
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 * Copyright (C) 2006, 2007 Maciej W. Rozycki
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15 #include <linux/bitrev.h>
16 #include <linux/compiler.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/errno.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/selection.h>
28 #include <linux/slab.h>
29 #include <linux/string.h>
30 #include <linux/tc.h>
31
32 #include <asm/io.h>
33
34 #include <video/tgafb.h>
35
36 #ifdef CONFIG_PCI
37 #define TGA_BUS_PCI(dev) (dev->bus == &pci_bus_type)
38 #else
39 #define TGA_BUS_PCI(dev) 0
40 #endif
41
42 #ifdef CONFIG_TC
43 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
44 #else
45 #define TGA_BUS_TC(dev) 0
46 #endif
47
48 /*
49 * Local functions.
50 */
51
52 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
53 static int tgafb_set_par(struct fb_info *);
54 static void tgafb_set_pll(struct tga_par *, int);
55 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
56 unsigned, struct fb_info *);
57 static int tgafb_blank(int, struct fb_info *);
58 static void tgafb_init_fix(struct fb_info *);
59
60 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
61 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
62 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
63 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
64
65 static int __devinit tgafb_register(struct device *dev);
66 static void __devexit tgafb_unregister(struct device *dev);
67
68 static const char *mode_option;
69 static const char *mode_option_pci = "640x480@60";
70 static const char *mode_option_tc = "1280x1024@72";
71
72
73 static struct pci_driver tgafb_pci_driver;
74 static struct tc_driver tgafb_tc_driver;
75
76 /*
77 * Frame buffer operations
78 */
79
80 static struct fb_ops tgafb_ops = {
81 .owner = THIS_MODULE,
82 .fb_check_var = tgafb_check_var,
83 .fb_set_par = tgafb_set_par,
84 .fb_setcolreg = tgafb_setcolreg,
85 .fb_blank = tgafb_blank,
86 .fb_pan_display = tgafb_pan_display,
87 .fb_fillrect = tgafb_fillrect,
88 .fb_copyarea = tgafb_copyarea,
89 .fb_imageblit = tgafb_imageblit,
90 };
91
92
93 #ifdef CONFIG_PCI
94 /*
95 * PCI registration operations
96 */
97 static int __devinit tgafb_pci_register(struct pci_dev *,
98 const struct pci_device_id *);
99 static void __devexit tgafb_pci_unregister(struct pci_dev *);
100
101 static struct pci_device_id const tgafb_pci_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
103 { }
104 };
105 MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
106
107 static struct pci_driver tgafb_pci_driver = {
108 .name = "tgafb",
109 .id_table = tgafb_pci_table,
110 .probe = tgafb_pci_register,
111 .remove = __devexit_p(tgafb_pci_unregister),
112 };
113
114 static int __devinit
115 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
116 {
117 return tgafb_register(&pdev->dev);
118 }
119
120 static void __devexit
121 tgafb_pci_unregister(struct pci_dev *pdev)
122 {
123 tgafb_unregister(&pdev->dev);
124 }
125 #endif /* CONFIG_PCI */
126
127 #ifdef CONFIG_TC
128 /*
129 * TC registration operations
130 */
131 static int __devinit tgafb_tc_register(struct device *);
132 static int __devexit tgafb_tc_unregister(struct device *);
133
134 static struct tc_device_id const tgafb_tc_table[] = {
135 { "DEC ", "PMAGD-AA" },
136 { "DEC ", "PMAGD " },
137 { }
138 };
139 MODULE_DEVICE_TABLE(tc, tgafb_tc_table);
140
141 static struct tc_driver tgafb_tc_driver = {
142 .id_table = tgafb_tc_table,
143 .driver = {
144 .name = "tgafb",
145 .bus = &tc_bus_type,
146 .probe = tgafb_tc_register,
147 .remove = __devexit_p(tgafb_tc_unregister),
148 },
149 };
150
151 static int __devinit
152 tgafb_tc_register(struct device *dev)
153 {
154 int status = tgafb_register(dev);
155 if (!status)
156 get_device(dev);
157 return status;
158 }
159
160 static int __devexit
161 tgafb_tc_unregister(struct device *dev)
162 {
163 put_device(dev);
164 tgafb_unregister(dev);
165 return 0;
166 }
167 #endif /* CONFIG_TC */
168
169
170 /**
171 * tgafb_check_var - Optional function. Validates a var passed in.
172 * @var: frame buffer variable screen structure
173 * @info: frame buffer structure that represents a single frame buffer
174 */
175 static int
176 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
177 {
178 struct tga_par *par = (struct tga_par *)info->par;
179
180 if (par->tga_type == TGA_TYPE_8PLANE) {
181 if (var->bits_per_pixel != 8)
182 return -EINVAL;
183 } else {
184 if (var->bits_per_pixel != 32)
185 return -EINVAL;
186 }
187 var->red.length = var->green.length = var->blue.length = 8;
188 if (var->bits_per_pixel == 32) {
189 var->red.offset = 16;
190 var->green.offset = 8;
191 var->blue.offset = 0;
192 }
193
194 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
195 return -EINVAL;
196 if (var->nonstd)
197 return -EINVAL;
198 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
199 return -EINVAL;
200 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
201 return -EINVAL;
202
203 /* Some of the acceleration routines assume the line width is
204 a multiple of 64 bytes. */
205 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
206 return -EINVAL;
207
208 return 0;
209 }
210
211 /**
212 * tgafb_set_par - Optional function. Alters the hardware state.
213 * @info: frame buffer structure that represents a single frame buffer
214 */
215 static int
216 tgafb_set_par(struct fb_info *info)
217 {
218 static unsigned int const deep_presets[4] = {
219 0x00004000,
220 0x0000440d,
221 0xffffffff,
222 0x0000441d
223 };
224 static unsigned int const rasterop_presets[4] = {
225 0x00000003,
226 0x00000303,
227 0xffffffff,
228 0x00000303
229 };
230 static unsigned int const mode_presets[4] = {
231 0x00000000,
232 0x00000300,
233 0xffffffff,
234 0x00000300
235 };
236 static unsigned int const base_addr_presets[4] = {
237 0x00000000,
238 0x00000001,
239 0xffffffff,
240 0x00000001
241 };
242
243 struct tga_par *par = (struct tga_par *) info->par;
244 int tga_bus_pci = TGA_BUS_PCI(par->dev);
245 int tga_bus_tc = TGA_BUS_TC(par->dev);
246 u32 htimings, vtimings, pll_freq;
247 u8 tga_type;
248 int i;
249
250 /* Encode video timings. */
251 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
252 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
253 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
254 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
255 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
256 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
257 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
258 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
259 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
260
261 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
262 htimings |= TGA_HORIZ_POLARITY;
263 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
264 vtimings |= TGA_VERT_POLARITY;
265
266 par->htimings = htimings;
267 par->vtimings = vtimings;
268
269 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
270
271 /* Store other useful values in par. */
272 par->xres = info->var.xres;
273 par->yres = info->var.yres;
274 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
275 par->bits_per_pixel = info->var.bits_per_pixel;
276
277 tga_type = par->tga_type;
278
279 /* First, disable video. */
280 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
281
282 /* Write the DEEP register. */
283 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
284 continue;
285 mb();
286 TGA_WRITE_REG(par, deep_presets[tga_type] |
287 (par->sync_on_green ? 0x0 : 0x00010000),
288 TGA_DEEP_REG);
289 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
290 continue;
291 mb();
292
293 /* Write some more registers. */
294 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
295 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
296 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
297
298 /* Calculate & write the PLL. */
299 tgafb_set_pll(par, pll_freq);
300
301 /* Write some more registers. */
302 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
303 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
304
305 /* Init video timing regs. */
306 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
307 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
308
309 /* Initalise RAMDAC. */
310 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
311
312 /* Init BT485 RAMDAC registers. */
313 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
314 BT485_CMD_0);
315 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
316 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
317 BT485_WRITE(par, 0x40, BT485_CMD_1);
318 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
319 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
320
321 /* Fill palette registers. */
322 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
323 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
324
325 for (i = 0; i < 256 * 3; i += 4) {
326 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
327 TGA_RAMDAC_REG);
328 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
329 TGA_RAMDAC_REG);
330 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
331 TGA_RAMDAC_REG);
332 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
333 TGA_RAMDAC_REG);
334 }
335
336 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
337
338 /* Init BT459 RAMDAC registers. */
339 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
340 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
341 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
342 (par->sync_on_green ? 0xc0 : 0x40));
343
344 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
345
346 /* Fill the palette. */
347 BT459_LOAD_ADDR(par, 0x0000);
348 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
349
350 for (i = 0; i < 256 * 3; i += 4) {
351 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
352 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
353 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
354 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
355 }
356
357 } else { /* 24-plane or 24plusZ */
358
359 /* Init BT463 RAMDAC registers. */
360 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
361 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
362 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
363 (par->sync_on_green ? 0xc0 : 0x40));
364
365 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
366 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
367 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
368 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
369
370 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
371 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
372 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
373 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
374
375 /* Fill the palette. */
376 BT463_LOAD_ADDR(par, 0x0000);
377 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
378
379 #ifdef CONFIG_HW_CONSOLE
380 for (i = 0; i < 16; i++) {
381 int j = color_table[i];
382
383 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
384 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
385 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
386 }
387 for (i = 0; i < 512 * 3; i += 4) {
388 #else
389 for (i = 0; i < 528 * 3; i += 4) {
390 #endif
391 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
392 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
393 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
394 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
395 }
396
397 /* Fill window type table after start of vertical retrace. */
398 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
399 continue;
400 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
401 mb();
402 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
403 continue;
404 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
405
406 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
407 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
408
409 for (i = 0; i < 16; i++) {
410 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
411 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
412 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
413 }
414
415 }
416
417 /* Finally, enable video scan (and pray for the monitor... :-) */
418 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
419
420 return 0;
421 }
422
423 #define DIFFCHECK(X) \
424 do { \
425 if (m <= 0x3f) { \
426 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
427 if (delta < 0) \
428 delta = -delta; \
429 if (delta < min_diff) \
430 min_diff = delta, vm = m, va = a, vr = r; \
431 } \
432 } while (0)
433
434 static void
435 tgafb_set_pll(struct tga_par *par, int f)
436 {
437 int n, shift, base, min_diff, target;
438 int r,a,m,vm = 34, va = 1, vr = 30;
439
440 for (r = 0 ; r < 12 ; r++)
441 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
442
443 if (f > TGA_PLL_MAX_FREQ)
444 f = TGA_PLL_MAX_FREQ;
445
446 if (f >= TGA_PLL_MAX_FREQ / 2)
447 shift = 0;
448 else if (f >= TGA_PLL_MAX_FREQ / 4)
449 shift = 1;
450 else
451 shift = 2;
452
453 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
454 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
455
456 for (r = 0 ; r < 10 ; r++)
457 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
458
459 if (f <= 120000) {
460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
461 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
462 }
463 else if (f <= 200000) {
464 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
465 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
466 }
467 else {
468 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
469 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
470 }
471
472 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
473 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
474 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
475 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
476 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
477 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
478
479 target = (f << shift) / TGA_PLL_BASE_FREQ;
480 min_diff = TGA_PLL_MAX_FREQ;
481
482 r = 7 / target;
483 if (!r) r = 1;
484
485 base = target * r;
486 while (base < 449) {
487 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
488 m = ((n + 3) / 7) - 1;
489 a = 0;
490 DIFFCHECK((m + 1) * 7);
491 m++;
492 DIFFCHECK((m + 1) * 7);
493 m = (n / 6) - 1;
494 if ((a = n % 6))
495 DIFFCHECK(n);
496 }
497 r++;
498 base += target;
499 }
500
501 vr--;
502
503 for (r = 0; r < 8; r++)
504 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
505 for (r = 0; r < 8 ; r++)
506 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
507 for (r = 0; r < 7 ; r++)
508 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
509 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
510 }
511
512
513 /**
514 * tgafb_setcolreg - Optional function. Sets a color register.
515 * @regno: boolean, 0 copy local, 1 get_user() function
516 * @red: frame buffer colormap structure
517 * @green: The green value which can be up to 16 bits wide
518 * @blue: The blue value which can be up to 16 bits wide.
519 * @transp: If supported the alpha value which can be up to 16 bits wide.
520 * @info: frame buffer info structure
521 */
522 static int
523 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
524 unsigned transp, struct fb_info *info)
525 {
526 struct tga_par *par = (struct tga_par *) info->par;
527 int tga_bus_pci = TGA_BUS_PCI(par->dev);
528 int tga_bus_tc = TGA_BUS_TC(par->dev);
529
530 if (regno > 255)
531 return 1;
532 red >>= 8;
533 green >>= 8;
534 blue >>= 8;
535
536 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
537 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
538 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
539 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
540 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
541 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
542 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
543 BT459_LOAD_ADDR(par, regno);
544 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
545 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
546 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
547 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
548 } else {
549 if (regno < 16) {
550 u32 value = (regno << 16) | (regno << 8) | regno;
551 ((u32 *)info->pseudo_palette)[regno] = value;
552 }
553 BT463_LOAD_ADDR(par, regno);
554 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
555 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
556 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
557 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
558 }
559
560 return 0;
561 }
562
563
564 /**
565 * tgafb_blank - Optional function. Blanks the display.
566 * @blank_mode: the blank mode we want.
567 * @info: frame buffer structure that represents a single frame buffer
568 */
569 static int
570 tgafb_blank(int blank, struct fb_info *info)
571 {
572 struct tga_par *par = (struct tga_par *) info->par;
573 u32 vhcr, vvcr, vvvr;
574 unsigned long flags;
575
576 local_irq_save(flags);
577
578 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
579 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
580 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
581 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
582
583 switch (blank) {
584 case FB_BLANK_UNBLANK: /* Unblanking */
585 if (par->vesa_blanked) {
586 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
587 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
588 par->vesa_blanked = 0;
589 }
590 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
591 break;
592
593 case FB_BLANK_NORMAL: /* Normal blanking */
594 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
595 TGA_VALID_REG);
596 break;
597
598 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
599 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
600 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
601 par->vesa_blanked = 1;
602 break;
603
604 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
605 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
606 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
607 par->vesa_blanked = 1;
608 break;
609
610 case FB_BLANK_POWERDOWN: /* Poweroff */
611 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
612 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
613 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
614 par->vesa_blanked = 1;
615 break;
616 }
617
618 local_irq_restore(flags);
619 return 0;
620 }
621
622
623 /*
624 * Acceleration.
625 */
626
627 static void
628 tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
629 {
630 struct tga_par *par = (struct tga_par *) info->par;
631 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
632 unsigned long rincr, line_length, shift, pos, is8bpp;
633 unsigned long i, j;
634 const unsigned char *data;
635 void __iomem *regs_base;
636 void __iomem *fb_base;
637
638 is8bpp = info->var.bits_per_pixel == 8;
639
640 /* For copies that aren't pixel expansion, there's little we
641 can do better than the generic code. */
642 /* ??? There is a DMA write mode; I wonder if that could be
643 made to pull the data from the image buffer... */
644 if (image->depth > 1) {
645 cfb_imageblit(info, image);
646 return;
647 }
648
649 dx = image->dx;
650 dy = image->dy;
651 width = image->width;
652 height = image->height;
653 vxres = info->var.xres_virtual;
654 vyres = info->var.yres_virtual;
655 line_length = info->fix.line_length;
656 rincr = (width + 7) / 8;
657
658 /* A shift below cannot cope with. */
659 if (unlikely(width == 0))
660 return;
661 /* Crop the image to the screen. */
662 if (dx > vxres || dy > vyres)
663 return;
664 if (dx + width > vxres)
665 width = vxres - dx;
666 if (dy + height > vyres)
667 height = vyres - dy;
668
669 regs_base = par->tga_regs_base;
670 fb_base = par->tga_fb_base;
671
672 /* Expand the color values to fill 32-bits. */
673 /* ??? Would be nice to notice colour changes elsewhere, so
674 that we can do this only when necessary. */
675 fgcolor = image->fg_color;
676 bgcolor = image->bg_color;
677 if (is8bpp) {
678 fgcolor |= fgcolor << 8;
679 fgcolor |= fgcolor << 16;
680 bgcolor |= bgcolor << 8;
681 bgcolor |= bgcolor << 16;
682 } else {
683 if (fgcolor < 16)
684 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
685 if (bgcolor < 16)
686 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
687 }
688 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
689 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
690
691 /* Acquire proper alignment; set up the PIXELMASK register
692 so that we only write the proper character cell. */
693 pos = dy * line_length;
694 if (is8bpp) {
695 pos += dx;
696 shift = pos & 3;
697 pos &= -4;
698 } else {
699 pos += dx * 4;
700 shift = (pos & 7) >> 2;
701 pos &= -8;
702 }
703
704 data = (const unsigned char *) image->data;
705
706 /* Enable opaque stipple mode. */
707 __raw_writel((is8bpp
708 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
709 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
710 regs_base + TGA_MODE_REG);
711
712 if (width + shift <= 32) {
713 unsigned long bwidth;
714
715 /* Handle common case of imaging a single character, in
716 a font less than or 32 pixels wide. */
717
718 /* Avoid a shift by 32; width > 0 implied. */
719 pixelmask = (2ul << (width - 1)) - 1;
720 pixelmask <<= shift;
721 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
722 wmb();
723
724 bwidth = (width + 7) / 8;
725
726 for (i = 0; i < height; ++i) {
727 u32 mask = 0;
728
729 /* The image data is bit big endian; we need
730 little endian. */
731 for (j = 0; j < bwidth; ++j)
732 mask |= bitrev8(data[j]) << (j * 8);
733
734 __raw_writel(mask << shift, fb_base + pos);
735
736 pos += line_length;
737 data += rincr;
738 }
739 wmb();
740 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
741 } else if (shift == 0) {
742 unsigned long pos0 = pos;
743 const unsigned char *data0 = data;
744 unsigned long bincr = (is8bpp ? 8 : 8*4);
745 unsigned long bwidth;
746
747 /* Handle another common case in which accel_putcs
748 generates a large bitmap, which happens to be aligned.
749 Allow the tail to be misaligned. This case is
750 interesting because we've not got to hold partial
751 bytes across the words being written. */
752
753 wmb();
754
755 bwidth = (width / 8) & -4;
756 for (i = 0; i < height; ++i) {
757 for (j = 0; j < bwidth; j += 4) {
758 u32 mask = 0;
759 mask |= bitrev8(data[j+0]) << (0 * 8);
760 mask |= bitrev8(data[j+1]) << (1 * 8);
761 mask |= bitrev8(data[j+2]) << (2 * 8);
762 mask |= bitrev8(data[j+3]) << (3 * 8);
763 __raw_writel(mask, fb_base + pos + j*bincr);
764 }
765 pos += line_length;
766 data += rincr;
767 }
768 wmb();
769
770 pixelmask = (1ul << (width & 31)) - 1;
771 if (pixelmask) {
772 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
773 wmb();
774
775 pos = pos0 + bwidth*bincr;
776 data = data0 + bwidth;
777 bwidth = ((width & 31) + 7) / 8;
778
779 for (i = 0; i < height; ++i) {
780 u32 mask = 0;
781 for (j = 0; j < bwidth; ++j)
782 mask |= bitrev8(data[j]) << (j * 8);
783 __raw_writel(mask, fb_base + pos);
784 pos += line_length;
785 data += rincr;
786 }
787 wmb();
788 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
789 }
790 } else {
791 unsigned long pos0 = pos;
792 const unsigned char *data0 = data;
793 unsigned long bincr = (is8bpp ? 8 : 8*4);
794 unsigned long bwidth;
795
796 /* Finally, handle the generic case of misaligned start.
797 Here we split the write into 16-bit spans. This allows
798 us to use only one pixel mask, instead of four as would
799 be required by writing 24-bit spans. */
800
801 pixelmask = 0xffff << shift;
802 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
803 wmb();
804
805 bwidth = (width / 8) & -2;
806 for (i = 0; i < height; ++i) {
807 for (j = 0; j < bwidth; j += 2) {
808 u32 mask = 0;
809 mask |= bitrev8(data[j+0]) << (0 * 8);
810 mask |= bitrev8(data[j+1]) << (1 * 8);
811 mask <<= shift;
812 __raw_writel(mask, fb_base + pos + j*bincr);
813 }
814 pos += line_length;
815 data += rincr;
816 }
817 wmb();
818
819 pixelmask = ((1ul << (width & 15)) - 1) << shift;
820 if (pixelmask) {
821 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
822 wmb();
823
824 pos = pos0 + bwidth*bincr;
825 data = data0 + bwidth;
826 bwidth = (width & 15) > 8;
827
828 for (i = 0; i < height; ++i) {
829 u32 mask = bitrev8(data[0]);
830 if (bwidth)
831 mask |= bitrev8(data[1]) << 8;
832 mask <<= shift;
833 __raw_writel(mask, fb_base + pos);
834 pos += line_length;
835 data += rincr;
836 }
837 wmb();
838 }
839 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
840 }
841
842 /* Disable opaque stipple mode. */
843 __raw_writel((is8bpp
844 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
845 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
846 regs_base + TGA_MODE_REG);
847 }
848
849 static void
850 tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
851 {
852 struct tga_par *par = (struct tga_par *) info->par;
853 u32 color, dx, dy, width, height, vxres, vyres;
854 u32 *palette = ((u32 *)info->pseudo_palette);
855 unsigned long pos, line_length, i, j;
856 const unsigned char *data;
857 void __iomem *regs_base, *fb_base;
858
859 dx = image->dx;
860 dy = image->dy;
861 width = image->width;
862 height = image->height;
863 vxres = info->var.xres_virtual;
864 vyres = info->var.yres_virtual;
865 line_length = info->fix.line_length;
866
867 /* Crop the image to the screen. */
868 if (dx > vxres || dy > vyres)
869 return;
870 if (dx + width > vxres)
871 width = vxres - dx;
872 if (dy + height > vyres)
873 height = vyres - dy;
874
875 regs_base = par->tga_regs_base;
876 fb_base = par->tga_fb_base;
877
878 pos = dy * line_length + (dx * 4);
879 data = image->data;
880
881 /* Now copy the image, color_expanding via the palette. */
882 for (i = 0; i < height; i++) {
883 for (j = 0; j < width; j++) {
884 color = palette[*data++];
885 __raw_writel(color, fb_base + pos + j*4);
886 }
887 pos += line_length;
888 }
889 }
890
891 /**
892 * tgafb_imageblit - REQUIRED function. Can use generic routines if
893 * non acclerated hardware and packed pixel based.
894 * Copies a image from system memory to the screen.
895 *
896 * @info: frame buffer structure that represents a single frame buffer
897 * @image: structure defining the image.
898 */
899 static void
900 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
901 {
902 unsigned int is8bpp = info->var.bits_per_pixel == 8;
903
904 /* If a mono image, regardless of FB depth, go do it. */
905 if (image->depth == 1) {
906 tgafb_mono_imageblit(info, image);
907 return;
908 }
909
910 /* For copies that aren't pixel expansion, there's little we
911 can do better than the generic code. */
912 /* ??? There is a DMA write mode; I wonder if that could be
913 made to pull the data from the image buffer... */
914 if (image->depth == info->var.bits_per_pixel) {
915 cfb_imageblit(info, image);
916 return;
917 }
918
919 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
920 if (!is8bpp && image->depth == 8) {
921 tgafb_clut_imageblit(info, image);
922 return;
923 }
924
925 /* Silently return... */
926 }
927
928 /**
929 * tgafb_fillrect - REQUIRED function. Can use generic routines if
930 * non acclerated hardware and packed pixel based.
931 * Draws a rectangle on the screen.
932 *
933 * @info: frame buffer structure that represents a single frame buffer
934 * @rect: structure defining the rectagle and operation.
935 */
936 static void
937 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
938 {
939 struct tga_par *par = (struct tga_par *) info->par;
940 int is8bpp = info->var.bits_per_pixel == 8;
941 u32 dx, dy, width, height, vxres, vyres, color;
942 unsigned long pos, align, line_length, i, j;
943 void __iomem *regs_base;
944 void __iomem *fb_base;
945
946 dx = rect->dx;
947 dy = rect->dy;
948 width = rect->width;
949 height = rect->height;
950 vxres = info->var.xres_virtual;
951 vyres = info->var.yres_virtual;
952 line_length = info->fix.line_length;
953 regs_base = par->tga_regs_base;
954 fb_base = par->tga_fb_base;
955
956 /* Crop the rectangle to the screen. */
957 if (dx > vxres || dy > vyres || !width || !height)
958 return;
959 if (dx + width > vxres)
960 width = vxres - dx;
961 if (dy + height > vyres)
962 height = vyres - dy;
963
964 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
965
966 /* ??? We could implement ROP_XOR with opaque fill mode
967 and a RasterOp setting of GXxor, but as far as I can
968 tell, this mode is not actually used in the kernel.
969 Thus I am ignoring it for now. */
970 if (rect->rop != ROP_COPY) {
971 cfb_fillrect(info, rect);
972 return;
973 }
974
975 /* Expand the color value to fill 8 pixels. */
976 color = rect->color;
977 if (is8bpp) {
978 color |= color << 8;
979 color |= color << 16;
980 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
981 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
982 } else {
983 if (color < 16)
984 color = ((u32 *)info->pseudo_palette)[color];
985 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
986 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
987 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
988 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
989 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
990 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
991 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
992 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
993 }
994
995 /* The DATA register holds the fill mask for block fill mode.
996 Since we're not stippling, this is all ones. */
997 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
998
999 /* Enable block fill mode. */
1000 __raw_writel((is8bpp
1001 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
1002 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
1003 regs_base + TGA_MODE_REG);
1004 wmb();
1005
1006 /* We can fill 2k pixels per operation. Notice blocks that fit
1007 the width of the screen so that we can take advantage of this
1008 and fill more than one line per write. */
1009 if (width == line_length)
1010 width *= height, height = 1;
1011
1012 /* The write into the frame buffer must be aligned to 4 bytes,
1013 but we are allowed to encode the offset within the word in
1014 the data word written. */
1015 align = (pos & 3) << 16;
1016 pos &= -4;
1017
1018 if (width <= 2048) {
1019 u32 data;
1020
1021 data = (width - 1) | align;
1022
1023 for (i = 0; i < height; ++i) {
1024 __raw_writel(data, fb_base + pos);
1025 pos += line_length;
1026 }
1027 } else {
1028 unsigned long Bpp = (is8bpp ? 1 : 4);
1029 unsigned long nwidth = width & -2048;
1030 u32 fdata, ldata;
1031
1032 fdata = (2048 - 1) | align;
1033 ldata = ((width & 2047) - 1) | align;
1034
1035 for (i = 0; i < height; ++i) {
1036 for (j = 0; j < nwidth; j += 2048)
1037 __raw_writel(fdata, fb_base + pos + j*Bpp);
1038 if (j < width)
1039 __raw_writel(ldata, fb_base + pos + j*Bpp);
1040 pos += line_length;
1041 }
1042 }
1043 wmb();
1044
1045 /* Disable block fill mode. */
1046 __raw_writel((is8bpp
1047 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
1048 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
1049 regs_base + TGA_MODE_REG);
1050 }
1051
1052 /**
1053 * tgafb_copyarea - REQUIRED function. Can use generic routines if
1054 * non acclerated hardware and packed pixel based.
1055 * Copies on area of the screen to another area.
1056 *
1057 * @info: frame buffer structure that represents a single frame buffer
1058 * @area: structure defining the source and destination.
1059 */
1060
1061 /* Handle the special case of copying entire lines, e.g. during scrolling.
1062 We can avoid a lot of needless computation in this case. In the 8bpp
1063 case we need to use the COPY64 registers instead of mask writes into
1064 the frame buffer to achieve maximum performance. */
1065
1066 static inline void
1067 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
1068 u32 height, u32 width)
1069 {
1070 struct tga_par *par = (struct tga_par *) info->par;
1071 void __iomem *tga_regs = par->tga_regs_base;
1072 unsigned long dpos, spos, i, n64;
1073
1074 /* Set up the MODE and PIXELSHIFT registers. */
1075 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1076 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1077 wmb();
1078
1079 n64 = (height * width) / 64;
1080
1081 if (sy < dy) {
1082 spos = (sy + height) * width;
1083 dpos = (dy + height) * width;
1084
1085 for (i = 0; i < n64; ++i) {
1086 spos -= 64;
1087 dpos -= 64;
1088 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1089 wmb();
1090 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1091 wmb();
1092 }
1093 } else {
1094 spos = sy * width;
1095 dpos = dy * width;
1096
1097 for (i = 0; i < n64; ++i) {
1098 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1099 wmb();
1100 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1101 wmb();
1102 spos += 64;
1103 dpos += 64;
1104 }
1105 }
1106
1107 /* Reset the MODE register to normal. */
1108 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1109 }
1110
1111 static inline void
1112 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
1113 u32 height, u32 width)
1114 {
1115 struct tga_par *par = (struct tga_par *) info->par;
1116 void __iomem *tga_regs = par->tga_regs_base;
1117 void __iomem *tga_fb = par->tga_fb_base;
1118 void __iomem *src;
1119 void __iomem *dst;
1120 unsigned long i, n16;
1121
1122 /* Set up the MODE and PIXELSHIFT registers. */
1123 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1124 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1125 wmb();
1126
1127 n16 = (height * width) / 16;
1128
1129 if (sy < dy) {
1130 src = tga_fb + (sy + height) * width * 4;
1131 dst = tga_fb + (dy + height) * width * 4;
1132
1133 for (i = 0; i < n16; ++i) {
1134 src -= 64;
1135 dst -= 64;
1136 __raw_writel(0xffff, src);
1137 wmb();
1138 __raw_writel(0xffff, dst);
1139 wmb();
1140 }
1141 } else {
1142 src = tga_fb + sy * width * 4;
1143 dst = tga_fb + dy * width * 4;
1144
1145 for (i = 0; i < n16; ++i) {
1146 __raw_writel(0xffff, src);
1147 wmb();
1148 __raw_writel(0xffff, dst);
1149 wmb();
1150 src += 64;
1151 dst += 64;
1152 }
1153 }
1154
1155 /* Reset the MODE register to normal. */
1156 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1157 }
1158
1159 /* The general case of forward copy in 8bpp mode. */
1160 static inline void
1161 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1162 u32 height, u32 width, u32 line_length)
1163 {
1164 struct tga_par *par = (struct tga_par *) info->par;
1165 unsigned long i, copied, left;
1166 unsigned long dpos, spos, dalign, salign, yincr;
1167 u32 smask_first, dmask_first, dmask_last;
1168 int pixel_shift, need_prime, need_second;
1169 unsigned long n64, n32, xincr_first;
1170 void __iomem *tga_regs;
1171 void __iomem *tga_fb;
1172
1173 yincr = line_length;
1174 if (dy > sy) {
1175 dy += height - 1;
1176 sy += height - 1;
1177 yincr = -yincr;
1178 }
1179
1180 /* Compute the offsets and alignments in the frame buffer.
1181 More than anything else, these control how we do copies. */
1182 dpos = dy * line_length + dx;
1183 spos = sy * line_length + sx;
1184 dalign = dpos & 7;
1185 salign = spos & 7;
1186 dpos &= -8;
1187 spos &= -8;
1188
1189 /* Compute the value for the PIXELSHIFT register. This controls
1190 both non-co-aligned source and destination and copy direction. */
1191 if (dalign >= salign)
1192 pixel_shift = dalign - salign;
1193 else
1194 pixel_shift = 8 - (salign - dalign);
1195
1196 /* Figure out if we need an additional priming step for the
1197 residue register. */
1198 need_prime = (salign > dalign);
1199 if (need_prime)
1200 dpos -= 8;
1201
1202 /* Begin by copying the leading unaligned destination. Copy enough
1203 to make the next destination address 32-byte aligned. */
1204 copied = 32 - (dalign + (dpos & 31));
1205 if (copied == 32)
1206 copied = 0;
1207 xincr_first = (copied + 7) & -8;
1208 smask_first = dmask_first = (1ul << copied) - 1;
1209 smask_first <<= salign;
1210 dmask_first <<= dalign + need_prime*8;
1211 if (need_prime && copied > 24)
1212 copied -= 8;
1213 left = width - copied;
1214
1215 /* Care for small copies. */
1216 if (copied > width) {
1217 u32 t;
1218 t = (1ul << width) - 1;
1219 t <<= dalign + need_prime*8;
1220 dmask_first &= t;
1221 left = 0;
1222 }
1223
1224 /* Attempt to use 64-byte copies. This is only possible if the
1225 source and destination are co-aligned at 64 bytes. */
1226 n64 = need_second = 0;
1227 if ((dpos & 63) == (spos & 63)
1228 && (height == 1 || line_length % 64 == 0)) {
1229 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1230 need_second = (dpos + xincr_first) & 63;
1231 if ((need_second & 32) != need_second)
1232 printk(KERN_ERR "tgafb: need_second wrong\n");
1233 if (left >= need_second + 64) {
1234 left -= need_second;
1235 n64 = left / 64;
1236 left %= 64;
1237 } else
1238 need_second = 0;
1239 }
1240
1241 /* Copy trailing full 32-byte sections. This will be the main
1242 loop if the 64 byte loop can't be used. */
1243 n32 = left / 32;
1244 left %= 32;
1245
1246 /* Copy the trailing unaligned destination. */
1247 dmask_last = (1ul << left) - 1;
1248
1249 tga_regs = par->tga_regs_base;
1250 tga_fb = par->tga_fb_base;
1251
1252 /* Set up the MODE and PIXELSHIFT registers. */
1253 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1254 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1255 wmb();
1256
1257 for (i = 0; i < height; ++i) {
1258 unsigned long j;
1259 void __iomem *sfb;
1260 void __iomem *dfb;
1261
1262 sfb = tga_fb + spos;
1263 dfb = tga_fb + dpos;
1264 if (dmask_first) {
1265 __raw_writel(smask_first, sfb);
1266 wmb();
1267 __raw_writel(dmask_first, dfb);
1268 wmb();
1269 sfb += xincr_first;
1270 dfb += xincr_first;
1271 }
1272
1273 if (need_second) {
1274 __raw_writel(0xffffffff, sfb);
1275 wmb();
1276 __raw_writel(0xffffffff, dfb);
1277 wmb();
1278 sfb += 32;
1279 dfb += 32;
1280 }
1281
1282 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1283 printk(KERN_ERR
1284 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1285 sfb, dfb);
1286
1287 for (j = 0; j < n64; ++j) {
1288 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1289 wmb();
1290 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1291 wmb();
1292 sfb += 64;
1293 dfb += 64;
1294 }
1295
1296 for (j = 0; j < n32; ++j) {
1297 __raw_writel(0xffffffff, sfb);
1298 wmb();
1299 __raw_writel(0xffffffff, dfb);
1300 wmb();
1301 sfb += 32;
1302 dfb += 32;
1303 }
1304
1305 if (dmask_last) {
1306 __raw_writel(0xffffffff, sfb);
1307 wmb();
1308 __raw_writel(dmask_last, dfb);
1309 wmb();
1310 }
1311
1312 spos += yincr;
1313 dpos += yincr;
1314 }
1315
1316 /* Reset the MODE register to normal. */
1317 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1318 }
1319
1320 /* The (almost) general case of backward copy in 8bpp mode. */
1321 static inline void
1322 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1323 u32 height, u32 width, u32 line_length,
1324 const struct fb_copyarea *area)
1325 {
1326 struct tga_par *par = (struct tga_par *) info->par;
1327 unsigned long i, left, yincr;
1328 unsigned long depos, sepos, dealign, sealign;
1329 u32 mask_first, mask_last;
1330 unsigned long n32;
1331 void __iomem *tga_regs;
1332 void __iomem *tga_fb;
1333
1334 yincr = line_length;
1335 if (dy > sy) {
1336 dy += height - 1;
1337 sy += height - 1;
1338 yincr = -yincr;
1339 }
1340
1341 /* Compute the offsets and alignments in the frame buffer.
1342 More than anything else, these control how we do copies. */
1343 depos = dy * line_length + dx + width;
1344 sepos = sy * line_length + sx + width;
1345 dealign = depos & 7;
1346 sealign = sepos & 7;
1347
1348 /* ??? The documentation appears to be incorrect (or very
1349 misleading) wrt how pixel shifting works in backward copy
1350 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1351 Do handle the common case of co-aligned backward copies,
1352 but frob everything else back on generic code. */
1353 if (dealign != sealign) {
1354 cfb_copyarea(info, area);
1355 return;
1356 }
1357
1358 /* We begin the copy with the trailing pixels of the
1359 unaligned destination. */
1360 mask_first = (1ul << dealign) - 1;
1361 left = width - dealign;
1362
1363 /* Care for small copies. */
1364 if (dealign > width) {
1365 mask_first ^= (1ul << (dealign - width)) - 1;
1366 left = 0;
1367 }
1368
1369 /* Next copy full words at a time. */
1370 n32 = left / 32;
1371 left %= 32;
1372
1373 /* Finally copy the unaligned head of the span. */
1374 mask_last = -1 << (32 - left);
1375
1376 tga_regs = par->tga_regs_base;
1377 tga_fb = par->tga_fb_base;
1378
1379 /* Set up the MODE and PIXELSHIFT registers. */
1380 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1381 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1382 wmb();
1383
1384 for (i = 0; i < height; ++i) {
1385 unsigned long j;
1386 void __iomem *sfb;
1387 void __iomem *dfb;
1388
1389 sfb = tga_fb + sepos;
1390 dfb = tga_fb + depos;
1391 if (mask_first) {
1392 __raw_writel(mask_first, sfb);
1393 wmb();
1394 __raw_writel(mask_first, dfb);
1395 wmb();
1396 }
1397
1398 for (j = 0; j < n32; ++j) {
1399 sfb -= 32;
1400 dfb -= 32;
1401 __raw_writel(0xffffffff, sfb);
1402 wmb();
1403 __raw_writel(0xffffffff, dfb);
1404 wmb();
1405 }
1406
1407 if (mask_last) {
1408 sfb -= 32;
1409 dfb -= 32;
1410 __raw_writel(mask_last, sfb);
1411 wmb();
1412 __raw_writel(mask_last, dfb);
1413 wmb();
1414 }
1415
1416 sepos += yincr;
1417 depos += yincr;
1418 }
1419
1420 /* Reset the MODE register to normal. */
1421 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1422 }
1423
1424 static void
1425 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1426 {
1427 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1428 unsigned long line_length, bpp;
1429
1430 dx = area->dx;
1431 dy = area->dy;
1432 width = area->width;
1433 height = area->height;
1434 sx = area->sx;
1435 sy = area->sy;
1436 vxres = info->var.xres_virtual;
1437 vyres = info->var.yres_virtual;
1438 line_length = info->fix.line_length;
1439
1440 /* The top left corners must be in the virtual screen. */
1441 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1442 return;
1443
1444 /* Clip the destination. */
1445 if (dx + width > vxres)
1446 width = vxres - dx;
1447 if (dy + height > vyres)
1448 height = vyres - dy;
1449
1450 /* The source must be completely inside the virtual screen. */
1451 if (sx + width > vxres || sy + height > vyres)
1452 return;
1453
1454 bpp = info->var.bits_per_pixel;
1455
1456 /* Detect copies of the entire line. */
1457 if (width * (bpp >> 3) == line_length) {
1458 if (bpp == 8)
1459 copyarea_line_8bpp(info, dy, sy, height, width);
1460 else
1461 copyarea_line_32bpp(info, dy, sy, height, width);
1462 }
1463
1464 /* ??? The documentation is unclear to me exactly how the pixelshift
1465 register works in 32bpp mode. Since I don't have hardware to test,
1466 give up for now and fall back on the generic routines. */
1467 else if (bpp == 32)
1468 cfb_copyarea(info, area);
1469
1470 /* Detect overlapping source and destination that requires
1471 a backward copy. */
1472 else if (dy == sy && dx > sx && dx < sx + width)
1473 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1474 width, line_length, area);
1475 else
1476 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1477 width, line_length);
1478 }
1479
1480
1481 /*
1482 * Initialisation
1483 */
1484
1485 static void
1486 tgafb_init_fix(struct fb_info *info)
1487 {
1488 struct tga_par *par = (struct tga_par *)info->par;
1489 int tga_bus_pci = TGA_BUS_PCI(par->dev);
1490 int tga_bus_tc = TGA_BUS_TC(par->dev);
1491 u8 tga_type = par->tga_type;
1492 const char *tga_type_name = NULL;
1493
1494 switch (tga_type) {
1495 case TGA_TYPE_8PLANE:
1496 if (tga_bus_pci)
1497 tga_type_name = "Digital ZLXp-E1";
1498 if (tga_bus_tc)
1499 tga_type_name = "Digital ZLX-E1";
1500 break;
1501 case TGA_TYPE_24PLANE:
1502 if (tga_bus_pci)
1503 tga_type_name = "Digital ZLXp-E2";
1504 if (tga_bus_tc)
1505 tga_type_name = "Digital ZLX-E2";
1506 break;
1507 case TGA_TYPE_24PLUSZ:
1508 if (tga_bus_pci)
1509 tga_type_name = "Digital ZLXp-E3";
1510 if (tga_bus_tc)
1511 tga_type_name = "Digital ZLX-E3";
1512 break;
1513 default:
1514 tga_type_name = "Unknown";
1515 break;
1516 }
1517
1518 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1519
1520 info->fix.type = FB_TYPE_PACKED_PIXELS;
1521 info->fix.type_aux = 0;
1522 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1523 ? FB_VISUAL_PSEUDOCOLOR
1524 : FB_VISUAL_DIRECTCOLOR);
1525
1526 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1527 info->fix.smem_start = (size_t) par->tga_fb_base;
1528 info->fix.smem_len = info->fix.line_length * par->yres;
1529 info->fix.mmio_start = (size_t) par->tga_regs_base;
1530 info->fix.mmio_len = 512;
1531
1532 info->fix.xpanstep = 0;
1533 info->fix.ypanstep = 0;
1534 info->fix.ywrapstep = 0;
1535
1536 info->fix.accel = FB_ACCEL_DEC_TGA;
1537
1538 /*
1539 * These are needed by fb_set_logo_truepalette(), so we
1540 * set them here for 24-plane cards.
1541 */
1542 if (tga_type != TGA_TYPE_8PLANE) {
1543 info->var.red.length = 8;
1544 info->var.green.length = 8;
1545 info->var.blue.length = 8;
1546 info->var.red.offset = 16;
1547 info->var.green.offset = 8;
1548 info->var.blue.offset = 0;
1549 }
1550 }
1551
1552 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1553 {
1554 /* We just use this to catch switches out of graphics mode. */
1555 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
1556 return 0;
1557 }
1558
1559 static int __devinit
1560 tgafb_register(struct device *dev)
1561 {
1562 static const struct fb_videomode modedb_tc = {
1563 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */
1564 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3,
1565 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED
1566 };
1567
1568 static unsigned int const fb_offset_presets[4] = {
1569 TGA_8PLANE_FB_OFFSET,
1570 TGA_24PLANE_FB_OFFSET,
1571 0xffffffff,
1572 TGA_24PLUSZ_FB_OFFSET
1573 };
1574
1575 const struct fb_videomode *modedb_tga = NULL;
1576 resource_size_t bar0_start = 0, bar0_len = 0;
1577 const char *mode_option_tga = NULL;
1578 int tga_bus_pci = TGA_BUS_PCI(dev);
1579 int tga_bus_tc = TGA_BUS_TC(dev);
1580 unsigned int modedbsize_tga = 0;
1581 void __iomem *mem_base;
1582 struct fb_info *info;
1583 struct tga_par *par;
1584 u8 tga_type;
1585 int ret = 0;
1586
1587 /* Enable device in PCI config. */
1588 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) {
1589 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1590 return -ENODEV;
1591 }
1592
1593 /* Allocate the fb and par structures. */
1594 info = framebuffer_alloc(sizeof(struct tga_par), dev);
1595 if (!info) {
1596 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1597 return -ENOMEM;
1598 }
1599
1600 par = info->par;
1601 dev_set_drvdata(dev, info);
1602
1603 /* Request the mem regions. */
1604 ret = -ENODEV;
1605 if (tga_bus_pci) {
1606 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1607 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1608 }
1609 if (tga_bus_tc) {
1610 bar0_start = to_tc_dev(dev)->resource.start;
1611 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1612 }
1613 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1614 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1615 goto err0;
1616 }
1617
1618 /* Map the framebuffer. */
1619 mem_base = ioremap_nocache(bar0_start, bar0_len);
1620 if (!mem_base) {
1621 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1622 goto err1;
1623 }
1624
1625 /* Grab info about the card. */
1626 tga_type = (readl(mem_base) >> 12) & 0x0f;
1627 par->dev = dev;
1628 par->tga_mem_base = mem_base;
1629 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1630 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1631 par->tga_type = tga_type;
1632 if (tga_bus_pci)
1633 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1634 if (tga_bus_tc)
1635 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1636
1637 /* Setup framebuffer. */
1638 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1639 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1640 info->fbops = &tgafb_ops;
1641 info->screen_base = par->tga_fb_base;
1642 info->pseudo_palette = par->palette;
1643
1644 /* This should give a reasonable default video mode. */
1645 if (tga_bus_pci) {
1646 mode_option_tga = mode_option_pci;
1647 }
1648 if (tga_bus_tc) {
1649 mode_option_tga = mode_option_tc;
1650 modedb_tga = &modedb_tc;
1651 modedbsize_tga = 1;
1652 }
1653 ret = fb_find_mode(&info->var, info,
1654 mode_option ? mode_option : mode_option_tga,
1655 modedb_tga, modedbsize_tga, NULL,
1656 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1657 if (ret == 0 || ret == 4) {
1658 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1659 ret = -EINVAL;
1660 goto err1;
1661 }
1662
1663 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1664 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1665 ret = -ENOMEM;
1666 goto err1;
1667 }
1668
1669 tgafb_set_par(info);
1670 tgafb_init_fix(info);
1671
1672 if (register_framebuffer(info) < 0) {
1673 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1674 ret = -EINVAL;
1675 goto err1;
1676 }
1677
1678 if (tga_bus_pci) {
1679 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1680 par->tga_chip_rev);
1681 pr_info("tgafb: at PCI bus %d, device %d, function %d\n",
1682 to_pci_dev(dev)->bus->number,
1683 PCI_SLOT(to_pci_dev(dev)->devfn),
1684 PCI_FUNC(to_pci_dev(dev)->devfn));
1685 }
1686 if (tga_bus_tc)
1687 pr_info("tgafb: SFB+ detected, rev=0x%02x\n",
1688 par->tga_chip_rev);
1689 pr_info("fb%d: %s frame buffer device at 0x%lx\n",
1690 info->node, info->fix.id, (long)bar0_start);
1691
1692 return 0;
1693
1694 err1:
1695 if (mem_base)
1696 iounmap(mem_base);
1697 release_mem_region(bar0_start, bar0_len);
1698 err0:
1699 framebuffer_release(info);
1700 return ret;
1701 }
1702
1703 static void __devexit
1704 tgafb_unregister(struct device *dev)
1705 {
1706 resource_size_t bar0_start = 0, bar0_len = 0;
1707 int tga_bus_pci = TGA_BUS_PCI(dev);
1708 int tga_bus_tc = TGA_BUS_TC(dev);
1709 struct fb_info *info = NULL;
1710 struct tga_par *par;
1711
1712 info = dev_get_drvdata(dev);
1713 if (!info)
1714 return;
1715
1716 par = info->par;
1717 unregister_framebuffer(info);
1718 fb_dealloc_cmap(&info->cmap);
1719 iounmap(par->tga_mem_base);
1720 if (tga_bus_pci) {
1721 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1722 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1723 }
1724 if (tga_bus_tc) {
1725 bar0_start = to_tc_dev(dev)->resource.start;
1726 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1727 }
1728 release_mem_region(bar0_start, bar0_len);
1729 framebuffer_release(info);
1730 }
1731
1732 static void __devexit
1733 tgafb_exit(void)
1734 {
1735 tc_unregister_driver(&tgafb_tc_driver);
1736 pci_unregister_driver(&tgafb_pci_driver);
1737 }
1738
1739 #ifndef MODULE
1740 static int __devinit
1741 tgafb_setup(char *arg)
1742 {
1743 char *this_opt;
1744
1745 if (arg && *arg) {
1746 while ((this_opt = strsep(&arg, ","))) {
1747 if (!*this_opt)
1748 continue;
1749 if (!strncmp(this_opt, "mode:", 5))
1750 mode_option = this_opt+5;
1751 else
1752 printk(KERN_ERR
1753 "tgafb: unknown parameter %s\n",
1754 this_opt);
1755 }
1756 }
1757
1758 return 0;
1759 }
1760 #endif /* !MODULE */
1761
1762 static int __devinit
1763 tgafb_init(void)
1764 {
1765 int status;
1766 #ifndef MODULE
1767 char *option = NULL;
1768
1769 if (fb_get_options("tgafb", &option))
1770 return -ENODEV;
1771 tgafb_setup(option);
1772 #endif
1773 status = pci_register_driver(&tgafb_pci_driver);
1774 if (!status)
1775 status = tc_register_driver(&tgafb_tc_driver);
1776 return status;
1777 }
1778
1779 /*
1780 * Modularisation
1781 */
1782
1783 module_init(tgafb_init);
1784 module_exit(tgafb_exit);
1785
1786 MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset");
1787 MODULE_LICENSE("GPL");
Stable & featurefull patchset based on Linus's git branch