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proc: move /proc/vmstat boilerplate to mm/vmstat.c
[linux-2.6/zen-sources.git] / drivers / net / jme.c
blob81c6cdc3851f8afd54d3319df5e6e9b99d516a25
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
41 #include "jme.h"
42
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
54
55 static int
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
57 {
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61 read_again:
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
65
66 wmb();
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68 udelay(20);
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
71 break;
72 }
73
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76 return 0;
77 }
78
79 if (again--)
80 goto read_again;
81
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83 }
84
85 static void
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
88 {
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96 wmb();
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 break;
101 }
102
103 if (i == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106 return;
107 }
108
109 static inline void
110 jme_reset_phy_processor(struct jme_adapter *jme)
111 {
112 u32 val;
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
133 return;
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139 {
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161 }
162
163 static inline void
164 jme_reset_mac_processor(struct jme_adapter *jme)
165 {
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_clear_pm(struct jme_adapter *jme)
205 {
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209 }
210
211 static int
212 jme_reload_eeprom(struct jme_adapter *jme)
213 {
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239 }
240
241 static void
242 jme_load_macaddr(struct net_device *netdev)
243 {
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259 }
260
261 static inline void
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 {
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
292 }
293
294 static void
295 jme_start_irq(struct jme_adapter *jme)
296 {
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314 }
315
316 static inline void
317 jme_stop_irq(struct jme_adapter *jme)
318 {
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 }
324
325 static inline void
326 jme_enable_shadow(struct jme_adapter *jme)
327 {
328 jwrite32(jme,
329 JME_SHBA_LO,
330 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
331 }
332
333 static inline void
334 jme_disable_shadow(struct jme_adapter *jme)
335 {
336 jwrite32(jme, JME_SHBA_LO, 0x0);
337 }
338
339 static u32
340 jme_linkstat_from_phy(struct jme_adapter *jme)
341 {
342 u32 phylink, bmsr;
343
344 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
346 if (bmsr & BMSR_ANCOMP)
347 phylink |= PHY_LINK_AUTONEG_COMPLETE;
348
349 return phylink;
350 }
351
352 static inline void
353 jme_set_phyfifoa(struct jme_adapter *jme)
354 {
355 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
356 }
357
358 static inline void
359 jme_set_phyfifob(struct jme_adapter *jme)
360 {
361 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
362 }
363
364 static int
365 jme_check_link(struct net_device *netdev, int testonly)
366 {
367 struct jme_adapter *jme = netdev_priv(netdev);
368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
369 char linkmsg[64];
370 int rc = 0;
371
372 linkmsg[0] = '\0';
373
374 if (jme->fpgaver)
375 phylink = jme_linkstat_from_phy(jme);
376 else
377 phylink = jread32(jme, JME_PHY_LINK);
378
379 if (phylink & PHY_LINK_UP) {
380 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
381 /*
382 * If we did not enable AN
383 * Speed/Duplex Info should be obtained from SMI
384 */
385 phylink = PHY_LINK_UP;
386
387 bmcr = jme_mdio_read(jme->dev,
388 jme->mii_if.phy_id,
389 MII_BMCR);
390
391 phylink |= ((bmcr & BMCR_SPEED1000) &&
392 (bmcr & BMCR_SPEED100) == 0) ?
393 PHY_LINK_SPEED_1000M :
394 (bmcr & BMCR_SPEED100) ?
395 PHY_LINK_SPEED_100M :
396 PHY_LINK_SPEED_10M;
397
398 phylink |= (bmcr & BMCR_FULLDPLX) ?
399 PHY_LINK_DUPLEX : 0;
400
401 strcat(linkmsg, "Forced: ");
402 } else {
403 /*
404 * Keep polling for speed/duplex resolve complete
405 */
406 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
407 --cnt) {
408
409 udelay(1);
410
411 if (jme->fpgaver)
412 phylink = jme_linkstat_from_phy(jme);
413 else
414 phylink = jread32(jme, JME_PHY_LINK);
415 }
416 if (!cnt)
417 jeprintk(jme->pdev,
418 "Waiting speed resolve timeout.\n");
419
420 strcat(linkmsg, "ANed: ");
421 }
422
423 if (jme->phylink == phylink) {
424 rc = 1;
425 goto out;
426 }
427 if (testonly)
428 goto out;
429
430 jme->phylink = phylink;
431
432 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
433 GHC_SPEED_100M |
434 GHC_SPEED_1000M |
435 GHC_DPX);
436 switch (phylink & PHY_LINK_SPEED_MASK) {
437 case PHY_LINK_SPEED_10M:
438 ghc |= GHC_SPEED_10M;
439 strcat(linkmsg, "10 Mbps, ");
440 break;
441 case PHY_LINK_SPEED_100M:
442 ghc |= GHC_SPEED_100M;
443 strcat(linkmsg, "100 Mbps, ");
444 break;
445 case PHY_LINK_SPEED_1000M:
446 ghc |= GHC_SPEED_1000M;
447 strcat(linkmsg, "1000 Mbps, ");
448 break;
449 default:
450 break;
451 }
452
453 if (phylink & PHY_LINK_DUPLEX) {
454 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
455 ghc |= GHC_DPX;
456 } else {
457 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
458 TXMCS_BACKOFF |
459 TXMCS_CARRIERSENSE |
460 TXMCS_COLLISION);
461 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
462 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
463 TXTRHD_TXREN |
464 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
465 }
466 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
467 "Full-Duplex, " :
468 "Half-Duplex, ");
469
470 if (phylink & PHY_LINK_MDI_STAT)
471 strcat(linkmsg, "MDI-X");
472 else
473 strcat(linkmsg, "MDI");
474
475 gpreg1 = GPREG1_DEFAULT;
476 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
477 if (!(phylink & PHY_LINK_DUPLEX))
478 gpreg1 |= GPREG1_HALFMODEPATCH;
479 switch (phylink & PHY_LINK_SPEED_MASK) {
480 case PHY_LINK_SPEED_10M:
481 jme_set_phyfifoa(jme);
482 gpreg1 |= GPREG1_RSSPATCH;
483 break;
484 case PHY_LINK_SPEED_100M:
485 jme_set_phyfifob(jme);
486 gpreg1 |= GPREG1_RSSPATCH;
487 break;
488 case PHY_LINK_SPEED_1000M:
489 jme_set_phyfifoa(jme);
490 break;
491 default:
492 break;
493 }
494 }
495 jwrite32(jme, JME_GPREG1, gpreg1);
496
497 jme->reg_ghc = ghc;
498 jwrite32(jme, JME_GHC, ghc);
499
500 msg_link(jme, "Link is up at %s.\n", linkmsg);
501 netif_carrier_on(netdev);
502 } else {
503 if (testonly)
504 goto out;
505
506 msg_link(jme, "Link is down.\n");
507 jme->phylink = 0;
508 netif_carrier_off(netdev);
509 }
510
511 out:
512 return rc;
513 }
514
515 static int
516 jme_setup_tx_resources(struct jme_adapter *jme)
517 {
518 struct jme_ring *txring = &(jme->txring[0]);
519
520 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
521 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
522 &(txring->dmaalloc),
523 GFP_ATOMIC);
524
525 if (!txring->alloc) {
526 txring->desc = NULL;
527 txring->dmaalloc = 0;
528 txring->dma = 0;
529 return -ENOMEM;
530 }
531
532 /*
533 * 16 Bytes align
534 */
535 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
536 RING_DESC_ALIGN);
537 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
538 txring->next_to_use = 0;
539 atomic_set(&txring->next_to_clean, 0);
540 atomic_set(&txring->nr_free, jme->tx_ring_size);
541
542 /*
543 * Initialize Transmit Descriptors
544 */
545 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
546 memset(txring->bufinf, 0,
547 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
548
549 return 0;
550 }
551
552 static void
553 jme_free_tx_resources(struct jme_adapter *jme)
554 {
555 int i;
556 struct jme_ring *txring = &(jme->txring[0]);
557 struct jme_buffer_info *txbi = txring->bufinf;
558
559 if (txring->alloc) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
562 if (txbi->skb) {
563 dev_kfree_skb(txbi->skb);
564 txbi->skb = NULL;
565 }
566 txbi->mapping = 0;
567 txbi->len = 0;
568 txbi->nr_desc = 0;
569 txbi->start_xmit = 0;
570 }
571
572 dma_free_coherent(&(jme->pdev->dev),
573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
574 txring->alloc,
575 txring->dmaalloc);
576
577 txring->alloc = NULL;
578 txring->desc = NULL;
579 txring->dmaalloc = 0;
580 txring->dma = 0;
581 }
582 txring->next_to_use = 0;
583 atomic_set(&txring->next_to_clean, 0);
584 atomic_set(&txring->nr_free, 0);
585
586 }
587
588 static inline void
589 jme_enable_tx_engine(struct jme_adapter *jme)
590 {
591 /*
592 * Select Queue 0
593 */
594 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
595 wmb();
596
597 /*
598 * Setup TX Queue 0 DMA Bass Address
599 */
600 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
601 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
602 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
603
604 /*
605 * Setup TX Descptor Count
606 */
607 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
608
609 /*
610 * Enable TX Engine
611 */
612 wmb();
613 jwrite32(jme, JME_TXCS, jme->reg_txcs |
614 TXCS_SELECT_QUEUE0 |
615 TXCS_ENABLE);
616
617 }
618
619 static inline void
620 jme_restart_tx_engine(struct jme_adapter *jme)
621 {
622 /*
623 * Restart TX Engine
624 */
625 jwrite32(jme, JME_TXCS, jme->reg_txcs |
626 TXCS_SELECT_QUEUE0 |
627 TXCS_ENABLE);
628 }
629
630 static inline void
631 jme_disable_tx_engine(struct jme_adapter *jme)
632 {
633 int i;
634 u32 val;
635
636 /*
637 * Disable TX Engine
638 */
639 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
640 wmb();
641
642 val = jread32(jme, JME_TXCS);
643 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
644 mdelay(1);
645 val = jread32(jme, JME_TXCS);
646 rmb();
647 }
648
649 if (!i)
650 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
651 }
652
653 static void
654 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
655 {
656 struct jme_ring *rxring = jme->rxring;
657 register struct rxdesc *rxdesc = rxring->desc;
658 struct jme_buffer_info *rxbi = rxring->bufinf;
659 rxdesc += i;
660 rxbi += i;
661
662 rxdesc->dw[0] = 0;
663 rxdesc->dw[1] = 0;
664 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
665 rxdesc->desc1.bufaddrl = cpu_to_le32(
666 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
667 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
668 if (jme->dev->features & NETIF_F_HIGHDMA)
669 rxdesc->desc1.flags = RXFLAG_64BIT;
670 wmb();
671 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
672 }
673
674 static int
675 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
676 {
677 struct jme_ring *rxring = &(jme->rxring[0]);
678 struct jme_buffer_info *rxbi = rxring->bufinf + i;
679 struct sk_buff *skb;
680
681 skb = netdev_alloc_skb(jme->dev,
682 jme->dev->mtu + RX_EXTRA_LEN);
683 if (unlikely(!skb))
684 return -ENOMEM;
685
686 rxbi->skb = skb;
687 rxbi->len = skb_tailroom(skb);
688 rxbi->mapping = pci_map_page(jme->pdev,
689 virt_to_page(skb->data),
690 offset_in_page(skb->data),
691 rxbi->len,
692 PCI_DMA_FROMDEVICE);
693
694 return 0;
695 }
696
697 static void
698 jme_free_rx_buf(struct jme_adapter *jme, int i)
699 {
700 struct jme_ring *rxring = &(jme->rxring[0]);
701 struct jme_buffer_info *rxbi = rxring->bufinf;
702 rxbi += i;
703
704 if (rxbi->skb) {
705 pci_unmap_page(jme->pdev,
706 rxbi->mapping,
707 rxbi->len,
708 PCI_DMA_FROMDEVICE);
709 dev_kfree_skb(rxbi->skb);
710 rxbi->skb = NULL;
711 rxbi->mapping = 0;
712 rxbi->len = 0;
713 }
714 }
715
716 static void
717 jme_free_rx_resources(struct jme_adapter *jme)
718 {
719 int i;
720 struct jme_ring *rxring = &(jme->rxring[0]);
721
722 if (rxring->alloc) {
723 for (i = 0 ; i < jme->rx_ring_size ; ++i)
724 jme_free_rx_buf(jme, i);
725
726 dma_free_coherent(&(jme->pdev->dev),
727 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
728 rxring->alloc,
729 rxring->dmaalloc);
730 rxring->alloc = NULL;
731 rxring->desc = NULL;
732 rxring->dmaalloc = 0;
733 rxring->dma = 0;
734 }
735 rxring->next_to_use = 0;
736 atomic_set(&rxring->next_to_clean, 0);
737 }
738
739 static int
740 jme_setup_rx_resources(struct jme_adapter *jme)
741 {
742 int i;
743 struct jme_ring *rxring = &(jme->rxring[0]);
744
745 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
746 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
747 &(rxring->dmaalloc),
748 GFP_ATOMIC);
749 if (!rxring->alloc) {
750 rxring->desc = NULL;
751 rxring->dmaalloc = 0;
752 rxring->dma = 0;
753 return -ENOMEM;
754 }
755
756 /*
757 * 16 Bytes align
758 */
759 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
760 RING_DESC_ALIGN);
761 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
762 rxring->next_to_use = 0;
763 atomic_set(&rxring->next_to_clean, 0);
764
765 /*
766 * Initiallize Receive Descriptors
767 */
768 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
769 if (unlikely(jme_make_new_rx_buf(jme, i))) {
770 jme_free_rx_resources(jme);
771 return -ENOMEM;
772 }
773
774 jme_set_clean_rxdesc(jme, i);
775 }
776
777 return 0;
778 }
779
780 static inline void
781 jme_enable_rx_engine(struct jme_adapter *jme)
782 {
783 /*
784 * Select Queue 0
785 */
786 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
787 RXCS_QUEUESEL_Q0);
788 wmb();
789
790 /*
791 * Setup RX DMA Bass Address
792 */
793 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
794 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
795 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
796
797 /*
798 * Setup RX Descriptor Count
799 */
800 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
801
802 /*
803 * Setup Unicast Filter
804 */
805 jme_set_multi(jme->dev);
806
807 /*
808 * Enable RX Engine
809 */
810 wmb();
811 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
812 RXCS_QUEUESEL_Q0 |
813 RXCS_ENABLE |
814 RXCS_QST);
815 }
816
817 static inline void
818 jme_restart_rx_engine(struct jme_adapter *jme)
819 {
820 /*
821 * Start RX Engine
822 */
823 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
824 RXCS_QUEUESEL_Q0 |
825 RXCS_ENABLE |
826 RXCS_QST);
827 }
828
829 static inline void
830 jme_disable_rx_engine(struct jme_adapter *jme)
831 {
832 int i;
833 u32 val;
834
835 /*
836 * Disable RX Engine
837 */
838 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
839 wmb();
840
841 val = jread32(jme, JME_RXCS);
842 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
843 mdelay(1);
844 val = jread32(jme, JME_RXCS);
845 rmb();
846 }
847
848 if (!i)
849 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
850
851 }
852
853 static int
854 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
855 {
856 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
857 return false;
858
859 if (unlikely(!(flags & RXWBFLAG_MF) &&
860 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
861 msg_rx_err(jme, "TCP Checksum error.\n");
862 goto out_sumerr;
863 }
864
865 if (unlikely(!(flags & RXWBFLAG_MF) &&
866 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
867 msg_rx_err(jme, "UDP Checksum error.\n");
868 goto out_sumerr;
869 }
870
871 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
872 msg_rx_err(jme, "IPv4 Checksum error.\n");
873 goto out_sumerr;
874 }
875
876 return true;
877
878 out_sumerr:
879 return false;
880 }
881
882 static void
883 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
884 {
885 struct jme_ring *rxring = &(jme->rxring[0]);
886 struct rxdesc *rxdesc = rxring->desc;
887 struct jme_buffer_info *rxbi = rxring->bufinf;
888 struct sk_buff *skb;
889 int framesize;
890
891 rxdesc += idx;
892 rxbi += idx;
893
894 skb = rxbi->skb;
895 pci_dma_sync_single_for_cpu(jme->pdev,
896 rxbi->mapping,
897 rxbi->len,
898 PCI_DMA_FROMDEVICE);
899
900 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
901 pci_dma_sync_single_for_device(jme->pdev,
902 rxbi->mapping,
903 rxbi->len,
904 PCI_DMA_FROMDEVICE);
905
906 ++(NET_STAT(jme).rx_dropped);
907 } else {
908 framesize = le16_to_cpu(rxdesc->descwb.framesize)
909 - RX_PREPAD_SIZE;
910
911 skb_reserve(skb, RX_PREPAD_SIZE);
912 skb_put(skb, framesize);
913 skb->protocol = eth_type_trans(skb, jme->dev);
914
915 if (jme_rxsum_ok(jme, rxdesc->descwb.flags))
916 skb->ip_summed = CHECKSUM_UNNECESSARY;
917 else
918 skb->ip_summed = CHECKSUM_NONE;
919
920 if (rxdesc->descwb.flags & RXWBFLAG_TAGON) {
921 if (jme->vlgrp) {
922 jme->jme_vlan_rx(skb, jme->vlgrp,
923 le32_to_cpu(rxdesc->descwb.vlan));
924 NET_STAT(jme).rx_bytes += 4;
925 }
926 } else {
927 jme->jme_rx(skb);
928 }
929
930 if ((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
931 RXWBFLAG_DEST_MUL)
932 ++(NET_STAT(jme).multicast);
933
934 jme->dev->last_rx = jiffies;
935 NET_STAT(jme).rx_bytes += framesize;
936 ++(NET_STAT(jme).rx_packets);
937 }
938
939 jme_set_clean_rxdesc(jme, idx);
940
941 }
942
943 static int
944 jme_process_receive(struct jme_adapter *jme, int limit)
945 {
946 struct jme_ring *rxring = &(jme->rxring[0]);
947 struct rxdesc *rxdesc = rxring->desc;
948 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
949
950 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
951 goto out_inc;
952
953 if (unlikely(atomic_read(&jme->link_changing) != 1))
954 goto out_inc;
955
956 if (unlikely(!netif_carrier_ok(jme->dev)))
957 goto out_inc;
958
959 i = atomic_read(&rxring->next_to_clean);
960 while (limit-- > 0) {
961 rxdesc = rxring->desc;
962 rxdesc += i;
963
964 if ((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
965 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
966 goto out;
967
968 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
969
970 if (unlikely(desccnt > 1 ||
971 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
972
973 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
974 ++(NET_STAT(jme).rx_crc_errors);
975 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
976 ++(NET_STAT(jme).rx_fifo_errors);
977 else
978 ++(NET_STAT(jme).rx_errors);
979
980 if (desccnt > 1)
981 limit -= desccnt - 1;
982
983 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
984 jme_set_clean_rxdesc(jme, j);
985 j = (j + 1) & (mask);
986 }
987
988 } else {
989 jme_alloc_and_feed_skb(jme, i);
990 }
991
992 i = (i + desccnt) & (mask);
993 }
994
995 out:
996 atomic_set(&rxring->next_to_clean, i);
997
998 out_inc:
999 atomic_inc(&jme->rx_cleaning);
1000
1001 return limit > 0 ? limit : 0;
1002
1003 }
1004
1005 static void
1006 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1007 {
1008 if (likely(atmp == dpi->cur)) {
1009 dpi->cnt = 0;
1010 return;
1011 }
1012
1013 if (dpi->attempt == atmp) {
1014 ++(dpi->cnt);
1015 } else {
1016 dpi->attempt = atmp;
1017 dpi->cnt = 0;
1018 }
1019
1020 }
1021
1022 static void
1023 jme_dynamic_pcc(struct jme_adapter *jme)
1024 {
1025 register struct dynpcc_info *dpi = &(jme->dpi);
1026
1027 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1028 jme_attempt_pcc(dpi, PCC_P3);
1029 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1030 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1031 jme_attempt_pcc(dpi, PCC_P2);
1032 else
1033 jme_attempt_pcc(dpi, PCC_P1);
1034
1035 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1036 if (dpi->attempt < dpi->cur)
1037 tasklet_schedule(&jme->rxclean_task);
1038 jme_set_rx_pcc(jme, dpi->attempt);
1039 dpi->cur = dpi->attempt;
1040 dpi->cnt = 0;
1041 }
1042 }
1043
1044 static void
1045 jme_start_pcc_timer(struct jme_adapter *jme)
1046 {
1047 struct dynpcc_info *dpi = &(jme->dpi);
1048 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1049 dpi->last_pkts = NET_STAT(jme).rx_packets;
1050 dpi->intr_cnt = 0;
1051 jwrite32(jme, JME_TMCSR,
1052 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1053 }
1054
1055 static inline void
1056 jme_stop_pcc_timer(struct jme_adapter *jme)
1057 {
1058 jwrite32(jme, JME_TMCSR, 0);
1059 }
1060
1061 static void
1062 jme_shutdown_nic(struct jme_adapter *jme)
1063 {
1064 u32 phylink;
1065
1066 phylink = jme_linkstat_from_phy(jme);
1067
1068 if (!(phylink & PHY_LINK_UP)) {
1069 /*
1070 * Disable all interrupt before issue timer
1071 */
1072 jme_stop_irq(jme);
1073 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1074 }
1075 }
1076
1077 static void
1078 jme_pcc_tasklet(unsigned long arg)
1079 {
1080 struct jme_adapter *jme = (struct jme_adapter *)arg;
1081 struct net_device *netdev = jme->dev;
1082
1083 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1084 jme_shutdown_nic(jme);
1085 return;
1086 }
1087
1088 if (unlikely(!netif_carrier_ok(netdev) ||
1089 (atomic_read(&jme->link_changing) != 1)
1090 )) {
1091 jme_stop_pcc_timer(jme);
1092 return;
1093 }
1094
1095 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1096 jme_dynamic_pcc(jme);
1097
1098 jme_start_pcc_timer(jme);
1099 }
1100
1101 static inline void
1102 jme_polling_mode(struct jme_adapter *jme)
1103 {
1104 jme_set_rx_pcc(jme, PCC_OFF);
1105 }
1106
1107 static inline void
1108 jme_interrupt_mode(struct jme_adapter *jme)
1109 {
1110 jme_set_rx_pcc(jme, PCC_P1);
1111 }
1112
1113 static inline int
1114 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1115 {
1116 u32 apmc;
1117 apmc = jread32(jme, JME_APMC);
1118 return apmc & JME_APMC_PSEUDO_HP_EN;
1119 }
1120
1121 static void
1122 jme_start_shutdown_timer(struct jme_adapter *jme)
1123 {
1124 u32 apmc;
1125
1126 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1127 apmc &= ~JME_APMC_EPIEN_CTRL;
1128 if (!no_extplug) {
1129 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1130 wmb();
1131 }
1132 jwrite32f(jme, JME_APMC, apmc);
1133
1134 jwrite32f(jme, JME_TIMER2, 0);
1135 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1136 jwrite32(jme, JME_TMCSR,
1137 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1138 }
1139
1140 static void
1141 jme_stop_shutdown_timer(struct jme_adapter *jme)
1142 {
1143 u32 apmc;
1144
1145 jwrite32f(jme, JME_TMCSR, 0);
1146 jwrite32f(jme, JME_TIMER2, 0);
1147 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1148
1149 apmc = jread32(jme, JME_APMC);
1150 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1151 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1152 wmb();
1153 jwrite32f(jme, JME_APMC, apmc);
1154 }
1155
1156 static void
1157 jme_link_change_tasklet(unsigned long arg)
1158 {
1159 struct jme_adapter *jme = (struct jme_adapter *)arg;
1160 struct net_device *netdev = jme->dev;
1161 int rc;
1162
1163 while (!atomic_dec_and_test(&jme->link_changing)) {
1164 atomic_inc(&jme->link_changing);
1165 msg_intr(jme, "Get link change lock failed.\n");
1166 while (atomic_read(&jme->link_changing) != 1)
1167 msg_intr(jme, "Waiting link change lock.\n");
1168 }
1169
1170 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1171 goto out;
1172
1173 jme->old_mtu = netdev->mtu;
1174 netif_stop_queue(netdev);
1175 if (jme_pseudo_hotplug_enabled(jme))
1176 jme_stop_shutdown_timer(jme);
1177
1178 jme_stop_pcc_timer(jme);
1179 tasklet_disable(&jme->txclean_task);
1180 tasklet_disable(&jme->rxclean_task);
1181 tasklet_disable(&jme->rxempty_task);
1182
1183 if (netif_carrier_ok(netdev)) {
1184 jme_reset_ghc_speed(jme);
1185 jme_disable_rx_engine(jme);
1186 jme_disable_tx_engine(jme);
1187 jme_reset_mac_processor(jme);
1188 jme_free_rx_resources(jme);
1189 jme_free_tx_resources(jme);
1190
1191 if (test_bit(JME_FLAG_POLL, &jme->flags))
1192 jme_polling_mode(jme);
1193
1194 netif_carrier_off(netdev);
1195 }
1196
1197 jme_check_link(netdev, 0);
1198 if (netif_carrier_ok(netdev)) {
1199 rc = jme_setup_rx_resources(jme);
1200 if (rc) {
1201 jeprintk(jme->pdev, "Allocating resources for RX error"
1202 ", Device STOPPED!\n");
1203 goto out_enable_tasklet;
1204 }
1205
1206 rc = jme_setup_tx_resources(jme);
1207 if (rc) {
1208 jeprintk(jme->pdev, "Allocating resources for TX error"
1209 ", Device STOPPED!\n");
1210 goto err_out_free_rx_resources;
1211 }
1212
1213 jme_enable_rx_engine(jme);
1214 jme_enable_tx_engine(jme);
1215
1216 netif_start_queue(netdev);
1217
1218 if (test_bit(JME_FLAG_POLL, &jme->flags))
1219 jme_interrupt_mode(jme);
1220
1221 jme_start_pcc_timer(jme);
1222 } else if (jme_pseudo_hotplug_enabled(jme)) {
1223 jme_start_shutdown_timer(jme);
1224 }
1225
1226 goto out_enable_tasklet;
1227
1228 err_out_free_rx_resources:
1229 jme_free_rx_resources(jme);
1230 out_enable_tasklet:
1231 tasklet_enable(&jme->txclean_task);
1232 tasklet_hi_enable(&jme->rxclean_task);
1233 tasklet_hi_enable(&jme->rxempty_task);
1234 out:
1235 atomic_inc(&jme->link_changing);
1236 }
1237
1238 static void
1239 jme_rx_clean_tasklet(unsigned long arg)
1240 {
1241 struct jme_adapter *jme = (struct jme_adapter *)arg;
1242 struct dynpcc_info *dpi = &(jme->dpi);
1243
1244 jme_process_receive(jme, jme->rx_ring_size);
1245 ++(dpi->intr_cnt);
1246
1247 }
1248
1249 static int
1250 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1251 {
1252 struct jme_adapter *jme = jme_napi_priv(holder);
1253 struct net_device *netdev = jme->dev;
1254 int rest;
1255
1256 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1257
1258 while (atomic_read(&jme->rx_empty) > 0) {
1259 atomic_dec(&jme->rx_empty);
1260 ++(NET_STAT(jme).rx_dropped);
1261 jme_restart_rx_engine(jme);
1262 }
1263 atomic_inc(&jme->rx_empty);
1264
1265 if (rest) {
1266 JME_RX_COMPLETE(netdev, holder);
1267 jme_interrupt_mode(jme);
1268 }
1269
1270 JME_NAPI_WEIGHT_SET(budget, rest);
1271 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1272 }
1273
1274 static void
1275 jme_rx_empty_tasklet(unsigned long arg)
1276 {
1277 struct jme_adapter *jme = (struct jme_adapter *)arg;
1278
1279 if (unlikely(atomic_read(&jme->link_changing) != 1))
1280 return;
1281
1282 if (unlikely(!netif_carrier_ok(jme->dev)))
1283 return;
1284
1285 msg_rx_status(jme, "RX Queue Full!\n");
1286
1287 jme_rx_clean_tasklet(arg);
1288
1289 while (atomic_read(&jme->rx_empty) > 0) {
1290 atomic_dec(&jme->rx_empty);
1291 ++(NET_STAT(jme).rx_dropped);
1292 jme_restart_rx_engine(jme);
1293 }
1294 atomic_inc(&jme->rx_empty);
1295 }
1296
1297 static void
1298 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1299 {
1300 struct jme_ring *txring = jme->txring;
1301
1302 smp_wmb();
1303 if (unlikely(netif_queue_stopped(jme->dev) &&
1304 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1305 msg_tx_done(jme, "TX Queue Waked.\n");
1306 netif_wake_queue(jme->dev);
1307 }
1308
1309 }
1310
1311 static void
1312 jme_tx_clean_tasklet(unsigned long arg)
1313 {
1314 struct jme_adapter *jme = (struct jme_adapter *)arg;
1315 struct jme_ring *txring = &(jme->txring[0]);
1316 struct txdesc *txdesc = txring->desc;
1317 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1318 int i, j, cnt = 0, max, err, mask;
1319
1320 tx_dbg(jme, "Into txclean.\n");
1321
1322 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1323 goto out;
1324
1325 if (unlikely(atomic_read(&jme->link_changing) != 1))
1326 goto out;
1327
1328 if (unlikely(!netif_carrier_ok(jme->dev)))
1329 goto out;
1330
1331 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1332 mask = jme->tx_ring_mask;
1333
1334 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1335
1336 ctxbi = txbi + i;
1337
1338 if (likely(ctxbi->skb &&
1339 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1340
1341 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1342 i, ctxbi->nr_desc, jiffies);
1343
1344 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1345
1346 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1347 ttxbi = txbi + ((i + j) & (mask));
1348 txdesc[(i + j) & (mask)].dw[0] = 0;
1349
1350 pci_unmap_page(jme->pdev,
1351 ttxbi->mapping,
1352 ttxbi->len,
1353 PCI_DMA_TODEVICE);
1354
1355 ttxbi->mapping = 0;
1356 ttxbi->len = 0;
1357 }
1358
1359 dev_kfree_skb(ctxbi->skb);
1360
1361 cnt += ctxbi->nr_desc;
1362
1363 if (unlikely(err)) {
1364 ++(NET_STAT(jme).tx_carrier_errors);
1365 } else {
1366 ++(NET_STAT(jme).tx_packets);
1367 NET_STAT(jme).tx_bytes += ctxbi->len;
1368 }
1369
1370 ctxbi->skb = NULL;
1371 ctxbi->len = 0;
1372 ctxbi->start_xmit = 0;
1373
1374 } else {
1375 break;
1376 }
1377
1378 i = (i + ctxbi->nr_desc) & mask;
1379
1380 ctxbi->nr_desc = 0;
1381 }
1382
1383 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1384 atomic_set(&txring->next_to_clean, i);
1385 atomic_add(cnt, &txring->nr_free);
1386
1387 jme_wake_queue_if_stopped(jme);
1388
1389 out:
1390 atomic_inc(&jme->tx_cleaning);
1391 }
1392
1393 static void
1394 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1395 {
1396 /*
1397 * Disable interrupt
1398 */
1399 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1400
1401 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1402 /*
1403 * Link change event is critical
1404 * all other events are ignored
1405 */
1406 jwrite32(jme, JME_IEVE, intrstat);
1407 tasklet_schedule(&jme->linkch_task);
1408 goto out_reenable;
1409 }
1410
1411 if (intrstat & INTR_TMINTR) {
1412 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1413 tasklet_schedule(&jme->pcc_task);
1414 }
1415
1416 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1417 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1418 tasklet_schedule(&jme->txclean_task);
1419 }
1420
1421 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1422 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1423 INTR_PCCRX0 |
1424 INTR_RX0EMP)) |
1425 INTR_RX0);
1426 }
1427
1428 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1429 if (intrstat & INTR_RX0EMP)
1430 atomic_inc(&jme->rx_empty);
1431
1432 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1433 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1434 jme_polling_mode(jme);
1435 JME_RX_SCHEDULE(jme);
1436 }
1437 }
1438 } else {
1439 if (intrstat & INTR_RX0EMP) {
1440 atomic_inc(&jme->rx_empty);
1441 tasklet_hi_schedule(&jme->rxempty_task);
1442 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1443 tasklet_hi_schedule(&jme->rxclean_task);
1444 }
1445 }
1446
1447 out_reenable:
1448 /*
1449 * Re-enable interrupt
1450 */
1451 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1452 }
1453
1454 static irqreturn_t
1455 jme_intr(int irq, void *dev_id)
1456 {
1457 struct net_device *netdev = dev_id;
1458 struct jme_adapter *jme = netdev_priv(netdev);
1459 u32 intrstat;
1460
1461 intrstat = jread32(jme, JME_IEVE);
1462
1463 /*
1464 * Check if it's really an interrupt for us
1465 */
1466 if (unlikely((intrstat & INTR_ENABLE) == 0))
1467 return IRQ_NONE;
1468
1469 /*
1470 * Check if the device still exist
1471 */
1472 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1473 return IRQ_NONE;
1474
1475 jme_intr_msi(jme, intrstat);
1476
1477 return IRQ_HANDLED;
1478 }
1479
1480 static irqreturn_t
1481 jme_msi(int irq, void *dev_id)
1482 {
1483 struct net_device *netdev = dev_id;
1484 struct jme_adapter *jme = netdev_priv(netdev);
1485 u32 intrstat;
1486
1487 pci_dma_sync_single_for_cpu(jme->pdev,
1488 jme->shadow_dma,
1489 sizeof(u32) * SHADOW_REG_NR,
1490 PCI_DMA_FROMDEVICE);
1491 intrstat = jme->shadow_regs[SHADOW_IEVE];
1492 jme->shadow_regs[SHADOW_IEVE] = 0;
1493
1494 jme_intr_msi(jme, intrstat);
1495
1496 return IRQ_HANDLED;
1497 }
1498
1499 static void
1500 jme_reset_link(struct jme_adapter *jme)
1501 {
1502 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1503 }
1504
1505 static void
1506 jme_restart_an(struct jme_adapter *jme)
1507 {
1508 u32 bmcr;
1509
1510 spin_lock_bh(&jme->phy_lock);
1511 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1512 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1513 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1514 spin_unlock_bh(&jme->phy_lock);
1515 }
1516
1517 static int
1518 jme_request_irq(struct jme_adapter *jme)
1519 {
1520 int rc;
1521 struct net_device *netdev = jme->dev;
1522 irq_handler_t handler = jme_intr;
1523 int irq_flags = IRQF_SHARED;
1524
1525 if (!pci_enable_msi(jme->pdev)) {
1526 set_bit(JME_FLAG_MSI, &jme->flags);
1527 handler = jme_msi;
1528 irq_flags = 0;
1529 }
1530
1531 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1532 netdev);
1533 if (rc) {
1534 jeprintk(jme->pdev,
1535 "Unable to request %s interrupt (return: %d)\n",
1536 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1537 rc);
1538
1539 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1540 pci_disable_msi(jme->pdev);
1541 clear_bit(JME_FLAG_MSI, &jme->flags);
1542 }
1543 } else {
1544 netdev->irq = jme->pdev->irq;
1545 }
1546
1547 return rc;
1548 }
1549
1550 static void
1551 jme_free_irq(struct jme_adapter *jme)
1552 {
1553 free_irq(jme->pdev->irq, jme->dev);
1554 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1555 pci_disable_msi(jme->pdev);
1556 clear_bit(JME_FLAG_MSI, &jme->flags);
1557 jme->dev->irq = jme->pdev->irq;
1558 }
1559 }
1560
1561 static int
1562 jme_open(struct net_device *netdev)
1563 {
1564 struct jme_adapter *jme = netdev_priv(netdev);
1565 int rc;
1566
1567 jme_clear_pm(jme);
1568 JME_NAPI_ENABLE(jme);
1569
1570 tasklet_enable(&jme->txclean_task);
1571 tasklet_hi_enable(&jme->rxclean_task);
1572 tasklet_hi_enable(&jme->rxempty_task);
1573
1574 rc = jme_request_irq(jme);
1575 if (rc)
1576 goto err_out;
1577
1578 jme_enable_shadow(jme);
1579 jme_start_irq(jme);
1580
1581 if (test_bit(JME_FLAG_SSET, &jme->flags))
1582 jme_set_settings(netdev, &jme->old_ecmd);
1583 else
1584 jme_reset_phy_processor(jme);
1585
1586 jme_reset_link(jme);
1587
1588 return 0;
1589
1590 err_out:
1591 netif_stop_queue(netdev);
1592 netif_carrier_off(netdev);
1593 return rc;
1594 }
1595
1596 #ifdef CONFIG_PM
1597 static void
1598 jme_set_100m_half(struct jme_adapter *jme)
1599 {
1600 u32 bmcr, tmp;
1601
1602 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1603 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1604 BMCR_SPEED1000 | BMCR_FULLDPLX);
1605 tmp |= BMCR_SPEED100;
1606
1607 if (bmcr != tmp)
1608 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1609
1610 if (jme->fpgaver)
1611 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1612 else
1613 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1614 }
1615
1616 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1617 static void
1618 jme_wait_link(struct jme_adapter *jme)
1619 {
1620 u32 phylink, to = JME_WAIT_LINK_TIME;
1621
1622 mdelay(1000);
1623 phylink = jme_linkstat_from_phy(jme);
1624 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1625 mdelay(10);
1626 phylink = jme_linkstat_from_phy(jme);
1627 }
1628 }
1629 #endif
1630
1631 static inline void
1632 jme_phy_off(struct jme_adapter *jme)
1633 {
1634 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1635 }
1636
1637 static int
1638 jme_close(struct net_device *netdev)
1639 {
1640 struct jme_adapter *jme = netdev_priv(netdev);
1641
1642 netif_stop_queue(netdev);
1643 netif_carrier_off(netdev);
1644
1645 jme_stop_irq(jme);
1646 jme_disable_shadow(jme);
1647 jme_free_irq(jme);
1648
1649 JME_NAPI_DISABLE(jme);
1650
1651 tasklet_kill(&jme->linkch_task);
1652 tasklet_kill(&jme->txclean_task);
1653 tasklet_kill(&jme->rxclean_task);
1654 tasklet_kill(&jme->rxempty_task);
1655
1656 jme_reset_ghc_speed(jme);
1657 jme_disable_rx_engine(jme);
1658 jme_disable_tx_engine(jme);
1659 jme_reset_mac_processor(jme);
1660 jme_free_rx_resources(jme);
1661 jme_free_tx_resources(jme);
1662 jme->phylink = 0;
1663 jme_phy_off(jme);
1664
1665 return 0;
1666 }
1667
1668 static int
1669 jme_alloc_txdesc(struct jme_adapter *jme,
1670 struct sk_buff *skb)
1671 {
1672 struct jme_ring *txring = jme->txring;
1673 int idx, nr_alloc, mask = jme->tx_ring_mask;
1674
1675 idx = txring->next_to_use;
1676 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1677
1678 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1679 return -1;
1680
1681 atomic_sub(nr_alloc, &txring->nr_free);
1682
1683 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1684
1685 return idx;
1686 }
1687
1688 static void
1689 jme_fill_tx_map(struct pci_dev *pdev,
1690 struct txdesc *txdesc,
1691 struct jme_buffer_info *txbi,
1692 struct page *page,
1693 u32 page_offset,
1694 u32 len,
1695 u8 hidma)
1696 {
1697 dma_addr_t dmaaddr;
1698
1699 dmaaddr = pci_map_page(pdev,
1700 page,
1701 page_offset,
1702 len,
1703 PCI_DMA_TODEVICE);
1704
1705 pci_dma_sync_single_for_device(pdev,
1706 dmaaddr,
1707 len,
1708 PCI_DMA_TODEVICE);
1709
1710 txdesc->dw[0] = 0;
1711 txdesc->dw[1] = 0;
1712 txdesc->desc2.flags = TXFLAG_OWN;
1713 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1714 txdesc->desc2.datalen = cpu_to_le16(len);
1715 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1716 txdesc->desc2.bufaddrl = cpu_to_le32(
1717 (__u64)dmaaddr & 0xFFFFFFFFUL);
1718
1719 txbi->mapping = dmaaddr;
1720 txbi->len = len;
1721 }
1722
1723 static void
1724 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1725 {
1726 struct jme_ring *txring = jme->txring;
1727 struct txdesc *txdesc = txring->desc, *ctxdesc;
1728 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1729 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1730 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1731 int mask = jme->tx_ring_mask;
1732 struct skb_frag_struct *frag;
1733 u32 len;
1734
1735 for (i = 0 ; i < nr_frags ; ++i) {
1736 frag = &skb_shinfo(skb)->frags[i];
1737 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1738 ctxbi = txbi + ((idx + i + 2) & (mask));
1739
1740 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1741 frag->page_offset, frag->size, hidma);
1742 }
1743
1744 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1745 ctxdesc = txdesc + ((idx + 1) & (mask));
1746 ctxbi = txbi + ((idx + 1) & (mask));
1747 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1748 offset_in_page(skb->data), len, hidma);
1749
1750 }
1751
1752 static int
1753 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1754 {
1755 if (unlikely(skb_shinfo(skb)->gso_size &&
1756 skb_header_cloned(skb) &&
1757 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1758 dev_kfree_skb(skb);
1759 return -1;
1760 }
1761
1762 return 0;
1763 }
1764
1765 static int
1766 jme_tx_tso(struct sk_buff *skb,
1767 u16 *mss, u8 *flags)
1768 {
1769 *mss = skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT;
1770 if (*mss) {
1771 *flags |= TXFLAG_LSEN;
1772
1773 if (skb->protocol == htons(ETH_P_IP)) {
1774 struct iphdr *iph = ip_hdr(skb);
1775
1776 iph->check = 0;
1777 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1778 iph->daddr, 0,
1779 IPPROTO_TCP,
1780 0);
1781 } else {
1782 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1783
1784 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1785 &ip6h->daddr, 0,
1786 IPPROTO_TCP,
1787 0);
1788 }
1789
1790 return 0;
1791 }
1792
1793 return 1;
1794 }
1795
1796 static void
1797 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1798 {
1799 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1800 u8 ip_proto;
1801
1802 switch (skb->protocol) {
1803 case htons(ETH_P_IP):
1804 ip_proto = ip_hdr(skb)->protocol;
1805 break;
1806 case htons(ETH_P_IPV6):
1807 ip_proto = ipv6_hdr(skb)->nexthdr;
1808 break;
1809 default:
1810 ip_proto = 0;
1811 break;
1812 }
1813
1814 switch (ip_proto) {
1815 case IPPROTO_TCP:
1816 *flags |= TXFLAG_TCPCS;
1817 break;
1818 case IPPROTO_UDP:
1819 *flags |= TXFLAG_UDPCS;
1820 break;
1821 default:
1822 msg_tx_err(jme, "Error upper layer protocol.\n");
1823 break;
1824 }
1825 }
1826 }
1827
1828 static inline void
1829 jme_tx_vlan(struct sk_buff *skb, u16 *vlan, u8 *flags)
1830 {
1831 if (vlan_tx_tag_present(skb)) {
1832 *flags |= TXFLAG_TAGON;
1833 *vlan = vlan_tx_tag_get(skb);
1834 }
1835 }
1836
1837 static int
1838 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1839 {
1840 struct jme_ring *txring = jme->txring;
1841 struct txdesc *txdesc;
1842 struct jme_buffer_info *txbi;
1843 u8 flags;
1844
1845 txdesc = (struct txdesc *)txring->desc + idx;
1846 txbi = txring->bufinf + idx;
1847
1848 txdesc->dw[0] = 0;
1849 txdesc->dw[1] = 0;
1850 txdesc->dw[2] = 0;
1851 txdesc->dw[3] = 0;
1852 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1853 /*
1854 * Set OWN bit at final.
1855 * When kernel transmit faster than NIC.
1856 * And NIC trying to send this descriptor before we tell
1857 * it to start sending this TX queue.
1858 * Other fields are already filled correctly.
1859 */
1860 wmb();
1861 flags = TXFLAG_OWN | TXFLAG_INT;
1862 /*
1863 * Set checksum flags while not tso
1864 */
1865 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1866 jme_tx_csum(jme, skb, &flags);
1867 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1868 txdesc->desc1.flags = flags;
1869 /*
1870 * Set tx buffer info after telling NIC to send
1871 * For better tx_clean timing
1872 */
1873 wmb();
1874 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1875 txbi->skb = skb;
1876 txbi->len = skb->len;
1877 txbi->start_xmit = jiffies;
1878 if (!txbi->start_xmit)
1879 txbi->start_xmit = (0UL-1);
1880
1881 return 0;
1882 }
1883
1884 static void
1885 jme_stop_queue_if_full(struct jme_adapter *jme)
1886 {
1887 struct jme_ring *txring = jme->txring;
1888 struct jme_buffer_info *txbi = txring->bufinf;
1889 int idx = atomic_read(&txring->next_to_clean);
1890
1891 txbi += idx;
1892
1893 smp_wmb();
1894 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1895 netif_stop_queue(jme->dev);
1896 msg_tx_queued(jme, "TX Queue Paused.\n");
1897 smp_wmb();
1898 if (atomic_read(&txring->nr_free)
1899 >= (jme->tx_wake_threshold)) {
1900 netif_wake_queue(jme->dev);
1901 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1902 }
1903 }
1904
1905 if (unlikely(txbi->start_xmit &&
1906 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1907 txbi->skb)) {
1908 netif_stop_queue(jme->dev);
1909 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1910 }
1911 }
1912
1913 /*
1914 * This function is already protected by netif_tx_lock()
1915 */
1916
1917 static int
1918 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1919 {
1920 struct jme_adapter *jme = netdev_priv(netdev);
1921 int idx;
1922
1923 if (unlikely(jme_expand_header(jme, skb))) {
1924 ++(NET_STAT(jme).tx_dropped);
1925 return NETDEV_TX_OK;
1926 }
1927
1928 idx = jme_alloc_txdesc(jme, skb);
1929
1930 if (unlikely(idx < 0)) {
1931 netif_stop_queue(netdev);
1932 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1933
1934 return NETDEV_TX_BUSY;
1935 }
1936
1937 jme_map_tx_skb(jme, skb, idx);
1938 jme_fill_first_tx_desc(jme, skb, idx);
1939
1940 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1941 TXCS_SELECT_QUEUE0 |
1942 TXCS_QUEUE0S |
1943 TXCS_ENABLE);
1944 netdev->trans_start = jiffies;
1945
1946 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1947 skb_shinfo(skb)->nr_frags + 2,
1948 jiffies);
1949 jme_stop_queue_if_full(jme);
1950
1951 return NETDEV_TX_OK;
1952 }
1953
1954 static int
1955 jme_set_macaddr(struct net_device *netdev, void *p)
1956 {
1957 struct jme_adapter *jme = netdev_priv(netdev);
1958 struct sockaddr *addr = p;
1959 u32 val;
1960
1961 if (netif_running(netdev))
1962 return -EBUSY;
1963
1964 spin_lock_bh(&jme->macaddr_lock);
1965 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1966
1967 val = (addr->sa_data[3] & 0xff) << 24 |
1968 (addr->sa_data[2] & 0xff) << 16 |
1969 (addr->sa_data[1] & 0xff) << 8 |
1970 (addr->sa_data[0] & 0xff);
1971 jwrite32(jme, JME_RXUMA_LO, val);
1972 val = (addr->sa_data[5] & 0xff) << 8 |
1973 (addr->sa_data[4] & 0xff);
1974 jwrite32(jme, JME_RXUMA_HI, val);
1975 spin_unlock_bh(&jme->macaddr_lock);
1976
1977 return 0;
1978 }
1979
1980 static void
1981 jme_set_multi(struct net_device *netdev)
1982 {
1983 struct jme_adapter *jme = netdev_priv(netdev);
1984 u32 mc_hash[2] = {};
1985 int i;
1986
1987 spin_lock_bh(&jme->rxmcs_lock);
1988
1989 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1990
1991 if (netdev->flags & IFF_PROMISC) {
1992 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1993 } else if (netdev->flags & IFF_ALLMULTI) {
1994 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1995 } else if (netdev->flags & IFF_MULTICAST) {
1996 struct dev_mc_list *mclist;
1997 int bit_nr;
1998
1999 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2000 for (i = 0, mclist = netdev->mc_list;
2001 mclist && i < netdev->mc_count;
2002 ++i, mclist = mclist->next) {
2003
2004 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2005 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2006 }
2007
2008 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2009 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2010 }
2011
2012 wmb();
2013 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2014
2015 spin_unlock_bh(&jme->rxmcs_lock);
2016 }
2017
2018 static int
2019 jme_change_mtu(struct net_device *netdev, int new_mtu)
2020 {
2021 struct jme_adapter *jme = netdev_priv(netdev);
2022
2023 if (new_mtu == jme->old_mtu)
2024 return 0;
2025
2026 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2027 ((new_mtu) < IPV6_MIN_MTU))
2028 return -EINVAL;
2029
2030 if (new_mtu > 4000) {
2031 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2032 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2033 jme_restart_rx_engine(jme);
2034 } else {
2035 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2036 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2037 jme_restart_rx_engine(jme);
2038 }
2039
2040 if (new_mtu > 1900) {
2041 netdev->features &= ~(NETIF_F_HW_CSUM |
2042 NETIF_F_TSO |
2043 NETIF_F_TSO6);
2044 } else {
2045 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2046 netdev->features |= NETIF_F_HW_CSUM;
2047 if (test_bit(JME_FLAG_TSO, &jme->flags))
2048 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2049 }
2050
2051 netdev->mtu = new_mtu;
2052 jme_reset_link(jme);
2053
2054 return 0;
2055 }
2056
2057 static void
2058 jme_tx_timeout(struct net_device *netdev)
2059 {
2060 struct jme_adapter *jme = netdev_priv(netdev);
2061
2062 jme->phylink = 0;
2063 jme_reset_phy_processor(jme);
2064 if (test_bit(JME_FLAG_SSET, &jme->flags))
2065 jme_set_settings(netdev, &jme->old_ecmd);
2066
2067 /*
2068 * Force to Reset the link again
2069 */
2070 jme_reset_link(jme);
2071 }
2072
2073 static void
2074 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2075 {
2076 struct jme_adapter *jme = netdev_priv(netdev);
2077
2078 jme->vlgrp = grp;
2079 }
2080
2081 static void
2082 jme_get_drvinfo(struct net_device *netdev,
2083 struct ethtool_drvinfo *info)
2084 {
2085 struct jme_adapter *jme = netdev_priv(netdev);
2086
2087 strcpy(info->driver, DRV_NAME);
2088 strcpy(info->version, DRV_VERSION);
2089 strcpy(info->bus_info, pci_name(jme->pdev));
2090 }
2091
2092 static int
2093 jme_get_regs_len(struct net_device *netdev)
2094 {
2095 return JME_REG_LEN;
2096 }
2097
2098 static void
2099 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2100 {
2101 int i;
2102
2103 for (i = 0 ; i < len ; i += 4)
2104 p[i >> 2] = jread32(jme, reg + i);
2105 }
2106
2107 static void
2108 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2109 {
2110 int i;
2111 u16 *p16 = (u16 *)p;
2112
2113 for (i = 0 ; i < reg_nr ; ++i)
2114 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2115 }
2116
2117 static void
2118 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2119 {
2120 struct jme_adapter *jme = netdev_priv(netdev);
2121 u32 *p32 = (u32 *)p;
2122
2123 memset(p, 0xFF, JME_REG_LEN);
2124
2125 regs->version = 1;
2126 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2127
2128 p32 += 0x100 >> 2;
2129 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2130
2131 p32 += 0x100 >> 2;
2132 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2133
2134 p32 += 0x100 >> 2;
2135 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2136
2137 p32 += 0x100 >> 2;
2138 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2139 }
2140
2141 static int
2142 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2143 {
2144 struct jme_adapter *jme = netdev_priv(netdev);
2145
2146 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2147 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2148
2149 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2150 ecmd->use_adaptive_rx_coalesce = false;
2151 ecmd->rx_coalesce_usecs = 0;
2152 ecmd->rx_max_coalesced_frames = 0;
2153 return 0;
2154 }
2155
2156 ecmd->use_adaptive_rx_coalesce = true;
2157
2158 switch (jme->dpi.cur) {
2159 case PCC_P1:
2160 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2161 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2162 break;
2163 case PCC_P2:
2164 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2165 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2166 break;
2167 case PCC_P3:
2168 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2169 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2170 break;
2171 default:
2172 break;
2173 }
2174
2175 return 0;
2176 }
2177
2178 static int
2179 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2180 {
2181 struct jme_adapter *jme = netdev_priv(netdev);
2182 struct dynpcc_info *dpi = &(jme->dpi);
2183
2184 if (netif_running(netdev))
2185 return -EBUSY;
2186
2187 if (ecmd->use_adaptive_rx_coalesce
2188 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2189 clear_bit(JME_FLAG_POLL, &jme->flags);
2190 jme->jme_rx = netif_rx;
2191 jme->jme_vlan_rx = vlan_hwaccel_rx;
2192 dpi->cur = PCC_P1;
2193 dpi->attempt = PCC_P1;
2194 dpi->cnt = 0;
2195 jme_set_rx_pcc(jme, PCC_P1);
2196 jme_interrupt_mode(jme);
2197 } else if (!(ecmd->use_adaptive_rx_coalesce)
2198 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2199 set_bit(JME_FLAG_POLL, &jme->flags);
2200 jme->jme_rx = netif_receive_skb;
2201 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2202 jme_interrupt_mode(jme);
2203 }
2204
2205 return 0;
2206 }
2207
2208 static void
2209 jme_get_pauseparam(struct net_device *netdev,
2210 struct ethtool_pauseparam *ecmd)
2211 {
2212 struct jme_adapter *jme = netdev_priv(netdev);
2213 u32 val;
2214
2215 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2216 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2217
2218 spin_lock_bh(&jme->phy_lock);
2219 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2220 spin_unlock_bh(&jme->phy_lock);
2221
2222 ecmd->autoneg =
2223 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2224 }
2225
2226 static int
2227 jme_set_pauseparam(struct net_device *netdev,
2228 struct ethtool_pauseparam *ecmd)
2229 {
2230 struct jme_adapter *jme = netdev_priv(netdev);
2231 u32 val;
2232
2233 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2234 (ecmd->tx_pause != 0)) {
2235
2236 if (ecmd->tx_pause)
2237 jme->reg_txpfc |= TXPFC_PF_EN;
2238 else
2239 jme->reg_txpfc &= ~TXPFC_PF_EN;
2240
2241 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2242 }
2243
2244 spin_lock_bh(&jme->rxmcs_lock);
2245 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2246 (ecmd->rx_pause != 0)) {
2247
2248 if (ecmd->rx_pause)
2249 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2250 else
2251 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2252
2253 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2254 }
2255 spin_unlock_bh(&jme->rxmcs_lock);
2256
2257 spin_lock_bh(&jme->phy_lock);
2258 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2259 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2260 (ecmd->autoneg != 0)) {
2261
2262 if (ecmd->autoneg)
2263 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2264 else
2265 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2266
2267 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2268 MII_ADVERTISE, val);
2269 }
2270 spin_unlock_bh(&jme->phy_lock);
2271
2272 return 0;
2273 }
2274
2275 static void
2276 jme_get_wol(struct net_device *netdev,
2277 struct ethtool_wolinfo *wol)
2278 {
2279 struct jme_adapter *jme = netdev_priv(netdev);
2280
2281 wol->supported = WAKE_MAGIC | WAKE_PHY;
2282
2283 wol->wolopts = 0;
2284
2285 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2286 wol->wolopts |= WAKE_PHY;
2287
2288 if (jme->reg_pmcs & PMCS_MFEN)
2289 wol->wolopts |= WAKE_MAGIC;
2290
2291 }
2292
2293 static int
2294 jme_set_wol(struct net_device *netdev,
2295 struct ethtool_wolinfo *wol)
2296 {
2297 struct jme_adapter *jme = netdev_priv(netdev);
2298
2299 if (wol->wolopts & (WAKE_MAGICSECURE |
2300 WAKE_UCAST |
2301 WAKE_MCAST |
2302 WAKE_BCAST |
2303 WAKE_ARP))
2304 return -EOPNOTSUPP;
2305
2306 jme->reg_pmcs = 0;
2307
2308 if (wol->wolopts & WAKE_PHY)
2309 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2310
2311 if (wol->wolopts & WAKE_MAGIC)
2312 jme->reg_pmcs |= PMCS_MFEN;
2313
2314 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2315
2316 return 0;
2317 }
2318
2319 static int
2320 jme_get_settings(struct net_device *netdev,
2321 struct ethtool_cmd *ecmd)
2322 {
2323 struct jme_adapter *jme = netdev_priv(netdev);
2324 int rc;
2325
2326 spin_lock_bh(&jme->phy_lock);
2327 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2328 spin_unlock_bh(&jme->phy_lock);
2329 return rc;
2330 }
2331
2332 static int
2333 jme_set_settings(struct net_device *netdev,
2334 struct ethtool_cmd *ecmd)
2335 {
2336 struct jme_adapter *jme = netdev_priv(netdev);
2337 int rc, fdc = 0;
2338
2339 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2340 return -EINVAL;
2341
2342 if (jme->mii_if.force_media &&
2343 ecmd->autoneg != AUTONEG_ENABLE &&
2344 (jme->mii_if.full_duplex != ecmd->duplex))
2345 fdc = 1;
2346
2347 spin_lock_bh(&jme->phy_lock);
2348 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2349 spin_unlock_bh(&jme->phy_lock);
2350
2351 if (!rc && fdc)
2352 jme_reset_link(jme);
2353
2354 if (!rc) {
2355 set_bit(JME_FLAG_SSET, &jme->flags);
2356 jme->old_ecmd = *ecmd;
2357 }
2358
2359 return rc;
2360 }
2361
2362 static u32
2363 jme_get_link(struct net_device *netdev)
2364 {
2365 struct jme_adapter *jme = netdev_priv(netdev);
2366 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2367 }
2368
2369 static u32
2370 jme_get_msglevel(struct net_device *netdev)
2371 {
2372 struct jme_adapter *jme = netdev_priv(netdev);
2373 return jme->msg_enable;
2374 }
2375
2376 static void
2377 jme_set_msglevel(struct net_device *netdev, u32 value)
2378 {
2379 struct jme_adapter *jme = netdev_priv(netdev);
2380 jme->msg_enable = value;
2381 }
2382
2383 static u32
2384 jme_get_rx_csum(struct net_device *netdev)
2385 {
2386 struct jme_adapter *jme = netdev_priv(netdev);
2387 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2388 }
2389
2390 static int
2391 jme_set_rx_csum(struct net_device *netdev, u32 on)
2392 {
2393 struct jme_adapter *jme = netdev_priv(netdev);
2394
2395 spin_lock_bh(&jme->rxmcs_lock);
2396 if (on)
2397 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2398 else
2399 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2400 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2401 spin_unlock_bh(&jme->rxmcs_lock);
2402
2403 return 0;
2404 }
2405
2406 static int
2407 jme_set_tx_csum(struct net_device *netdev, u32 on)
2408 {
2409 struct jme_adapter *jme = netdev_priv(netdev);
2410
2411 if (on) {
2412 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2413 if (netdev->mtu <= 1900)
2414 netdev->features |= NETIF_F_HW_CSUM;
2415 } else {
2416 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2417 netdev->features &= ~NETIF_F_HW_CSUM;
2418 }
2419
2420 return 0;
2421 }
2422
2423 static int
2424 jme_set_tso(struct net_device *netdev, u32 on)
2425 {
2426 struct jme_adapter *jme = netdev_priv(netdev);
2427
2428 if (on) {
2429 set_bit(JME_FLAG_TSO, &jme->flags);
2430 if (netdev->mtu <= 1900)
2431 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2432 } else {
2433 clear_bit(JME_FLAG_TSO, &jme->flags);
2434 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2435 }
2436
2437 return 0;
2438 }
2439
2440 static int
2441 jme_nway_reset(struct net_device *netdev)
2442 {
2443 struct jme_adapter *jme = netdev_priv(netdev);
2444 jme_restart_an(jme);
2445 return 0;
2446 }
2447
2448 static u8
2449 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2450 {
2451 u32 val;
2452 int to;
2453
2454 val = jread32(jme, JME_SMBCSR);
2455 to = JME_SMB_BUSY_TIMEOUT;
2456 while ((val & SMBCSR_BUSY) && --to) {
2457 msleep(1);
2458 val = jread32(jme, JME_SMBCSR);
2459 }
2460 if (!to) {
2461 msg_hw(jme, "SMB Bus Busy.\n");
2462 return 0xFF;
2463 }
2464
2465 jwrite32(jme, JME_SMBINTF,
2466 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2467 SMBINTF_HWRWN_READ |
2468 SMBINTF_HWCMD);
2469
2470 val = jread32(jme, JME_SMBINTF);
2471 to = JME_SMB_BUSY_TIMEOUT;
2472 while ((val & SMBINTF_HWCMD) && --to) {
2473 msleep(1);
2474 val = jread32(jme, JME_SMBINTF);
2475 }
2476 if (!to) {
2477 msg_hw(jme, "SMB Bus Busy.\n");
2478 return 0xFF;
2479 }
2480
2481 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2482 }
2483
2484 static void
2485 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2486 {
2487 u32 val;
2488 int to;
2489
2490 val = jread32(jme, JME_SMBCSR);
2491 to = JME_SMB_BUSY_TIMEOUT;
2492 while ((val & SMBCSR_BUSY) && --to) {
2493 msleep(1);
2494 val = jread32(jme, JME_SMBCSR);
2495 }
2496 if (!to) {
2497 msg_hw(jme, "SMB Bus Busy.\n");
2498 return;
2499 }
2500
2501 jwrite32(jme, JME_SMBINTF,
2502 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2503 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2504 SMBINTF_HWRWN_WRITE |
2505 SMBINTF_HWCMD);
2506
2507 val = jread32(jme, JME_SMBINTF);
2508 to = JME_SMB_BUSY_TIMEOUT;
2509 while ((val & SMBINTF_HWCMD) && --to) {
2510 msleep(1);
2511 val = jread32(jme, JME_SMBINTF);
2512 }
2513 if (!to) {
2514 msg_hw(jme, "SMB Bus Busy.\n");
2515 return;
2516 }
2517
2518 mdelay(2);
2519 }
2520
2521 static int
2522 jme_get_eeprom_len(struct net_device *netdev)
2523 {
2524 struct jme_adapter *jme = netdev_priv(netdev);
2525 u32 val;
2526 val = jread32(jme, JME_SMBCSR);
2527 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2528 }
2529
2530 static int
2531 jme_get_eeprom(struct net_device *netdev,
2532 struct ethtool_eeprom *eeprom, u8 *data)
2533 {
2534 struct jme_adapter *jme = netdev_priv(netdev);
2535 int i, offset = eeprom->offset, len = eeprom->len;
2536
2537 /*
2538 * ethtool will check the boundary for us
2539 */
2540 eeprom->magic = JME_EEPROM_MAGIC;
2541 for (i = 0 ; i < len ; ++i)
2542 data[i] = jme_smb_read(jme, i + offset);
2543
2544 return 0;
2545 }
2546
2547 static int
2548 jme_set_eeprom(struct net_device *netdev,
2549 struct ethtool_eeprom *eeprom, u8 *data)
2550 {
2551 struct jme_adapter *jme = netdev_priv(netdev);
2552 int i, offset = eeprom->offset, len = eeprom->len;
2553
2554 if (eeprom->magic != JME_EEPROM_MAGIC)
2555 return -EINVAL;
2556
2557 /*
2558 * ethtool will check the boundary for us
2559 */
2560 for (i = 0 ; i < len ; ++i)
2561 jme_smb_write(jme, i + offset, data[i]);
2562
2563 return 0;
2564 }
2565
2566 static const struct ethtool_ops jme_ethtool_ops = {
2567 .get_drvinfo = jme_get_drvinfo,
2568 .get_regs_len = jme_get_regs_len,
2569 .get_regs = jme_get_regs,
2570 .get_coalesce = jme_get_coalesce,
2571 .set_coalesce = jme_set_coalesce,
2572 .get_pauseparam = jme_get_pauseparam,
2573 .set_pauseparam = jme_set_pauseparam,
2574 .get_wol = jme_get_wol,
2575 .set_wol = jme_set_wol,
2576 .get_settings = jme_get_settings,
2577 .set_settings = jme_set_settings,
2578 .get_link = jme_get_link,
2579 .get_msglevel = jme_get_msglevel,
2580 .set_msglevel = jme_set_msglevel,
2581 .get_rx_csum = jme_get_rx_csum,
2582 .set_rx_csum = jme_set_rx_csum,
2583 .set_tx_csum = jme_set_tx_csum,
2584 .set_tso = jme_set_tso,
2585 .set_sg = ethtool_op_set_sg,
2586 .nway_reset = jme_nway_reset,
2587 .get_eeprom_len = jme_get_eeprom_len,
2588 .get_eeprom = jme_get_eeprom,
2589 .set_eeprom = jme_set_eeprom,
2590 };
2591
2592 static int
2593 jme_pci_dma64(struct pci_dev *pdev)
2594 {
2595 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2596 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2597 return 1;
2598
2599 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2600 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2601 return 1;
2602
2603 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2604 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2605 return 0;
2606
2607 return -1;
2608 }
2609
2610 static inline void
2611 jme_phy_init(struct jme_adapter *jme)
2612 {
2613 u16 reg26;
2614
2615 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2616 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2617 }
2618
2619 static inline void
2620 jme_check_hw_ver(struct jme_adapter *jme)
2621 {
2622 u32 chipmode;
2623
2624 chipmode = jread32(jme, JME_CHIPMODE);
2625
2626 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2627 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2628 }
2629
2630 static int __devinit
2631 jme_init_one(struct pci_dev *pdev,
2632 const struct pci_device_id *ent)
2633 {
2634 int rc = 0, using_dac, i;
2635 struct net_device *netdev;
2636 struct jme_adapter *jme;
2637 u16 bmcr, bmsr;
2638 u32 apmc;
2639
2640 /*
2641 * set up PCI device basics
2642 */
2643 rc = pci_enable_device(pdev);
2644 if (rc) {
2645 jeprintk(pdev, "Cannot enable PCI device.\n");
2646 goto err_out;
2647 }
2648
2649 using_dac = jme_pci_dma64(pdev);
2650 if (using_dac < 0) {
2651 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2652 rc = -EIO;
2653 goto err_out_disable_pdev;
2654 }
2655
2656 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2657 jeprintk(pdev, "No PCI resource region found.\n");
2658 rc = -ENOMEM;
2659 goto err_out_disable_pdev;
2660 }
2661
2662 rc = pci_request_regions(pdev, DRV_NAME);
2663 if (rc) {
2664 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2665 goto err_out_disable_pdev;
2666 }
2667
2668 pci_set_master(pdev);
2669
2670 /*
2671 * alloc and init net device
2672 */
2673 netdev = alloc_etherdev(sizeof(*jme));
2674 if (!netdev) {
2675 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2676 rc = -ENOMEM;
2677 goto err_out_release_regions;
2678 }
2679 netdev->open = jme_open;
2680 netdev->stop = jme_close;
2681 netdev->hard_start_xmit = jme_start_xmit;
2682 netdev->set_mac_address = jme_set_macaddr;
2683 netdev->set_multicast_list = jme_set_multi;
2684 netdev->change_mtu = jme_change_mtu;
2685 netdev->ethtool_ops = &jme_ethtool_ops;
2686 netdev->tx_timeout = jme_tx_timeout;
2687 netdev->watchdog_timeo = TX_TIMEOUT;
2688 netdev->vlan_rx_register = jme_vlan_rx_register;
2689 NETDEV_GET_STATS(netdev, &jme_get_stats);
2690 netdev->features = NETIF_F_HW_CSUM |
2691 NETIF_F_SG |
2692 NETIF_F_TSO |
2693 NETIF_F_TSO6 |
2694 NETIF_F_HW_VLAN_TX |
2695 NETIF_F_HW_VLAN_RX;
2696 if (using_dac)
2697 netdev->features |= NETIF_F_HIGHDMA;
2698
2699 SET_NETDEV_DEV(netdev, &pdev->dev);
2700 pci_set_drvdata(pdev, netdev);
2701
2702 /*
2703 * init adapter info
2704 */
2705 jme = netdev_priv(netdev);
2706 jme->pdev = pdev;
2707 jme->dev = netdev;
2708 jme->jme_rx = netif_rx;
2709 jme->jme_vlan_rx = vlan_hwaccel_rx;
2710 jme->old_mtu = netdev->mtu = 1500;
2711 jme->phylink = 0;
2712 jme->tx_ring_size = 1 << 10;
2713 jme->tx_ring_mask = jme->tx_ring_size - 1;
2714 jme->tx_wake_threshold = 1 << 9;
2715 jme->rx_ring_size = 1 << 9;
2716 jme->rx_ring_mask = jme->rx_ring_size - 1;
2717 jme->msg_enable = JME_DEF_MSG_ENABLE;
2718 jme->regs = ioremap(pci_resource_start(pdev, 0),
2719 pci_resource_len(pdev, 0));
2720 if (!(jme->regs)) {
2721 jeprintk(pdev, "Mapping PCI resource region error.\n");
2722 rc = -ENOMEM;
2723 goto err_out_free_netdev;
2724 }
2725 jme->shadow_regs = pci_alloc_consistent(pdev,
2726 sizeof(u32) * SHADOW_REG_NR,
2727 &(jme->shadow_dma));
2728 if (!(jme->shadow_regs)) {
2729 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2730 rc = -ENOMEM;
2731 goto err_out_unmap;
2732 }
2733
2734 if (no_pseudohp) {
2735 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2736 jwrite32(jme, JME_APMC, apmc);
2737 } else if (force_pseudohp) {
2738 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2739 jwrite32(jme, JME_APMC, apmc);
2740 }
2741
2742 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2743
2744 spin_lock_init(&jme->phy_lock);
2745 spin_lock_init(&jme->macaddr_lock);
2746 spin_lock_init(&jme->rxmcs_lock);
2747
2748 atomic_set(&jme->link_changing, 1);
2749 atomic_set(&jme->rx_cleaning, 1);
2750 atomic_set(&jme->tx_cleaning, 1);
2751 atomic_set(&jme->rx_empty, 1);
2752
2753 tasklet_init(&jme->pcc_task,
2754 &jme_pcc_tasklet,
2755 (unsigned long) jme);
2756 tasklet_init(&jme->linkch_task,
2757 &jme_link_change_tasklet,
2758 (unsigned long) jme);
2759 tasklet_init(&jme->txclean_task,
2760 &jme_tx_clean_tasklet,
2761 (unsigned long) jme);
2762 tasklet_init(&jme->rxclean_task,
2763 &jme_rx_clean_tasklet,
2764 (unsigned long) jme);
2765 tasklet_init(&jme->rxempty_task,
2766 &jme_rx_empty_tasklet,
2767 (unsigned long) jme);
2768 tasklet_disable_nosync(&jme->txclean_task);
2769 tasklet_disable_nosync(&jme->rxclean_task);
2770 tasklet_disable_nosync(&jme->rxempty_task);
2771 jme->dpi.cur = PCC_P1;
2772
2773 jme->reg_ghc = 0;
2774 jme->reg_rxcs = RXCS_DEFAULT;
2775 jme->reg_rxmcs = RXMCS_DEFAULT;
2776 jme->reg_txpfc = 0;
2777 jme->reg_pmcs = PMCS_MFEN;
2778 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2779 set_bit(JME_FLAG_TSO, &jme->flags);
2780
2781 /*
2782 * Get Max Read Req Size from PCI Config Space
2783 */
2784 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2785 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2786 switch (jme->mrrs) {
2787 case MRRS_128B:
2788 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2789 break;
2790 case MRRS_256B:
2791 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2792 break;
2793 default:
2794 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2795 break;
2796 };
2797
2798 /*
2799 * Must check before reset_mac_processor
2800 */
2801 jme_check_hw_ver(jme);
2802 jme->mii_if.dev = netdev;
2803 if (jme->fpgaver) {
2804 jme->mii_if.phy_id = 0;
2805 for (i = 1 ; i < 32 ; ++i) {
2806 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2807 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2808 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2809 jme->mii_if.phy_id = i;
2810 break;
2811 }
2812 }
2813
2814 if (!jme->mii_if.phy_id) {
2815 rc = -EIO;
2816 jeprintk(pdev, "Can not find phy_id.\n");
2817 goto err_out_free_shadow;
2818 }
2819
2820 jme->reg_ghc |= GHC_LINK_POLL;
2821 } else {
2822 jme->mii_if.phy_id = 1;
2823 }
2824 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2825 jme->mii_if.supports_gmii = true;
2826 else
2827 jme->mii_if.supports_gmii = false;
2828 jme->mii_if.mdio_read = jme_mdio_read;
2829 jme->mii_if.mdio_write = jme_mdio_write;
2830
2831 jme_clear_pm(jme);
2832 jme_set_phyfifoa(jme);
2833 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2834 if (!jme->fpgaver)
2835 jme_phy_init(jme);
2836 jme_phy_off(jme);
2837
2838 /*
2839 * Reset MAC processor and reload EEPROM for MAC Address
2840 */
2841 jme_reset_mac_processor(jme);
2842 rc = jme_reload_eeprom(jme);
2843 if (rc) {
2844 jeprintk(pdev,
2845 "Reload eeprom for reading MAC Address error.\n");
2846 goto err_out_free_shadow;
2847 }
2848 jme_load_macaddr(netdev);
2849
2850 /*
2851 * Tell stack that we are not ready to work until open()
2852 */
2853 netif_carrier_off(netdev);
2854 netif_stop_queue(netdev);
2855
2856 /*
2857 * Register netdev
2858 */
2859 rc = register_netdev(netdev);
2860 if (rc) {
2861 jeprintk(pdev, "Cannot register net device.\n");
2862 goto err_out_free_shadow;
2863 }
2864
2865 msg_probe(jme,
2866 "JMC250 gigabit%s ver:%x rev:%x "
2867 "macaddr:%02x:%02x:%02x:%02x:%02x:%02x\n",
2868 (jme->fpgaver != 0) ? " (FPGA)" : "",
2869 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2870 jme->rev,
2871 netdev->dev_addr[0],
2872 netdev->dev_addr[1],
2873 netdev->dev_addr[2],
2874 netdev->dev_addr[3],
2875 netdev->dev_addr[4],
2876 netdev->dev_addr[5]);
2877
2878 return 0;
2879
2880 err_out_free_shadow:
2881 pci_free_consistent(pdev,
2882 sizeof(u32) * SHADOW_REG_NR,
2883 jme->shadow_regs,
2884 jme->shadow_dma);
2885 err_out_unmap:
2886 iounmap(jme->regs);
2887 err_out_free_netdev:
2888 pci_set_drvdata(pdev, NULL);
2889 free_netdev(netdev);
2890 err_out_release_regions:
2891 pci_release_regions(pdev);
2892 err_out_disable_pdev:
2893 pci_disable_device(pdev);
2894 err_out:
2895 return rc;
2896 }
2897
2898 static void __devexit
2899 jme_remove_one(struct pci_dev *pdev)
2900 {
2901 struct net_device *netdev = pci_get_drvdata(pdev);
2902 struct jme_adapter *jme = netdev_priv(netdev);
2903
2904 unregister_netdev(netdev);
2905 pci_free_consistent(pdev,
2906 sizeof(u32) * SHADOW_REG_NR,
2907 jme->shadow_regs,
2908 jme->shadow_dma);
2909 iounmap(jme->regs);
2910 pci_set_drvdata(pdev, NULL);
2911 free_netdev(netdev);
2912 pci_release_regions(pdev);
2913 pci_disable_device(pdev);
2914
2915 }
2916
2917 #ifdef CONFIG_PM
2918 static int
2919 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2920 {
2921 struct net_device *netdev = pci_get_drvdata(pdev);
2922 struct jme_adapter *jme = netdev_priv(netdev);
2923
2924 atomic_dec(&jme->link_changing);
2925
2926 netif_device_detach(netdev);
2927 netif_stop_queue(netdev);
2928 jme_stop_irq(jme);
2929
2930 tasklet_disable(&jme->txclean_task);
2931 tasklet_disable(&jme->rxclean_task);
2932 tasklet_disable(&jme->rxempty_task);
2933
2934 jme_disable_shadow(jme);
2935
2936 if (netif_carrier_ok(netdev)) {
2937 if (test_bit(JME_FLAG_POLL, &jme->flags))
2938 jme_polling_mode(jme);
2939
2940 jme_stop_pcc_timer(jme);
2941 jme_reset_ghc_speed(jme);
2942 jme_disable_rx_engine(jme);
2943 jme_disable_tx_engine(jme);
2944 jme_reset_mac_processor(jme);
2945 jme_free_rx_resources(jme);
2946 jme_free_tx_resources(jme);
2947 netif_carrier_off(netdev);
2948 jme->phylink = 0;
2949 }
2950
2951 tasklet_enable(&jme->txclean_task);
2952 tasklet_hi_enable(&jme->rxclean_task);
2953 tasklet_hi_enable(&jme->rxempty_task);
2954
2955 pci_save_state(pdev);
2956 if (jme->reg_pmcs) {
2957 jme_set_100m_half(jme);
2958
2959 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2960 jme_wait_link(jme);
2961
2962 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2963
2964 pci_enable_wake(pdev, PCI_D3cold, true);
2965 } else {
2966 jme_phy_off(jme);
2967 }
2968 pci_set_power_state(pdev, PCI_D3cold);
2969
2970 return 0;
2971 }
2972
2973 static int
2974 jme_resume(struct pci_dev *pdev)
2975 {
2976 struct net_device *netdev = pci_get_drvdata(pdev);
2977 struct jme_adapter *jme = netdev_priv(netdev);
2978
2979 jme_clear_pm(jme);
2980 pci_restore_state(pdev);
2981
2982 if (test_bit(JME_FLAG_SSET, &jme->flags))
2983 jme_set_settings(netdev, &jme->old_ecmd);
2984 else
2985 jme_reset_phy_processor(jme);
2986
2987 jme_enable_shadow(jme);
2988 jme_start_irq(jme);
2989 netif_device_attach(netdev);
2990
2991 atomic_inc(&jme->link_changing);
2992
2993 jme_reset_link(jme);
2994
2995 return 0;
2996 }
2997 #endif
2998
2999 static struct pci_device_id jme_pci_tbl[] = {
3000 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3001 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3002 { }
3003 };
3004
3005 static struct pci_driver jme_driver = {
3006 .name = DRV_NAME,
3007 .id_table = jme_pci_tbl,
3008 .probe = jme_init_one,
3009 .remove = __devexit_p(jme_remove_one),
3010 #ifdef CONFIG_PM
3011 .suspend = jme_suspend,
3012 .resume = jme_resume,
3013 #endif /* CONFIG_PM */
3014 };
3015
3016 static int __init
3017 jme_init_module(void)
3018 {
3019 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
3020 "driver version %s\n", DRV_VERSION);
3021 return pci_register_driver(&jme_driver);
3022 }
3023
3024 static void __exit
3025 jme_cleanup_module(void)
3026 {
3027 pci_unregister_driver(&jme_driver);
3028 }
3029
3030 module_init(jme_init_module);
3031 module_exit(jme_cleanup_module);
3032
3033 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3034 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3035 MODULE_LICENSE("GPL");
3036 MODULE_VERSION(DRV_VERSION);
3037 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3038
Stable & featurefull patchset based on Linus's git branch