include/asm-sh/mmu_context.h

   1 /*
   2  * Copyright (C) 1999 Niibe Yutaka
   3  * Copyright (C) 2003 - 2007 Paul Mundt
   4  *
   5  * ASID handling idea taken from MIPS implementation.
   6  */
   7 #ifndef __ASM_SH_MMU_CONTEXT_H
   8 #define __ASM_SH_MMU_CONTEXT_H
   9
  10 #ifdef __KERNEL__
  11 #include <asm/cpu/mmu_context.h>
  12 #include <asm/tlbflush.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/io.h>
  15 #include <asm-generic/mm_hooks.h>
  16
  17 /*
  18  * The MMU "context" consists of two things:
  19  *    (a) TLB cache version (or round, cycle whatever expression you like)
  20  *    (b) ASID (Address Space IDentifier)
  21  */
  22 #define MMU_CONTEXT_ASID_MASK           0x000000ff
  23 #define MMU_CONTEXT_VERSION_MASK        0xffffff00
  24 #define MMU_CONTEXT_FIRST_VERSION       0x00000100
  25 #define NO_CONTEXT                      0
  26
  27 /* ASID is 8-bit value, so it can't be 0x100 */
  28 #define MMU_NO_ASID                     0x100
  29
  30 #ifdef CONFIG_MMU
  31 #define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
  32 #define cpu_context(cpu, mm)    ((mm)->context.id[cpu])
  33
  34 #define cpu_asid(cpu, mm)       \
  35         (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)
  36
  37 /*
  38  * Virtual Page Number mask
  39  */
  40 #define MMU_VPN_MASK    0xfffff000
  41
  42 #if defined(CONFIG_SUPERH32)
  43 #include "mmu_context_32.h"
  44 #else
  45 #include "mmu_context_64.h"
  46 #endif
  47
  48 /*
  49  * Get MMU context if needed.
  50  */
  51 static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
  52 {
  53         unsigned long asid = asid_cache(cpu);
  54
  55         /* Check if we have old version of context. */
  56         if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
  57                 /* It's up to date, do nothing */
  58                 return;
  59
  60         /* It's old, we need to get new context with new version. */
  61         if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
  62                 /*
  63                  * We exhaust ASID of this version.
  64                  * Flush all TLB and start new cycle.
  65                  */
  66                 flush_tlb_all();
  67
  68 #ifdef CONFIG_SUPERH64
  69                 /*
  70                  * The SH-5 cache uses the ASIDs, requiring both the I and D
  71                  * cache to be flushed when the ASID is exhausted. Weak.
  72                  */
  73                 flush_cache_all();
  74 #endif
  75
  76                 /*
  77                  * Fix version; Note that we avoid version #0
  78                  * to distingush NO_CONTEXT.
  79                  */
  80                 if (!asid)
  81                         asid = MMU_CONTEXT_FIRST_VERSION;
  82         }
  83
  84         cpu_context(cpu, mm) = asid_cache(cpu) = asid;
  85 }
  86
  87 /*
  88  * Initialize the context related info for a new mm_struct
  89  * instance.
  90  */
  91 static inline int init_new_context(struct task_struct *tsk,
  92                                    struct mm_struct *mm)
  93 {
  94         int i;
  95
  96         for (i = 0; i < num_online_cpus(); i++)
  97                 cpu_context(i, mm) = NO_CONTEXT;
  98
  99         return 0;
 100 }
 101
 102 /*
 103  * After we have set current->mm to a new value, this activates
 104  * the context for the new mm so we see the new mappings.
 105  */
 106 static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
 107 {
 108         get_mmu_context(mm, cpu);
 109         set_asid(cpu_asid(cpu, mm));
 110 }
 111
 112 static inline void switch_mm(struct mm_struct *prev,
 113                              struct mm_struct *next,
 114                              struct task_struct *tsk)
 115 {
 116         unsigned int cpu = smp_processor_id();
 117
 118         if (likely(prev != next)) {
 119                 cpu_set(cpu, next->cpu_vm_mask);
 120                 set_TTB(next->pgd);
 121                 activate_context(next, cpu);
 122         } else
 123                 if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
 124                         activate_context(next, cpu);
 125 }
 126 #else
 127 #define get_mmu_context(mm)             do { } while (0)
 128 #define init_new_context(tsk,mm)        (0)
 129 #define destroy_context(mm)             do { } while (0)
 130 #define set_asid(asid)                  do { } while (0)
 131 #define get_asid()                      (0)
 132 #define cpu_asid(cpu, mm)               ({ (void)cpu; 0; })
 133 #define switch_and_save_asid(asid)      (0)
 134 #define set_TTB(pgd)                    do { } while (0)
 135 #define get_TTB()                       (0)
 136 #define activate_context(mm,cpu)        do { } while (0)
 137 #define switch_mm(prev,next,tsk)        do { } while (0)
 138 #endif /* CONFIG_MMU */
 139
 140 #define activate_mm(prev, next)         switch_mm((prev),(next),NULL)
 141 #define deactivate_mm(tsk,mm)           do { } while (0)
 142 #define enter_lazy_tlb(mm,tsk)          do { } while (0)
 143
 144 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
 145 /*
 146  * If this processor has an MMU, we need methods to turn it off/on ..
 147  * paging_init() will also have to be updated for the processor in
 148  * question.
 149  */
 150 static inline void enable_mmu(void)
 151 {
 152         unsigned int cpu = smp_processor_id();
 153
 154         /* Enable MMU */
 155         ctrl_outl(MMU_CONTROL_INIT, MMUCR);
 156         ctrl_barrier();
 157
 158         if (asid_cache(cpu) == NO_CONTEXT)
 159                 asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
 160
 161         set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
 162 }
 163
 164 static inline void disable_mmu(void)
 165 {
 166         unsigned long cr;
 167
 168         cr = ctrl_inl(MMUCR);
 169         cr &= ~MMU_CONTROL_INIT;
 170         ctrl_outl(cr, MMUCR);
 171
 172         ctrl_barrier();
 173 }
 174 #else
 175 /*
 176  * MMU control handlers for processors lacking memory
 177  * management hardware.
 178  */
 179 #define enable_mmu()    do { } while (0)
 180 #define disable_mmu()   do { } while (0)
 181 #endif
 182
 183 #endif /* __KERNEL__ */
 184 #endif /* __ASM_SH_MMU_CONTEXT_H */