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[PATCH] USB: Export IEEE-1284 device id in sysfs for usblp devices
[linux-2.6/zen-sources.git] / drivers / net / au1000_eth.c
blobcd0b1dccfb6102119334a357762b1c93502fec72
1 /*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
5 * Copyright 2001,2002,2003 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Author: MontaVista Software, Inc.
13 * ppopov@mvista.com or source@mvista.com
14 *
15 * ########################################################################
16 *
17 * This program is free software; you can distribute it and/or modify it
18 * under the terms of the GNU General Public License (Version 2) as
19 * published by the Free Software Foundation.
20 *
21 * This program is distributed in the hope it will be useful, but WITHOUT
22 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
29 *
30 * ########################################################################
31 *
32 *
33 */
34
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/string.h>
40 #include <linux/timer.h>
41 #include <linux/errno.h>
42 #include <linux/in.h>
43 #include <linux/ioport.h>
44 #include <linux/bitops.h>
45 #include <linux/slab.h>
46 #include <linux/interrupt.h>
47 #include <linux/pci.h>
48 #include <linux/init.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/ethtool.h>
52 #include <linux/mii.h>
53 #include <linux/skbuff.h>
54 #include <linux/delay.h>
55 #include <asm/mipsregs.h>
56 #include <asm/irq.h>
57 #include <asm/io.h>
58 #include <asm/processor.h>
59
60 #include <asm/mach-au1x00/au1000.h>
61 #include <asm/cpu.h>
62 #include "au1000_eth.h"
63
64 #ifdef AU1000_ETH_DEBUG
65 static int au1000_debug = 5;
66 #else
67 static int au1000_debug = 3;
68 #endif
69
70 #define DRV_NAME "au1000eth"
71 #define DRV_VERSION "1.5"
72 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
73 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
74
75 MODULE_AUTHOR(DRV_AUTHOR);
76 MODULE_DESCRIPTION(DRV_DESC);
77 MODULE_LICENSE("GPL");
78
79 // prototypes
80 static void hard_stop(struct net_device *);
81 static void enable_rx_tx(struct net_device *dev);
82 static struct net_device * au1000_probe(u32 ioaddr, int irq, int port_num);
83 static int au1000_init(struct net_device *);
84 static int au1000_open(struct net_device *);
85 static int au1000_close(struct net_device *);
86 static int au1000_tx(struct sk_buff *, struct net_device *);
87 static int au1000_rx(struct net_device *);
88 static irqreturn_t au1000_interrupt(int, void *, struct pt_regs *);
89 static void au1000_tx_timeout(struct net_device *);
90 static int au1000_set_config(struct net_device *dev, struct ifmap *map);
91 static void set_rx_mode(struct net_device *);
92 static struct net_device_stats *au1000_get_stats(struct net_device *);
93 static inline void update_tx_stats(struct net_device *, u32, u32);
94 static inline void update_rx_stats(struct net_device *, u32);
95 static void au1000_timer(unsigned long);
96 static int au1000_ioctl(struct net_device *, struct ifreq *, int);
97 static int mdio_read(struct net_device *, int, int);
98 static void mdio_write(struct net_device *, int, int, u16);
99 static void dump_mii(struct net_device *dev, int phy_id);
100
101 // externs
102 extern void ack_rise_edge_irq(unsigned int);
103 extern int get_ethernet_addr(char *ethernet_addr);
104 extern void str2eaddr(unsigned char *ea, unsigned char *str);
105 extern char * __init prom_getcmdline(void);
106
107 /*
108 * Theory of operation
109 *
110 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
111 * There are four receive and four transmit descriptors. These
112 * descriptors are not in memory; rather, they are just a set of
113 * hardware registers.
114 *
115 * Since the Au1000 has a coherent data cache, the receive and
116 * transmit buffers are allocated from the KSEG0 segment. The
117 * hardware registers, however, are still mapped at KSEG1 to
118 * make sure there's no out-of-order writes, and that all writes
119 * complete immediately.
120 */
121
122 /* These addresses are only used if yamon doesn't tell us what
123 * the mac address is, and the mac address is not passed on the
124 * command line.
125 */
126 static unsigned char au1000_mac_addr[6] __devinitdata = {
127 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
128 };
129
130 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
131 #define RUN_AT(x) (jiffies + (x))
132
133 // For reading/writing 32-bit words from/to DMA memory
134 #define cpu_to_dma32 cpu_to_be32
135 #define dma32_to_cpu be32_to_cpu
136
137 struct au1000_private *au_macs[NUM_ETH_INTERFACES];
138
139 /* FIXME
140 * All of the PHY code really should be detached from the MAC
141 * code.
142 */
143
144 /* Default advertise */
145 #define GENMII_DEFAULT_ADVERTISE \
146 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
147 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
148 ADVERTISED_Autoneg
149
150 #define GENMII_DEFAULT_FEATURES \
151 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
152 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
153 SUPPORTED_Autoneg
154
155 int bcm_5201_init(struct net_device *dev, int phy_addr)
156 {
157 s16 data;
158
159 /* Stop auto-negotiation */
160 data = mdio_read(dev, phy_addr, MII_CONTROL);
161 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
162
163 /* Set advertisement to 10/100 and Half/Full duplex
164 * (full capabilities) */
165 data = mdio_read(dev, phy_addr, MII_ANADV);
166 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
167 mdio_write(dev, phy_addr, MII_ANADV, data);
168
169 /* Restart auto-negotiation */
170 data = mdio_read(dev, phy_addr, MII_CONTROL);
171 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
172 mdio_write(dev, phy_addr, MII_CONTROL, data);
173
174 if (au1000_debug > 4)
175 dump_mii(dev, phy_addr);
176 return 0;
177 }
178
179 int bcm_5201_reset(struct net_device *dev, int phy_addr)
180 {
181 s16 mii_control, timeout;
182
183 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
184 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
185 mdelay(1);
186 for (timeout = 100; timeout > 0; --timeout) {
187 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
188 if ((mii_control & MII_CNTL_RESET) == 0)
189 break;
190 mdelay(1);
191 }
192 if (mii_control & MII_CNTL_RESET) {
193 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
194 return -1;
195 }
196 return 0;
197 }
198
199 int
200 bcm_5201_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
201 {
202 u16 mii_data;
203 struct au1000_private *aup;
204
205 if (!dev) {
206 printk(KERN_ERR "bcm_5201_status error: NULL dev\n");
207 return -1;
208 }
209 aup = (struct au1000_private *) dev->priv;
210
211 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
212 if (mii_data & MII_STAT_LINK) {
213 *link = 1;
214 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
215 if (mii_data & MII_AUX_100) {
216 if (mii_data & MII_AUX_FDX) {
217 *speed = IF_PORT_100BASEFX;
218 dev->if_port = IF_PORT_100BASEFX;
219 }
220 else {
221 *speed = IF_PORT_100BASETX;
222 dev->if_port = IF_PORT_100BASETX;
223 }
224 }
225 else {
226 *speed = IF_PORT_10BASET;
227 dev->if_port = IF_PORT_10BASET;
228 }
229
230 }
231 else {
232 *link = 0;
233 *speed = 0;
234 dev->if_port = IF_PORT_UNKNOWN;
235 }
236 return 0;
237 }
238
239 int lsi_80227_init(struct net_device *dev, int phy_addr)
240 {
241 if (au1000_debug > 4)
242 printk("lsi_80227_init\n");
243
244 /* restart auto-negotiation */
245 mdio_write(dev, phy_addr, MII_CONTROL,
246 MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_RST_AUTO); // | MII_CNTL_FDX);
247 mdelay(1);
248
249 /* set up LEDs to correct display */
250 #ifdef CONFIG_MIPS_MTX1
251 mdio_write(dev, phy_addr, 17, 0xff80);
252 #else
253 mdio_write(dev, phy_addr, 17, 0xffc0);
254 #endif
255
256 if (au1000_debug > 4)
257 dump_mii(dev, phy_addr);
258 return 0;
259 }
260
261 int lsi_80227_reset(struct net_device *dev, int phy_addr)
262 {
263 s16 mii_control, timeout;
264
265 if (au1000_debug > 4) {
266 printk("lsi_80227_reset\n");
267 dump_mii(dev, phy_addr);
268 }
269
270 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
271 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
272 mdelay(1);
273 for (timeout = 100; timeout > 0; --timeout) {
274 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
275 if ((mii_control & MII_CNTL_RESET) == 0)
276 break;
277 mdelay(1);
278 }
279 if (mii_control & MII_CNTL_RESET) {
280 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
281 return -1;
282 }
283 return 0;
284 }
285
286 int
287 lsi_80227_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
288 {
289 u16 mii_data;
290 struct au1000_private *aup;
291
292 if (!dev) {
293 printk(KERN_ERR "lsi_80227_status error: NULL dev\n");
294 return -1;
295 }
296 aup = (struct au1000_private *) dev->priv;
297
298 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
299 if (mii_data & MII_STAT_LINK) {
300 *link = 1;
301 mii_data = mdio_read(dev, aup->phy_addr, MII_LSI_PHY_STAT);
302 if (mii_data & MII_LSI_PHY_STAT_SPD) {
303 if (mii_data & MII_LSI_PHY_STAT_FDX) {
304 *speed = IF_PORT_100BASEFX;
305 dev->if_port = IF_PORT_100BASEFX;
306 }
307 else {
308 *speed = IF_PORT_100BASETX;
309 dev->if_port = IF_PORT_100BASETX;
310 }
311 }
312 else {
313 *speed = IF_PORT_10BASET;
314 dev->if_port = IF_PORT_10BASET;
315 }
316
317 }
318 else {
319 *link = 0;
320 *speed = 0;
321 dev->if_port = IF_PORT_UNKNOWN;
322 }
323 return 0;
324 }
325
326 int am79c901_init(struct net_device *dev, int phy_addr)
327 {
328 printk("am79c901_init\n");
329 return 0;
330 }
331
332 int am79c901_reset(struct net_device *dev, int phy_addr)
333 {
334 printk("am79c901_reset\n");
335 return 0;
336 }
337
338 int
339 am79c901_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
340 {
341 return 0;
342 }
343
344 int am79c874_init(struct net_device *dev, int phy_addr)
345 {
346 s16 data;
347
348 /* 79c874 has quit resembled bit assignments to BCM5201 */
349 if (au1000_debug > 4)
350 printk("am79c847_init\n");
351
352 /* Stop auto-negotiation */
353 data = mdio_read(dev, phy_addr, MII_CONTROL);
354 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
355
356 /* Set advertisement to 10/100 and Half/Full duplex
357 * (full capabilities) */
358 data = mdio_read(dev, phy_addr, MII_ANADV);
359 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
360 mdio_write(dev, phy_addr, MII_ANADV, data);
361
362 /* Restart auto-negotiation */
363 data = mdio_read(dev, phy_addr, MII_CONTROL);
364 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
365
366 mdio_write(dev, phy_addr, MII_CONTROL, data);
367
368 if (au1000_debug > 4) dump_mii(dev, phy_addr);
369 return 0;
370 }
371
372 int am79c874_reset(struct net_device *dev, int phy_addr)
373 {
374 s16 mii_control, timeout;
375
376 if (au1000_debug > 4)
377 printk("am79c874_reset\n");
378
379 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
380 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
381 mdelay(1);
382 for (timeout = 100; timeout > 0; --timeout) {
383 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
384 if ((mii_control & MII_CNTL_RESET) == 0)
385 break;
386 mdelay(1);
387 }
388 if (mii_control & MII_CNTL_RESET) {
389 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
390 return -1;
391 }
392 return 0;
393 }
394
395 int
396 am79c874_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
397 {
398 u16 mii_data;
399 struct au1000_private *aup;
400
401 // printk("am79c874_status\n");
402 if (!dev) {
403 printk(KERN_ERR "am79c874_status error: NULL dev\n");
404 return -1;
405 }
406
407 aup = (struct au1000_private *) dev->priv;
408 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
409
410 if (mii_data & MII_STAT_LINK) {
411 *link = 1;
412 mii_data = mdio_read(dev, aup->phy_addr, MII_AMD_PHY_STAT);
413 if (mii_data & MII_AMD_PHY_STAT_SPD) {
414 if (mii_data & MII_AMD_PHY_STAT_FDX) {
415 *speed = IF_PORT_100BASEFX;
416 dev->if_port = IF_PORT_100BASEFX;
417 }
418 else {
419 *speed = IF_PORT_100BASETX;
420 dev->if_port = IF_PORT_100BASETX;
421 }
422 }
423 else {
424 *speed = IF_PORT_10BASET;
425 dev->if_port = IF_PORT_10BASET;
426 }
427
428 }
429 else {
430 *link = 0;
431 *speed = 0;
432 dev->if_port = IF_PORT_UNKNOWN;
433 }
434 return 0;
435 }
436
437 int lxt971a_init(struct net_device *dev, int phy_addr)
438 {
439 if (au1000_debug > 4)
440 printk("lxt971a_init\n");
441
442 /* restart auto-negotiation */
443 mdio_write(dev, phy_addr, MII_CONTROL,
444 MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_RST_AUTO | MII_CNTL_FDX);
445
446 /* set up LEDs to correct display */
447 mdio_write(dev, phy_addr, 20, 0x0422);
448
449 if (au1000_debug > 4)
450 dump_mii(dev, phy_addr);
451 return 0;
452 }
453
454 int lxt971a_reset(struct net_device *dev, int phy_addr)
455 {
456 s16 mii_control, timeout;
457
458 if (au1000_debug > 4) {
459 printk("lxt971a_reset\n");
460 dump_mii(dev, phy_addr);
461 }
462
463 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
464 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
465 mdelay(1);
466 for (timeout = 100; timeout > 0; --timeout) {
467 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
468 if ((mii_control & MII_CNTL_RESET) == 0)
469 break;
470 mdelay(1);
471 }
472 if (mii_control & MII_CNTL_RESET) {
473 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
474 return -1;
475 }
476 return 0;
477 }
478
479 int
480 lxt971a_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
481 {
482 u16 mii_data;
483 struct au1000_private *aup;
484
485 if (!dev) {
486 printk(KERN_ERR "lxt971a_status error: NULL dev\n");
487 return -1;
488 }
489 aup = (struct au1000_private *) dev->priv;
490
491 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
492 if (mii_data & MII_STAT_LINK) {
493 *link = 1;
494 mii_data = mdio_read(dev, aup->phy_addr, MII_INTEL_PHY_STAT);
495 if (mii_data & MII_INTEL_PHY_STAT_SPD) {
496 if (mii_data & MII_INTEL_PHY_STAT_FDX) {
497 *speed = IF_PORT_100BASEFX;
498 dev->if_port = IF_PORT_100BASEFX;
499 }
500 else {
501 *speed = IF_PORT_100BASETX;
502 dev->if_port = IF_PORT_100BASETX;
503 }
504 }
505 else {
506 *speed = IF_PORT_10BASET;
507 dev->if_port = IF_PORT_10BASET;
508 }
509
510 }
511 else {
512 *link = 0;
513 *speed = 0;
514 dev->if_port = IF_PORT_UNKNOWN;
515 }
516 return 0;
517 }
518
519 int ks8995m_init(struct net_device *dev, int phy_addr)
520 {
521 s16 data;
522
523 // printk("ks8995m_init\n");
524 /* Stop auto-negotiation */
525 data = mdio_read(dev, phy_addr, MII_CONTROL);
526 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
527
528 /* Set advertisement to 10/100 and Half/Full duplex
529 * (full capabilities) */
530 data = mdio_read(dev, phy_addr, MII_ANADV);
531 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
532 mdio_write(dev, phy_addr, MII_ANADV, data);
533
534 /* Restart auto-negotiation */
535 data = mdio_read(dev, phy_addr, MII_CONTROL);
536 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
537 mdio_write(dev, phy_addr, MII_CONTROL, data);
538
539 if (au1000_debug > 4) dump_mii(dev, phy_addr);
540
541 return 0;
542 }
543
544 int ks8995m_reset(struct net_device *dev, int phy_addr)
545 {
546 s16 mii_control, timeout;
547
548 // printk("ks8995m_reset\n");
549 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
550 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
551 mdelay(1);
552 for (timeout = 100; timeout > 0; --timeout) {
553 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
554 if ((mii_control & MII_CNTL_RESET) == 0)
555 break;
556 mdelay(1);
557 }
558 if (mii_control & MII_CNTL_RESET) {
559 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
560 return -1;
561 }
562 return 0;
563 }
564
565 int ks8995m_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
566 {
567 u16 mii_data;
568 struct au1000_private *aup;
569
570 if (!dev) {
571 printk(KERN_ERR "ks8995m_status error: NULL dev\n");
572 return -1;
573 }
574 aup = (struct au1000_private *) dev->priv;
575
576 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
577 if (mii_data & MII_STAT_LINK) {
578 *link = 1;
579 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
580 if (mii_data & MII_AUX_100) {
581 if (mii_data & MII_AUX_FDX) {
582 *speed = IF_PORT_100BASEFX;
583 dev->if_port = IF_PORT_100BASEFX;
584 }
585 else {
586 *speed = IF_PORT_100BASETX;
587 dev->if_port = IF_PORT_100BASETX;
588 }
589 }
590 else {
591 *speed = IF_PORT_10BASET;
592 dev->if_port = IF_PORT_10BASET;
593 }
594
595 }
596 else {
597 *link = 0;
598 *speed = 0;
599 dev->if_port = IF_PORT_UNKNOWN;
600 }
601 return 0;
602 }
603
604 int
605 smsc_83C185_init (struct net_device *dev, int phy_addr)
606 {
607 s16 data;
608
609 if (au1000_debug > 4)
610 printk("smsc_83C185_init\n");
611
612 /* Stop auto-negotiation */
613 data = mdio_read(dev, phy_addr, MII_CONTROL);
614 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
615
616 /* Set advertisement to 10/100 and Half/Full duplex
617 * (full capabilities) */
618 data = mdio_read(dev, phy_addr, MII_ANADV);
619 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
620 mdio_write(dev, phy_addr, MII_ANADV, data);
621
622 /* Restart auto-negotiation */
623 data = mdio_read(dev, phy_addr, MII_CONTROL);
624 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
625
626 mdio_write(dev, phy_addr, MII_CONTROL, data);
627
628 if (au1000_debug > 4) dump_mii(dev, phy_addr);
629 return 0;
630 }
631
632 int
633 smsc_83C185_reset (struct net_device *dev, int phy_addr)
634 {
635 s16 mii_control, timeout;
636
637 if (au1000_debug > 4)
638 printk("smsc_83C185_reset\n");
639
640 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
641 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
642 mdelay(1);
643 for (timeout = 100; timeout > 0; --timeout) {
644 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
645 if ((mii_control & MII_CNTL_RESET) == 0)
646 break;
647 mdelay(1);
648 }
649 if (mii_control & MII_CNTL_RESET) {
650 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
651 return -1;
652 }
653 return 0;
654 }
655
656 int
657 smsc_83C185_status (struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
658 {
659 u16 mii_data;
660 struct au1000_private *aup;
661
662 if (!dev) {
663 printk(KERN_ERR "smsc_83C185_status error: NULL dev\n");
664 return -1;
665 }
666
667 aup = (struct au1000_private *) dev->priv;
668 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
669
670 if (mii_data & MII_STAT_LINK) {
671 *link = 1;
672 mii_data = mdio_read(dev, aup->phy_addr, 0x1f);
673 if (mii_data & (1<<3)) {
674 if (mii_data & (1<<4)) {
675 *speed = IF_PORT_100BASEFX;
676 dev->if_port = IF_PORT_100BASEFX;
677 }
678 else {
679 *speed = IF_PORT_100BASETX;
680 dev->if_port = IF_PORT_100BASETX;
681 }
682 }
683 else {
684 *speed = IF_PORT_10BASET;
685 dev->if_port = IF_PORT_10BASET;
686 }
687 }
688 else {
689 *link = 0;
690 *speed = 0;
691 dev->if_port = IF_PORT_UNKNOWN;
692 }
693 return 0;
694 }
695
696
697 #ifdef CONFIG_MIPS_BOSPORUS
698 int stub_init(struct net_device *dev, int phy_addr)
699 {
700 //printk("PHY stub_init\n");
701 return 0;
702 }
703
704 int stub_reset(struct net_device *dev, int phy_addr)
705 {
706 //printk("PHY stub_reset\n");
707 return 0;
708 }
709
710 int
711 stub_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
712 {
713 //printk("PHY stub_status\n");
714 *link = 1;
715 /* hmmm, revisit */
716 *speed = IF_PORT_100BASEFX;
717 dev->if_port = IF_PORT_100BASEFX;
718 return 0;
719 }
720 #endif
721
722 struct phy_ops bcm_5201_ops = {
723 bcm_5201_init,
724 bcm_5201_reset,
725 bcm_5201_status,
726 };
727
728 struct phy_ops am79c874_ops = {
729 am79c874_init,
730 am79c874_reset,
731 am79c874_status,
732 };
733
734 struct phy_ops am79c901_ops = {
735 am79c901_init,
736 am79c901_reset,
737 am79c901_status,
738 };
739
740 struct phy_ops lsi_80227_ops = {
741 lsi_80227_init,
742 lsi_80227_reset,
743 lsi_80227_status,
744 };
745
746 struct phy_ops lxt971a_ops = {
747 lxt971a_init,
748 lxt971a_reset,
749 lxt971a_status,
750 };
751
752 struct phy_ops ks8995m_ops = {
753 ks8995m_init,
754 ks8995m_reset,
755 ks8995m_status,
756 };
757
758 struct phy_ops smsc_83C185_ops = {
759 smsc_83C185_init,
760 smsc_83C185_reset,
761 smsc_83C185_status,
762 };
763
764 #ifdef CONFIG_MIPS_BOSPORUS
765 struct phy_ops stub_ops = {
766 stub_init,
767 stub_reset,
768 stub_status,
769 };
770 #endif
771
772 static struct mii_chip_info {
773 const char * name;
774 u16 phy_id0;
775 u16 phy_id1;
776 struct phy_ops *phy_ops;
777 int dual_phy;
778 } mii_chip_table[] = {
779 {"Broadcom BCM5201 10/100 BaseT PHY",0x0040,0x6212, &bcm_5201_ops,0},
780 {"Broadcom BCM5221 10/100 BaseT PHY",0x0040,0x61e4, &bcm_5201_ops,0},
781 {"Broadcom BCM5222 10/100 BaseT PHY",0x0040,0x6322, &bcm_5201_ops,1},
782 {"NS DP83847 PHY", 0x2000, 0x5c30, &bcm_5201_ops ,0},
783 {"AMD 79C901 HomePNA PHY",0x0000,0x35c8, &am79c901_ops,0},
784 {"AMD 79C874 10/100 BaseT PHY",0x0022,0x561b, &am79c874_ops,0},
785 {"LSI 80227 10/100 BaseT PHY",0x0016,0xf840, &lsi_80227_ops,0},
786 {"Intel LXT971A Dual Speed PHY",0x0013,0x78e2, &lxt971a_ops,0},
787 {"Kendin KS8995M 10/100 BaseT PHY",0x0022,0x1450, &ks8995m_ops,0},
788 {"SMSC LAN83C185 10/100 BaseT PHY",0x0007,0xc0a3, &smsc_83C185_ops,0},
789 #ifdef CONFIG_MIPS_BOSPORUS
790 {"Stub", 0x1234, 0x5678, &stub_ops },
791 #endif
792 {0,},
793 };
794
795 static int mdio_read(struct net_device *dev, int phy_id, int reg)
796 {
797 struct au1000_private *aup = (struct au1000_private *) dev->priv;
798 volatile u32 *mii_control_reg;
799 volatile u32 *mii_data_reg;
800 u32 timedout = 20;
801 u32 mii_control;
802
803 #ifdef CONFIG_BCM5222_DUAL_PHY
804 /* First time we probe, it's for the mac0 phy.
805 * Since we haven't determined yet that we have a dual phy,
806 * aup->mii->mii_control_reg won't be setup and we'll
807 * default to the else statement.
808 * By the time we probe for the mac1 phy, the mii_control_reg
809 * will be setup to be the address of the mac0 phy control since
810 * both phys are controlled through mac0.
811 */
812 if (aup->mii && aup->mii->mii_control_reg) {
813 mii_control_reg = aup->mii->mii_control_reg;
814 mii_data_reg = aup->mii->mii_data_reg;
815 }
816 else if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
817 /* assume both phys are controlled through mac0 */
818 mii_control_reg = au_macs[0]->mii->mii_control_reg;
819 mii_data_reg = au_macs[0]->mii->mii_data_reg;
820 }
821 else
822 #endif
823 {
824 /* default control and data reg addresses */
825 mii_control_reg = &aup->mac->mii_control;
826 mii_data_reg = &aup->mac->mii_data;
827 }
828
829 while (*mii_control_reg & MAC_MII_BUSY) {
830 mdelay(1);
831 if (--timedout == 0) {
832 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
833 dev->name);
834 return -1;
835 }
836 }
837
838 mii_control = MAC_SET_MII_SELECT_REG(reg) |
839 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_READ;
840
841 *mii_control_reg = mii_control;
842
843 timedout = 20;
844 while (*mii_control_reg & MAC_MII_BUSY) {
845 mdelay(1);
846 if (--timedout == 0) {
847 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
848 dev->name);
849 return -1;
850 }
851 }
852 return (int)*mii_data_reg;
853 }
854
855 static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 value)
856 {
857 struct au1000_private *aup = (struct au1000_private *) dev->priv;
858 volatile u32 *mii_control_reg;
859 volatile u32 *mii_data_reg;
860 u32 timedout = 20;
861 u32 mii_control;
862
863 #ifdef CONFIG_BCM5222_DUAL_PHY
864 if (aup->mii && aup->mii->mii_control_reg) {
865 mii_control_reg = aup->mii->mii_control_reg;
866 mii_data_reg = aup->mii->mii_data_reg;
867 }
868 else if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
869 /* assume both phys are controlled through mac0 */
870 mii_control_reg = au_macs[0]->mii->mii_control_reg;
871 mii_data_reg = au_macs[0]->mii->mii_data_reg;
872 }
873 else
874 #endif
875 {
876 /* default control and data reg addresses */
877 mii_control_reg = &aup->mac->mii_control;
878 mii_data_reg = &aup->mac->mii_data;
879 }
880
881 while (*mii_control_reg & MAC_MII_BUSY) {
882 mdelay(1);
883 if (--timedout == 0) {
884 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
885 dev->name);
886 return;
887 }
888 }
889
890 mii_control = MAC_SET_MII_SELECT_REG(reg) |
891 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_WRITE;
892
893 *mii_data_reg = value;
894 *mii_control_reg = mii_control;
895 }
896
897
898 static void dump_mii(struct net_device *dev, int phy_id)
899 {
900 int i, val;
901
902 for (i = 0; i < 7; i++) {
903 if ((val = mdio_read(dev, phy_id, i)) >= 0)
904 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
905 }
906 for (i = 16; i < 25; i++) {
907 if ((val = mdio_read(dev, phy_id, i)) >= 0)
908 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
909 }
910 }
911
912 static int mii_probe (struct net_device * dev)
913 {
914 struct au1000_private *aup = (struct au1000_private *) dev->priv;
915 int phy_addr;
916 #ifdef CONFIG_MIPS_BOSPORUS
917 int phy_found=0;
918 #endif
919
920 /* search for total of 32 possible mii phy addresses */
921 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
922 u16 mii_status;
923 u16 phy_id0, phy_id1;
924 int i;
925
926 #ifdef CONFIG_BCM5222_DUAL_PHY
927 /* Mask the already found phy, try next one */
928 if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
929 if (au_macs[0]->phy_addr == phy_addr)
930 continue;
931 }
932 #endif
933
934 mii_status = mdio_read(dev, phy_addr, MII_STATUS);
935 if (mii_status == 0xffff || mii_status == 0x0000)
936 /* the mii is not accessable, try next one */
937 continue;
938
939 phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0);
940 phy_id1 = mdio_read(dev, phy_addr, MII_PHY_ID1);
941
942 /* search our mii table for the current mii */
943 for (i = 0; mii_chip_table[i].phy_id1; i++) {
944 if (phy_id0 == mii_chip_table[i].phy_id0 &&
945 phy_id1 == mii_chip_table[i].phy_id1) {
946 struct mii_phy * mii_phy = aup->mii;
947
948 printk(KERN_INFO "%s: %s at phy address %d\n",
949 dev->name, mii_chip_table[i].name,
950 phy_addr);
951 #ifdef CONFIG_MIPS_BOSPORUS
952 phy_found = 1;
953 #endif
954 mii_phy->chip_info = mii_chip_table+i;
955 aup->phy_addr = phy_addr;
956 aup->want_autoneg = 1;
957 aup->phy_ops = mii_chip_table[i].phy_ops;
958 aup->phy_ops->phy_init(dev,phy_addr);
959
960 // Check for dual-phy and then store required
961 // values and set indicators. We need to do
962 // this now since mdio_{read,write} need the
963 // control and data register addresses.
964 #ifdef CONFIG_BCM5222_DUAL_PHY
965 if ( mii_chip_table[i].dual_phy) {
966
967 /* assume both phys are controlled
968 * through MAC0. Board specific? */
969
970 /* sanity check */
971 if (!au_macs[0] || !au_macs[0]->mii)
972 return -1;
973 aup->mii->mii_control_reg = (u32 *)
974 &au_macs[0]->mac->mii_control;
975 aup->mii->mii_data_reg = (u32 *)
976 &au_macs[0]->mac->mii_data;
977 }
978 #endif
979 goto found;
980 }
981 }
982 }
983 found:
984
985 #ifdef CONFIG_MIPS_BOSPORUS
986 /* This is a workaround for the Micrel/Kendin 5 port switch
987 The second MAC doesn't see a PHY connected... so we need to
988 trick it into thinking we have one.
989
990 If this kernel is run on another Au1500 development board
991 the stub will be found as well as the actual PHY. However,
992 the last found PHY will be used... usually at Addr 31 (Db1500).
993 */
994 if ( (!phy_found) )
995 {
996 u16 phy_id0, phy_id1;
997 int i;
998
999 phy_id0 = 0x1234;
1000 phy_id1 = 0x5678;
1001
1002 /* search our mii table for the current mii */
1003 for (i = 0; mii_chip_table[i].phy_id1; i++) {
1004 if (phy_id0 == mii_chip_table[i].phy_id0 &&
1005 phy_id1 == mii_chip_table[i].phy_id1) {
1006 struct mii_phy * mii_phy;
1007
1008 printk(KERN_INFO "%s: %s at phy address %d\n",
1009 dev->name, mii_chip_table[i].name,
1010 phy_addr);
1011 mii_phy = kmalloc(sizeof(struct mii_phy),
1012 GFP_KERNEL);
1013 if (mii_phy) {
1014 mii_phy->chip_info = mii_chip_table+i;
1015 aup->phy_addr = phy_addr;
1016 mii_phy->next = aup->mii;
1017 aup->phy_ops =
1018 mii_chip_table[i].phy_ops;
1019 aup->mii = mii_phy;
1020 aup->phy_ops->phy_init(dev,phy_addr);
1021 } else {
1022 printk(KERN_ERR "%s: out of memory\n",
1023 dev->name);
1024 return -1;
1025 }
1026 mii_phy->chip_info = mii_chip_table+i;
1027 aup->phy_addr = phy_addr;
1028 aup->phy_ops = mii_chip_table[i].phy_ops;
1029 aup->phy_ops->phy_init(dev,phy_addr);
1030 break;
1031 }
1032 }
1033 }
1034 if (aup->mac_id == 0) {
1035 /* the Bosporus phy responds to addresses 0-5 but
1036 * 5 is the correct one.
1037 */
1038 aup->phy_addr = 5;
1039 }
1040 #endif
1041
1042 if (aup->mii->chip_info == NULL) {
1043 printk(KERN_ERR "%s: Au1x No known MII transceivers found!\n",
1044 dev->name);
1045 return -1;
1046 }
1047
1048 printk(KERN_INFO "%s: Using %s as default\n",
1049 dev->name, aup->mii->chip_info->name);
1050
1051 return 0;
1052 }
1053
1054
1055 /*
1056 * Buffer allocation/deallocation routines. The buffer descriptor returned
1057 * has the virtual and dma address of a buffer suitable for
1058 * both, receive and transmit operations.
1059 */
1060 static db_dest_t *GetFreeDB(struct au1000_private *aup)
1061 {
1062 db_dest_t *pDB;
1063 pDB = aup->pDBfree;
1064
1065 if (pDB) {
1066 aup->pDBfree = pDB->pnext;
1067 }
1068 return pDB;
1069 }
1070
1071 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
1072 {
1073 db_dest_t *pDBfree = aup->pDBfree;
1074 if (pDBfree)
1075 pDBfree->pnext = pDB;
1076 aup->pDBfree = pDB;
1077 }
1078
1079 static void enable_rx_tx(struct net_device *dev)
1080 {
1081 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1082
1083 if (au1000_debug > 4)
1084 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
1085
1086 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
1087 au_sync_delay(10);
1088 }
1089
1090 static void hard_stop(struct net_device *dev)
1091 {
1092 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1093
1094 if (au1000_debug > 4)
1095 printk(KERN_INFO "%s: hard stop\n", dev->name);
1096
1097 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
1098 au_sync_delay(10);
1099 }
1100
1101
1102 static void reset_mac(struct net_device *dev)
1103 {
1104 int i;
1105 u32 flags;
1106 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1107
1108 if (au1000_debug > 4)
1109 printk(KERN_INFO "%s: reset mac, aup %x\n",
1110 dev->name, (unsigned)aup);
1111
1112 spin_lock_irqsave(&aup->lock, flags);
1113 if (aup->timer.function == &au1000_timer) {/* check if timer initted */
1114 del_timer(&aup->timer);
1115 }
1116
1117 hard_stop(dev);
1118 #ifdef CONFIG_BCM5222_DUAL_PHY
1119 if (aup->mac_id != 0) {
1120 #endif
1121 /* If BCM5222, we can't leave MAC0 in reset because then
1122 * we can't access the dual phy for ETH1 */
1123 *aup->enable = MAC_EN_CLOCK_ENABLE;
1124 au_sync_delay(2);
1125 *aup->enable = 0;
1126 au_sync_delay(2);
1127 #ifdef CONFIG_BCM5222_DUAL_PHY
1128 }
1129 #endif
1130 aup->tx_full = 0;
1131 for (i = 0; i < NUM_RX_DMA; i++) {
1132 /* reset control bits */
1133 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
1134 }
1135 for (i = 0; i < NUM_TX_DMA; i++) {
1136 /* reset control bits */
1137 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
1138 }
1139 spin_unlock_irqrestore(&aup->lock, flags);
1140 }
1141
1142
1143 /*
1144 * Setup the receive and transmit "rings". These pointers are the addresses
1145 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
1146 * these are not descriptors sitting in memory.
1147 */
1148 static void
1149 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
1150 {
1151 int i;
1152
1153 for (i = 0; i < NUM_RX_DMA; i++) {
1154 aup->rx_dma_ring[i] =
1155 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
1156 }
1157 for (i = 0; i < NUM_TX_DMA; i++) {
1158 aup->tx_dma_ring[i] =
1159 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
1160 }
1161 }
1162
1163 static struct {
1164 int port;
1165 u32 base_addr;
1166 u32 macen_addr;
1167 int irq;
1168 struct net_device *dev;
1169 } iflist[2];
1170
1171 static int num_ifs;
1172
1173 /*
1174 * Setup the base address and interupt of the Au1xxx ethernet macs
1175 * based on cpu type and whether the interface is enabled in sys_pinfunc
1176 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
1177 */
1178 static int __init au1000_init_module(void)
1179 {
1180 struct cpuinfo_mips *c = &current_cpu_data;
1181 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
1182 struct net_device *dev;
1183 int i, found_one = 0;
1184
1185 switch (c->cputype) {
1186 #ifdef CONFIG_SOC_AU1000
1187 case CPU_AU1000:
1188 num_ifs = 2 - ni;
1189 iflist[0].base_addr = AU1000_ETH0_BASE;
1190 iflist[1].base_addr = AU1000_ETH1_BASE;
1191 iflist[0].macen_addr = AU1000_MAC0_ENABLE;
1192 iflist[1].macen_addr = AU1000_MAC1_ENABLE;
1193 iflist[0].irq = AU1000_MAC0_DMA_INT;
1194 iflist[1].irq = AU1000_MAC1_DMA_INT;
1195 break;
1196 #endif
1197 #ifdef CONFIG_SOC_AU1100
1198 case CPU_AU1100:
1199 num_ifs = 1 - ni;
1200 iflist[0].base_addr = AU1100_ETH0_BASE;
1201 iflist[0].macen_addr = AU1100_MAC0_ENABLE;
1202 iflist[0].irq = AU1100_MAC0_DMA_INT;
1203 break;
1204 #endif
1205 #ifdef CONFIG_SOC_AU1500
1206 case CPU_AU1500:
1207 num_ifs = 2 - ni;
1208 iflist[0].base_addr = AU1500_ETH0_BASE;
1209 iflist[1].base_addr = AU1500_ETH1_BASE;
1210 iflist[0].macen_addr = AU1500_MAC0_ENABLE;
1211 iflist[1].macen_addr = AU1500_MAC1_ENABLE;
1212 iflist[0].irq = AU1500_MAC0_DMA_INT;
1213 iflist[1].irq = AU1500_MAC1_DMA_INT;
1214 break;
1215 #endif
1216 #ifdef CONFIG_SOC_AU1550
1217 case CPU_AU1550:
1218 num_ifs = 2 - ni;
1219 iflist[0].base_addr = AU1550_ETH0_BASE;
1220 iflist[1].base_addr = AU1550_ETH1_BASE;
1221 iflist[0].macen_addr = AU1550_MAC0_ENABLE;
1222 iflist[1].macen_addr = AU1550_MAC1_ENABLE;
1223 iflist[0].irq = AU1550_MAC0_DMA_INT;
1224 iflist[1].irq = AU1550_MAC1_DMA_INT;
1225 break;
1226 #endif
1227 default:
1228 num_ifs = 0;
1229 }
1230 for(i = 0; i < num_ifs; i++) {
1231 dev = au1000_probe(iflist[i].base_addr, iflist[i].irq, i);
1232 iflist[i].dev = dev;
1233 if (dev)
1234 found_one++;
1235 }
1236 if (!found_one)
1237 return -ENODEV;
1238 return 0;
1239 }
1240
1241 static int au1000_setup_aneg(struct net_device *dev, u32 advertise)
1242 {
1243 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1244 u16 ctl, adv;
1245
1246 /* Setup standard advertise */
1247 adv = mdio_read(dev, aup->phy_addr, MII_ADVERTISE);
1248 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1249 if (advertise & ADVERTISED_10baseT_Half)
1250 adv |= ADVERTISE_10HALF;
1251 if (advertise & ADVERTISED_10baseT_Full)
1252 adv |= ADVERTISE_10FULL;
1253 if (advertise & ADVERTISED_100baseT_Half)
1254 adv |= ADVERTISE_100HALF;
1255 if (advertise & ADVERTISED_100baseT_Full)
1256 adv |= ADVERTISE_100FULL;
1257 mdio_write(dev, aup->phy_addr, MII_ADVERTISE, adv);
1258
1259 /* Start/Restart aneg */
1260 ctl = mdio_read(dev, aup->phy_addr, MII_BMCR);
1261 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1262 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl);
1263
1264 return 0;
1265 }
1266
1267 static int au1000_setup_forced(struct net_device *dev, int speed, int fd)
1268 {
1269 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1270 u16 ctl;
1271
1272 ctl = mdio_read(dev, aup->phy_addr, MII_BMCR);
1273 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE);
1274
1275 /* First reset the PHY */
1276 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl | BMCR_RESET);
1277
1278 /* Select speed & duplex */
1279 switch (speed) {
1280 case SPEED_10:
1281 break;
1282 case SPEED_100:
1283 ctl |= BMCR_SPEED100;
1284 break;
1285 case SPEED_1000:
1286 default:
1287 return -EINVAL;
1288 }
1289 if (fd == DUPLEX_FULL)
1290 ctl |= BMCR_FULLDPLX;
1291 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl);
1292
1293 return 0;
1294 }
1295
1296
1297 static void
1298 au1000_start_link(struct net_device *dev, struct ethtool_cmd *cmd)
1299 {
1300 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1301 u32 advertise;
1302 int autoneg;
1303 int forced_speed;
1304 int forced_duplex;
1305
1306 /* Default advertise */
1307 advertise = GENMII_DEFAULT_ADVERTISE;
1308 autoneg = aup->want_autoneg;
1309 forced_speed = SPEED_100;
1310 forced_duplex = DUPLEX_FULL;
1311
1312 /* Setup link parameters */
1313 if (cmd) {
1314 if (cmd->autoneg == AUTONEG_ENABLE) {
1315 advertise = cmd->advertising;
1316 autoneg = 1;
1317 } else {
1318 autoneg = 0;
1319
1320 forced_speed = cmd->speed;
1321 forced_duplex = cmd->duplex;
1322 }
1323 }
1324
1325 /* Configure PHY & start aneg */
1326 aup->want_autoneg = autoneg;
1327 if (autoneg)
1328 au1000_setup_aneg(dev, advertise);
1329 else
1330 au1000_setup_forced(dev, forced_speed, forced_duplex);
1331 mod_timer(&aup->timer, jiffies + HZ);
1332 }
1333
1334 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1335 {
1336 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1337 u16 link, speed;
1338
1339 cmd->supported = GENMII_DEFAULT_FEATURES;
1340 cmd->advertising = GENMII_DEFAULT_ADVERTISE;
1341 cmd->port = PORT_MII;
1342 cmd->transceiver = XCVR_EXTERNAL;
1343 cmd->phy_address = aup->phy_addr;
1344 spin_lock_irq(&aup->lock);
1345 cmd->autoneg = aup->want_autoneg;
1346 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
1347 if ((speed == IF_PORT_100BASETX) || (speed == IF_PORT_100BASEFX))
1348 cmd->speed = SPEED_100;
1349 else if (speed == IF_PORT_10BASET)
1350 cmd->speed = SPEED_10;
1351 if (link && (dev->if_port == IF_PORT_100BASEFX))
1352 cmd->duplex = DUPLEX_FULL;
1353 else
1354 cmd->duplex = DUPLEX_HALF;
1355 spin_unlock_irq(&aup->lock);
1356 return 0;
1357 }
1358
1359 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1360 {
1361 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1362 unsigned long features = GENMII_DEFAULT_FEATURES;
1363
1364 if (!capable(CAP_NET_ADMIN))
1365 return -EPERM;
1366
1367 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1368 return -EINVAL;
1369 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1370 return -EINVAL;
1371 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1372 return -EINVAL;
1373 if (cmd->autoneg == AUTONEG_DISABLE)
1374 switch (cmd->speed) {
1375 case SPEED_10:
1376 if (cmd->duplex == DUPLEX_HALF &&
1377 (features & SUPPORTED_10baseT_Half) == 0)
1378 return -EINVAL;
1379 if (cmd->duplex == DUPLEX_FULL &&
1380 (features & SUPPORTED_10baseT_Full) == 0)
1381 return -EINVAL;
1382 break;
1383 case SPEED_100:
1384 if (cmd->duplex == DUPLEX_HALF &&
1385 (features & SUPPORTED_100baseT_Half) == 0)
1386 return -EINVAL;
1387 if (cmd->duplex == DUPLEX_FULL &&
1388 (features & SUPPORTED_100baseT_Full) == 0)
1389 return -EINVAL;
1390 break;
1391 default:
1392 return -EINVAL;
1393 }
1394 else if ((features & SUPPORTED_Autoneg) == 0)
1395 return -EINVAL;
1396
1397 spin_lock_irq(&aup->lock);
1398 au1000_start_link(dev, cmd);
1399 spin_unlock_irq(&aup->lock);
1400 return 0;
1401 }
1402
1403 static int au1000_nway_reset(struct net_device *dev)
1404 {
1405 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1406
1407 if (!aup->want_autoneg)
1408 return -EINVAL;
1409 spin_lock_irq(&aup->lock);
1410 au1000_start_link(dev, NULL);
1411 spin_unlock_irq(&aup->lock);
1412 return 0;
1413 }
1414
1415 static void
1416 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1417 {
1418 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1419
1420 strcpy(info->driver, DRV_NAME);
1421 strcpy(info->version, DRV_VERSION);
1422 info->fw_version[0] = '\0';
1423 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
1424 info->regdump_len = 0;
1425 }
1426
1427 static u32 au1000_get_link(struct net_device *dev)
1428 {
1429 return netif_carrier_ok(dev);
1430 }
1431
1432 static struct ethtool_ops au1000_ethtool_ops = {
1433 .get_settings = au1000_get_settings,
1434 .set_settings = au1000_set_settings,
1435 .get_drvinfo = au1000_get_drvinfo,
1436 .nway_reset = au1000_nway_reset,
1437 .get_link = au1000_get_link
1438 };
1439
1440 static struct net_device *
1441 au1000_probe(u32 ioaddr, int irq, int port_num)
1442 {
1443 static unsigned version_printed = 0;
1444 struct au1000_private *aup = NULL;
1445 struct net_device *dev = NULL;
1446 db_dest_t *pDB, *pDBfree;
1447 char *pmac, *argptr;
1448 char ethaddr[6];
1449 int i, err;
1450
1451 if (!request_mem_region(CPHYSADDR(ioaddr), MAC_IOSIZE, "Au1x00 ENET"))
1452 return NULL;
1453
1454 if (version_printed++ == 0)
1455 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1456
1457 dev = alloc_etherdev(sizeof(struct au1000_private));
1458 if (!dev) {
1459 printk (KERN_ERR "au1000 eth: alloc_etherdev failed\n");
1460 return NULL;
1461 }
1462
1463 if ((err = register_netdev(dev))) {
1464 printk(KERN_ERR "Au1x_eth Cannot register net device err %d\n",
1465 err);
1466 free_netdev(dev);
1467 return NULL;
1468 }
1469
1470 printk("%s: Au1x Ethernet found at 0x%x, irq %d\n",
1471 dev->name, ioaddr, irq);
1472
1473 aup = dev->priv;
1474
1475 /* Allocate the data buffers */
1476 /* Snooping works fine with eth on all au1xxx */
1477 aup->vaddr = (u32)dma_alloc_noncoherent(NULL,
1478 MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS),
1479 &aup->dma_addr,
1480 0);
1481 if (!aup->vaddr) {
1482 free_netdev(dev);
1483 release_mem_region(CPHYSADDR(ioaddr), MAC_IOSIZE);
1484 return NULL;
1485 }
1486
1487 /* aup->mac is the base address of the MAC's registers */
1488 aup->mac = (volatile mac_reg_t *)((unsigned long)ioaddr);
1489 /* Setup some variables for quick register address access */
1490 if (ioaddr == iflist[0].base_addr)
1491 {
1492 /* check env variables first */
1493 if (!get_ethernet_addr(ethaddr)) {
1494 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
1495 } else {
1496 /* Check command line */
1497 argptr = prom_getcmdline();
1498 if ((pmac = strstr(argptr, "ethaddr=")) == NULL) {
1499 printk(KERN_INFO "%s: No mac address found\n",
1500 dev->name);
1501 /* use the hard coded mac addresses */
1502 } else {
1503 str2eaddr(ethaddr, pmac + strlen("ethaddr="));
1504 memcpy(au1000_mac_addr, ethaddr,
1505 sizeof(au1000_mac_addr));
1506 }
1507 }
1508 aup->enable = (volatile u32 *)
1509 ((unsigned long)iflist[0].macen_addr);
1510 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
1511 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
1512 aup->mac_id = 0;
1513 au_macs[0] = aup;
1514 }
1515 else
1516 if (ioaddr == iflist[1].base_addr)
1517 {
1518 aup->enable = (volatile u32 *)
1519 ((unsigned long)iflist[1].macen_addr);
1520 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
1521 dev->dev_addr[4] += 0x10;
1522 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
1523 aup->mac_id = 1;
1524 au_macs[1] = aup;
1525 }
1526 else
1527 {
1528 printk(KERN_ERR "%s: bad ioaddr\n", dev->name);
1529 }
1530
1531 /* bring the device out of reset, otherwise probing the mii
1532 * will hang */
1533 *aup->enable = MAC_EN_CLOCK_ENABLE;
1534 au_sync_delay(2);
1535 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
1536 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
1537 au_sync_delay(2);
1538
1539 aup->mii = kmalloc(sizeof(struct mii_phy), GFP_KERNEL);
1540 if (!aup->mii) {
1541 printk(KERN_ERR "%s: out of memory\n", dev->name);
1542 goto err_out;
1543 }
1544 aup->mii->next = NULL;
1545 aup->mii->chip_info = NULL;
1546 aup->mii->status = 0;
1547 aup->mii->mii_control_reg = 0;
1548 aup->mii->mii_data_reg = 0;
1549
1550 if (mii_probe(dev) != 0) {
1551 goto err_out;
1552 }
1553
1554 pDBfree = NULL;
1555 /* setup the data buffer descriptors and attach a buffer to each one */
1556 pDB = aup->db;
1557 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1558 pDB->pnext = pDBfree;
1559 pDBfree = pDB;
1560 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1561 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1562 pDB++;
1563 }
1564 aup->pDBfree = pDBfree;
1565
1566 for (i = 0; i < NUM_RX_DMA; i++) {
1567 pDB = GetFreeDB(aup);
1568 if (!pDB) {
1569 goto err_out;
1570 }
1571 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1572 aup->rx_db_inuse[i] = pDB;
1573 }
1574 for (i = 0; i < NUM_TX_DMA; i++) {
1575 pDB = GetFreeDB(aup);
1576 if (!pDB) {
1577 goto err_out;
1578 }
1579 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1580 aup->tx_dma_ring[i]->len = 0;
1581 aup->tx_db_inuse[i] = pDB;
1582 }
1583
1584 spin_lock_init(&aup->lock);
1585 dev->base_addr = ioaddr;
1586 dev->irq = irq;
1587 dev->open = au1000_open;
1588 dev->hard_start_xmit = au1000_tx;
1589 dev->stop = au1000_close;
1590 dev->get_stats = au1000_get_stats;
1591 dev->set_multicast_list = &set_rx_mode;
1592 dev->do_ioctl = &au1000_ioctl;
1593 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1594 dev->set_config = &au1000_set_config;
1595 dev->tx_timeout = au1000_tx_timeout;
1596 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1597
1598 /*
1599 * The boot code uses the ethernet controller, so reset it to start
1600 * fresh. au1000_init() expects that the device is in reset state.
1601 */
1602 reset_mac(dev);
1603
1604 return dev;
1605
1606 err_out:
1607 /* here we should have a valid dev plus aup-> register addresses
1608 * so we can reset the mac properly.*/
1609 reset_mac(dev);
1610 kfree(aup->mii);
1611 for (i = 0; i < NUM_RX_DMA; i++) {
1612 if (aup->rx_db_inuse[i])
1613 ReleaseDB(aup, aup->rx_db_inuse[i]);
1614 }
1615 for (i = 0; i < NUM_TX_DMA; i++) {
1616 if (aup->tx_db_inuse[i])
1617 ReleaseDB(aup, aup->tx_db_inuse[i]);
1618 }
1619 dma_free_noncoherent(NULL,
1620 MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS),
1621 (void *)aup->vaddr,
1622 aup->dma_addr);
1623 unregister_netdev(dev);
1624 free_netdev(dev);
1625 release_mem_region(CPHYSADDR(ioaddr), MAC_IOSIZE);
1626 return NULL;
1627 }
1628
1629 /*
1630 * Initialize the interface.
1631 *
1632 * When the device powers up, the clocks are disabled and the
1633 * mac is in reset state. When the interface is closed, we
1634 * do the same -- reset the device and disable the clocks to
1635 * conserve power. Thus, whenever au1000_init() is called,
1636 * the device should already be in reset state.
1637 */
1638 static int au1000_init(struct net_device *dev)
1639 {
1640 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1641 u32 flags;
1642 int i;
1643 u32 control;
1644 u16 link, speed;
1645
1646 if (au1000_debug > 4)
1647 printk("%s: au1000_init\n", dev->name);
1648
1649 spin_lock_irqsave(&aup->lock, flags);
1650
1651 /* bring the device out of reset */
1652 *aup->enable = MAC_EN_CLOCK_ENABLE;
1653 au_sync_delay(2);
1654 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
1655 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
1656 au_sync_delay(20);
1657
1658 aup->mac->control = 0;
1659 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
1660 aup->tx_tail = aup->tx_head;
1661 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
1662
1663 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
1664 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
1665 dev->dev_addr[1]<<8 | dev->dev_addr[0];
1666
1667 for (i = 0; i < NUM_RX_DMA; i++) {
1668 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
1669 }
1670 au_sync();
1671
1672 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
1673 control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
1674 #ifndef CONFIG_CPU_LITTLE_ENDIAN
1675 control |= MAC_BIG_ENDIAN;
1676 #endif
1677 if (link && (dev->if_port == IF_PORT_100BASEFX)) {
1678 control |= MAC_FULL_DUPLEX;
1679 }
1680
1681 aup->mac->control = control;
1682 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
1683 au_sync();
1684
1685 spin_unlock_irqrestore(&aup->lock, flags);
1686 return 0;
1687 }
1688
1689 static void au1000_timer(unsigned long data)
1690 {
1691 struct net_device *dev = (struct net_device *)data;
1692 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1693 unsigned char if_port;
1694 u16 link, speed;
1695
1696 if (!dev) {
1697 /* fatal error, don't restart the timer */
1698 printk(KERN_ERR "au1000_timer error: NULL dev\n");
1699 return;
1700 }
1701
1702 if_port = dev->if_port;
1703 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
1704 if (link) {
1705 if (!netif_carrier_ok(dev)) {
1706 netif_carrier_on(dev);
1707 printk(KERN_INFO "%s: link up\n", dev->name);
1708 }
1709 }
1710 else {
1711 if (netif_carrier_ok(dev)) {
1712 netif_carrier_off(dev);
1713 dev->if_port = 0;
1714 printk(KERN_INFO "%s: link down\n", dev->name);
1715 }
1716 }
1717 }
1718
1719 if (link && (dev->if_port != if_port) &&
1720 (dev->if_port != IF_PORT_UNKNOWN)) {
1721 hard_stop(dev);
1722 if (dev->if_port == IF_PORT_100BASEFX) {
1723 printk(KERN_INFO "%s: going to full duplex\n",
1724 dev->name);
1725 aup->mac->control |= MAC_FULL_DUPLEX;
1726 au_sync_delay(1);
1727 }
1728 else {
1729 aup->mac->control &= ~MAC_FULL_DUPLEX;
1730 au_sync_delay(1);
1731 }
1732 enable_rx_tx(dev);
1733 }
1734
1735 aup->timer.expires = RUN_AT((1*HZ));
1736 aup->timer.data = (unsigned long)dev;
1737 aup->timer.function = &au1000_timer; /* timer handler */
1738 add_timer(&aup->timer);
1739
1740 }
1741
1742 static int au1000_open(struct net_device *dev)
1743 {
1744 int retval;
1745 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1746
1747 if (au1000_debug > 4)
1748 printk("%s: open: dev=%p\n", dev->name, dev);
1749
1750 if ((retval = au1000_init(dev))) {
1751 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
1752 free_irq(dev->irq, dev);
1753 return retval;
1754 }
1755 netif_start_queue(dev);
1756
1757 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
1758 dev->name, dev))) {
1759 printk(KERN_ERR "%s: unable to get IRQ %d\n",
1760 dev->name, dev->irq);
1761 return retval;
1762 }
1763
1764 init_timer(&aup->timer); /* used in ioctl() */
1765 aup->timer.expires = RUN_AT((3*HZ));
1766 aup->timer.data = (unsigned long)dev;
1767 aup->timer.function = &au1000_timer; /* timer handler */
1768 add_timer(&aup->timer);
1769
1770 if (au1000_debug > 4)
1771 printk("%s: open: Initialization done.\n", dev->name);
1772
1773 return 0;
1774 }
1775
1776 static int au1000_close(struct net_device *dev)
1777 {
1778 u32 flags;
1779 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1780
1781 if (au1000_debug > 4)
1782 printk("%s: close: dev=%p\n", dev->name, dev);
1783
1784 reset_mac(dev);
1785
1786 spin_lock_irqsave(&aup->lock, flags);
1787
1788 /* stop the device */
1789 netif_stop_queue(dev);
1790
1791 /* disable the interrupt */
1792 free_irq(dev->irq, dev);
1793 spin_unlock_irqrestore(&aup->lock, flags);
1794
1795 return 0;
1796 }
1797
1798 static void __exit au1000_cleanup_module(void)
1799 {
1800 int i, j;
1801 struct net_device *dev;
1802 struct au1000_private *aup;
1803
1804 for (i = 0; i < num_ifs; i++) {
1805 dev = iflist[i].dev;
1806 if (dev) {
1807 aup = (struct au1000_private *) dev->priv;
1808 unregister_netdev(dev);
1809 kfree(aup->mii);
1810 for (j = 0; j < NUM_RX_DMA; j++) {
1811 if (aup->rx_db_inuse[j])
1812 ReleaseDB(aup, aup->rx_db_inuse[j]);
1813 }
1814 for (j = 0; j < NUM_TX_DMA; j++) {
1815 if (aup->tx_db_inuse[j])
1816 ReleaseDB(aup, aup->tx_db_inuse[j]);
1817 }
1818 dma_free_noncoherent(NULL,
1819 MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS),
1820 (void *)aup->vaddr,
1821 aup->dma_addr);
1822 free_netdev(dev);
1823 release_mem_region(CPHYSADDR(iflist[i].base_addr), MAC_IOSIZE);
1824 }
1825 }
1826 }
1827
1828
1829 static inline void
1830 update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
1831 {
1832 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1833 struct net_device_stats *ps = &aup->stats;
1834
1835 ps->tx_packets++;
1836 ps->tx_bytes += pkt_len;
1837
1838 if (status & TX_FRAME_ABORTED) {
1839 if (dev->if_port == IF_PORT_100BASEFX) {
1840 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1841 /* any other tx errors are only valid
1842 * in half duplex mode */
1843 ps->tx_errors++;
1844 ps->tx_aborted_errors++;
1845 }
1846 }
1847 else {
1848 ps->tx_errors++;
1849 ps->tx_aborted_errors++;
1850 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1851 ps->tx_carrier_errors++;
1852 }
1853 }
1854 }
1855
1856
1857 /*
1858 * Called from the interrupt service routine to acknowledge
1859 * the TX DONE bits. This is a must if the irq is setup as
1860 * edge triggered.
1861 */
1862 static void au1000_tx_ack(struct net_device *dev)
1863 {
1864 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1865 volatile tx_dma_t *ptxd;
1866
1867 ptxd = aup->tx_dma_ring[aup->tx_tail];
1868
1869 while (ptxd->buff_stat & TX_T_DONE) {
1870 update_tx_stats(dev, ptxd->status, ptxd->len & 0x3ff);
1871 ptxd->buff_stat &= ~TX_T_DONE;
1872 ptxd->len = 0;
1873 au_sync();
1874
1875 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1876 ptxd = aup->tx_dma_ring[aup->tx_tail];
1877
1878 if (aup->tx_full) {
1879 aup->tx_full = 0;
1880 netif_wake_queue(dev);
1881 }
1882 }
1883 }
1884
1885
1886 /*
1887 * Au1000 transmit routine.
1888 */
1889 static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1890 {
1891 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1892 volatile tx_dma_t *ptxd;
1893 u32 buff_stat;
1894 db_dest_t *pDB;
1895 int i;
1896
1897 if (au1000_debug > 5)
1898 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1899 dev->name, (unsigned)aup, skb->len,
1900 skb->data, aup->tx_head);
1901
1902 ptxd = aup->tx_dma_ring[aup->tx_head];
1903 buff_stat = ptxd->buff_stat;
1904 if (buff_stat & TX_DMA_ENABLE) {
1905 /* We've wrapped around and the transmitter is still busy */
1906 netif_stop_queue(dev);
1907 aup->tx_full = 1;
1908 return 1;
1909 }
1910 else if (buff_stat & TX_T_DONE) {
1911 update_tx_stats(dev, ptxd->status, ptxd->len & 0x3ff);
1912 ptxd->len = 0;
1913 }
1914
1915 if (aup->tx_full) {
1916 aup->tx_full = 0;
1917 netif_wake_queue(dev);
1918 }
1919
1920 pDB = aup->tx_db_inuse[aup->tx_head];
1921 memcpy((void *)pDB->vaddr, skb->data, skb->len);
1922 if (skb->len < ETH_ZLEN) {
1923 for (i=skb->len; i<ETH_ZLEN; i++) {
1924 ((char *)pDB->vaddr)[i] = 0;
1925 }
1926 ptxd->len = ETH_ZLEN;
1927 }
1928 else
1929 ptxd->len = skb->len;
1930
1931 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1932 au_sync();
1933 dev_kfree_skb(skb);
1934 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1935 dev->trans_start = jiffies;
1936 return 0;
1937 }
1938
1939
1940 static inline void update_rx_stats(struct net_device *dev, u32 status)
1941 {
1942 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1943 struct net_device_stats *ps = &aup->stats;
1944
1945 ps->rx_packets++;
1946 if (status & RX_MCAST_FRAME)
1947 ps->multicast++;
1948
1949 if (status & RX_ERROR) {
1950 ps->rx_errors++;
1951 if (status & RX_MISSED_FRAME)
1952 ps->rx_missed_errors++;
1953 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1954 ps->rx_length_errors++;
1955 if (status & RX_CRC_ERROR)
1956 ps->rx_crc_errors++;
1957 if (status & RX_COLL)
1958 ps->collisions++;
1959 }
1960 else
1961 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1962
1963 }
1964
1965 /*
1966 * Au1000 receive routine.
1967 */
1968 static int au1000_rx(struct net_device *dev)
1969 {
1970 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1971 struct sk_buff *skb;
1972 volatile rx_dma_t *prxd;
1973 u32 buff_stat, status;
1974 db_dest_t *pDB;
1975 u32 frmlen;
1976
1977 if (au1000_debug > 5)
1978 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1979
1980 prxd = aup->rx_dma_ring[aup->rx_head];
1981 buff_stat = prxd->buff_stat;
1982 while (buff_stat & RX_T_DONE) {
1983 status = prxd->status;
1984 pDB = aup->rx_db_inuse[aup->rx_head];
1985 update_rx_stats(dev, status);
1986 if (!(status & RX_ERROR)) {
1987
1988 /* good frame */
1989 frmlen = (status & RX_FRAME_LEN_MASK);
1990 frmlen -= 4; /* Remove FCS */
1991 skb = dev_alloc_skb(frmlen + 2);
1992 if (skb == NULL) {
1993 printk(KERN_ERR
1994 "%s: Memory squeeze, dropping packet.\n",
1995 dev->name);
1996 aup->stats.rx_dropped++;
1997 continue;
1998 }
1999 skb->dev = dev;
2000 skb_reserve(skb, 2); /* 16 byte IP header align */
2001 eth_copy_and_sum(skb,
2002 (unsigned char *)pDB->vaddr, frmlen, 0);
2003 skb_put(skb, frmlen);
2004 skb->protocol = eth_type_trans(skb, dev);
2005 netif_rx(skb); /* pass the packet to upper layers */
2006 }
2007 else {
2008 if (au1000_debug > 4) {
2009 if (status & RX_MISSED_FRAME)
2010 printk("rx miss\n");
2011 if (status & RX_WDOG_TIMER)
2012 printk("rx wdog\n");
2013 if (status & RX_RUNT)
2014 printk("rx runt\n");
2015 if (status & RX_OVERLEN)
2016 printk("rx overlen\n");
2017 if (status & RX_COLL)
2018 printk("rx coll\n");
2019 if (status & RX_MII_ERROR)
2020 printk("rx mii error\n");
2021 if (status & RX_CRC_ERROR)
2022 printk("rx crc error\n");
2023 if (status & RX_LEN_ERROR)
2024 printk("rx len error\n");
2025 if (status & RX_U_CNTRL_FRAME)
2026 printk("rx u control frame\n");
2027 if (status & RX_MISSED_FRAME)
2028 printk("rx miss\n");
2029 }
2030 }
2031 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
2032 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
2033 au_sync();
2034
2035 /* next descriptor */
2036 prxd = aup->rx_dma_ring[aup->rx_head];
2037 buff_stat = prxd->buff_stat;
2038 dev->last_rx = jiffies;
2039 }
2040 return 0;
2041 }
2042
2043
2044 /*
2045 * Au1000 interrupt service routine.
2046 */
2047 static irqreturn_t au1000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2048 {
2049 struct net_device *dev = (struct net_device *) dev_id;
2050
2051 if (dev == NULL) {
2052 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
2053 return IRQ_RETVAL(1);
2054 }
2055
2056 /* Handle RX interrupts first to minimize chance of overrun */
2057
2058 au1000_rx(dev);
2059 au1000_tx_ack(dev);
2060 return IRQ_RETVAL(1);
2061 }
2062
2063
2064 /*
2065 * The Tx ring has been full longer than the watchdog timeout
2066 * value. The transmitter must be hung?
2067 */
2068 static void au1000_tx_timeout(struct net_device *dev)
2069 {
2070 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
2071 reset_mac(dev);
2072 au1000_init(dev);
2073 dev->trans_start = jiffies;
2074 netif_wake_queue(dev);
2075 }
2076
2077
2078 static unsigned const ethernet_polynomial = 0x04c11db7U;
2079 static inline u32 ether_crc(int length, unsigned char *data)
2080 {
2081 int crc = -1;
2082
2083 while(--length >= 0) {
2084 unsigned char current_octet = *data++;
2085 int bit;
2086 for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2087 crc = (crc << 1) ^
2088 ((crc < 0) ^ (current_octet & 1) ?
2089 ethernet_polynomial : 0);
2090 }
2091 return crc;
2092 }
2093
2094 static void set_rx_mode(struct net_device *dev)
2095 {
2096 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2097
2098 if (au1000_debug > 4)
2099 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
2100
2101 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2102 aup->mac->control |= MAC_PROMISCUOUS;
2103 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2104 } else if ((dev->flags & IFF_ALLMULTI) ||
2105 dev->mc_count > MULTICAST_FILTER_LIMIT) {
2106 aup->mac->control |= MAC_PASS_ALL_MULTI;
2107 aup->mac->control &= ~MAC_PROMISCUOUS;
2108 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
2109 } else {
2110 int i;
2111 struct dev_mc_list *mclist;
2112 u32 mc_filter[2]; /* Multicast hash filter */
2113
2114 mc_filter[1] = mc_filter[0] = 0;
2115 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2116 i++, mclist = mclist->next) {
2117 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
2118 (long *)mc_filter);
2119 }
2120 aup->mac->multi_hash_high = mc_filter[1];
2121 aup->mac->multi_hash_low = mc_filter[0];
2122 aup->mac->control &= ~MAC_PROMISCUOUS;
2123 aup->mac->control |= MAC_HASH_MODE;
2124 }
2125 }
2126
2127
2128 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2129 {
2130 struct au1000_private *aup = (struct au1000_private *)dev->priv;
2131 u16 *data = (u16 *)&rq->ifr_ifru;
2132
2133 switch(cmd) {
2134 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2135 case SIOCGMIIPHY:
2136 if (!netif_running(dev)) return -EINVAL;
2137 data[0] = aup->phy_addr;
2138 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2139 case SIOCGMIIREG:
2140 data[3] = mdio_read(dev, data[0], data[1]);
2141 return 0;
2142 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2143 case SIOCSMIIREG:
2144 if (!capable(CAP_NET_ADMIN))
2145 return -EPERM;
2146 mdio_write(dev, data[0], data[1],data[2]);
2147 return 0;
2148 default:
2149 return -EOPNOTSUPP;
2150 }
2151
2152 }
2153
2154
2155 static int au1000_set_config(struct net_device *dev, struct ifmap *map)
2156 {
2157 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2158 u16 control;
2159
2160 if (au1000_debug > 4) {
2161 printk("%s: set_config called: dev->if_port %d map->port %x\n",
2162 dev->name, dev->if_port, map->port);
2163 }
2164
2165 switch(map->port){
2166 case IF_PORT_UNKNOWN: /* use auto here */
2167 printk(KERN_INFO "%s: config phy for aneg\n",
2168 dev->name);
2169 dev->if_port = map->port;
2170 /* Link Down: the timer will bring it up */
2171 netif_carrier_off(dev);
2172
2173 /* read current control */
2174 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2175 control &= ~(MII_CNTL_FDX | MII_CNTL_F100);
2176
2177 /* enable auto negotiation and reset the negotiation */
2178 mdio_write(dev, aup->phy_addr, MII_CONTROL,
2179 control | MII_CNTL_AUTO |
2180 MII_CNTL_RST_AUTO);
2181
2182 break;
2183
2184 case IF_PORT_10BASET: /* 10BaseT */
2185 printk(KERN_INFO "%s: config phy for 10BaseT\n",
2186 dev->name);
2187 dev->if_port = map->port;
2188
2189 /* Link Down: the timer will bring it up */
2190 netif_carrier_off(dev);
2191
2192 /* set Speed to 10Mbps, Half Duplex */
2193 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2194 control &= ~(MII_CNTL_F100 | MII_CNTL_AUTO |
2195 MII_CNTL_FDX);
2196
2197 /* disable auto negotiation and force 10M/HD mode*/
2198 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2199 break;
2200
2201 case IF_PORT_100BASET: /* 100BaseT */
2202 case IF_PORT_100BASETX: /* 100BaseTx */
2203 printk(KERN_INFO "%s: config phy for 100BaseTX\n",
2204 dev->name);
2205 dev->if_port = map->port;
2206
2207 /* Link Down: the timer will bring it up */
2208 netif_carrier_off(dev);
2209
2210 /* set Speed to 100Mbps, Half Duplex */
2211 /* disable auto negotiation and enable 100MBit Mode */
2212 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2213 control &= ~(MII_CNTL_AUTO | MII_CNTL_FDX);
2214 control |= MII_CNTL_F100;
2215 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2216 break;
2217
2218 case IF_PORT_100BASEFX: /* 100BaseFx */
2219 printk(KERN_INFO "%s: config phy for 100BaseFX\n",
2220 dev->name);
2221 dev->if_port = map->port;
2222
2223 /* Link Down: the timer will bring it up */
2224 netif_carrier_off(dev);
2225
2226 /* set Speed to 100Mbps, Full Duplex */
2227 /* disable auto negotiation and enable 100MBit Mode */
2228 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2229 control &= ~MII_CNTL_AUTO;
2230 control |= MII_CNTL_F100 | MII_CNTL_FDX;
2231 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2232 break;
2233 case IF_PORT_10BASE2: /* 10Base2 */
2234 case IF_PORT_AUI: /* AUI */
2235 /* These Modes are not supported (are they?)*/
2236 printk(KERN_ERR "%s: 10Base2/AUI not supported",
2237 dev->name);
2238 return -EOPNOTSUPP;
2239 break;
2240
2241 default:
2242 printk(KERN_ERR "%s: Invalid media selected",
2243 dev->name);
2244 return -EINVAL;
2245 }
2246 return 0;
2247 }
2248
2249 static struct net_device_stats *au1000_get_stats(struct net_device *dev)
2250 {
2251 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2252
2253 if (au1000_debug > 4)
2254 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
2255
2256 if (netif_device_present(dev)) {
2257 return &aup->stats;
2258 }
2259 return 0;
2260 }
2261
2262 module_init(au1000_init_module);
2263 module_exit(au1000_cleanup_module);
Stable & featurefull patchset based on Linus's git branch