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e1000: Add enabled Jumbo frame support for 82573L
[linux-2.6/zen-sources.git] / drivers / net / bnx2.c
bloba24200d0a616d8285e3f597d9addd6803ffd1552
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #include "bnx2.h"
13 #include "bnx2_fw.h"
14
15 #define DRV_MODULE_NAME "bnx2"
16 #define PFX DRV_MODULE_NAME ": "
17 #define DRV_MODULE_VERSION "1.4.31"
18 #define DRV_MODULE_RELDATE "January 19, 2006"
19
20 #define RUN_AT(x) (jiffies + (x))
21
22 /* Time in jiffies before concluding the transmitter is hung. */
23 #define TX_TIMEOUT (5*HZ)
24
25 static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_VERSION(DRV_MODULE_VERSION);
32
33 static int disable_msi = 0;
34
35 module_param(disable_msi, int, 0);
36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38 typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
44 BCM5708,
45 BCM5708S,
46 } board_t;
47
48 /* indexed by board_t, above */
49 static struct {
50 char *name;
51 } board_info[] __devinitdata = {
52 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
53 { "HP NC370T Multifunction Gigabit Server Adapter" },
54 { "HP NC370i Multifunction Gigabit Server Adapter" },
55 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
56 { "HP NC370F Multifunction Gigabit Server Adapter" },
57 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
59 };
60
61 static struct pci_device_id bnx2_pci_tbl[] = {
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
65 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
68 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
70 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
71 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
72 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
74 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
76 { 0, }
77 };
78
79 static struct flash_spec flash_table[] =
80 {
81 /* Slow EEPROM */
82 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
83 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
84 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
85 "EEPROM - slow"},
86 /* Expansion entry 0001 */
87 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
88 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
89 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
90 "Entry 0001"},
91 /* Saifun SA25F010 (non-buffered flash) */
92 /* strap, cfg1, & write1 need updates */
93 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
94 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
95 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
96 "Non-buffered flash (128kB)"},
97 /* Saifun SA25F020 (non-buffered flash) */
98 /* strap, cfg1, & write1 need updates */
99 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
100 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
101 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
102 "Non-buffered flash (256kB)"},
103 /* Expansion entry 0100 */
104 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
105 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
107 "Entry 0100"},
108 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
109 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
110 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
111 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
112 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
113 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
114 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
115 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
116 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
117 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
118 /* Saifun SA25F005 (non-buffered flash) */
119 /* strap, cfg1, & write1 need updates */
120 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
121 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
122 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
123 "Non-buffered flash (64kB)"},
124 /* Fast EEPROM */
125 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
126 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
127 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128 "EEPROM - fast"},
129 /* Expansion entry 1001 */
130 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
131 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
132 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133 "Entry 1001"},
134 /* Expansion entry 1010 */
135 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138 "Entry 1010"},
139 /* ATMEL AT45DB011B (buffered flash) */
140 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
141 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
142 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
143 "Buffered flash (128kB)"},
144 /* Expansion entry 1100 */
145 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 "Entry 1100"},
149 /* Expansion entry 1101 */
150 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
151 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
153 "Entry 1101"},
154 /* Ateml Expansion entry 1110 */
155 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
156 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
157 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
158 "Entry 1110 (Atmel)"},
159 /* ATMEL AT45DB021B (buffered flash) */
160 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
161 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
162 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
163 "Buffered flash (256kB)"},
164 };
165
166 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
167
168 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
169 {
170 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
171
172 if (diff > MAX_TX_DESC_CNT)
173 diff = (diff & MAX_TX_DESC_CNT) - 1;
174 return (bp->tx_ring_size - diff);
175 }
176
177 static u32
178 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
179 {
180 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
181 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
182 }
183
184 static void
185 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
186 {
187 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
188 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
189 }
190
191 static void
192 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
193 {
194 offset += cid_addr;
195 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
196 REG_WR(bp, BNX2_CTX_DATA, val);
197 }
198
199 static int
200 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
201 {
202 u32 val1;
203 int i, ret;
204
205 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
206 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
207 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
208
209 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
210 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
211
212 udelay(40);
213 }
214
215 val1 = (bp->phy_addr << 21) | (reg << 16) |
216 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
217 BNX2_EMAC_MDIO_COMM_START_BUSY;
218 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
219
220 for (i = 0; i < 50; i++) {
221 udelay(10);
222
223 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
224 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
225 udelay(5);
226
227 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
228 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
229
230 break;
231 }
232 }
233
234 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
235 *val = 0x0;
236 ret = -EBUSY;
237 }
238 else {
239 *val = val1;
240 ret = 0;
241 }
242
243 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
244 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
245 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
246
247 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
248 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249
250 udelay(40);
251 }
252
253 return ret;
254 }
255
256 static int
257 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
258 {
259 u32 val1;
260 int i, ret;
261
262 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
263 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
264 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
265
266 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
267 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
268
269 udelay(40);
270 }
271
272 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
273 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
274 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
275 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
276
277 for (i = 0; i < 50; i++) {
278 udelay(10);
279
280 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
281 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
282 udelay(5);
283 break;
284 }
285 }
286
287 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
288 ret = -EBUSY;
289 else
290 ret = 0;
291
292 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
293 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
294 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
295
296 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
297 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
298
299 udelay(40);
300 }
301
302 return ret;
303 }
304
305 static void
306 bnx2_disable_int(struct bnx2 *bp)
307 {
308 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
309 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
310 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
311 }
312
313 static void
314 bnx2_enable_int(struct bnx2 *bp)
315 {
316 u32 val;
317
318 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
320 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
321
322 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
323 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
324
325 val = REG_RD(bp, BNX2_HC_COMMAND);
326 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
327 }
328
329 static void
330 bnx2_disable_int_sync(struct bnx2 *bp)
331 {
332 atomic_inc(&bp->intr_sem);
333 bnx2_disable_int(bp);
334 synchronize_irq(bp->pdev->irq);
335 }
336
337 static void
338 bnx2_netif_stop(struct bnx2 *bp)
339 {
340 bnx2_disable_int_sync(bp);
341 if (netif_running(bp->dev)) {
342 netif_poll_disable(bp->dev);
343 netif_tx_disable(bp->dev);
344 bp->dev->trans_start = jiffies; /* prevent tx timeout */
345 }
346 }
347
348 static void
349 bnx2_netif_start(struct bnx2 *bp)
350 {
351 if (atomic_dec_and_test(&bp->intr_sem)) {
352 if (netif_running(bp->dev)) {
353 netif_wake_queue(bp->dev);
354 netif_poll_enable(bp->dev);
355 bnx2_enable_int(bp);
356 }
357 }
358 }
359
360 static void
361 bnx2_free_mem(struct bnx2 *bp)
362 {
363 if (bp->stats_blk) {
364 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
365 bp->stats_blk, bp->stats_blk_mapping);
366 bp->stats_blk = NULL;
367 }
368 if (bp->status_blk) {
369 pci_free_consistent(bp->pdev, sizeof(struct status_block),
370 bp->status_blk, bp->status_blk_mapping);
371 bp->status_blk = NULL;
372 }
373 if (bp->tx_desc_ring) {
374 pci_free_consistent(bp->pdev,
375 sizeof(struct tx_bd) * TX_DESC_CNT,
376 bp->tx_desc_ring, bp->tx_desc_mapping);
377 bp->tx_desc_ring = NULL;
378 }
379 kfree(bp->tx_buf_ring);
380 bp->tx_buf_ring = NULL;
381 if (bp->rx_desc_ring) {
382 pci_free_consistent(bp->pdev,
383 sizeof(struct rx_bd) * RX_DESC_CNT,
384 bp->rx_desc_ring, bp->rx_desc_mapping);
385 bp->rx_desc_ring = NULL;
386 }
387 kfree(bp->rx_buf_ring);
388 bp->rx_buf_ring = NULL;
389 }
390
391 static int
392 bnx2_alloc_mem(struct bnx2 *bp)
393 {
394 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
395 GFP_KERNEL);
396 if (bp->tx_buf_ring == NULL)
397 return -ENOMEM;
398
399 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
400 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
401 sizeof(struct tx_bd) *
402 TX_DESC_CNT,
403 &bp->tx_desc_mapping);
404 if (bp->tx_desc_ring == NULL)
405 goto alloc_mem_err;
406
407 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
408 GFP_KERNEL);
409 if (bp->rx_buf_ring == NULL)
410 goto alloc_mem_err;
411
412 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
413 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
414 sizeof(struct rx_bd) *
415 RX_DESC_CNT,
416 &bp->rx_desc_mapping);
417 if (bp->rx_desc_ring == NULL)
418 goto alloc_mem_err;
419
420 bp->status_blk = pci_alloc_consistent(bp->pdev,
421 sizeof(struct status_block),
422 &bp->status_blk_mapping);
423 if (bp->status_blk == NULL)
424 goto alloc_mem_err;
425
426 memset(bp->status_blk, 0, sizeof(struct status_block));
427
428 bp->stats_blk = pci_alloc_consistent(bp->pdev,
429 sizeof(struct statistics_block),
430 &bp->stats_blk_mapping);
431 if (bp->stats_blk == NULL)
432 goto alloc_mem_err;
433
434 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
435
436 return 0;
437
438 alloc_mem_err:
439 bnx2_free_mem(bp);
440 return -ENOMEM;
441 }
442
443 static void
444 bnx2_report_fw_link(struct bnx2 *bp)
445 {
446 u32 fw_link_status = 0;
447
448 if (bp->link_up) {
449 u32 bmsr;
450
451 switch (bp->line_speed) {
452 case SPEED_10:
453 if (bp->duplex == DUPLEX_HALF)
454 fw_link_status = BNX2_LINK_STATUS_10HALF;
455 else
456 fw_link_status = BNX2_LINK_STATUS_10FULL;
457 break;
458 case SPEED_100:
459 if (bp->duplex == DUPLEX_HALF)
460 fw_link_status = BNX2_LINK_STATUS_100HALF;
461 else
462 fw_link_status = BNX2_LINK_STATUS_100FULL;
463 break;
464 case SPEED_1000:
465 if (bp->duplex == DUPLEX_HALF)
466 fw_link_status = BNX2_LINK_STATUS_1000HALF;
467 else
468 fw_link_status = BNX2_LINK_STATUS_1000FULL;
469 break;
470 case SPEED_2500:
471 if (bp->duplex == DUPLEX_HALF)
472 fw_link_status = BNX2_LINK_STATUS_2500HALF;
473 else
474 fw_link_status = BNX2_LINK_STATUS_2500FULL;
475 break;
476 }
477
478 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
479
480 if (bp->autoneg) {
481 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
482
483 bnx2_read_phy(bp, MII_BMSR, &bmsr);
484 bnx2_read_phy(bp, MII_BMSR, &bmsr);
485
486 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
487 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
488 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
489 else
490 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
491 }
492 }
493 else
494 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
495
496 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
497 }
498
499 static void
500 bnx2_report_link(struct bnx2 *bp)
501 {
502 if (bp->link_up) {
503 netif_carrier_on(bp->dev);
504 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
505
506 printk("%d Mbps ", bp->line_speed);
507
508 if (bp->duplex == DUPLEX_FULL)
509 printk("full duplex");
510 else
511 printk("half duplex");
512
513 if (bp->flow_ctrl) {
514 if (bp->flow_ctrl & FLOW_CTRL_RX) {
515 printk(", receive ");
516 if (bp->flow_ctrl & FLOW_CTRL_TX)
517 printk("& transmit ");
518 }
519 else {
520 printk(", transmit ");
521 }
522 printk("flow control ON");
523 }
524 printk("\n");
525 }
526 else {
527 netif_carrier_off(bp->dev);
528 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
529 }
530
531 bnx2_report_fw_link(bp);
532 }
533
534 static void
535 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
536 {
537 u32 local_adv, remote_adv;
538
539 bp->flow_ctrl = 0;
540 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
541 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
542
543 if (bp->duplex == DUPLEX_FULL) {
544 bp->flow_ctrl = bp->req_flow_ctrl;
545 }
546 return;
547 }
548
549 if (bp->duplex != DUPLEX_FULL) {
550 return;
551 }
552
553 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
554 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
555 u32 val;
556
557 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
558 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
559 bp->flow_ctrl |= FLOW_CTRL_TX;
560 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
561 bp->flow_ctrl |= FLOW_CTRL_RX;
562 return;
563 }
564
565 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
566 bnx2_read_phy(bp, MII_LPA, &remote_adv);
567
568 if (bp->phy_flags & PHY_SERDES_FLAG) {
569 u32 new_local_adv = 0;
570 u32 new_remote_adv = 0;
571
572 if (local_adv & ADVERTISE_1000XPAUSE)
573 new_local_adv |= ADVERTISE_PAUSE_CAP;
574 if (local_adv & ADVERTISE_1000XPSE_ASYM)
575 new_local_adv |= ADVERTISE_PAUSE_ASYM;
576 if (remote_adv & ADVERTISE_1000XPAUSE)
577 new_remote_adv |= ADVERTISE_PAUSE_CAP;
578 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
579 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
580
581 local_adv = new_local_adv;
582 remote_adv = new_remote_adv;
583 }
584
585 /* See Table 28B-3 of 802.3ab-1999 spec. */
586 if (local_adv & ADVERTISE_PAUSE_CAP) {
587 if(local_adv & ADVERTISE_PAUSE_ASYM) {
588 if (remote_adv & ADVERTISE_PAUSE_CAP) {
589 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
590 }
591 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
592 bp->flow_ctrl = FLOW_CTRL_RX;
593 }
594 }
595 else {
596 if (remote_adv & ADVERTISE_PAUSE_CAP) {
597 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
598 }
599 }
600 }
601 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
602 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
603 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
604
605 bp->flow_ctrl = FLOW_CTRL_TX;
606 }
607 }
608 }
609
610 static int
611 bnx2_5708s_linkup(struct bnx2 *bp)
612 {
613 u32 val;
614
615 bp->link_up = 1;
616 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
617 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
618 case BCM5708S_1000X_STAT1_SPEED_10:
619 bp->line_speed = SPEED_10;
620 break;
621 case BCM5708S_1000X_STAT1_SPEED_100:
622 bp->line_speed = SPEED_100;
623 break;
624 case BCM5708S_1000X_STAT1_SPEED_1G:
625 bp->line_speed = SPEED_1000;
626 break;
627 case BCM5708S_1000X_STAT1_SPEED_2G5:
628 bp->line_speed = SPEED_2500;
629 break;
630 }
631 if (val & BCM5708S_1000X_STAT1_FD)
632 bp->duplex = DUPLEX_FULL;
633 else
634 bp->duplex = DUPLEX_HALF;
635
636 return 0;
637 }
638
639 static int
640 bnx2_5706s_linkup(struct bnx2 *bp)
641 {
642 u32 bmcr, local_adv, remote_adv, common;
643
644 bp->link_up = 1;
645 bp->line_speed = SPEED_1000;
646
647 bnx2_read_phy(bp, MII_BMCR, &bmcr);
648 if (bmcr & BMCR_FULLDPLX) {
649 bp->duplex = DUPLEX_FULL;
650 }
651 else {
652 bp->duplex = DUPLEX_HALF;
653 }
654
655 if (!(bmcr & BMCR_ANENABLE)) {
656 return 0;
657 }
658
659 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
660 bnx2_read_phy(bp, MII_LPA, &remote_adv);
661
662 common = local_adv & remote_adv;
663 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
664
665 if (common & ADVERTISE_1000XFULL) {
666 bp->duplex = DUPLEX_FULL;
667 }
668 else {
669 bp->duplex = DUPLEX_HALF;
670 }
671 }
672
673 return 0;
674 }
675
676 static int
677 bnx2_copper_linkup(struct bnx2 *bp)
678 {
679 u32 bmcr;
680
681 bnx2_read_phy(bp, MII_BMCR, &bmcr);
682 if (bmcr & BMCR_ANENABLE) {
683 u32 local_adv, remote_adv, common;
684
685 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
686 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
687
688 common = local_adv & (remote_adv >> 2);
689 if (common & ADVERTISE_1000FULL) {
690 bp->line_speed = SPEED_1000;
691 bp->duplex = DUPLEX_FULL;
692 }
693 else if (common & ADVERTISE_1000HALF) {
694 bp->line_speed = SPEED_1000;
695 bp->duplex = DUPLEX_HALF;
696 }
697 else {
698 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
699 bnx2_read_phy(bp, MII_LPA, &remote_adv);
700
701 common = local_adv & remote_adv;
702 if (common & ADVERTISE_100FULL) {
703 bp->line_speed = SPEED_100;
704 bp->duplex = DUPLEX_FULL;
705 }
706 else if (common & ADVERTISE_100HALF) {
707 bp->line_speed = SPEED_100;
708 bp->duplex = DUPLEX_HALF;
709 }
710 else if (common & ADVERTISE_10FULL) {
711 bp->line_speed = SPEED_10;
712 bp->duplex = DUPLEX_FULL;
713 }
714 else if (common & ADVERTISE_10HALF) {
715 bp->line_speed = SPEED_10;
716 bp->duplex = DUPLEX_HALF;
717 }
718 else {
719 bp->line_speed = 0;
720 bp->link_up = 0;
721 }
722 }
723 }
724 else {
725 if (bmcr & BMCR_SPEED100) {
726 bp->line_speed = SPEED_100;
727 }
728 else {
729 bp->line_speed = SPEED_10;
730 }
731 if (bmcr & BMCR_FULLDPLX) {
732 bp->duplex = DUPLEX_FULL;
733 }
734 else {
735 bp->duplex = DUPLEX_HALF;
736 }
737 }
738
739 return 0;
740 }
741
742 static int
743 bnx2_set_mac_link(struct bnx2 *bp)
744 {
745 u32 val;
746
747 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
748 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
749 (bp->duplex == DUPLEX_HALF)) {
750 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
751 }
752
753 /* Configure the EMAC mode register. */
754 val = REG_RD(bp, BNX2_EMAC_MODE);
755
756 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
757 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
758 BNX2_EMAC_MODE_25G);
759
760 if (bp->link_up) {
761 switch (bp->line_speed) {
762 case SPEED_10:
763 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
764 val |= BNX2_EMAC_MODE_PORT_MII_10;
765 break;
766 }
767 /* fall through */
768 case SPEED_100:
769 val |= BNX2_EMAC_MODE_PORT_MII;
770 break;
771 case SPEED_2500:
772 val |= BNX2_EMAC_MODE_25G;
773 /* fall through */
774 case SPEED_1000:
775 val |= BNX2_EMAC_MODE_PORT_GMII;
776 break;
777 }
778 }
779 else {
780 val |= BNX2_EMAC_MODE_PORT_GMII;
781 }
782
783 /* Set the MAC to operate in the appropriate duplex mode. */
784 if (bp->duplex == DUPLEX_HALF)
785 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
786 REG_WR(bp, BNX2_EMAC_MODE, val);
787
788 /* Enable/disable rx PAUSE. */
789 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
790
791 if (bp->flow_ctrl & FLOW_CTRL_RX)
792 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
793 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
794
795 /* Enable/disable tx PAUSE. */
796 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
797 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
798
799 if (bp->flow_ctrl & FLOW_CTRL_TX)
800 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
801 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
802
803 /* Acknowledge the interrupt. */
804 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
805
806 return 0;
807 }
808
809 static int
810 bnx2_set_link(struct bnx2 *bp)
811 {
812 u32 bmsr;
813 u8 link_up;
814
815 if (bp->loopback == MAC_LOOPBACK) {
816 bp->link_up = 1;
817 return 0;
818 }
819
820 link_up = bp->link_up;
821
822 bnx2_read_phy(bp, MII_BMSR, &bmsr);
823 bnx2_read_phy(bp, MII_BMSR, &bmsr);
824
825 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
826 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
827 u32 val;
828
829 val = REG_RD(bp, BNX2_EMAC_STATUS);
830 if (val & BNX2_EMAC_STATUS_LINK)
831 bmsr |= BMSR_LSTATUS;
832 else
833 bmsr &= ~BMSR_LSTATUS;
834 }
835
836 if (bmsr & BMSR_LSTATUS) {
837 bp->link_up = 1;
838
839 if (bp->phy_flags & PHY_SERDES_FLAG) {
840 if (CHIP_NUM(bp) == CHIP_NUM_5706)
841 bnx2_5706s_linkup(bp);
842 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
843 bnx2_5708s_linkup(bp);
844 }
845 else {
846 bnx2_copper_linkup(bp);
847 }
848 bnx2_resolve_flow_ctrl(bp);
849 }
850 else {
851 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
852 (bp->autoneg & AUTONEG_SPEED)) {
853
854 u32 bmcr;
855
856 bnx2_read_phy(bp, MII_BMCR, &bmcr);
857 if (!(bmcr & BMCR_ANENABLE)) {
858 bnx2_write_phy(bp, MII_BMCR, bmcr |
859 BMCR_ANENABLE);
860 }
861 }
862 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
863 bp->link_up = 0;
864 }
865
866 if (bp->link_up != link_up) {
867 bnx2_report_link(bp);
868 }
869
870 bnx2_set_mac_link(bp);
871
872 return 0;
873 }
874
875 static int
876 bnx2_reset_phy(struct bnx2 *bp)
877 {
878 int i;
879 u32 reg;
880
881 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
882
883 #define PHY_RESET_MAX_WAIT 100
884 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
885 udelay(10);
886
887 bnx2_read_phy(bp, MII_BMCR, &reg);
888 if (!(reg & BMCR_RESET)) {
889 udelay(20);
890 break;
891 }
892 }
893 if (i == PHY_RESET_MAX_WAIT) {
894 return -EBUSY;
895 }
896 return 0;
897 }
898
899 static u32
900 bnx2_phy_get_pause_adv(struct bnx2 *bp)
901 {
902 u32 adv = 0;
903
904 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
905 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
906
907 if (bp->phy_flags & PHY_SERDES_FLAG) {
908 adv = ADVERTISE_1000XPAUSE;
909 }
910 else {
911 adv = ADVERTISE_PAUSE_CAP;
912 }
913 }
914 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
915 if (bp->phy_flags & PHY_SERDES_FLAG) {
916 adv = ADVERTISE_1000XPSE_ASYM;
917 }
918 else {
919 adv = ADVERTISE_PAUSE_ASYM;
920 }
921 }
922 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
923 if (bp->phy_flags & PHY_SERDES_FLAG) {
924 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
925 }
926 else {
927 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
928 }
929 }
930 return adv;
931 }
932
933 static int
934 bnx2_setup_serdes_phy(struct bnx2 *bp)
935 {
936 u32 adv, bmcr, up1;
937 u32 new_adv = 0;
938
939 if (!(bp->autoneg & AUTONEG_SPEED)) {
940 u32 new_bmcr;
941 int force_link_down = 0;
942
943 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
944 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
945 if (up1 & BCM5708S_UP1_2G5) {
946 up1 &= ~BCM5708S_UP1_2G5;
947 bnx2_write_phy(bp, BCM5708S_UP1, up1);
948 force_link_down = 1;
949 }
950 }
951
952 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
953 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
954
955 bnx2_read_phy(bp, MII_BMCR, &bmcr);
956 new_bmcr = bmcr & ~BMCR_ANENABLE;
957 new_bmcr |= BMCR_SPEED1000;
958 if (bp->req_duplex == DUPLEX_FULL) {
959 adv |= ADVERTISE_1000XFULL;
960 new_bmcr |= BMCR_FULLDPLX;
961 }
962 else {
963 adv |= ADVERTISE_1000XHALF;
964 new_bmcr &= ~BMCR_FULLDPLX;
965 }
966 if ((new_bmcr != bmcr) || (force_link_down)) {
967 /* Force a link down visible on the other side */
968 if (bp->link_up) {
969 bnx2_write_phy(bp, MII_ADVERTISE, adv &
970 ~(ADVERTISE_1000XFULL |
971 ADVERTISE_1000XHALF));
972 bnx2_write_phy(bp, MII_BMCR, bmcr |
973 BMCR_ANRESTART | BMCR_ANENABLE);
974
975 bp->link_up = 0;
976 netif_carrier_off(bp->dev);
977 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
978 }
979 bnx2_write_phy(bp, MII_ADVERTISE, adv);
980 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
981 }
982 return 0;
983 }
984
985 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
986 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
987 up1 |= BCM5708S_UP1_2G5;
988 bnx2_write_phy(bp, BCM5708S_UP1, up1);
989 }
990
991 if (bp->advertising & ADVERTISED_1000baseT_Full)
992 new_adv |= ADVERTISE_1000XFULL;
993
994 new_adv |= bnx2_phy_get_pause_adv(bp);
995
996 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
997 bnx2_read_phy(bp, MII_BMCR, &bmcr);
998
999 bp->serdes_an_pending = 0;
1000 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1001 /* Force a link down visible on the other side */
1002 if (bp->link_up) {
1003 int i;
1004
1005 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1006 for (i = 0; i < 110; i++) {
1007 udelay(100);
1008 }
1009 }
1010
1011 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1012 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1013 BMCR_ANENABLE);
1014 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1015 /* Speed up link-up time when the link partner
1016 * does not autonegotiate which is very common
1017 * in blade servers. Some blade servers use
1018 * IPMI for kerboard input and it's important
1019 * to minimize link disruptions. Autoneg. involves
1020 * exchanging base pages plus 3 next pages and
1021 * normally completes in about 120 msec.
1022 */
1023 bp->current_interval = SERDES_AN_TIMEOUT;
1024 bp->serdes_an_pending = 1;
1025 mod_timer(&bp->timer, jiffies + bp->current_interval);
1026 }
1027 }
1028
1029 return 0;
1030 }
1031
1032 #define ETHTOOL_ALL_FIBRE_SPEED \
1033 (ADVERTISED_1000baseT_Full)
1034
1035 #define ETHTOOL_ALL_COPPER_SPEED \
1036 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1037 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1038 ADVERTISED_1000baseT_Full)
1039
1040 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1041 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1042
1043 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1044
1045 static int
1046 bnx2_setup_copper_phy(struct bnx2 *bp)
1047 {
1048 u32 bmcr;
1049 u32 new_bmcr;
1050
1051 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1052
1053 if (bp->autoneg & AUTONEG_SPEED) {
1054 u32 adv_reg, adv1000_reg;
1055 u32 new_adv_reg = 0;
1056 u32 new_adv1000_reg = 0;
1057
1058 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1059 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1060 ADVERTISE_PAUSE_ASYM);
1061
1062 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1063 adv1000_reg &= PHY_ALL_1000_SPEED;
1064
1065 if (bp->advertising & ADVERTISED_10baseT_Half)
1066 new_adv_reg |= ADVERTISE_10HALF;
1067 if (bp->advertising & ADVERTISED_10baseT_Full)
1068 new_adv_reg |= ADVERTISE_10FULL;
1069 if (bp->advertising & ADVERTISED_100baseT_Half)
1070 new_adv_reg |= ADVERTISE_100HALF;
1071 if (bp->advertising & ADVERTISED_100baseT_Full)
1072 new_adv_reg |= ADVERTISE_100FULL;
1073 if (bp->advertising & ADVERTISED_1000baseT_Full)
1074 new_adv1000_reg |= ADVERTISE_1000FULL;
1075
1076 new_adv_reg |= ADVERTISE_CSMA;
1077
1078 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1079
1080 if ((adv1000_reg != new_adv1000_reg) ||
1081 (adv_reg != new_adv_reg) ||
1082 ((bmcr & BMCR_ANENABLE) == 0)) {
1083
1084 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1085 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1086 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1087 BMCR_ANENABLE);
1088 }
1089 else if (bp->link_up) {
1090 /* Flow ctrl may have changed from auto to forced */
1091 /* or vice-versa. */
1092
1093 bnx2_resolve_flow_ctrl(bp);
1094 bnx2_set_mac_link(bp);
1095 }
1096 return 0;
1097 }
1098
1099 new_bmcr = 0;
1100 if (bp->req_line_speed == SPEED_100) {
1101 new_bmcr |= BMCR_SPEED100;
1102 }
1103 if (bp->req_duplex == DUPLEX_FULL) {
1104 new_bmcr |= BMCR_FULLDPLX;
1105 }
1106 if (new_bmcr != bmcr) {
1107 u32 bmsr;
1108 int i = 0;
1109
1110 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1111 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1112
1113 if (bmsr & BMSR_LSTATUS) {
1114 /* Force link down */
1115 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1116 do {
1117 udelay(100);
1118 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1119 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1120 i++;
1121 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1122 }
1123
1124 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1125
1126 /* Normally, the new speed is setup after the link has
1127 * gone down and up again. In some cases, link will not go
1128 * down so we need to set up the new speed here.
1129 */
1130 if (bmsr & BMSR_LSTATUS) {
1131 bp->line_speed = bp->req_line_speed;
1132 bp->duplex = bp->req_duplex;
1133 bnx2_resolve_flow_ctrl(bp);
1134 bnx2_set_mac_link(bp);
1135 }
1136 }
1137 return 0;
1138 }
1139
1140 static int
1141 bnx2_setup_phy(struct bnx2 *bp)
1142 {
1143 if (bp->loopback == MAC_LOOPBACK)
1144 return 0;
1145
1146 if (bp->phy_flags & PHY_SERDES_FLAG) {
1147 return (bnx2_setup_serdes_phy(bp));
1148 }
1149 else {
1150 return (bnx2_setup_copper_phy(bp));
1151 }
1152 }
1153
1154 static int
1155 bnx2_init_5708s_phy(struct bnx2 *bp)
1156 {
1157 u32 val;
1158
1159 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1160 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1161 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1162
1163 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1164 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1165 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1166
1167 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1168 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1169 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1170
1171 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1172 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1173 val |= BCM5708S_UP1_2G5;
1174 bnx2_write_phy(bp, BCM5708S_UP1, val);
1175 }
1176
1177 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1178 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1179 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1180 /* increase tx signal amplitude */
1181 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1182 BCM5708S_BLK_ADDR_TX_MISC);
1183 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1184 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1185 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1186 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1187 }
1188
1189 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1190 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1191
1192 if (val) {
1193 u32 is_backplane;
1194
1195 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1196 BNX2_SHARED_HW_CFG_CONFIG);
1197 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1198 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1199 BCM5708S_BLK_ADDR_TX_MISC);
1200 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1201 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1202 BCM5708S_BLK_ADDR_DIG);
1203 }
1204 }
1205 return 0;
1206 }
1207
1208 static int
1209 bnx2_init_5706s_phy(struct bnx2 *bp)
1210 {
1211 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1212
1213 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1214 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1215 }
1216
1217 if (bp->dev->mtu > 1500) {
1218 u32 val;
1219
1220 /* Set extended packet length bit */
1221 bnx2_write_phy(bp, 0x18, 0x7);
1222 bnx2_read_phy(bp, 0x18, &val);
1223 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1224
1225 bnx2_write_phy(bp, 0x1c, 0x6c00);
1226 bnx2_read_phy(bp, 0x1c, &val);
1227 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1228 }
1229 else {
1230 u32 val;
1231
1232 bnx2_write_phy(bp, 0x18, 0x7);
1233 bnx2_read_phy(bp, 0x18, &val);
1234 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1235
1236 bnx2_write_phy(bp, 0x1c, 0x6c00);
1237 bnx2_read_phy(bp, 0x1c, &val);
1238 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1239 }
1240
1241 return 0;
1242 }
1243
1244 static int
1245 bnx2_init_copper_phy(struct bnx2 *bp)
1246 {
1247 u32 val;
1248
1249 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1250
1251 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1252 bnx2_write_phy(bp, 0x18, 0x0c00);
1253 bnx2_write_phy(bp, 0x17, 0x000a);
1254 bnx2_write_phy(bp, 0x15, 0x310b);
1255 bnx2_write_phy(bp, 0x17, 0x201f);
1256 bnx2_write_phy(bp, 0x15, 0x9506);
1257 bnx2_write_phy(bp, 0x17, 0x401f);
1258 bnx2_write_phy(bp, 0x15, 0x14e2);
1259 bnx2_write_phy(bp, 0x18, 0x0400);
1260 }
1261
1262 if (bp->dev->mtu > 1500) {
1263 /* Set extended packet length bit */
1264 bnx2_write_phy(bp, 0x18, 0x7);
1265 bnx2_read_phy(bp, 0x18, &val);
1266 bnx2_write_phy(bp, 0x18, val | 0x4000);
1267
1268 bnx2_read_phy(bp, 0x10, &val);
1269 bnx2_write_phy(bp, 0x10, val | 0x1);
1270 }
1271 else {
1272 bnx2_write_phy(bp, 0x18, 0x7);
1273 bnx2_read_phy(bp, 0x18, &val);
1274 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1275
1276 bnx2_read_phy(bp, 0x10, &val);
1277 bnx2_write_phy(bp, 0x10, val & ~0x1);
1278 }
1279
1280 /* ethernet@wirespeed */
1281 bnx2_write_phy(bp, 0x18, 0x7007);
1282 bnx2_read_phy(bp, 0x18, &val);
1283 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1284 return 0;
1285 }
1286
1287
1288 static int
1289 bnx2_init_phy(struct bnx2 *bp)
1290 {
1291 u32 val;
1292 int rc = 0;
1293
1294 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1295 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1296
1297 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1298
1299 bnx2_reset_phy(bp);
1300
1301 bnx2_read_phy(bp, MII_PHYSID1, &val);
1302 bp->phy_id = val << 16;
1303 bnx2_read_phy(bp, MII_PHYSID2, &val);
1304 bp->phy_id |= val & 0xffff;
1305
1306 if (bp->phy_flags & PHY_SERDES_FLAG) {
1307 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1308 rc = bnx2_init_5706s_phy(bp);
1309 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1310 rc = bnx2_init_5708s_phy(bp);
1311 }
1312 else {
1313 rc = bnx2_init_copper_phy(bp);
1314 }
1315
1316 bnx2_setup_phy(bp);
1317
1318 return rc;
1319 }
1320
1321 static int
1322 bnx2_set_mac_loopback(struct bnx2 *bp)
1323 {
1324 u32 mac_mode;
1325
1326 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1327 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1328 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1329 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1330 bp->link_up = 1;
1331 return 0;
1332 }
1333
1334 static int bnx2_test_link(struct bnx2 *);
1335
1336 static int
1337 bnx2_set_phy_loopback(struct bnx2 *bp)
1338 {
1339 u32 mac_mode;
1340 int rc, i;
1341
1342 spin_lock_bh(&bp->phy_lock);
1343 rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1344 BMCR_SPEED1000);
1345 spin_unlock_bh(&bp->phy_lock);
1346 if (rc)
1347 return rc;
1348
1349 for (i = 0; i < 10; i++) {
1350 if (bnx2_test_link(bp) == 0)
1351 break;
1352 udelay(10);
1353 }
1354
1355 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1356 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1357 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1358 BNX2_EMAC_MODE_25G);
1359
1360 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1361 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1362 bp->link_up = 1;
1363 return 0;
1364 }
1365
1366 static int
1367 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1368 {
1369 int i;
1370 u32 val;
1371
1372 bp->fw_wr_seq++;
1373 msg_data |= bp->fw_wr_seq;
1374
1375 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1376
1377 /* wait for an acknowledgement. */
1378 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1379 msleep(10);
1380
1381 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1382
1383 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1384 break;
1385 }
1386 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1387 return 0;
1388
1389 /* If we timed out, inform the firmware that this is the case. */
1390 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1391 if (!silent)
1392 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1393 "%x\n", msg_data);
1394
1395 msg_data &= ~BNX2_DRV_MSG_CODE;
1396 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1397
1398 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1399
1400 return -EBUSY;
1401 }
1402
1403 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1404 return -EIO;
1405
1406 return 0;
1407 }
1408
1409 static void
1410 bnx2_init_context(struct bnx2 *bp)
1411 {
1412 u32 vcid;
1413
1414 vcid = 96;
1415 while (vcid) {
1416 u32 vcid_addr, pcid_addr, offset;
1417
1418 vcid--;
1419
1420 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1421 u32 new_vcid;
1422
1423 vcid_addr = GET_PCID_ADDR(vcid);
1424 if (vcid & 0x8) {
1425 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1426 }
1427 else {
1428 new_vcid = vcid;
1429 }
1430 pcid_addr = GET_PCID_ADDR(new_vcid);
1431 }
1432 else {
1433 vcid_addr = GET_CID_ADDR(vcid);
1434 pcid_addr = vcid_addr;
1435 }
1436
1437 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1438 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1439
1440 /* Zero out the context. */
1441 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1442 CTX_WR(bp, 0x00, offset, 0);
1443 }
1444
1445 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1446 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1447 }
1448 }
1449
1450 static int
1451 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1452 {
1453 u16 *good_mbuf;
1454 u32 good_mbuf_cnt;
1455 u32 val;
1456
1457 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1458 if (good_mbuf == NULL) {
1459 printk(KERN_ERR PFX "Failed to allocate memory in "
1460 "bnx2_alloc_bad_rbuf\n");
1461 return -ENOMEM;
1462 }
1463
1464 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1465 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1466
1467 good_mbuf_cnt = 0;
1468
1469 /* Allocate a bunch of mbufs and save the good ones in an array. */
1470 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1471 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1472 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1473
1474 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1475
1476 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1477
1478 /* The addresses with Bit 9 set are bad memory blocks. */
1479 if (!(val & (1 << 9))) {
1480 good_mbuf[good_mbuf_cnt] = (u16) val;
1481 good_mbuf_cnt++;
1482 }
1483
1484 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1485 }
1486
1487 /* Free the good ones back to the mbuf pool thus discarding
1488 * all the bad ones. */
1489 while (good_mbuf_cnt) {
1490 good_mbuf_cnt--;
1491
1492 val = good_mbuf[good_mbuf_cnt];
1493 val = (val << 9) | val | 1;
1494
1495 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1496 }
1497 kfree(good_mbuf);
1498 return 0;
1499 }
1500
1501 static void
1502 bnx2_set_mac_addr(struct bnx2 *bp)
1503 {
1504 u32 val;
1505 u8 *mac_addr = bp->dev->dev_addr;
1506
1507 val = (mac_addr[0] << 8) | mac_addr[1];
1508
1509 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1510
1511 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1512 (mac_addr[4] << 8) | mac_addr[5];
1513
1514 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1515 }
1516
1517 static inline int
1518 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1519 {
1520 struct sk_buff *skb;
1521 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1522 dma_addr_t mapping;
1523 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1524 unsigned long align;
1525
1526 skb = dev_alloc_skb(bp->rx_buf_size);
1527 if (skb == NULL) {
1528 return -ENOMEM;
1529 }
1530
1531 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1532 skb_reserve(skb, 8 - align);
1533 }
1534
1535 skb->dev = bp->dev;
1536 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1537 PCI_DMA_FROMDEVICE);
1538
1539 rx_buf->skb = skb;
1540 pci_unmap_addr_set(rx_buf, mapping, mapping);
1541
1542 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1543 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1544
1545 bp->rx_prod_bseq += bp->rx_buf_use_size;
1546
1547 return 0;
1548 }
1549
1550 static void
1551 bnx2_phy_int(struct bnx2 *bp)
1552 {
1553 u32 new_link_state, old_link_state;
1554
1555 new_link_state = bp->status_blk->status_attn_bits &
1556 STATUS_ATTN_BITS_LINK_STATE;
1557 old_link_state = bp->status_blk->status_attn_bits_ack &
1558 STATUS_ATTN_BITS_LINK_STATE;
1559 if (new_link_state != old_link_state) {
1560 if (new_link_state) {
1561 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1562 STATUS_ATTN_BITS_LINK_STATE);
1563 }
1564 else {
1565 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1566 STATUS_ATTN_BITS_LINK_STATE);
1567 }
1568 bnx2_set_link(bp);
1569 }
1570 }
1571
1572 static void
1573 bnx2_tx_int(struct bnx2 *bp)
1574 {
1575 struct status_block *sblk = bp->status_blk;
1576 u16 hw_cons, sw_cons, sw_ring_cons;
1577 int tx_free_bd = 0;
1578
1579 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1580 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1581 hw_cons++;
1582 }
1583 sw_cons = bp->tx_cons;
1584
1585 while (sw_cons != hw_cons) {
1586 struct sw_bd *tx_buf;
1587 struct sk_buff *skb;
1588 int i, last;
1589
1590 sw_ring_cons = TX_RING_IDX(sw_cons);
1591
1592 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1593 skb = tx_buf->skb;
1594 #ifdef BCM_TSO
1595 /* partial BD completions possible with TSO packets */
1596 if (skb_shinfo(skb)->tso_size) {
1597 u16 last_idx, last_ring_idx;
1598
1599 last_idx = sw_cons +
1600 skb_shinfo(skb)->nr_frags + 1;
1601 last_ring_idx = sw_ring_cons +
1602 skb_shinfo(skb)->nr_frags + 1;
1603 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1604 last_idx++;
1605 }
1606 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1607 break;
1608 }
1609 }
1610 #endif
1611 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1612 skb_headlen(skb), PCI_DMA_TODEVICE);
1613
1614 tx_buf->skb = NULL;
1615 last = skb_shinfo(skb)->nr_frags;
1616
1617 for (i = 0; i < last; i++) {
1618 sw_cons = NEXT_TX_BD(sw_cons);
1619
1620 pci_unmap_page(bp->pdev,
1621 pci_unmap_addr(
1622 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1623 mapping),
1624 skb_shinfo(skb)->frags[i].size,
1625 PCI_DMA_TODEVICE);
1626 }
1627
1628 sw_cons = NEXT_TX_BD(sw_cons);
1629
1630 tx_free_bd += last + 1;
1631
1632 dev_kfree_skb_irq(skb);
1633
1634 hw_cons = bp->hw_tx_cons =
1635 sblk->status_tx_quick_consumer_index0;
1636
1637 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1638 hw_cons++;
1639 }
1640 }
1641
1642 bp->tx_cons = sw_cons;
1643
1644 if (unlikely(netif_queue_stopped(bp->dev))) {
1645 spin_lock(&bp->tx_lock);
1646 if ((netif_queue_stopped(bp->dev)) &&
1647 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1648
1649 netif_wake_queue(bp->dev);
1650 }
1651 spin_unlock(&bp->tx_lock);
1652 }
1653 }
1654
1655 static inline void
1656 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1657 u16 cons, u16 prod)
1658 {
1659 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1660 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1661 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1662 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1663
1664 pci_dma_sync_single_for_device(bp->pdev,
1665 pci_unmap_addr(cons_rx_buf, mapping),
1666 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1667
1668 prod_rx_buf->skb = cons_rx_buf->skb;
1669 pci_unmap_addr_set(prod_rx_buf, mapping,
1670 pci_unmap_addr(cons_rx_buf, mapping));
1671
1672 memcpy(prod_bd, cons_bd, 8);
1673
1674 bp->rx_prod_bseq += bp->rx_buf_use_size;
1675
1676 }
1677
1678 static int
1679 bnx2_rx_int(struct bnx2 *bp, int budget)
1680 {
1681 struct status_block *sblk = bp->status_blk;
1682 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1683 struct l2_fhdr *rx_hdr;
1684 int rx_pkt = 0;
1685
1686 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1687 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1688 hw_cons++;
1689 }
1690 sw_cons = bp->rx_cons;
1691 sw_prod = bp->rx_prod;
1692
1693 /* Memory barrier necessary as speculative reads of the rx
1694 * buffer can be ahead of the index in the status block
1695 */
1696 rmb();
1697 while (sw_cons != hw_cons) {
1698 unsigned int len;
1699 u32 status;
1700 struct sw_bd *rx_buf;
1701 struct sk_buff *skb;
1702
1703 sw_ring_cons = RX_RING_IDX(sw_cons);
1704 sw_ring_prod = RX_RING_IDX(sw_prod);
1705
1706 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1707 skb = rx_buf->skb;
1708 pci_dma_sync_single_for_cpu(bp->pdev,
1709 pci_unmap_addr(rx_buf, mapping),
1710 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1711
1712 rx_hdr = (struct l2_fhdr *) skb->data;
1713 len = rx_hdr->l2_fhdr_pkt_len - 4;
1714
1715 if ((status = rx_hdr->l2_fhdr_status) &
1716 (L2_FHDR_ERRORS_BAD_CRC |
1717 L2_FHDR_ERRORS_PHY_DECODE |
1718 L2_FHDR_ERRORS_ALIGNMENT |
1719 L2_FHDR_ERRORS_TOO_SHORT |
1720 L2_FHDR_ERRORS_GIANT_FRAME)) {
1721
1722 goto reuse_rx;
1723 }
1724
1725 /* Since we don't have a jumbo ring, copy small packets
1726 * if mtu > 1500
1727 */
1728 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1729 struct sk_buff *new_skb;
1730
1731 new_skb = dev_alloc_skb(len + 2);
1732 if (new_skb == NULL)
1733 goto reuse_rx;
1734
1735 /* aligned copy */
1736 memcpy(new_skb->data,
1737 skb->data + bp->rx_offset - 2,
1738 len + 2);
1739
1740 skb_reserve(new_skb, 2);
1741 skb_put(new_skb, len);
1742 new_skb->dev = bp->dev;
1743
1744 bnx2_reuse_rx_skb(bp, skb,
1745 sw_ring_cons, sw_ring_prod);
1746
1747 skb = new_skb;
1748 }
1749 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1750 pci_unmap_single(bp->pdev,
1751 pci_unmap_addr(rx_buf, mapping),
1752 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1753
1754 skb_reserve(skb, bp->rx_offset);
1755 skb_put(skb, len);
1756 }
1757 else {
1758 reuse_rx:
1759 bnx2_reuse_rx_skb(bp, skb,
1760 sw_ring_cons, sw_ring_prod);
1761 goto next_rx;
1762 }
1763
1764 skb->protocol = eth_type_trans(skb, bp->dev);
1765
1766 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1767 (htons(skb->protocol) != 0x8100)) {
1768
1769 dev_kfree_skb_irq(skb);
1770 goto next_rx;
1771
1772 }
1773
1774 skb->ip_summed = CHECKSUM_NONE;
1775 if (bp->rx_csum &&
1776 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1777 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1778
1779 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1780 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1781 skb->ip_summed = CHECKSUM_UNNECESSARY;
1782 }
1783
1784 #ifdef BCM_VLAN
1785 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1786 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1787 rx_hdr->l2_fhdr_vlan_tag);
1788 }
1789 else
1790 #endif
1791 netif_receive_skb(skb);
1792
1793 bp->dev->last_rx = jiffies;
1794 rx_pkt++;
1795
1796 next_rx:
1797 rx_buf->skb = NULL;
1798
1799 sw_cons = NEXT_RX_BD(sw_cons);
1800 sw_prod = NEXT_RX_BD(sw_prod);
1801
1802 if ((rx_pkt == budget))
1803 break;
1804
1805 /* Refresh hw_cons to see if there is new work */
1806 if (sw_cons == hw_cons) {
1807 hw_cons = bp->hw_rx_cons =
1808 sblk->status_rx_quick_consumer_index0;
1809 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1810 hw_cons++;
1811 rmb();
1812 }
1813 }
1814 bp->rx_cons = sw_cons;
1815 bp->rx_prod = sw_prod;
1816
1817 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1818
1819 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1820
1821 mmiowb();
1822
1823 return rx_pkt;
1824
1825 }
1826
1827 /* MSI ISR - The only difference between this and the INTx ISR
1828 * is that the MSI interrupt is always serviced.
1829 */
1830 static irqreturn_t
1831 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1832 {
1833 struct net_device *dev = dev_instance;
1834 struct bnx2 *bp = netdev_priv(dev);
1835
1836 prefetch(bp->status_blk);
1837 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1838 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1839 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1840
1841 /* Return here if interrupt is disabled. */
1842 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1843 return IRQ_HANDLED;
1844
1845 netif_rx_schedule(dev);
1846
1847 return IRQ_HANDLED;
1848 }
1849
1850 static irqreturn_t
1851 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1852 {
1853 struct net_device *dev = dev_instance;
1854 struct bnx2 *bp = netdev_priv(dev);
1855
1856 /* When using INTx, it is possible for the interrupt to arrive
1857 * at the CPU before the status block posted prior to the
1858 * interrupt. Reading a register will flush the status block.
1859 * When using MSI, the MSI message will always complete after
1860 * the status block write.
1861 */
1862 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1863 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1864 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1865 return IRQ_NONE;
1866
1867 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1868 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1869 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1870
1871 /* Return here if interrupt is shared and is disabled. */
1872 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1873 return IRQ_HANDLED;
1874
1875 netif_rx_schedule(dev);
1876
1877 return IRQ_HANDLED;
1878 }
1879
1880 static inline int
1881 bnx2_has_work(struct bnx2 *bp)
1882 {
1883 struct status_block *sblk = bp->status_blk;
1884
1885 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1886 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1887 return 1;
1888
1889 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1890 bp->link_up)
1891 return 1;
1892
1893 return 0;
1894 }
1895
1896 static int
1897 bnx2_poll(struct net_device *dev, int *budget)
1898 {
1899 struct bnx2 *bp = netdev_priv(dev);
1900
1901 if ((bp->status_blk->status_attn_bits &
1902 STATUS_ATTN_BITS_LINK_STATE) !=
1903 (bp->status_blk->status_attn_bits_ack &
1904 STATUS_ATTN_BITS_LINK_STATE)) {
1905
1906 spin_lock(&bp->phy_lock);
1907 bnx2_phy_int(bp);
1908 spin_unlock(&bp->phy_lock);
1909 }
1910
1911 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1912 bnx2_tx_int(bp);
1913
1914 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1915 int orig_budget = *budget;
1916 int work_done;
1917
1918 if (orig_budget > dev->quota)
1919 orig_budget = dev->quota;
1920
1921 work_done = bnx2_rx_int(bp, orig_budget);
1922 *budget -= work_done;
1923 dev->quota -= work_done;
1924 }
1925
1926 bp->last_status_idx = bp->status_blk->status_idx;
1927 rmb();
1928
1929 if (!bnx2_has_work(bp)) {
1930 netif_rx_complete(dev);
1931 if (likely(bp->flags & USING_MSI_FLAG)) {
1932 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1933 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1934 bp->last_status_idx);
1935 return 0;
1936 }
1937 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1938 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1939 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
1940 bp->last_status_idx);
1941
1942 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1943 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1944 bp->last_status_idx);
1945 return 0;
1946 }
1947
1948 return 1;
1949 }
1950
1951 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1952 * from set_multicast.
1953 */
1954 static void
1955 bnx2_set_rx_mode(struct net_device *dev)
1956 {
1957 struct bnx2 *bp = netdev_priv(dev);
1958 u32 rx_mode, sort_mode;
1959 int i;
1960
1961 spin_lock_bh(&bp->phy_lock);
1962
1963 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1964 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1965 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1966 #ifdef BCM_VLAN
1967 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
1968 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1969 #else
1970 if (!(bp->flags & ASF_ENABLE_FLAG))
1971 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1972 #endif
1973 if (dev->flags & IFF_PROMISC) {
1974 /* Promiscuous mode. */
1975 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1976 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1977 }
1978 else if (dev->flags & IFF_ALLMULTI) {
1979 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1980 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1981 0xffffffff);
1982 }
1983 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1984 }
1985 else {
1986 /* Accept one or more multicast(s). */
1987 struct dev_mc_list *mclist;
1988 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1989 u32 regidx;
1990 u32 bit;
1991 u32 crc;
1992
1993 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1994
1995 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1996 i++, mclist = mclist->next) {
1997
1998 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1999 bit = crc & 0xff;
2000 regidx = (bit & 0xe0) >> 5;
2001 bit &= 0x1f;
2002 mc_filter[regidx] |= (1 << bit);
2003 }
2004
2005 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2006 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2007 mc_filter[i]);
2008 }
2009
2010 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2011 }
2012
2013 if (rx_mode != bp->rx_mode) {
2014 bp->rx_mode = rx_mode;
2015 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2016 }
2017
2018 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2019 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2020 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2021
2022 spin_unlock_bh(&bp->phy_lock);
2023 }
2024
2025 static void
2026 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2027 u32 rv2p_proc)
2028 {
2029 int i;
2030 u32 val;
2031
2032
2033 for (i = 0; i < rv2p_code_len; i += 8) {
2034 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
2035 rv2p_code++;
2036 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
2037 rv2p_code++;
2038
2039 if (rv2p_proc == RV2P_PROC1) {
2040 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2041 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2042 }
2043 else {
2044 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2045 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2046 }
2047 }
2048
2049 /* Reset the processor, un-stall is done later. */
2050 if (rv2p_proc == RV2P_PROC1) {
2051 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2052 }
2053 else {
2054 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2055 }
2056 }
2057
2058 static void
2059 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2060 {
2061 u32 offset;
2062 u32 val;
2063
2064 /* Halt the CPU. */
2065 val = REG_RD_IND(bp, cpu_reg->mode);
2066 val |= cpu_reg->mode_value_halt;
2067 REG_WR_IND(bp, cpu_reg->mode, val);
2068 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2069
2070 /* Load the Text area. */
2071 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2072 if (fw->text) {
2073 int j;
2074
2075 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2076 REG_WR_IND(bp, offset, fw->text[j]);
2077 }
2078 }
2079
2080 /* Load the Data area. */
2081 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2082 if (fw->data) {
2083 int j;
2084
2085 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2086 REG_WR_IND(bp, offset, fw->data[j]);
2087 }
2088 }
2089
2090 /* Load the SBSS area. */
2091 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2092 if (fw->sbss) {
2093 int j;
2094
2095 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2096 REG_WR_IND(bp, offset, fw->sbss[j]);
2097 }
2098 }
2099
2100 /* Load the BSS area. */
2101 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2102 if (fw->bss) {
2103 int j;
2104
2105 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2106 REG_WR_IND(bp, offset, fw->bss[j]);
2107 }
2108 }
2109
2110 /* Load the Read-Only area. */
2111 offset = cpu_reg->spad_base +
2112 (fw->rodata_addr - cpu_reg->mips_view_base);
2113 if (fw->rodata) {
2114 int j;
2115
2116 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2117 REG_WR_IND(bp, offset, fw->rodata[j]);
2118 }
2119 }
2120
2121 /* Clear the pre-fetch instruction. */
2122 REG_WR_IND(bp, cpu_reg->inst, 0);
2123 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2124
2125 /* Start the CPU. */
2126 val = REG_RD_IND(bp, cpu_reg->mode);
2127 val &= ~cpu_reg->mode_value_halt;
2128 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2129 REG_WR_IND(bp, cpu_reg->mode, val);
2130 }
2131
2132 static void
2133 bnx2_init_cpus(struct bnx2 *bp)
2134 {
2135 struct cpu_reg cpu_reg;
2136 struct fw_info fw;
2137
2138 /* Initialize the RV2P processor. */
2139 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2140 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2141
2142 /* Initialize the RX Processor. */
2143 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2144 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2145 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2146 cpu_reg.state = BNX2_RXP_CPU_STATE;
2147 cpu_reg.state_value_clear = 0xffffff;
2148 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2149 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2150 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2151 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2152 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2153 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2154 cpu_reg.mips_view_base = 0x8000000;
2155
2156 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2157 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2158 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2159 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2160
2161 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2162 fw.text_len = bnx2_RXP_b06FwTextLen;
2163 fw.text_index = 0;
2164 fw.text = bnx2_RXP_b06FwText;
2165
2166 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2167 fw.data_len = bnx2_RXP_b06FwDataLen;
2168 fw.data_index = 0;
2169 fw.data = bnx2_RXP_b06FwData;
2170
2171 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2172 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2173 fw.sbss_index = 0;
2174 fw.sbss = bnx2_RXP_b06FwSbss;
2175
2176 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2177 fw.bss_len = bnx2_RXP_b06FwBssLen;
2178 fw.bss_index = 0;
2179 fw.bss = bnx2_RXP_b06FwBss;
2180
2181 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2182 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2183 fw.rodata_index = 0;
2184 fw.rodata = bnx2_RXP_b06FwRodata;
2185
2186 load_cpu_fw(bp, &cpu_reg, &fw);
2187
2188 /* Initialize the TX Processor. */
2189 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2190 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2191 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2192 cpu_reg.state = BNX2_TXP_CPU_STATE;
2193 cpu_reg.state_value_clear = 0xffffff;
2194 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2195 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2196 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2197 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2198 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2199 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2200 cpu_reg.mips_view_base = 0x8000000;
2201
2202 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2203 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2204 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2205 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2206
2207 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2208 fw.text_len = bnx2_TXP_b06FwTextLen;
2209 fw.text_index = 0;
2210 fw.text = bnx2_TXP_b06FwText;
2211
2212 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2213 fw.data_len = bnx2_TXP_b06FwDataLen;
2214 fw.data_index = 0;
2215 fw.data = bnx2_TXP_b06FwData;
2216
2217 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2218 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2219 fw.sbss_index = 0;
2220 fw.sbss = bnx2_TXP_b06FwSbss;
2221
2222 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2223 fw.bss_len = bnx2_TXP_b06FwBssLen;
2224 fw.bss_index = 0;
2225 fw.bss = bnx2_TXP_b06FwBss;
2226
2227 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2228 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2229 fw.rodata_index = 0;
2230 fw.rodata = bnx2_TXP_b06FwRodata;
2231
2232 load_cpu_fw(bp, &cpu_reg, &fw);
2233
2234 /* Initialize the TX Patch-up Processor. */
2235 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2236 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2237 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2238 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2239 cpu_reg.state_value_clear = 0xffffff;
2240 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2241 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2242 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2243 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2244 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2245 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2246 cpu_reg.mips_view_base = 0x8000000;
2247
2248 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2249 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2250 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2251 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2252
2253 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2254 fw.text_len = bnx2_TPAT_b06FwTextLen;
2255 fw.text_index = 0;
2256 fw.text = bnx2_TPAT_b06FwText;
2257
2258 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2259 fw.data_len = bnx2_TPAT_b06FwDataLen;
2260 fw.data_index = 0;
2261 fw.data = bnx2_TPAT_b06FwData;
2262
2263 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2264 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2265 fw.sbss_index = 0;
2266 fw.sbss = bnx2_TPAT_b06FwSbss;
2267
2268 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2269 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2270 fw.bss_index = 0;
2271 fw.bss = bnx2_TPAT_b06FwBss;
2272
2273 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2274 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2275 fw.rodata_index = 0;
2276 fw.rodata = bnx2_TPAT_b06FwRodata;
2277
2278 load_cpu_fw(bp, &cpu_reg, &fw);
2279
2280 /* Initialize the Completion Processor. */
2281 cpu_reg.mode = BNX2_COM_CPU_MODE;
2282 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2283 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2284 cpu_reg.state = BNX2_COM_CPU_STATE;
2285 cpu_reg.state_value_clear = 0xffffff;
2286 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2287 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2288 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2289 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2290 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2291 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2292 cpu_reg.mips_view_base = 0x8000000;
2293
2294 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2295 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2296 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2297 fw.start_addr = bnx2_COM_b06FwStartAddr;
2298
2299 fw.text_addr = bnx2_COM_b06FwTextAddr;
2300 fw.text_len = bnx2_COM_b06FwTextLen;
2301 fw.text_index = 0;
2302 fw.text = bnx2_COM_b06FwText;
2303
2304 fw.data_addr = bnx2_COM_b06FwDataAddr;
2305 fw.data_len = bnx2_COM_b06FwDataLen;
2306 fw.data_index = 0;
2307 fw.data = bnx2_COM_b06FwData;
2308
2309 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2310 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2311 fw.sbss_index = 0;
2312 fw.sbss = bnx2_COM_b06FwSbss;
2313
2314 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2315 fw.bss_len = bnx2_COM_b06FwBssLen;
2316 fw.bss_index = 0;
2317 fw.bss = bnx2_COM_b06FwBss;
2318
2319 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2320 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2321 fw.rodata_index = 0;
2322 fw.rodata = bnx2_COM_b06FwRodata;
2323
2324 load_cpu_fw(bp, &cpu_reg, &fw);
2325
2326 }
2327
2328 static int
2329 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2330 {
2331 u16 pmcsr;
2332
2333 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2334
2335 switch (state) {
2336 case PCI_D0: {
2337 u32 val;
2338
2339 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2340 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2341 PCI_PM_CTRL_PME_STATUS);
2342
2343 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2344 /* delay required during transition out of D3hot */
2345 msleep(20);
2346
2347 val = REG_RD(bp, BNX2_EMAC_MODE);
2348 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2349 val &= ~BNX2_EMAC_MODE_MPKT;
2350 REG_WR(bp, BNX2_EMAC_MODE, val);
2351
2352 val = REG_RD(bp, BNX2_RPM_CONFIG);
2353 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2354 REG_WR(bp, BNX2_RPM_CONFIG, val);
2355 break;
2356 }
2357 case PCI_D3hot: {
2358 int i;
2359 u32 val, wol_msg;
2360
2361 if (bp->wol) {
2362 u32 advertising;
2363 u8 autoneg;
2364
2365 autoneg = bp->autoneg;
2366 advertising = bp->advertising;
2367
2368 bp->autoneg = AUTONEG_SPEED;
2369 bp->advertising = ADVERTISED_10baseT_Half |
2370 ADVERTISED_10baseT_Full |
2371 ADVERTISED_100baseT_Half |
2372 ADVERTISED_100baseT_Full |
2373 ADVERTISED_Autoneg;
2374
2375 bnx2_setup_copper_phy(bp);
2376
2377 bp->autoneg = autoneg;
2378 bp->advertising = advertising;
2379
2380 bnx2_set_mac_addr(bp);
2381
2382 val = REG_RD(bp, BNX2_EMAC_MODE);
2383
2384 /* Enable port mode. */
2385 val &= ~BNX2_EMAC_MODE_PORT;
2386 val |= BNX2_EMAC_MODE_PORT_MII |
2387 BNX2_EMAC_MODE_MPKT_RCVD |
2388 BNX2_EMAC_MODE_ACPI_RCVD |
2389 BNX2_EMAC_MODE_MPKT;
2390
2391 REG_WR(bp, BNX2_EMAC_MODE, val);
2392
2393 /* receive all multicast */
2394 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2395 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2396 0xffffffff);
2397 }
2398 REG_WR(bp, BNX2_EMAC_RX_MODE,
2399 BNX2_EMAC_RX_MODE_SORT_MODE);
2400
2401 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2402 BNX2_RPM_SORT_USER0_MC_EN;
2403 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2404 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2405 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2406 BNX2_RPM_SORT_USER0_ENA);
2407
2408 /* Need to enable EMAC and RPM for WOL. */
2409 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2410 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2411 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2412 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2413
2414 val = REG_RD(bp, BNX2_RPM_CONFIG);
2415 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2416 REG_WR(bp, BNX2_RPM_CONFIG, val);
2417
2418 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2419 }
2420 else {
2421 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2422 }
2423
2424 if (!(bp->flags & NO_WOL_FLAG))
2425 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2426
2427 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2428 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2429 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2430
2431 if (bp->wol)
2432 pmcsr |= 3;
2433 }
2434 else {
2435 pmcsr |= 3;
2436 }
2437 if (bp->wol) {
2438 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2439 }
2440 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2441 pmcsr);
2442
2443 /* No more memory access after this point until
2444 * device is brought back to D0.
2445 */
2446 udelay(50);
2447 break;
2448 }
2449 default:
2450 return -EINVAL;
2451 }
2452 return 0;
2453 }
2454
2455 static int
2456 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2457 {
2458 u32 val;
2459 int j;
2460
2461 /* Request access to the flash interface. */
2462 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2463 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2464 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2465 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2466 break;
2467
2468 udelay(5);
2469 }
2470
2471 if (j >= NVRAM_TIMEOUT_COUNT)
2472 return -EBUSY;
2473
2474 return 0;
2475 }
2476
2477 static int
2478 bnx2_release_nvram_lock(struct bnx2 *bp)
2479 {
2480 int j;
2481 u32 val;
2482
2483 /* Relinquish nvram interface. */
2484 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2485
2486 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2487 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2488 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2489 break;
2490
2491 udelay(5);
2492 }
2493
2494 if (j >= NVRAM_TIMEOUT_COUNT)
2495 return -EBUSY;
2496
2497 return 0;
2498 }
2499
2500
2501 static int
2502 bnx2_enable_nvram_write(struct bnx2 *bp)
2503 {
2504 u32 val;
2505
2506 val = REG_RD(bp, BNX2_MISC_CFG);
2507 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2508
2509 if (!bp->flash_info->buffered) {
2510 int j;
2511
2512 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2513 REG_WR(bp, BNX2_NVM_COMMAND,
2514 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2515
2516 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2517 udelay(5);
2518
2519 val = REG_RD(bp, BNX2_NVM_COMMAND);
2520 if (val & BNX2_NVM_COMMAND_DONE)
2521 break;
2522 }
2523
2524 if (j >= NVRAM_TIMEOUT_COUNT)
2525 return -EBUSY;
2526 }
2527 return 0;
2528 }
2529
2530 static void
2531 bnx2_disable_nvram_write(struct bnx2 *bp)
2532 {
2533 u32 val;
2534
2535 val = REG_RD(bp, BNX2_MISC_CFG);
2536 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2537 }
2538
2539
2540 static void
2541 bnx2_enable_nvram_access(struct bnx2 *bp)
2542 {
2543 u32 val;
2544
2545 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2546 /* Enable both bits, even on read. */
2547 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2548 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2549 }
2550
2551 static void
2552 bnx2_disable_nvram_access(struct bnx2 *bp)
2553 {
2554 u32 val;
2555
2556 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2557 /* Disable both bits, even after read. */
2558 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2559 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2560 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2561 }
2562
2563 static int
2564 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2565 {
2566 u32 cmd;
2567 int j;
2568
2569 if (bp->flash_info->buffered)
2570 /* Buffered flash, no erase needed */
2571 return 0;
2572
2573 /* Build an erase command */
2574 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2575 BNX2_NVM_COMMAND_DOIT;
2576
2577 /* Need to clear DONE bit separately. */
2578 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2579
2580 /* Address of the NVRAM to read from. */
2581 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2582
2583 /* Issue an erase command. */
2584 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2585
2586 /* Wait for completion. */
2587 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2588 u32 val;
2589
2590 udelay(5);
2591
2592 val = REG_RD(bp, BNX2_NVM_COMMAND);
2593 if (val & BNX2_NVM_COMMAND_DONE)
2594 break;
2595 }
2596
2597 if (j >= NVRAM_TIMEOUT_COUNT)
2598 return -EBUSY;
2599
2600 return 0;
2601 }
2602
2603 static int
2604 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2605 {
2606 u32 cmd;
2607 int j;
2608
2609 /* Build the command word. */
2610 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2611
2612 /* Calculate an offset of a buffered flash. */
2613 if (bp->flash_info->buffered) {
2614 offset = ((offset / bp->flash_info->page_size) <<
2615 bp->flash_info->page_bits) +
2616 (offset % bp->flash_info->page_size);
2617 }
2618
2619 /* Need to clear DONE bit separately. */
2620 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2621
2622 /* Address of the NVRAM to read from. */
2623 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2624
2625 /* Issue a read command. */
2626 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2627
2628 /* Wait for completion. */
2629 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2630 u32 val;
2631
2632 udelay(5);
2633
2634 val = REG_RD(bp, BNX2_NVM_COMMAND);
2635 if (val & BNX2_NVM_COMMAND_DONE) {
2636 val = REG_RD(bp, BNX2_NVM_READ);
2637
2638 val = be32_to_cpu(val);
2639 memcpy(ret_val, &val, 4);
2640 break;
2641 }
2642 }
2643 if (j >= NVRAM_TIMEOUT_COUNT)
2644 return -EBUSY;
2645
2646 return 0;
2647 }
2648
2649
2650 static int
2651 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2652 {
2653 u32 cmd, val32;
2654 int j;
2655
2656 /* Build the command word. */
2657 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2658
2659 /* Calculate an offset of a buffered flash. */
2660 if (bp->flash_info->buffered) {
2661 offset = ((offset / bp->flash_info->page_size) <<
2662 bp->flash_info->page_bits) +
2663 (offset % bp->flash_info->page_size);
2664 }
2665
2666 /* Need to clear DONE bit separately. */
2667 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2668
2669 memcpy(&val32, val, 4);
2670 val32 = cpu_to_be32(val32);
2671
2672 /* Write the data. */
2673 REG_WR(bp, BNX2_NVM_WRITE, val32);
2674
2675 /* Address of the NVRAM to write to. */
2676 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2677
2678 /* Issue the write command. */
2679 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2680
2681 /* Wait for completion. */
2682 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2683 udelay(5);
2684
2685 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2686 break;
2687 }
2688 if (j >= NVRAM_TIMEOUT_COUNT)
2689 return -EBUSY;
2690
2691 return 0;
2692 }
2693
2694 static int
2695 bnx2_init_nvram(struct bnx2 *bp)
2696 {
2697 u32 val;
2698 int j, entry_count, rc;
2699 struct flash_spec *flash;
2700
2701 /* Determine the selected interface. */
2702 val = REG_RD(bp, BNX2_NVM_CFG1);
2703
2704 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2705
2706 rc = 0;
2707 if (val & 0x40000000) {
2708
2709 /* Flash interface has been reconfigured */
2710 for (j = 0, flash = &flash_table[0]; j < entry_count;
2711 j++, flash++) {
2712 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2713 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2714 bp->flash_info = flash;
2715 break;
2716 }
2717 }
2718 }
2719 else {
2720 u32 mask;
2721 /* Not yet been reconfigured */
2722
2723 if (val & (1 << 23))
2724 mask = FLASH_BACKUP_STRAP_MASK;
2725 else
2726 mask = FLASH_STRAP_MASK;
2727
2728 for (j = 0, flash = &flash_table[0]; j < entry_count;
2729 j++, flash++) {
2730
2731 if ((val & mask) == (flash->strapping & mask)) {
2732 bp->flash_info = flash;
2733
2734 /* Request access to the flash interface. */
2735 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2736 return rc;
2737
2738 /* Enable access to flash interface */
2739 bnx2_enable_nvram_access(bp);
2740
2741 /* Reconfigure the flash interface */
2742 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2743 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2744 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2745 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2746
2747 /* Disable access to flash interface */
2748 bnx2_disable_nvram_access(bp);
2749 bnx2_release_nvram_lock(bp);
2750
2751 break;
2752 }
2753 }
2754 } /* if (val & 0x40000000) */
2755
2756 if (j == entry_count) {
2757 bp->flash_info = NULL;
2758 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2759 return -ENODEV;
2760 }
2761
2762 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2763 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2764 if (val)
2765 bp->flash_size = val;
2766 else
2767 bp->flash_size = bp->flash_info->total_size;
2768
2769 return rc;
2770 }
2771
2772 static int
2773 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2774 int buf_size)
2775 {
2776 int rc = 0;
2777 u32 cmd_flags, offset32, len32, extra;
2778
2779 if (buf_size == 0)
2780 return 0;
2781
2782 /* Request access to the flash interface. */
2783 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2784 return rc;
2785
2786 /* Enable access to flash interface */
2787 bnx2_enable_nvram_access(bp);
2788
2789 len32 = buf_size;
2790 offset32 = offset;
2791 extra = 0;
2792
2793 cmd_flags = 0;
2794
2795 if (offset32 & 3) {
2796 u8 buf[4];
2797 u32 pre_len;
2798
2799 offset32 &= ~3;
2800 pre_len = 4 - (offset & 3);
2801
2802 if (pre_len >= len32) {
2803 pre_len = len32;
2804 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2805 BNX2_NVM_COMMAND_LAST;
2806 }
2807 else {
2808 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2809 }
2810
2811 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2812
2813 if (rc)
2814 return rc;
2815
2816 memcpy(ret_buf, buf + (offset & 3), pre_len);
2817
2818 offset32 += 4;
2819 ret_buf += pre_len;
2820 len32 -= pre_len;
2821 }
2822 if (len32 & 3) {
2823 extra = 4 - (len32 & 3);
2824 len32 = (len32 + 4) & ~3;
2825 }
2826
2827 if (len32 == 4) {
2828 u8 buf[4];
2829
2830 if (cmd_flags)
2831 cmd_flags = BNX2_NVM_COMMAND_LAST;
2832 else
2833 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2834 BNX2_NVM_COMMAND_LAST;
2835
2836 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2837
2838 memcpy(ret_buf, buf, 4 - extra);
2839 }
2840 else if (len32 > 0) {
2841 u8 buf[4];
2842
2843 /* Read the first word. */
2844 if (cmd_flags)
2845 cmd_flags = 0;
2846 else
2847 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2848
2849 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2850
2851 /* Advance to the next dword. */
2852 offset32 += 4;
2853 ret_buf += 4;
2854 len32 -= 4;
2855
2856 while (len32 > 4 && rc == 0) {
2857 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2858
2859 /* Advance to the next dword. */
2860 offset32 += 4;
2861 ret_buf += 4;
2862 len32 -= 4;
2863 }
2864
2865 if (rc)
2866 return rc;
2867
2868 cmd_flags = BNX2_NVM_COMMAND_LAST;
2869 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2870
2871 memcpy(ret_buf, buf, 4 - extra);
2872 }
2873
2874 /* Disable access to flash interface */
2875 bnx2_disable_nvram_access(bp);
2876
2877 bnx2_release_nvram_lock(bp);
2878
2879 return rc;
2880 }
2881
2882 static int
2883 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2884 int buf_size)
2885 {
2886 u32 written, offset32, len32;
2887 u8 *buf, start[4], end[4];
2888 int rc = 0;
2889 int align_start, align_end;
2890
2891 buf = data_buf;
2892 offset32 = offset;
2893 len32 = buf_size;
2894 align_start = align_end = 0;
2895
2896 if ((align_start = (offset32 & 3))) {
2897 offset32 &= ~3;
2898 len32 += align_start;
2899 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2900 return rc;
2901 }
2902
2903 if (len32 & 3) {
2904 if ((len32 > 4) || !align_start) {
2905 align_end = 4 - (len32 & 3);
2906 len32 += align_end;
2907 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2908 end, 4))) {
2909 return rc;
2910 }
2911 }
2912 }
2913
2914 if (align_start || align_end) {
2915 buf = kmalloc(len32, GFP_KERNEL);
2916 if (buf == 0)
2917 return -ENOMEM;
2918 if (align_start) {
2919 memcpy(buf, start, 4);
2920 }
2921 if (align_end) {
2922 memcpy(buf + len32 - 4, end, 4);
2923 }
2924 memcpy(buf + align_start, data_buf, buf_size);
2925 }
2926
2927 written = 0;
2928 while ((written < len32) && (rc == 0)) {
2929 u32 page_start, page_end, data_start, data_end;
2930 u32 addr, cmd_flags;
2931 int i;
2932 u8 flash_buffer[264];
2933
2934 /* Find the page_start addr */
2935 page_start = offset32 + written;
2936 page_start -= (page_start % bp->flash_info->page_size);
2937 /* Find the page_end addr */
2938 page_end = page_start + bp->flash_info->page_size;
2939 /* Find the data_start addr */
2940 data_start = (written == 0) ? offset32 : page_start;
2941 /* Find the data_end addr */
2942 data_end = (page_end > offset32 + len32) ?
2943 (offset32 + len32) : page_end;
2944
2945 /* Request access to the flash interface. */
2946 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2947 goto nvram_write_end;
2948
2949 /* Enable access to flash interface */
2950 bnx2_enable_nvram_access(bp);
2951
2952 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2953 if (bp->flash_info->buffered == 0) {
2954 int j;
2955
2956 /* Read the whole page into the buffer
2957 * (non-buffer flash only) */
2958 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2959 if (j == (bp->flash_info->page_size - 4)) {
2960 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2961 }
2962 rc = bnx2_nvram_read_dword(bp,
2963 page_start + j,
2964 &flash_buffer[j],
2965 cmd_flags);
2966
2967 if (rc)
2968 goto nvram_write_end;
2969
2970 cmd_flags = 0;
2971 }
2972 }
2973
2974 /* Enable writes to flash interface (unlock write-protect) */
2975 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2976 goto nvram_write_end;
2977
2978 /* Erase the page */
2979 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2980 goto nvram_write_end;
2981
2982 /* Re-enable the write again for the actual write */
2983 bnx2_enable_nvram_write(bp);
2984
2985 /* Loop to write back the buffer data from page_start to
2986 * data_start */
2987 i = 0;
2988 if (bp->flash_info->buffered == 0) {
2989 for (addr = page_start; addr < data_start;
2990 addr += 4, i += 4) {
2991
2992 rc = bnx2_nvram_write_dword(bp, addr,
2993 &flash_buffer[i], cmd_flags);
2994
2995 if (rc != 0)
2996 goto nvram_write_end;
2997
2998 cmd_flags = 0;
2999 }
3000 }
3001
3002 /* Loop to write the new data from data_start to data_end */
3003 for (addr = data_start; addr < data_end; addr += 4, i++) {
3004 if ((addr == page_end - 4) ||
3005 ((bp->flash_info->buffered) &&
3006 (addr == data_end - 4))) {
3007
3008 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3009 }
3010 rc = bnx2_nvram_write_dword(bp, addr, buf,
3011 cmd_flags);
3012
3013 if (rc != 0)
3014 goto nvram_write_end;
3015
3016 cmd_flags = 0;
3017 buf += 4;
3018 }
3019
3020 /* Loop to write back the buffer data from data_end
3021 * to page_end */
3022 if (bp->flash_info->buffered == 0) {
3023 for (addr = data_end; addr < page_end;
3024 addr += 4, i += 4) {
3025
3026 if (addr == page_end-4) {
3027 cmd_flags = BNX2_NVM_COMMAND_LAST;
3028 }
3029 rc = bnx2_nvram_write_dword(bp, addr,
3030 &flash_buffer[i], cmd_flags);
3031
3032 if (rc != 0)
3033 goto nvram_write_end;
3034
3035 cmd_flags = 0;
3036 }
3037 }
3038
3039 /* Disable writes to flash interface (lock write-protect) */
3040 bnx2_disable_nvram_write(bp);
3041
3042 /* Disable access to flash interface */
3043 bnx2_disable_nvram_access(bp);
3044 bnx2_release_nvram_lock(bp);
3045
3046 /* Increment written */
3047 written += data_end - data_start;
3048 }
3049
3050 nvram_write_end:
3051 if (align_start || align_end)
3052 kfree(buf);
3053 return rc;
3054 }
3055
3056 static int
3057 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3058 {
3059 u32 val;
3060 int i, rc = 0;
3061
3062 /* Wait for the current PCI transaction to complete before
3063 * issuing a reset. */
3064 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3065 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3066 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3067 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3068 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3069 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3070 udelay(5);
3071
3072 /* Wait for the firmware to tell us it is ok to issue a reset. */
3073 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3074
3075 /* Deposit a driver reset signature so the firmware knows that
3076 * this is a soft reset. */
3077 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3078 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3079
3080 /* Do a dummy read to force the chip to complete all current transaction
3081 * before we issue a reset. */
3082 val = REG_RD(bp, BNX2_MISC_ID);
3083
3084 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3085 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3086 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3087
3088 /* Chip reset. */
3089 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3090
3091 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3092 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3093 msleep(15);
3094
3095 /* Reset takes approximate 30 usec */
3096 for (i = 0; i < 10; i++) {
3097 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3098 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3099 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3100 break;
3101 }
3102 udelay(10);
3103 }
3104
3105 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3106 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3107 printk(KERN_ERR PFX "Chip reset did not complete\n");
3108 return -EBUSY;
3109 }
3110
3111 /* Make sure byte swapping is properly configured. */
3112 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3113 if (val != 0x01020304) {
3114 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3115 return -ENODEV;
3116 }
3117
3118 /* Wait for the firmware to finish its initialization. */
3119 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3120 if (rc)
3121 return rc;
3122
3123 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3124 /* Adjust the voltage regular to two steps lower. The default
3125 * of this register is 0x0000000e. */
3126 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3127
3128 /* Remove bad rbuf memory from the free pool. */
3129 rc = bnx2_alloc_bad_rbuf(bp);
3130 }
3131
3132 return rc;
3133 }
3134
3135 static int
3136 bnx2_init_chip(struct bnx2 *bp)
3137 {
3138 u32 val;
3139 int rc;
3140
3141 /* Make sure the interrupt is not active. */
3142 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3143
3144 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3145 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3146 #ifdef __BIG_ENDIAN
3147 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3148 #endif
3149 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3150 DMA_READ_CHANS << 12 |
3151 DMA_WRITE_CHANS << 16;
3152
3153 val |= (0x2 << 20) | (1 << 11);
3154
3155 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3156 val |= (1 << 23);
3157
3158 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3159 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3160 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3161
3162 REG_WR(bp, BNX2_DMA_CONFIG, val);
3163
3164 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3165 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3166 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3167 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3168 }
3169
3170 if (bp->flags & PCIX_FLAG) {
3171 u16 val16;
3172
3173 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3174 &val16);
3175 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3176 val16 & ~PCI_X_CMD_ERO);
3177 }
3178
3179 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3180 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3181 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3182 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3183
3184 /* Initialize context mapping and zero out the quick contexts. The
3185 * context block must have already been enabled. */
3186 bnx2_init_context(bp);
3187
3188 bnx2_init_cpus(bp);
3189 bnx2_init_nvram(bp);
3190
3191 bnx2_set_mac_addr(bp);
3192
3193 val = REG_RD(bp, BNX2_MQ_CONFIG);
3194 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3195 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3196 REG_WR(bp, BNX2_MQ_CONFIG, val);
3197
3198 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3199 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3200 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3201
3202 val = (BCM_PAGE_BITS - 8) << 24;
3203 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3204
3205 /* Configure page size. */
3206 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3207 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3208 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3209 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3210
3211 val = bp->mac_addr[0] +
3212 (bp->mac_addr[1] << 8) +
3213 (bp->mac_addr[2] << 16) +
3214 bp->mac_addr[3] +
3215 (bp->mac_addr[4] << 8) +
3216 (bp->mac_addr[5] << 16);
3217 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3218
3219 /* Program the MTU. Also include 4 bytes for CRC32. */
3220 val = bp->dev->mtu + ETH_HLEN + 4;
3221 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3222 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3223 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3224
3225 bp->last_status_idx = 0;
3226 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3227
3228 /* Set up how to generate a link change interrupt. */
3229 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3230
3231 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3232 (u64) bp->status_blk_mapping & 0xffffffff);
3233 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3234
3235 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3236 (u64) bp->stats_blk_mapping & 0xffffffff);
3237 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3238 (u64) bp->stats_blk_mapping >> 32);
3239
3240 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3241 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3242
3243 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3244 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3245
3246 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3247 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3248
3249 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3250
3251 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3252
3253 REG_WR(bp, BNX2_HC_COM_TICKS,
3254 (bp->com_ticks_int << 16) | bp->com_ticks);
3255
3256 REG_WR(bp, BNX2_HC_CMD_TICKS,
3257 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3258
3259 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3260 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3261
3262 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3263 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3264 else {
3265 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3266 BNX2_HC_CONFIG_TX_TMR_MODE |
3267 BNX2_HC_CONFIG_COLLECT_STATS);
3268 }
3269
3270 /* Clear internal stats counters. */
3271 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3272
3273 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3274
3275 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3276 BNX2_PORT_FEATURE_ASF_ENABLED)
3277 bp->flags |= ASF_ENABLE_FLAG;
3278
3279 /* Initialize the receive filter. */
3280 bnx2_set_rx_mode(bp->dev);
3281
3282 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3283 0);
3284
3285 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3286 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3287
3288 udelay(20);
3289
3290 return rc;
3291 }
3292
3293
3294 static void
3295 bnx2_init_tx_ring(struct bnx2 *bp)
3296 {
3297 struct tx_bd *txbd;
3298 u32 val;
3299
3300 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3301
3302 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3303 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3304
3305 bp->tx_prod = 0;
3306 bp->tx_cons = 0;
3307 bp->hw_tx_cons = 0;
3308 bp->tx_prod_bseq = 0;
3309
3310 val = BNX2_L2CTX_TYPE_TYPE_L2;
3311 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3312 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3313
3314 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3315 val |= 8 << 16;
3316 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3317
3318 val = (u64) bp->tx_desc_mapping >> 32;
3319 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3320
3321 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3322 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3323 }
3324
3325 static void
3326 bnx2_init_rx_ring(struct bnx2 *bp)
3327 {
3328 struct rx_bd *rxbd;
3329 int i;
3330 u16 prod, ring_prod;
3331 u32 val;
3332
3333 /* 8 for CRC and VLAN */
3334 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3335 /* 8 for alignment */
3336 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3337
3338 ring_prod = prod = bp->rx_prod = 0;
3339 bp->rx_cons = 0;
3340 bp->hw_rx_cons = 0;
3341 bp->rx_prod_bseq = 0;
3342
3343 rxbd = &bp->rx_desc_ring[0];
3344 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3345 rxbd->rx_bd_len = bp->rx_buf_use_size;
3346 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3347 }
3348
3349 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3350 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3351
3352 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3353 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3354 val |= 0x02 << 8;
3355 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3356
3357 val = (u64) bp->rx_desc_mapping >> 32;
3358 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3359
3360 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3361 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3362
3363 for ( ;ring_prod < bp->rx_ring_size; ) {
3364 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3365 break;
3366 }
3367 prod = NEXT_RX_BD(prod);
3368 ring_prod = RX_RING_IDX(prod);
3369 }
3370 bp->rx_prod = prod;
3371
3372 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3373
3374 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3375 }
3376
3377 static void
3378 bnx2_free_tx_skbs(struct bnx2 *bp)
3379 {
3380 int i;
3381
3382 if (bp->tx_buf_ring == NULL)
3383 return;
3384
3385 for (i = 0; i < TX_DESC_CNT; ) {
3386 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3387 struct sk_buff *skb = tx_buf->skb;
3388 int j, last;
3389
3390 if (skb == NULL) {
3391 i++;
3392 continue;
3393 }
3394
3395 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3396 skb_headlen(skb), PCI_DMA_TODEVICE);
3397
3398 tx_buf->skb = NULL;
3399
3400 last = skb_shinfo(skb)->nr_frags;
3401 for (j = 0; j < last; j++) {
3402 tx_buf = &bp->tx_buf_ring[i + j + 1];
3403 pci_unmap_page(bp->pdev,
3404 pci_unmap_addr(tx_buf, mapping),
3405 skb_shinfo(skb)->frags[j].size,
3406 PCI_DMA_TODEVICE);
3407 }
3408 dev_kfree_skb_any(skb);
3409 i += j + 1;
3410 }
3411
3412 }
3413
3414 static void
3415 bnx2_free_rx_skbs(struct bnx2 *bp)
3416 {
3417 int i;
3418
3419 if (bp->rx_buf_ring == NULL)
3420 return;
3421
3422 for (i = 0; i < RX_DESC_CNT; i++) {
3423 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3424 struct sk_buff *skb = rx_buf->skb;
3425
3426 if (skb == NULL)
3427 continue;
3428
3429 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3430 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3431
3432 rx_buf->skb = NULL;
3433
3434 dev_kfree_skb_any(skb);
3435 }
3436 }
3437
3438 static void
3439 bnx2_free_skbs(struct bnx2 *bp)
3440 {
3441 bnx2_free_tx_skbs(bp);
3442 bnx2_free_rx_skbs(bp);
3443 }
3444
3445 static int
3446 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3447 {
3448 int rc;
3449
3450 rc = bnx2_reset_chip(bp, reset_code);
3451 bnx2_free_skbs(bp);
3452 if (rc)
3453 return rc;
3454
3455 bnx2_init_chip(bp);
3456 bnx2_init_tx_ring(bp);
3457 bnx2_init_rx_ring(bp);
3458 return 0;
3459 }
3460
3461 static int
3462 bnx2_init_nic(struct bnx2 *bp)
3463 {
3464 int rc;
3465
3466 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3467 return rc;
3468
3469 bnx2_init_phy(bp);
3470 bnx2_set_link(bp);
3471 return 0;
3472 }
3473
3474 static int
3475 bnx2_test_registers(struct bnx2 *bp)
3476 {
3477 int ret;
3478 int i;
3479 static struct {
3480 u16 offset;
3481 u16 flags;
3482 u32 rw_mask;
3483 u32 ro_mask;
3484 } reg_tbl[] = {
3485 { 0x006c, 0, 0x00000000, 0x0000003f },
3486 { 0x0090, 0, 0xffffffff, 0x00000000 },
3487 { 0x0094, 0, 0x00000000, 0x00000000 },
3488
3489 { 0x0404, 0, 0x00003f00, 0x00000000 },
3490 { 0x0418, 0, 0x00000000, 0xffffffff },
3491 { 0x041c, 0, 0x00000000, 0xffffffff },
3492 { 0x0420, 0, 0x00000000, 0x80ffffff },
3493 { 0x0424, 0, 0x00000000, 0x00000000 },
3494 { 0x0428, 0, 0x00000000, 0x00000001 },
3495 { 0x0450, 0, 0x00000000, 0x0000ffff },
3496 { 0x0454, 0, 0x00000000, 0xffffffff },
3497 { 0x0458, 0, 0x00000000, 0xffffffff },
3498
3499 { 0x0808, 0, 0x00000000, 0xffffffff },
3500 { 0x0854, 0, 0x00000000, 0xffffffff },
3501 { 0x0868, 0, 0x00000000, 0x77777777 },
3502 { 0x086c, 0, 0x00000000, 0x77777777 },
3503 { 0x0870, 0, 0x00000000, 0x77777777 },
3504 { 0x0874, 0, 0x00000000, 0x77777777 },
3505
3506 { 0x0c00, 0, 0x00000000, 0x00000001 },
3507 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3508 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3509 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3510 { 0x0c30, 0, 0x00000000, 0xffffffff },
3511 { 0x0c34, 0, 0x00000000, 0xffffffff },
3512 { 0x0c38, 0, 0x00000000, 0xffffffff },
3513 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3514 { 0x0c40, 0, 0x00000000, 0xffffffff },
3515 { 0x0c44, 0, 0x00000000, 0xffffffff },
3516 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3517 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3518 { 0x0c50, 0, 0x00000000, 0xffffffff },
3519 { 0x0c54, 0, 0x00000000, 0xffffffff },
3520 { 0x0c58, 0, 0x00000000, 0xffffffff },
3521 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3522 { 0x0c60, 0, 0x00000000, 0xffffffff },
3523 { 0x0c64, 0, 0x00000000, 0xffffffff },
3524 { 0x0c68, 0, 0x00000000, 0xffffffff },
3525 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3526 { 0x0c70, 0, 0x00000000, 0xffffffff },
3527 { 0x0c74, 0, 0x00000000, 0xffffffff },
3528 { 0x0c78, 0, 0x00000000, 0xffffffff },
3529 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3530 { 0x0c80, 0, 0x00000000, 0xffffffff },
3531 { 0x0c84, 0, 0x00000000, 0xffffffff },
3532 { 0x0c88, 0, 0x00000000, 0xffffffff },
3533 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3534 { 0x0c90, 0, 0x00000000, 0xffffffff },
3535 { 0x0c94, 0, 0x00000000, 0xffffffff },
3536 { 0x0c98, 0, 0x00000000, 0xffffffff },
3537 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3538 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3539 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3540 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3541 { 0x0cac, 0, 0x00000000, 0xffffffff },
3542 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3543 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3544 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3545 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3546 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3547 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3548 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3549 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3550 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3551 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3552 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3553 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3554 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3555 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3556 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3557 { 0x0cec, 0, 0x00000000, 0xffffffff },
3558 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3559 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3560 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3561 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3562 { 0x0d00, 0, 0x00000000, 0xffffffff },
3563 { 0x0d04, 0, 0x00000000, 0xffffffff },
3564
3565 { 0x1000, 0, 0x00000000, 0x00000001 },
3566 { 0x1004, 0, 0x00000000, 0x000f0001 },
3567 { 0x1044, 0, 0x00000000, 0xffc003ff },
3568 { 0x1080, 0, 0x00000000, 0x0001ffff },
3569 { 0x1084, 0, 0x00000000, 0xffffffff },
3570 { 0x1088, 0, 0x00000000, 0xffffffff },
3571 { 0x108c, 0, 0x00000000, 0xffffffff },
3572 { 0x1090, 0, 0x00000000, 0xffffffff },
3573 { 0x1094, 0, 0x00000000, 0xffffffff },
3574 { 0x1098, 0, 0x00000000, 0xffffffff },
3575 { 0x109c, 0, 0x00000000, 0xffffffff },
3576 { 0x10a0, 0, 0x00000000, 0xffffffff },
3577
3578 { 0x1408, 0, 0x01c00800, 0x00000000 },
3579 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3580 { 0x14a8, 0, 0x00000000, 0x000001ff },
3581 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3582 { 0x14b0, 0, 0x00000002, 0x00000001 },
3583 { 0x14b8, 0, 0x00000000, 0x00000000 },
3584 { 0x14c0, 0, 0x00000000, 0x00000009 },
3585 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3586 { 0x14cc, 0, 0x00000000, 0x00000001 },
3587 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3588 { 0x1500, 0, 0x00000000, 0xffffffff },
3589 { 0x1504, 0, 0x00000000, 0xffffffff },
3590 { 0x1508, 0, 0x00000000, 0xffffffff },
3591 { 0x150c, 0, 0x00000000, 0xffffffff },
3592 { 0x1510, 0, 0x00000000, 0xffffffff },
3593 { 0x1514, 0, 0x00000000, 0xffffffff },
3594 { 0x1518, 0, 0x00000000, 0xffffffff },
3595 { 0x151c, 0, 0x00000000, 0xffffffff },
3596 { 0x1520, 0, 0x00000000, 0xffffffff },
3597 { 0x1524, 0, 0x00000000, 0xffffffff },
3598 { 0x1528, 0, 0x00000000, 0xffffffff },
3599 { 0x152c, 0, 0x00000000, 0xffffffff },
3600 { 0x1530, 0, 0x00000000, 0xffffffff },
3601 { 0x1534, 0, 0x00000000, 0xffffffff },
3602 { 0x1538, 0, 0x00000000, 0xffffffff },
3603 { 0x153c, 0, 0x00000000, 0xffffffff },
3604 { 0x1540, 0, 0x00000000, 0xffffffff },
3605 { 0x1544, 0, 0x00000000, 0xffffffff },
3606 { 0x1548, 0, 0x00000000, 0xffffffff },
3607 { 0x154c, 0, 0x00000000, 0xffffffff },
3608 { 0x1550, 0, 0x00000000, 0xffffffff },
3609 { 0x1554, 0, 0x00000000, 0xffffffff },
3610 { 0x1558, 0, 0x00000000, 0xffffffff },
3611 { 0x1600, 0, 0x00000000, 0xffffffff },
3612 { 0x1604, 0, 0x00000000, 0xffffffff },
3613 { 0x1608, 0, 0x00000000, 0xffffffff },
3614 { 0x160c, 0, 0x00000000, 0xffffffff },
3615 { 0x1610, 0, 0x00000000, 0xffffffff },
3616 { 0x1614, 0, 0x00000000, 0xffffffff },
3617 { 0x1618, 0, 0x00000000, 0xffffffff },
3618 { 0x161c, 0, 0x00000000, 0xffffffff },
3619 { 0x1620, 0, 0x00000000, 0xffffffff },
3620 { 0x1624, 0, 0x00000000, 0xffffffff },
3621 { 0x1628, 0, 0x00000000, 0xffffffff },
3622 { 0x162c, 0, 0x00000000, 0xffffffff },
3623 { 0x1630, 0, 0x00000000, 0xffffffff },
3624 { 0x1634, 0, 0x00000000, 0xffffffff },
3625 { 0x1638, 0, 0x00000000, 0xffffffff },
3626 { 0x163c, 0, 0x00000000, 0xffffffff },
3627 { 0x1640, 0, 0x00000000, 0xffffffff },
3628 { 0x1644, 0, 0x00000000, 0xffffffff },
3629 { 0x1648, 0, 0x00000000, 0xffffffff },
3630 { 0x164c, 0, 0x00000000, 0xffffffff },
3631 { 0x1650, 0, 0x00000000, 0xffffffff },
3632 { 0x1654, 0, 0x00000000, 0xffffffff },
3633
3634 { 0x1800, 0, 0x00000000, 0x00000001 },
3635 { 0x1804, 0, 0x00000000, 0x00000003 },
3636 { 0x1840, 0, 0x00000000, 0xffffffff },
3637 { 0x1844, 0, 0x00000000, 0xffffffff },
3638 { 0x1848, 0, 0x00000000, 0xffffffff },
3639 { 0x184c, 0, 0x00000000, 0xffffffff },
3640 { 0x1850, 0, 0x00000000, 0xffffffff },
3641 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3642 { 0x1904, 0, 0xffffffff, 0x00000000 },
3643 { 0x190c, 0, 0xffffffff, 0x00000000 },
3644 { 0x1914, 0, 0xffffffff, 0x00000000 },
3645 { 0x191c, 0, 0xffffffff, 0x00000000 },
3646 { 0x1924, 0, 0xffffffff, 0x00000000 },
3647 { 0x192c, 0, 0xffffffff, 0x00000000 },
3648 { 0x1934, 0, 0xffffffff, 0x00000000 },
3649 { 0x193c, 0, 0xffffffff, 0x00000000 },
3650 { 0x1944, 0, 0xffffffff, 0x00000000 },
3651 { 0x194c, 0, 0xffffffff, 0x00000000 },
3652 { 0x1954, 0, 0xffffffff, 0x00000000 },
3653 { 0x195c, 0, 0xffffffff, 0x00000000 },
3654 { 0x1964, 0, 0xffffffff, 0x00000000 },
3655 { 0x196c, 0, 0xffffffff, 0x00000000 },
3656 { 0x1974, 0, 0xffffffff, 0x00000000 },
3657 { 0x197c, 0, 0xffffffff, 0x00000000 },
3658 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3659
3660 { 0x1c00, 0, 0x00000000, 0x00000001 },
3661 { 0x1c04, 0, 0x00000000, 0x00000003 },
3662 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3663 { 0x1c40, 0, 0x00000000, 0xffffffff },
3664 { 0x1c44, 0, 0x00000000, 0xffffffff },
3665 { 0x1c48, 0, 0x00000000, 0xffffffff },
3666 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3667 { 0x1c50, 0, 0x00000000, 0xffffffff },
3668 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3669 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3670 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3671 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3672 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3673 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3674 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3675 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3676 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3677 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3678 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3679 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3680 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3681 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3682 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3683 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3684 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3685 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3686
3687 { 0x2004, 0, 0x00000000, 0x0337000f },
3688 { 0x2008, 0, 0xffffffff, 0x00000000 },
3689 { 0x200c, 0, 0xffffffff, 0x00000000 },
3690 { 0x2010, 0, 0xffffffff, 0x00000000 },
3691 { 0x2014, 0, 0x801fff80, 0x00000000 },
3692 { 0x2018, 0, 0x000003ff, 0x00000000 },
3693
3694 { 0x2800, 0, 0x00000000, 0x00000001 },
3695 { 0x2804, 0, 0x00000000, 0x00003f01 },
3696 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3697 { 0x2810, 0, 0xffff0000, 0x00000000 },
3698 { 0x2814, 0, 0xffff0000, 0x00000000 },
3699 { 0x2818, 0, 0xffff0000, 0x00000000 },
3700 { 0x281c, 0, 0xffff0000, 0x00000000 },
3701 { 0x2834, 0, 0xffffffff, 0x00000000 },
3702 { 0x2840, 0, 0x00000000, 0xffffffff },
3703 { 0x2844, 0, 0x00000000, 0xffffffff },
3704 { 0x2848, 0, 0xffffffff, 0x00000000 },
3705 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3706
3707 { 0x2c00, 0, 0x00000000, 0x00000011 },
3708 { 0x2c04, 0, 0x00000000, 0x00030007 },
3709
3710 { 0x3000, 0, 0x00000000, 0x00000001 },
3711 { 0x3004, 0, 0x00000000, 0x007007ff },
3712 { 0x3008, 0, 0x00000003, 0x00000000 },
3713 { 0x300c, 0, 0xffffffff, 0x00000000 },
3714 { 0x3010, 0, 0xffffffff, 0x00000000 },
3715 { 0x3014, 0, 0xffffffff, 0x00000000 },
3716 { 0x3034, 0, 0xffffffff, 0x00000000 },
3717 { 0x3038, 0, 0xffffffff, 0x00000000 },
3718 { 0x3050, 0, 0x00000001, 0x00000000 },
3719
3720 { 0x3c00, 0, 0x00000000, 0x00000001 },
3721 { 0x3c04, 0, 0x00000000, 0x00070000 },
3722 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3723 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3724 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3725 { 0x3c14, 0, 0x00000000, 0xffffffff },
3726 { 0x3c18, 0, 0x00000000, 0xffffffff },
3727 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3728 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3729 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3730 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3731 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3732 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3733 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3734 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3735 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3736 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3737 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3738 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3739 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3740 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3741 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3742 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3743 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3744 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3745 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3746 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3747 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3748 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3749 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3750 { 0x3c78, 0, 0x00000000, 0x00000000 },
3751 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3752 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3753 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3754 { 0x3c88, 0, 0x00000000, 0xffffffff },
3755 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3756
3757 { 0x4000, 0, 0x00000000, 0x00000001 },
3758 { 0x4004, 0, 0x00000000, 0x00030000 },
3759 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3760 { 0x400c, 0, 0xffffffff, 0x00000000 },
3761 { 0x4088, 0, 0x00000000, 0x00070303 },
3762
3763 { 0x4400, 0, 0x00000000, 0x00000001 },
3764 { 0x4404, 0, 0x00000000, 0x00003f01 },
3765 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3766 { 0x440c, 0, 0xffffffff, 0x00000000 },
3767 { 0x4410, 0, 0xffff, 0x0000 },
3768 { 0x4414, 0, 0xffff, 0x0000 },
3769 { 0x4418, 0, 0xffff, 0x0000 },
3770 { 0x441c, 0, 0xffff, 0x0000 },
3771 { 0x4428, 0, 0xffffffff, 0x00000000 },
3772 { 0x442c, 0, 0xffffffff, 0x00000000 },
3773 { 0x4430, 0, 0xffffffff, 0x00000000 },
3774 { 0x4434, 0, 0xffffffff, 0x00000000 },
3775 { 0x4438, 0, 0xffffffff, 0x00000000 },
3776 { 0x443c, 0, 0xffffffff, 0x00000000 },
3777 { 0x4440, 0, 0xffffffff, 0x00000000 },
3778 { 0x4444, 0, 0xffffffff, 0x00000000 },
3779
3780 { 0x4c00, 0, 0x00000000, 0x00000001 },
3781 { 0x4c04, 0, 0x00000000, 0x0000003f },
3782 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3783 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3784 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3785 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3786 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3787 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3788 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3789 { 0x4c50, 0, 0x00000000, 0xffffffff },
3790
3791 { 0x5004, 0, 0x00000000, 0x0000007f },
3792 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3793 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3794
3795 { 0x5400, 0, 0x00000008, 0x00000001 },
3796 { 0x5404, 0, 0x00000000, 0x0000003f },
3797 { 0x5408, 0, 0x0000001f, 0x00000000 },
3798 { 0x540c, 0, 0xffffffff, 0x00000000 },
3799 { 0x5410, 0, 0xffffffff, 0x00000000 },
3800 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3801 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3802 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3803 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3804 { 0x5428, 0, 0x000000ff, 0x00000000 },
3805 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3806 { 0x5430, 0, 0x001fff80, 0x00000000 },
3807 { 0x5438, 0, 0xffffffff, 0x00000000 },
3808 { 0x543c, 0, 0xffffffff, 0x00000000 },
3809 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3810
3811 { 0x5c00, 0, 0x00000000, 0x00000001 },
3812 { 0x5c04, 0, 0x00000000, 0x0003000f },
3813 { 0x5c08, 0, 0x00000003, 0x00000000 },
3814 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3815 { 0x5c10, 0, 0x00000000, 0xffffffff },
3816 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3817 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3818 { 0x5c88, 0, 0x00000000, 0x00077373 },
3819 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3820
3821 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3822 { 0x680c, 0, 0xffffffff, 0x00000000 },
3823 { 0x6810, 0, 0xffffffff, 0x00000000 },
3824 { 0x6814, 0, 0xffffffff, 0x00000000 },
3825 { 0x6818, 0, 0xffffffff, 0x00000000 },
3826 { 0x681c, 0, 0xffffffff, 0x00000000 },
3827 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3828 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3829 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3830 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3831 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3832 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3833 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3834 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3835 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3836 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3837 { 0x684c, 0, 0xffffffff, 0x00000000 },
3838 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3839 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3840 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3841 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3842 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3843 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3844
3845 { 0xffff, 0, 0x00000000, 0x00000000 },
3846 };
3847
3848 ret = 0;
3849 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3850 u32 offset, rw_mask, ro_mask, save_val, val;
3851
3852 offset = (u32) reg_tbl[i].offset;
3853 rw_mask = reg_tbl[i].rw_mask;
3854 ro_mask = reg_tbl[i].ro_mask;
3855
3856 save_val = readl(bp->regview + offset);
3857
3858 writel(0, bp->regview + offset);
3859
3860 val = readl(bp->regview + offset);
3861 if ((val & rw_mask) != 0) {
3862 goto reg_test_err;
3863 }
3864
3865 if ((val & ro_mask) != (save_val & ro_mask)) {
3866 goto reg_test_err;
3867 }
3868
3869 writel(0xffffffff, bp->regview + offset);
3870
3871 val = readl(bp->regview + offset);
3872 if ((val & rw_mask) != rw_mask) {
3873 goto reg_test_err;
3874 }
3875
3876 if ((val & ro_mask) != (save_val & ro_mask)) {
3877 goto reg_test_err;
3878 }
3879
3880 writel(save_val, bp->regview + offset);
3881 continue;
3882
3883 reg_test_err:
3884 writel(save_val, bp->regview + offset);
3885 ret = -ENODEV;
3886 break;
3887 }
3888 return ret;
3889 }
3890
3891 static int
3892 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3893 {
3894 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3895 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3896 int i;
3897
3898 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3899 u32 offset;
3900
3901 for (offset = 0; offset < size; offset += 4) {
3902
3903 REG_WR_IND(bp, start + offset, test_pattern[i]);
3904
3905 if (REG_RD_IND(bp, start + offset) !=
3906 test_pattern[i]) {
3907 return -ENODEV;
3908 }
3909 }
3910 }
3911 return 0;
3912 }
3913
3914 static int
3915 bnx2_test_memory(struct bnx2 *bp)
3916 {
3917 int ret = 0;
3918 int i;
3919 static struct {
3920 u32 offset;
3921 u32 len;
3922 } mem_tbl[] = {
3923 { 0x60000, 0x4000 },
3924 { 0xa0000, 0x3000 },
3925 { 0xe0000, 0x4000 },
3926 { 0x120000, 0x4000 },
3927 { 0x1a0000, 0x4000 },
3928 { 0x160000, 0x4000 },
3929 { 0xffffffff, 0 },
3930 };
3931
3932 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3933 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3934 mem_tbl[i].len)) != 0) {
3935 return ret;
3936 }
3937 }
3938
3939 return ret;
3940 }
3941
3942 #define BNX2_MAC_LOOPBACK 0
3943 #define BNX2_PHY_LOOPBACK 1
3944
3945 static int
3946 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3947 {
3948 unsigned int pkt_size, num_pkts, i;
3949 struct sk_buff *skb, *rx_skb;
3950 unsigned char *packet;
3951 u16 rx_start_idx, rx_idx;
3952 u32 val;
3953 dma_addr_t map;
3954 struct tx_bd *txbd;
3955 struct sw_bd *rx_buf;
3956 struct l2_fhdr *rx_hdr;
3957 int ret = -ENODEV;
3958
3959 if (loopback_mode == BNX2_MAC_LOOPBACK) {
3960 bp->loopback = MAC_LOOPBACK;
3961 bnx2_set_mac_loopback(bp);
3962 }
3963 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
3964 bp->loopback = 0;
3965 bnx2_set_phy_loopback(bp);
3966 }
3967 else
3968 return -EINVAL;
3969
3970 pkt_size = 1514;
3971 skb = dev_alloc_skb(pkt_size);
3972 if (!skb)
3973 return -ENOMEM;
3974 packet = skb_put(skb, pkt_size);
3975 memcpy(packet, bp->mac_addr, 6);
3976 memset(packet + 6, 0x0, 8);
3977 for (i = 14; i < pkt_size; i++)
3978 packet[i] = (unsigned char) (i & 0xff);
3979
3980 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3981 PCI_DMA_TODEVICE);
3982
3983 val = REG_RD(bp, BNX2_HC_COMMAND);
3984 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3985 REG_RD(bp, BNX2_HC_COMMAND);
3986
3987 udelay(5);
3988 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3989
3990 num_pkts = 0;
3991
3992 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
3993
3994 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3995 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3996 txbd->tx_bd_mss_nbytes = pkt_size;
3997 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3998
3999 num_pkts++;
4000 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4001 bp->tx_prod_bseq += pkt_size;
4002
4003 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
4004 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4005
4006 udelay(100);
4007
4008 val = REG_RD(bp, BNX2_HC_COMMAND);
4009 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4010 REG_RD(bp, BNX2_HC_COMMAND);
4011
4012 udelay(5);
4013
4014 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4015 dev_kfree_skb_irq(skb);
4016
4017 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4018 goto loopback_test_done;
4019 }
4020
4021 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4022 if (rx_idx != rx_start_idx + num_pkts) {
4023 goto loopback_test_done;
4024 }
4025
4026 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4027 rx_skb = rx_buf->skb;
4028
4029 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4030 skb_reserve(rx_skb, bp->rx_offset);
4031
4032 pci_dma_sync_single_for_cpu(bp->pdev,
4033 pci_unmap_addr(rx_buf, mapping),
4034 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4035
4036 if (rx_hdr->l2_fhdr_status &
4037 (L2_FHDR_ERRORS_BAD_CRC |
4038 L2_FHDR_ERRORS_PHY_DECODE |
4039 L2_FHDR_ERRORS_ALIGNMENT |
4040 L2_FHDR_ERRORS_TOO_SHORT |
4041 L2_FHDR_ERRORS_GIANT_FRAME)) {
4042
4043 goto loopback_test_done;
4044 }
4045
4046 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4047 goto loopback_test_done;
4048 }
4049
4050 for (i = 14; i < pkt_size; i++) {
4051 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4052 goto loopback_test_done;
4053 }
4054 }
4055
4056 ret = 0;
4057
4058 loopback_test_done:
4059 bp->loopback = 0;
4060 return ret;
4061 }
4062
4063 #define BNX2_MAC_LOOPBACK_FAILED 1
4064 #define BNX2_PHY_LOOPBACK_FAILED 2
4065 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4066 BNX2_PHY_LOOPBACK_FAILED)
4067
4068 static int
4069 bnx2_test_loopback(struct bnx2 *bp)
4070 {
4071 int rc = 0;
4072
4073 if (!netif_running(bp->dev))
4074 return BNX2_LOOPBACK_FAILED;
4075
4076 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4077 spin_lock_bh(&bp->phy_lock);
4078 bnx2_init_phy(bp);
4079 spin_unlock_bh(&bp->phy_lock);
4080 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4081 rc |= BNX2_MAC_LOOPBACK_FAILED;
4082 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4083 rc |= BNX2_PHY_LOOPBACK_FAILED;
4084 return rc;
4085 }
4086
4087 #define NVRAM_SIZE 0x200
4088 #define CRC32_RESIDUAL 0xdebb20e3
4089
4090 static int
4091 bnx2_test_nvram(struct bnx2 *bp)
4092 {
4093 u32 buf[NVRAM_SIZE / 4];
4094 u8 *data = (u8 *) buf;
4095 int rc = 0;
4096 u32 magic, csum;
4097
4098 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4099 goto test_nvram_done;
4100
4101 magic = be32_to_cpu(buf[0]);
4102 if (magic != 0x669955aa) {
4103 rc = -ENODEV;
4104 goto test_nvram_done;
4105 }
4106
4107 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4108 goto test_nvram_done;
4109
4110 csum = ether_crc_le(0x100, data);
4111 if (csum != CRC32_RESIDUAL) {
4112 rc = -ENODEV;
4113 goto test_nvram_done;
4114 }
4115
4116 csum = ether_crc_le(0x100, data + 0x100);
4117 if (csum != CRC32_RESIDUAL) {
4118 rc = -ENODEV;
4119 }
4120
4121 test_nvram_done:
4122 return rc;
4123 }
4124
4125 static int
4126 bnx2_test_link(struct bnx2 *bp)
4127 {
4128 u32 bmsr;
4129
4130 spin_lock_bh(&bp->phy_lock);
4131 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4132 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4133 spin_unlock_bh(&bp->phy_lock);
4134
4135 if (bmsr & BMSR_LSTATUS) {
4136 return 0;
4137 }
4138 return -ENODEV;
4139 }
4140
4141 static int
4142 bnx2_test_intr(struct bnx2 *bp)
4143 {
4144 int i;
4145 u32 val;
4146 u16 status_idx;
4147
4148 if (!netif_running(bp->dev))
4149 return -ENODEV;
4150
4151 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4152
4153 /* This register is not touched during run-time. */
4154 val = REG_RD(bp, BNX2_HC_COMMAND);
4155 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
4156 REG_RD(bp, BNX2_HC_COMMAND);
4157
4158 for (i = 0; i < 10; i++) {
4159 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4160 status_idx) {
4161
4162 break;
4163 }
4164
4165 msleep_interruptible(10);
4166 }
4167 if (i < 10)
4168 return 0;
4169
4170 return -ENODEV;
4171 }
4172
4173 static void
4174 bnx2_timer(unsigned long data)
4175 {
4176 struct bnx2 *bp = (struct bnx2 *) data;
4177 u32 msg;
4178
4179 if (!netif_running(bp->dev))
4180 return;
4181
4182 if (atomic_read(&bp->intr_sem) != 0)
4183 goto bnx2_restart_timer;
4184
4185 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4186 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4187
4188 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4189 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4190
4191 spin_lock(&bp->phy_lock);
4192 if (bp->serdes_an_pending) {
4193 bp->serdes_an_pending--;
4194 }
4195 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4196 u32 bmcr;
4197
4198 bp->current_interval = bp->timer_interval;
4199
4200 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4201
4202 if (bmcr & BMCR_ANENABLE) {
4203 u32 phy1, phy2;
4204
4205 bnx2_write_phy(bp, 0x1c, 0x7c00);
4206 bnx2_read_phy(bp, 0x1c, &phy1);
4207
4208 bnx2_write_phy(bp, 0x17, 0x0f01);
4209 bnx2_read_phy(bp, 0x15, &phy2);
4210 bnx2_write_phy(bp, 0x17, 0x0f01);
4211 bnx2_read_phy(bp, 0x15, &phy2);
4212
4213 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4214 !(phy2 & 0x20)) { /* no CONFIG */
4215
4216 bmcr &= ~BMCR_ANENABLE;
4217 bmcr |= BMCR_SPEED1000 |
4218 BMCR_FULLDPLX;
4219 bnx2_write_phy(bp, MII_BMCR, bmcr);
4220 bp->phy_flags |=
4221 PHY_PARALLEL_DETECT_FLAG;
4222 }
4223 }
4224 }
4225 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4226 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4227 u32 phy2;
4228
4229 bnx2_write_phy(bp, 0x17, 0x0f01);
4230 bnx2_read_phy(bp, 0x15, &phy2);
4231 if (phy2 & 0x20) {
4232 u32 bmcr;
4233
4234 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4235 bmcr |= BMCR_ANENABLE;
4236 bnx2_write_phy(bp, MII_BMCR, bmcr);
4237
4238 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4239
4240 }
4241 }
4242 else
4243 bp->current_interval = bp->timer_interval;
4244
4245 spin_unlock(&bp->phy_lock);
4246 }
4247
4248 bnx2_restart_timer:
4249 mod_timer(&bp->timer, jiffies + bp->current_interval);
4250 }
4251
4252 /* Called with rtnl_lock */
4253 static int
4254 bnx2_open(struct net_device *dev)
4255 {
4256 struct bnx2 *bp = netdev_priv(dev);
4257 int rc;
4258
4259 bnx2_set_power_state(bp, PCI_D0);
4260 bnx2_disable_int(bp);
4261
4262 rc = bnx2_alloc_mem(bp);
4263 if (rc)
4264 return rc;
4265
4266 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4267 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4268 !disable_msi) {
4269
4270 if (pci_enable_msi(bp->pdev) == 0) {
4271 bp->flags |= USING_MSI_FLAG;
4272 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4273 dev);
4274 }
4275 else {
4276 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4277 SA_SHIRQ, dev->name, dev);
4278 }
4279 }
4280 else {
4281 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4282 dev->name, dev);
4283 }
4284 if (rc) {
4285 bnx2_free_mem(bp);
4286 return rc;
4287 }
4288
4289 rc = bnx2_init_nic(bp);
4290
4291 if (rc) {
4292 free_irq(bp->pdev->irq, dev);
4293 if (bp->flags & USING_MSI_FLAG) {
4294 pci_disable_msi(bp->pdev);
4295 bp->flags &= ~USING_MSI_FLAG;
4296 }
4297 bnx2_free_skbs(bp);
4298 bnx2_free_mem(bp);
4299 return rc;
4300 }
4301
4302 mod_timer(&bp->timer, jiffies + bp->current_interval);
4303
4304 atomic_set(&bp->intr_sem, 0);
4305
4306 bnx2_enable_int(bp);
4307
4308 if (bp->flags & USING_MSI_FLAG) {
4309 /* Test MSI to make sure it is working
4310 * If MSI test fails, go back to INTx mode
4311 */
4312 if (bnx2_test_intr(bp) != 0) {
4313 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4314 " using MSI, switching to INTx mode. Please"
4315 " report this failure to the PCI maintainer"
4316 " and include system chipset information.\n",
4317 bp->dev->name);
4318
4319 bnx2_disable_int(bp);
4320 free_irq(bp->pdev->irq, dev);
4321 pci_disable_msi(bp->pdev);
4322 bp->flags &= ~USING_MSI_FLAG;
4323
4324 rc = bnx2_init_nic(bp);
4325
4326 if (!rc) {
4327 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4328 SA_SHIRQ, dev->name, dev);
4329 }
4330 if (rc) {
4331 bnx2_free_skbs(bp);
4332 bnx2_free_mem(bp);
4333 del_timer_sync(&bp->timer);
4334 return rc;
4335 }
4336 bnx2_enable_int(bp);
4337 }
4338 }
4339 if (bp->flags & USING_MSI_FLAG) {
4340 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4341 }
4342
4343 netif_start_queue(dev);
4344
4345 return 0;
4346 }
4347
4348 static void
4349 bnx2_reset_task(void *data)
4350 {
4351 struct bnx2 *bp = data;
4352
4353 if (!netif_running(bp->dev))
4354 return;
4355
4356 bp->in_reset_task = 1;
4357 bnx2_netif_stop(bp);
4358
4359 bnx2_init_nic(bp);
4360
4361 atomic_set(&bp->intr_sem, 1);
4362 bnx2_netif_start(bp);
4363 bp->in_reset_task = 0;
4364 }
4365
4366 static void
4367 bnx2_tx_timeout(struct net_device *dev)
4368 {
4369 struct bnx2 *bp = netdev_priv(dev);
4370
4371 /* This allows the netif to be shutdown gracefully before resetting */
4372 schedule_work(&bp->reset_task);
4373 }
4374
4375 #ifdef BCM_VLAN
4376 /* Called with rtnl_lock */
4377 static void
4378 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4379 {
4380 struct bnx2 *bp = netdev_priv(dev);
4381
4382 bnx2_netif_stop(bp);
4383
4384 bp->vlgrp = vlgrp;
4385 bnx2_set_rx_mode(dev);
4386
4387 bnx2_netif_start(bp);
4388 }
4389
4390 /* Called with rtnl_lock */
4391 static void
4392 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4393 {
4394 struct bnx2 *bp = netdev_priv(dev);
4395
4396 bnx2_netif_stop(bp);
4397
4398 if (bp->vlgrp)
4399 bp->vlgrp->vlan_devices[vid] = NULL;
4400 bnx2_set_rx_mode(dev);
4401
4402 bnx2_netif_start(bp);
4403 }
4404 #endif
4405
4406 /* Called with dev->xmit_lock.
4407 * hard_start_xmit is pseudo-lockless - a lock is only required when
4408 * the tx queue is full. This way, we get the benefit of lockless
4409 * operations most of the time without the complexities to handle
4410 * netif_stop_queue/wake_queue race conditions.
4411 */
4412 static int
4413 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4414 {
4415 struct bnx2 *bp = netdev_priv(dev);
4416 dma_addr_t mapping;
4417 struct tx_bd *txbd;
4418 struct sw_bd *tx_buf;
4419 u32 len, vlan_tag_flags, last_frag, mss;
4420 u16 prod, ring_prod;
4421 int i;
4422
4423 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4424 netif_stop_queue(dev);
4425 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4426 dev->name);
4427
4428 return NETDEV_TX_BUSY;
4429 }
4430 len = skb_headlen(skb);
4431 prod = bp->tx_prod;
4432 ring_prod = TX_RING_IDX(prod);
4433
4434 vlan_tag_flags = 0;
4435 if (skb->ip_summed == CHECKSUM_HW) {
4436 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4437 }
4438
4439 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4440 vlan_tag_flags |=
4441 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4442 }
4443 #ifdef BCM_TSO
4444 if ((mss = skb_shinfo(skb)->tso_size) &&
4445 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4446 u32 tcp_opt_len, ip_tcp_len;
4447
4448 if (skb_header_cloned(skb) &&
4449 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4450 dev_kfree_skb(skb);
4451 return NETDEV_TX_OK;
4452 }
4453
4454 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4455 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4456
4457 tcp_opt_len = 0;
4458 if (skb->h.th->doff > 5) {
4459 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4460 }
4461 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4462
4463 skb->nh.iph->check = 0;
4464 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4465 skb->h.th->check =
4466 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4467 skb->nh.iph->daddr,
4468 0, IPPROTO_TCP, 0);
4469
4470 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4471 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4472 (tcp_opt_len >> 2)) << 8;
4473 }
4474 }
4475 else
4476 #endif
4477 {
4478 mss = 0;
4479 }
4480
4481 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4482
4483 tx_buf = &bp->tx_buf_ring[ring_prod];
4484 tx_buf->skb = skb;
4485 pci_unmap_addr_set(tx_buf, mapping, mapping);
4486
4487 txbd = &bp->tx_desc_ring[ring_prod];
4488
4489 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4490 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4491 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4492 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4493
4494 last_frag = skb_shinfo(skb)->nr_frags;
4495
4496 for (i = 0; i < last_frag; i++) {
4497 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4498
4499 prod = NEXT_TX_BD(prod);
4500 ring_prod = TX_RING_IDX(prod);
4501 txbd = &bp->tx_desc_ring[ring_prod];
4502
4503 len = frag->size;
4504 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4505 len, PCI_DMA_TODEVICE);
4506 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4507 mapping, mapping);
4508
4509 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4510 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4511 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4512 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4513
4514 }
4515 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4516
4517 prod = NEXT_TX_BD(prod);
4518 bp->tx_prod_bseq += skb->len;
4519
4520 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4521 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4522
4523 mmiowb();
4524
4525 bp->tx_prod = prod;
4526 dev->trans_start = jiffies;
4527
4528 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4529 spin_lock(&bp->tx_lock);
4530 netif_stop_queue(dev);
4531
4532 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4533 netif_wake_queue(dev);
4534 spin_unlock(&bp->tx_lock);
4535 }
4536
4537 return NETDEV_TX_OK;
4538 }
4539
4540 /* Called with rtnl_lock */
4541 static int
4542 bnx2_close(struct net_device *dev)
4543 {
4544 struct bnx2 *bp = netdev_priv(dev);
4545 u32 reset_code;
4546
4547 /* Calling flush_scheduled_work() may deadlock because
4548 * linkwatch_event() may be on the workqueue and it will try to get
4549 * the rtnl_lock which we are holding.
4550 */
4551 while (bp->in_reset_task)
4552 msleep(1);
4553
4554 bnx2_netif_stop(bp);
4555 del_timer_sync(&bp->timer);
4556 if (bp->flags & NO_WOL_FLAG)
4557 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
4558 else if (bp->wol)
4559 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4560 else
4561 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4562 bnx2_reset_chip(bp, reset_code);
4563 free_irq(bp->pdev->irq, dev);
4564 if (bp->flags & USING_MSI_FLAG) {
4565 pci_disable_msi(bp->pdev);
4566 bp->flags &= ~USING_MSI_FLAG;
4567 }
4568 bnx2_free_skbs(bp);
4569 bnx2_free_mem(bp);
4570 bp->link_up = 0;
4571 netif_carrier_off(bp->dev);
4572 bnx2_set_power_state(bp, PCI_D3hot);
4573 return 0;
4574 }
4575
4576 #define GET_NET_STATS64(ctr) \
4577 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4578 (unsigned long) (ctr##_lo)
4579
4580 #define GET_NET_STATS32(ctr) \
4581 (ctr##_lo)
4582
4583 #if (BITS_PER_LONG == 64)
4584 #define GET_NET_STATS GET_NET_STATS64
4585 #else
4586 #define GET_NET_STATS GET_NET_STATS32
4587 #endif
4588
4589 static struct net_device_stats *
4590 bnx2_get_stats(struct net_device *dev)
4591 {
4592 struct bnx2 *bp = netdev_priv(dev);
4593 struct statistics_block *stats_blk = bp->stats_blk;
4594 struct net_device_stats *net_stats = &bp->net_stats;
4595
4596 if (bp->stats_blk == NULL) {
4597 return net_stats;
4598 }
4599 net_stats->rx_packets =
4600 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4601 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4602 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4603
4604 net_stats->tx_packets =
4605 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4606 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4607 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4608
4609 net_stats->rx_bytes =
4610 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4611
4612 net_stats->tx_bytes =
4613 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4614
4615 net_stats->multicast =
4616 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4617
4618 net_stats->collisions =
4619 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4620
4621 net_stats->rx_length_errors =
4622 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4623 stats_blk->stat_EtherStatsOverrsizePkts);
4624
4625 net_stats->rx_over_errors =
4626 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4627
4628 net_stats->rx_frame_errors =
4629 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4630
4631 net_stats->rx_crc_errors =
4632 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4633
4634 net_stats->rx_errors = net_stats->rx_length_errors +
4635 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4636 net_stats->rx_crc_errors;
4637
4638 net_stats->tx_aborted_errors =
4639 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4640 stats_blk->stat_Dot3StatsLateCollisions);
4641
4642 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4643 (CHIP_ID(bp) == CHIP_ID_5708_A0))
4644 net_stats->tx_carrier_errors = 0;
4645 else {
4646 net_stats->tx_carrier_errors =
4647 (unsigned long)
4648 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4649 }
4650
4651 net_stats->tx_errors =
4652 (unsigned long)
4653 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4654 +
4655 net_stats->tx_aborted_errors +
4656 net_stats->tx_carrier_errors;
4657
4658 return net_stats;
4659 }
4660
4661 /* All ethtool functions called with rtnl_lock */
4662
4663 static int
4664 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4665 {
4666 struct bnx2 *bp = netdev_priv(dev);
4667
4668 cmd->supported = SUPPORTED_Autoneg;
4669 if (bp->phy_flags & PHY_SERDES_FLAG) {
4670 cmd->supported |= SUPPORTED_1000baseT_Full |
4671 SUPPORTED_FIBRE;
4672
4673 cmd->port = PORT_FIBRE;
4674 }
4675 else {
4676 cmd->supported |= SUPPORTED_10baseT_Half |
4677 SUPPORTED_10baseT_Full |
4678 SUPPORTED_100baseT_Half |
4679 SUPPORTED_100baseT_Full |
4680 SUPPORTED_1000baseT_Full |
4681 SUPPORTED_TP;
4682
4683 cmd->port = PORT_TP;
4684 }
4685
4686 cmd->advertising = bp->advertising;
4687
4688 if (bp->autoneg & AUTONEG_SPEED) {
4689 cmd->autoneg = AUTONEG_ENABLE;
4690 }
4691 else {
4692 cmd->autoneg = AUTONEG_DISABLE;
4693 }
4694
4695 if (netif_carrier_ok(dev)) {
4696 cmd->speed = bp->line_speed;
4697 cmd->duplex = bp->duplex;
4698 }
4699 else {
4700 cmd->speed = -1;
4701 cmd->duplex = -1;
4702 }
4703
4704 cmd->transceiver = XCVR_INTERNAL;
4705 cmd->phy_address = bp->phy_addr;
4706
4707 return 0;
4708 }
4709
4710 static int
4711 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4712 {
4713 struct bnx2 *bp = netdev_priv(dev);
4714 u8 autoneg = bp->autoneg;
4715 u8 req_duplex = bp->req_duplex;
4716 u16 req_line_speed = bp->req_line_speed;
4717 u32 advertising = bp->advertising;
4718
4719 if (cmd->autoneg == AUTONEG_ENABLE) {
4720 autoneg |= AUTONEG_SPEED;
4721
4722 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4723
4724 /* allow advertising 1 speed */
4725 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4726 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4727 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4728 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4729
4730 if (bp->phy_flags & PHY_SERDES_FLAG)
4731 return -EINVAL;
4732
4733 advertising = cmd->advertising;
4734
4735 }
4736 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4737 advertising = cmd->advertising;
4738 }
4739 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4740 return -EINVAL;
4741 }
4742 else {
4743 if (bp->phy_flags & PHY_SERDES_FLAG) {
4744 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4745 }
4746 else {
4747 advertising = ETHTOOL_ALL_COPPER_SPEED;
4748 }
4749 }
4750 advertising |= ADVERTISED_Autoneg;
4751 }
4752 else {
4753 if (bp->phy_flags & PHY_SERDES_FLAG) {
4754 if ((cmd->speed != SPEED_1000) ||
4755 (cmd->duplex != DUPLEX_FULL)) {
4756 return -EINVAL;
4757 }
4758 }
4759 else if (cmd->speed == SPEED_1000) {
4760 return -EINVAL;
4761 }
4762 autoneg &= ~AUTONEG_SPEED;
4763 req_line_speed = cmd->speed;
4764 req_duplex = cmd->duplex;
4765 advertising = 0;
4766 }
4767
4768 bp->autoneg = autoneg;
4769 bp->advertising = advertising;
4770 bp->req_line_speed = req_line_speed;
4771 bp->req_duplex = req_duplex;
4772
4773 spin_lock_bh(&bp->phy_lock);
4774
4775 bnx2_setup_phy(bp);
4776
4777 spin_unlock_bh(&bp->phy_lock);
4778
4779 return 0;
4780 }
4781
4782 static void
4783 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4784 {
4785 struct bnx2 *bp = netdev_priv(dev);
4786
4787 strcpy(info->driver, DRV_MODULE_NAME);
4788 strcpy(info->version, DRV_MODULE_VERSION);
4789 strcpy(info->bus_info, pci_name(bp->pdev));
4790 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4791 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4792 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4793 info->fw_version[1] = info->fw_version[3] = '.';
4794 info->fw_version[5] = 0;
4795 }
4796
4797 static void
4798 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4799 {
4800 struct bnx2 *bp = netdev_priv(dev);
4801
4802 if (bp->flags & NO_WOL_FLAG) {
4803 wol->supported = 0;
4804 wol->wolopts = 0;
4805 }
4806 else {
4807 wol->supported = WAKE_MAGIC;
4808 if (bp->wol)
4809 wol->wolopts = WAKE_MAGIC;
4810 else
4811 wol->wolopts = 0;
4812 }
4813 memset(&wol->sopass, 0, sizeof(wol->sopass));
4814 }
4815
4816 static int
4817 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4818 {
4819 struct bnx2 *bp = netdev_priv(dev);
4820
4821 if (wol->wolopts & ~WAKE_MAGIC)
4822 return -EINVAL;
4823
4824 if (wol->wolopts & WAKE_MAGIC) {
4825 if (bp->flags & NO_WOL_FLAG)
4826 return -EINVAL;
4827
4828 bp->wol = 1;
4829 }
4830 else {
4831 bp->wol = 0;
4832 }
4833 return 0;
4834 }
4835
4836 static int
4837 bnx2_nway_reset(struct net_device *dev)
4838 {
4839 struct bnx2 *bp = netdev_priv(dev);
4840 u32 bmcr;
4841
4842 if (!(bp->autoneg & AUTONEG_SPEED)) {
4843 return -EINVAL;
4844 }
4845
4846 spin_lock_bh(&bp->phy_lock);
4847
4848 /* Force a link down visible on the other side */
4849 if (bp->phy_flags & PHY_SERDES_FLAG) {
4850 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4851 spin_unlock_bh(&bp->phy_lock);
4852
4853 msleep(20);
4854
4855 spin_lock_bh(&bp->phy_lock);
4856 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4857 bp->current_interval = SERDES_AN_TIMEOUT;
4858 bp->serdes_an_pending = 1;
4859 mod_timer(&bp->timer, jiffies + bp->current_interval);
4860 }
4861 }
4862
4863 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4864 bmcr &= ~BMCR_LOOPBACK;
4865 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4866
4867 spin_unlock_bh(&bp->phy_lock);
4868
4869 return 0;
4870 }
4871
4872 static int
4873 bnx2_get_eeprom_len(struct net_device *dev)
4874 {
4875 struct bnx2 *bp = netdev_priv(dev);
4876
4877 if (bp->flash_info == NULL)
4878 return 0;
4879
4880 return (int) bp->flash_size;
4881 }
4882
4883 static int
4884 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4885 u8 *eebuf)
4886 {
4887 struct bnx2 *bp = netdev_priv(dev);
4888 int rc;
4889
4890 /* parameters already validated in ethtool_get_eeprom */
4891
4892 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4893
4894 return rc;
4895 }
4896
4897 static int
4898 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4899 u8 *eebuf)
4900 {
4901 struct bnx2 *bp = netdev_priv(dev);
4902 int rc;
4903
4904 /* parameters already validated in ethtool_set_eeprom */
4905
4906 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4907
4908 return rc;
4909 }
4910
4911 static int
4912 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4913 {
4914 struct bnx2 *bp = netdev_priv(dev);
4915
4916 memset(coal, 0, sizeof(struct ethtool_coalesce));
4917
4918 coal->rx_coalesce_usecs = bp->rx_ticks;
4919 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4920 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4921 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4922
4923 coal->tx_coalesce_usecs = bp->tx_ticks;
4924 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4925 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4926 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4927
4928 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4929
4930 return 0;
4931 }
4932
4933 static int
4934 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4935 {
4936 struct bnx2 *bp = netdev_priv(dev);
4937
4938 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4939 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4940
4941 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4942 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4943
4944 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4945 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4946
4947 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4948 if (bp->rx_quick_cons_trip_int > 0xff)
4949 bp->rx_quick_cons_trip_int = 0xff;
4950
4951 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4952 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4953
4954 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4955 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4956
4957 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4958 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4959
4960 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4961 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4962 0xff;
4963
4964 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4965 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4966 bp->stats_ticks &= 0xffff00;
4967
4968 if (netif_running(bp->dev)) {
4969 bnx2_netif_stop(bp);
4970 bnx2_init_nic(bp);
4971 bnx2_netif_start(bp);
4972 }
4973
4974 return 0;
4975 }
4976
4977 static void
4978 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4979 {
4980 struct bnx2 *bp = netdev_priv(dev);
4981
4982 ering->rx_max_pending = MAX_RX_DESC_CNT;
4983 ering->rx_mini_max_pending = 0;
4984 ering->rx_jumbo_max_pending = 0;
4985
4986 ering->rx_pending = bp->rx_ring_size;
4987 ering->rx_mini_pending = 0;
4988 ering->rx_jumbo_pending = 0;
4989
4990 ering->tx_max_pending = MAX_TX_DESC_CNT;
4991 ering->tx_pending = bp->tx_ring_size;
4992 }
4993
4994 static int
4995 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4996 {
4997 struct bnx2 *bp = netdev_priv(dev);
4998
4999 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
5000 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5001 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5002
5003 return -EINVAL;
5004 }
5005 bp->rx_ring_size = ering->rx_pending;
5006 bp->tx_ring_size = ering->tx_pending;
5007
5008 if (netif_running(bp->dev)) {
5009 bnx2_netif_stop(bp);
5010 bnx2_init_nic(bp);
5011 bnx2_netif_start(bp);
5012 }
5013
5014 return 0;
5015 }
5016
5017 static void
5018 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5019 {
5020 struct bnx2 *bp = netdev_priv(dev);
5021
5022 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5023 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5024 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5025 }
5026
5027 static int
5028 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5029 {
5030 struct bnx2 *bp = netdev_priv(dev);
5031
5032 bp->req_flow_ctrl = 0;
5033 if (epause->rx_pause)
5034 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5035 if (epause->tx_pause)
5036 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5037
5038 if (epause->autoneg) {
5039 bp->autoneg |= AUTONEG_FLOW_CTRL;
5040 }
5041 else {
5042 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5043 }
5044
5045 spin_lock_bh(&bp->phy_lock);
5046
5047 bnx2_setup_phy(bp);
5048
5049 spin_unlock_bh(&bp->phy_lock);
5050
5051 return 0;
5052 }
5053
5054 static u32
5055 bnx2_get_rx_csum(struct net_device *dev)
5056 {
5057 struct bnx2 *bp = netdev_priv(dev);
5058
5059 return bp->rx_csum;
5060 }
5061
5062 static int
5063 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5064 {
5065 struct bnx2 *bp = netdev_priv(dev);
5066
5067 bp->rx_csum = data;
5068 return 0;
5069 }
5070
5071 #define BNX2_NUM_STATS 45
5072
5073 static struct {
5074 char string[ETH_GSTRING_LEN];
5075 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5076 { "rx_bytes" },
5077 { "rx_error_bytes" },
5078 { "tx_bytes" },
5079 { "tx_error_bytes" },
5080 { "rx_ucast_packets" },
5081 { "rx_mcast_packets" },
5082 { "rx_bcast_packets" },
5083 { "tx_ucast_packets" },
5084 { "tx_mcast_packets" },
5085 { "tx_bcast_packets" },
5086 { "tx_mac_errors" },
5087 { "tx_carrier_errors" },
5088 { "rx_crc_errors" },
5089 { "rx_align_errors" },
5090 { "tx_single_collisions" },
5091 { "tx_multi_collisions" },
5092 { "tx_deferred" },
5093 { "tx_excess_collisions" },
5094 { "tx_late_collisions" },
5095 { "tx_total_collisions" },
5096 { "rx_fragments" },
5097 { "rx_jabbers" },
5098 { "rx_undersize_packets" },
5099 { "rx_oversize_packets" },
5100 { "rx_64_byte_packets" },
5101 { "rx_65_to_127_byte_packets" },
5102 { "rx_128_to_255_byte_packets" },
5103 { "rx_256_to_511_byte_packets" },
5104 { "rx_512_to_1023_byte_packets" },
5105 { "rx_1024_to_1522_byte_packets" },
5106 { "rx_1523_to_9022_byte_packets" },
5107 { "tx_64_byte_packets" },
5108 { "tx_65_to_127_byte_packets" },
5109 { "tx_128_to_255_byte_packets" },
5110 { "tx_256_to_511_byte_packets" },
5111 { "tx_512_to_1023_byte_packets" },
5112 { "tx_1024_to_1522_byte_packets" },
5113 { "tx_1523_to_9022_byte_packets" },
5114 { "rx_xon_frames" },
5115 { "rx_xoff_frames" },
5116 { "tx_xon_frames" },
5117 { "tx_xoff_frames" },
5118 { "rx_mac_ctrl_frames" },
5119 { "rx_filtered_packets" },
5120 { "rx_discards" },
5121 };
5122
5123 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5124
5125 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5126 STATS_OFFSET32(stat_IfHCInOctets_hi),
5127 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5128 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5129 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5130 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5131 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5132 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5133 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5134 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5135 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5136 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5137 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5138 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5139 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5140 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5141 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5142 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5143 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5144 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5145 STATS_OFFSET32(stat_EtherStatsCollisions),
5146 STATS_OFFSET32(stat_EtherStatsFragments),
5147 STATS_OFFSET32(stat_EtherStatsJabbers),
5148 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5149 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5150 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5151 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5152 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5153 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5154 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5155 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5156 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5157 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5158 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5159 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5160 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5161 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5162 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5163 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5164 STATS_OFFSET32(stat_XonPauseFramesReceived),
5165 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5166 STATS_OFFSET32(stat_OutXonSent),
5167 STATS_OFFSET32(stat_OutXoffSent),
5168 STATS_OFFSET32(stat_MacControlFramesReceived),
5169 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5170 STATS_OFFSET32(stat_IfInMBUFDiscards),
5171 };
5172
5173 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5174 * skipped because of errata.
5175 */
5176 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5177 8,0,8,8,8,8,8,8,8,8,
5178 4,0,4,4,4,4,4,4,4,4,
5179 4,4,4,4,4,4,4,4,4,4,
5180 4,4,4,4,4,4,4,4,4,4,
5181 4,4,4,4,4,
5182 };
5183
5184 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5185 8,0,8,8,8,8,8,8,8,8,
5186 4,4,4,4,4,4,4,4,4,4,
5187 4,4,4,4,4,4,4,4,4,4,
5188 4,4,4,4,4,4,4,4,4,4,
5189 4,4,4,4,4,
5190 };
5191
5192 #define BNX2_NUM_TESTS 6
5193
5194 static struct {
5195 char string[ETH_GSTRING_LEN];
5196 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5197 { "register_test (offline)" },
5198 { "memory_test (offline)" },
5199 { "loopback_test (offline)" },
5200 { "nvram_test (online)" },
5201 { "interrupt_test (online)" },
5202 { "link_test (online)" },
5203 };
5204
5205 static int
5206 bnx2_self_test_count(struct net_device *dev)
5207 {
5208 return BNX2_NUM_TESTS;
5209 }
5210
5211 static void
5212 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5213 {
5214 struct bnx2 *bp = netdev_priv(dev);
5215
5216 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5217 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5218 bnx2_netif_stop(bp);
5219 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5220 bnx2_free_skbs(bp);
5221
5222 if (bnx2_test_registers(bp) != 0) {
5223 buf[0] = 1;
5224 etest->flags |= ETH_TEST_FL_FAILED;
5225 }
5226 if (bnx2_test_memory(bp) != 0) {
5227 buf[1] = 1;
5228 etest->flags |= ETH_TEST_FL_FAILED;
5229 }
5230 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
5231 etest->flags |= ETH_TEST_FL_FAILED;
5232
5233 if (!netif_running(bp->dev)) {
5234 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5235 }
5236 else {
5237 bnx2_init_nic(bp);
5238 bnx2_netif_start(bp);
5239 }
5240
5241 /* wait for link up */
5242 msleep_interruptible(3000);
5243 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5244 msleep_interruptible(4000);
5245 }
5246
5247 if (bnx2_test_nvram(bp) != 0) {
5248 buf[3] = 1;
5249 etest->flags |= ETH_TEST_FL_FAILED;
5250 }
5251 if (bnx2_test_intr(bp) != 0) {
5252 buf[4] = 1;
5253 etest->flags |= ETH_TEST_FL_FAILED;
5254 }
5255
5256 if (bnx2_test_link(bp) != 0) {
5257 buf[5] = 1;
5258 etest->flags |= ETH_TEST_FL_FAILED;
5259
5260 }
5261 }
5262
5263 static void
5264 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5265 {
5266 switch (stringset) {
5267 case ETH_SS_STATS:
5268 memcpy(buf, bnx2_stats_str_arr,
5269 sizeof(bnx2_stats_str_arr));
5270 break;
5271 case ETH_SS_TEST:
5272 memcpy(buf, bnx2_tests_str_arr,
5273 sizeof(bnx2_tests_str_arr));
5274 break;
5275 }
5276 }
5277
5278 static int
5279 bnx2_get_stats_count(struct net_device *dev)
5280 {
5281 return BNX2_NUM_STATS;
5282 }
5283
5284 static void
5285 bnx2_get_ethtool_stats(struct net_device *dev,
5286 struct ethtool_stats *stats, u64 *buf)
5287 {
5288 struct bnx2 *bp = netdev_priv(dev);
5289 int i;
5290 u32 *hw_stats = (u32 *) bp->stats_blk;
5291 u8 *stats_len_arr = NULL;
5292
5293 if (hw_stats == NULL) {
5294 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5295 return;
5296 }
5297
5298 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5299 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5300 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5301 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5302 stats_len_arr = bnx2_5706_stats_len_arr;
5303 else
5304 stats_len_arr = bnx2_5708_stats_len_arr;
5305
5306 for (i = 0; i < BNX2_NUM_STATS; i++) {
5307 if (stats_len_arr[i] == 0) {
5308 /* skip this counter */
5309 buf[i] = 0;
5310 continue;
5311 }
5312 if (stats_len_arr[i] == 4) {
5313 /* 4-byte counter */
5314 buf[i] = (u64)
5315 *(hw_stats + bnx2_stats_offset_arr[i]);
5316 continue;
5317 }
5318 /* 8-byte counter */
5319 buf[i] = (((u64) *(hw_stats +
5320 bnx2_stats_offset_arr[i])) << 32) +
5321 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5322 }
5323 }
5324
5325 static int
5326 bnx2_phys_id(struct net_device *dev, u32 data)
5327 {
5328 struct bnx2 *bp = netdev_priv(dev);
5329 int i;
5330 u32 save;
5331
5332 if (data == 0)
5333 data = 2;
5334
5335 save = REG_RD(bp, BNX2_MISC_CFG);
5336 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5337
5338 for (i = 0; i < (data * 2); i++) {
5339 if ((i % 2) == 0) {
5340 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5341 }
5342 else {
5343 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5344 BNX2_EMAC_LED_1000MB_OVERRIDE |
5345 BNX2_EMAC_LED_100MB_OVERRIDE |
5346 BNX2_EMAC_LED_10MB_OVERRIDE |
5347 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5348 BNX2_EMAC_LED_TRAFFIC);
5349 }
5350 msleep_interruptible(500);
5351 if (signal_pending(current))
5352 break;
5353 }
5354 REG_WR(bp, BNX2_EMAC_LED, 0);
5355 REG_WR(bp, BNX2_MISC_CFG, save);
5356 return 0;
5357 }
5358
5359 static struct ethtool_ops bnx2_ethtool_ops = {
5360 .get_settings = bnx2_get_settings,
5361 .set_settings = bnx2_set_settings,
5362 .get_drvinfo = bnx2_get_drvinfo,
5363 .get_wol = bnx2_get_wol,
5364 .set_wol = bnx2_set_wol,
5365 .nway_reset = bnx2_nway_reset,
5366 .get_link = ethtool_op_get_link,
5367 .get_eeprom_len = bnx2_get_eeprom_len,
5368 .get_eeprom = bnx2_get_eeprom,
5369 .set_eeprom = bnx2_set_eeprom,
5370 .get_coalesce = bnx2_get_coalesce,
5371 .set_coalesce = bnx2_set_coalesce,
5372 .get_ringparam = bnx2_get_ringparam,
5373 .set_ringparam = bnx2_set_ringparam,
5374 .get_pauseparam = bnx2_get_pauseparam,
5375 .set_pauseparam = bnx2_set_pauseparam,
5376 .get_rx_csum = bnx2_get_rx_csum,
5377 .set_rx_csum = bnx2_set_rx_csum,
5378 .get_tx_csum = ethtool_op_get_tx_csum,
5379 .set_tx_csum = ethtool_op_set_tx_csum,
5380 .get_sg = ethtool_op_get_sg,
5381 .set_sg = ethtool_op_set_sg,
5382 #ifdef BCM_TSO
5383 .get_tso = ethtool_op_get_tso,
5384 .set_tso = ethtool_op_set_tso,
5385 #endif
5386 .self_test_count = bnx2_self_test_count,
5387 .self_test = bnx2_self_test,
5388 .get_strings = bnx2_get_strings,
5389 .phys_id = bnx2_phys_id,
5390 .get_stats_count = bnx2_get_stats_count,
5391 .get_ethtool_stats = bnx2_get_ethtool_stats,
5392 .get_perm_addr = ethtool_op_get_perm_addr,
5393 };
5394
5395 /* Called with rtnl_lock */
5396 static int
5397 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5398 {
5399 struct mii_ioctl_data *data = if_mii(ifr);
5400 struct bnx2 *bp = netdev_priv(dev);
5401 int err;
5402
5403 switch(cmd) {
5404 case SIOCGMIIPHY:
5405 data->phy_id = bp->phy_addr;
5406
5407 /* fallthru */
5408 case SIOCGMIIREG: {
5409 u32 mii_regval;
5410
5411 spin_lock_bh(&bp->phy_lock);
5412 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5413 spin_unlock_bh(&bp->phy_lock);
5414
5415 data->val_out = mii_regval;
5416
5417 return err;
5418 }
5419
5420 case SIOCSMIIREG:
5421 if (!capable(CAP_NET_ADMIN))
5422 return -EPERM;
5423
5424 spin_lock_bh(&bp->phy_lock);
5425 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5426 spin_unlock_bh(&bp->phy_lock);
5427
5428 return err;
5429
5430 default:
5431 /* do nothing */
5432 break;
5433 }
5434 return -EOPNOTSUPP;
5435 }
5436
5437 /* Called with rtnl_lock */
5438 static int
5439 bnx2_change_mac_addr(struct net_device *dev, void *p)
5440 {
5441 struct sockaddr *addr = p;
5442 struct bnx2 *bp = netdev_priv(dev);
5443
5444 if (!is_valid_ether_addr(addr->sa_data))
5445 return -EINVAL;
5446
5447 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5448 if (netif_running(dev))
5449 bnx2_set_mac_addr(bp);
5450
5451 return 0;
5452 }
5453
5454 /* Called with rtnl_lock */
5455 static int
5456 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5457 {
5458 struct bnx2 *bp = netdev_priv(dev);
5459
5460 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5461 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5462 return -EINVAL;
5463
5464 dev->mtu = new_mtu;
5465 if (netif_running(dev)) {
5466 bnx2_netif_stop(bp);
5467
5468 bnx2_init_nic(bp);
5469
5470 bnx2_netif_start(bp);
5471 }
5472 return 0;
5473 }
5474
5475 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5476 static void
5477 poll_bnx2(struct net_device *dev)
5478 {
5479 struct bnx2 *bp = netdev_priv(dev);
5480
5481 disable_irq(bp->pdev->irq);
5482 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5483 enable_irq(bp->pdev->irq);
5484 }
5485 #endif
5486
5487 static int __devinit
5488 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5489 {
5490 struct bnx2 *bp;
5491 unsigned long mem_len;
5492 int rc;
5493 u32 reg;
5494
5495 SET_MODULE_OWNER(dev);
5496 SET_NETDEV_DEV(dev, &pdev->dev);
5497 bp = netdev_priv(dev);
5498
5499 bp->flags = 0;
5500 bp->phy_flags = 0;
5501
5502 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5503 rc = pci_enable_device(pdev);
5504 if (rc) {
5505 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5506 goto err_out;
5507 }
5508
5509 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5510 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5511 "aborting.\n");
5512 rc = -ENODEV;
5513 goto err_out_disable;
5514 }
5515
5516 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5517 if (rc) {
5518 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5519 goto err_out_disable;
5520 }
5521
5522 pci_set_master(pdev);
5523
5524 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5525 if (bp->pm_cap == 0) {
5526 printk(KERN_ERR PFX "Cannot find power management capability, "
5527 "aborting.\n");
5528 rc = -EIO;
5529 goto err_out_release;
5530 }
5531
5532 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5533 if (bp->pcix_cap == 0) {
5534 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5535 rc = -EIO;
5536 goto err_out_release;
5537 }
5538
5539 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5540 bp->flags |= USING_DAC_FLAG;
5541 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5542 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5543 "failed, aborting.\n");
5544 rc = -EIO;
5545 goto err_out_release;
5546 }
5547 }
5548 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5549 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5550 rc = -EIO;
5551 goto err_out_release;
5552 }
5553
5554 bp->dev = dev;
5555 bp->pdev = pdev;
5556
5557 spin_lock_init(&bp->phy_lock);
5558 spin_lock_init(&bp->tx_lock);
5559 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5560
5561 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5562 mem_len = MB_GET_CID_ADDR(17);
5563 dev->mem_end = dev->mem_start + mem_len;
5564 dev->irq = pdev->irq;
5565
5566 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5567
5568 if (!bp->regview) {
5569 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5570 rc = -ENOMEM;
5571 goto err_out_release;
5572 }
5573
5574 /* Configure byte swap and enable write to the reg_window registers.
5575 * Rely on CPU to do target byte swapping on big endian systems
5576 * The chip's target access swapping will not swap all accesses
5577 */
5578 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5579 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5580 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5581
5582 bnx2_set_power_state(bp, PCI_D0);
5583
5584 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5585
5586 /* Get bus information. */
5587 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5588 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5589 u32 clkreg;
5590
5591 bp->flags |= PCIX_FLAG;
5592
5593 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5594
5595 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5596 switch (clkreg) {
5597 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5598 bp->bus_speed_mhz = 133;
5599 break;
5600
5601 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5602 bp->bus_speed_mhz = 100;
5603 break;
5604
5605 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5606 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5607 bp->bus_speed_mhz = 66;
5608 break;
5609
5610 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5611 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5612 bp->bus_speed_mhz = 50;
5613 break;
5614
5615 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5616 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5617 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5618 bp->bus_speed_mhz = 33;
5619 break;
5620 }
5621 }
5622 else {
5623 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5624 bp->bus_speed_mhz = 66;
5625 else
5626 bp->bus_speed_mhz = 33;
5627 }
5628
5629 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5630 bp->flags |= PCI_32BIT_FLAG;
5631
5632 /* 5706A0 may falsely detect SERR and PERR. */
5633 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5634 reg = REG_RD(bp, PCI_COMMAND);
5635 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5636 REG_WR(bp, PCI_COMMAND, reg);
5637 }
5638 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5639 !(bp->flags & PCIX_FLAG)) {
5640
5641 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5642 "aborting.\n");
5643 goto err_out_unmap;
5644 }
5645
5646 bnx2_init_nvram(bp);
5647
5648 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5649
5650 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5651 BNX2_SHM_HDR_SIGNATURE_SIG)
5652 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5653 else
5654 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5655
5656 /* Get the permanent MAC address. First we need to make sure the
5657 * firmware is actually running.
5658 */
5659 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5660
5661 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5662 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5663 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5664 rc = -ENODEV;
5665 goto err_out_unmap;
5666 }
5667
5668 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5669
5670 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5671 bp->mac_addr[0] = (u8) (reg >> 8);
5672 bp->mac_addr[1] = (u8) reg;
5673
5674 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5675 bp->mac_addr[2] = (u8) (reg >> 24);
5676 bp->mac_addr[3] = (u8) (reg >> 16);
5677 bp->mac_addr[4] = (u8) (reg >> 8);
5678 bp->mac_addr[5] = (u8) reg;
5679
5680 bp->tx_ring_size = MAX_TX_DESC_CNT;
5681 bp->rx_ring_size = 100;
5682
5683 bp->rx_csum = 1;
5684
5685 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5686
5687 bp->tx_quick_cons_trip_int = 20;
5688 bp->tx_quick_cons_trip = 20;
5689 bp->tx_ticks_int = 80;
5690 bp->tx_ticks = 80;
5691
5692 bp->rx_quick_cons_trip_int = 6;
5693 bp->rx_quick_cons_trip = 6;
5694 bp->rx_ticks_int = 18;
5695 bp->rx_ticks = 18;
5696
5697 bp->stats_ticks = 1000000 & 0xffff00;
5698
5699 bp->timer_interval = HZ;
5700 bp->current_interval = HZ;
5701
5702 bp->phy_addr = 1;
5703
5704 /* Disable WOL support if we are running on a SERDES chip. */
5705 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5706 bp->phy_flags |= PHY_SERDES_FLAG;
5707 bp->flags |= NO_WOL_FLAG;
5708 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5709 bp->phy_addr = 2;
5710 reg = REG_RD_IND(bp, bp->shmem_base +
5711 BNX2_SHARED_HW_CFG_CONFIG);
5712 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5713 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5714 }
5715 }
5716
5717 if (CHIP_NUM(bp) == CHIP_NUM_5708)
5718 bp->flags |= NO_WOL_FLAG;
5719
5720 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5721 bp->tx_quick_cons_trip_int =
5722 bp->tx_quick_cons_trip;
5723 bp->tx_ticks_int = bp->tx_ticks;
5724 bp->rx_quick_cons_trip_int =
5725 bp->rx_quick_cons_trip;
5726 bp->rx_ticks_int = bp->rx_ticks;
5727 bp->comp_prod_trip_int = bp->comp_prod_trip;
5728 bp->com_ticks_int = bp->com_ticks;
5729 bp->cmd_ticks_int = bp->cmd_ticks;
5730 }
5731
5732 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5733 bp->req_line_speed = 0;
5734 if (bp->phy_flags & PHY_SERDES_FLAG) {
5735 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5736
5737 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5738 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5739 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5740 bp->autoneg = 0;
5741 bp->req_line_speed = bp->line_speed = SPEED_1000;
5742 bp->req_duplex = DUPLEX_FULL;
5743 }
5744 }
5745 else {
5746 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5747 }
5748
5749 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5750
5751 init_timer(&bp->timer);
5752 bp->timer.expires = RUN_AT(bp->timer_interval);
5753 bp->timer.data = (unsigned long) bp;
5754 bp->timer.function = bnx2_timer;
5755
5756 return 0;
5757
5758 err_out_unmap:
5759 if (bp->regview) {
5760 iounmap(bp->regview);
5761 bp->regview = NULL;
5762 }
5763
5764 err_out_release:
5765 pci_release_regions(pdev);
5766
5767 err_out_disable:
5768 pci_disable_device(pdev);
5769 pci_set_drvdata(pdev, NULL);
5770
5771 err_out:
5772 return rc;
5773 }
5774
5775 static int __devinit
5776 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5777 {
5778 static int version_printed = 0;
5779 struct net_device *dev = NULL;
5780 struct bnx2 *bp;
5781 int rc, i;
5782
5783 if (version_printed++ == 0)
5784 printk(KERN_INFO "%s", version);
5785
5786 /* dev zeroed in init_etherdev */
5787 dev = alloc_etherdev(sizeof(*bp));
5788
5789 if (!dev)
5790 return -ENOMEM;
5791
5792 rc = bnx2_init_board(pdev, dev);
5793 if (rc < 0) {
5794 free_netdev(dev);
5795 return rc;
5796 }
5797
5798 dev->open = bnx2_open;
5799 dev->hard_start_xmit = bnx2_start_xmit;
5800 dev->stop = bnx2_close;
5801 dev->get_stats = bnx2_get_stats;
5802 dev->set_multicast_list = bnx2_set_rx_mode;
5803 dev->do_ioctl = bnx2_ioctl;
5804 dev->set_mac_address = bnx2_change_mac_addr;
5805 dev->change_mtu = bnx2_change_mtu;
5806 dev->tx_timeout = bnx2_tx_timeout;
5807 dev->watchdog_timeo = TX_TIMEOUT;
5808 #ifdef BCM_VLAN
5809 dev->vlan_rx_register = bnx2_vlan_rx_register;
5810 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5811 #endif
5812 dev->poll = bnx2_poll;
5813 dev->ethtool_ops = &bnx2_ethtool_ops;
5814 dev->weight = 64;
5815
5816 bp = netdev_priv(dev);
5817
5818 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5819 dev->poll_controller = poll_bnx2;
5820 #endif
5821
5822 if ((rc = register_netdev(dev))) {
5823 printk(KERN_ERR PFX "Cannot register net device\n");
5824 if (bp->regview)
5825 iounmap(bp->regview);
5826 pci_release_regions(pdev);
5827 pci_disable_device(pdev);
5828 pci_set_drvdata(pdev, NULL);
5829 free_netdev(dev);
5830 return rc;
5831 }
5832
5833 pci_set_drvdata(pdev, dev);
5834
5835 memcpy(dev->dev_addr, bp->mac_addr, 6);
5836 memcpy(dev->perm_addr, bp->mac_addr, 6);
5837 bp->name = board_info[ent->driver_data].name,
5838 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5839 "IRQ %d, ",
5840 dev->name,
5841 bp->name,
5842 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5843 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5844 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5845 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5846 bp->bus_speed_mhz,
5847 dev->base_addr,
5848 bp->pdev->irq);
5849
5850 printk("node addr ");
5851 for (i = 0; i < 6; i++)
5852 printk("%2.2x", dev->dev_addr[i]);
5853 printk("\n");
5854
5855 dev->features |= NETIF_F_SG;
5856 if (bp->flags & USING_DAC_FLAG)
5857 dev->features |= NETIF_F_HIGHDMA;
5858 dev->features |= NETIF_F_IP_CSUM;
5859 #ifdef BCM_VLAN
5860 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5861 #endif
5862 #ifdef BCM_TSO
5863 dev->features |= NETIF_F_TSO;
5864 #endif
5865
5866 netif_carrier_off(bp->dev);
5867
5868 return 0;
5869 }
5870
5871 static void __devexit
5872 bnx2_remove_one(struct pci_dev *pdev)
5873 {
5874 struct net_device *dev = pci_get_drvdata(pdev);
5875 struct bnx2 *bp = netdev_priv(dev);
5876
5877 flush_scheduled_work();
5878
5879 unregister_netdev(dev);
5880
5881 if (bp->regview)
5882 iounmap(bp->regview);
5883
5884 free_netdev(dev);
5885 pci_release_regions(pdev);
5886 pci_disable_device(pdev);
5887 pci_set_drvdata(pdev, NULL);
5888 }
5889
5890 static int
5891 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5892 {
5893 struct net_device *dev = pci_get_drvdata(pdev);
5894 struct bnx2 *bp = netdev_priv(dev);
5895 u32 reset_code;
5896
5897 if (!netif_running(dev))
5898 return 0;
5899
5900 bnx2_netif_stop(bp);
5901 netif_device_detach(dev);
5902 del_timer_sync(&bp->timer);
5903 if (bp->flags & NO_WOL_FLAG)
5904 reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
5905 else if (bp->wol)
5906 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5907 else
5908 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5909 bnx2_reset_chip(bp, reset_code);
5910 bnx2_free_skbs(bp);
5911 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5912 return 0;
5913 }
5914
5915 static int
5916 bnx2_resume(struct pci_dev *pdev)
5917 {
5918 struct net_device *dev = pci_get_drvdata(pdev);
5919 struct bnx2 *bp = netdev_priv(dev);
5920
5921 if (!netif_running(dev))
5922 return 0;
5923
5924 bnx2_set_power_state(bp, PCI_D0);
5925 netif_device_attach(dev);
5926 bnx2_init_nic(bp);
5927 bnx2_netif_start(bp);
5928 return 0;
5929 }
5930
5931 static struct pci_driver bnx2_pci_driver = {
5932 .name = DRV_MODULE_NAME,
5933 .id_table = bnx2_pci_tbl,
5934 .probe = bnx2_init_one,
5935 .remove = __devexit_p(bnx2_remove_one),
5936 .suspend = bnx2_suspend,
5937 .resume = bnx2_resume,
5938 };
5939
5940 static int __init bnx2_init(void)
5941 {
5942 return pci_module_init(&bnx2_pci_driver);
5943 }
5944
5945 static void __exit bnx2_cleanup(void)
5946 {
5947 pci_unregister_driver(&bnx2_pci_driver);
5948 }
5949
5950 module_init(bnx2_init);
5951 module_exit(bnx2_cleanup);
5952
5953
5954
Stable & featurefull patchset based on Linus's git branch