?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[CPUFREQ] move policy's governor initialisation out of low-level drivers into cpufreq...
[linux-2.6/zen-sources.git] / drivers / net / ns83820.c
blobea80e6cb3dec1600ba4b5baecba4f4d56c612bba
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/ip.h> /* for iph */
110 #include <linux/in.h> /* for IPPROTO_... */
111 #include <linux/compiler.h>
112 #include <linux/prefetch.h>
113 #include <linux/ethtool.h>
114 #include <linux/timer.h>
115 #include <linux/if_vlan.h>
116 #include <linux/rtnetlink.h>
117 #include <linux/jiffies.h>
118
119 #include <asm/io.h>
120 #include <asm/uaccess.h>
121 #include <asm/system.h>
122
123 #define DRV_NAME "ns83820"
124
125 /* Global parameters. See module_param near the bottom. */
126 static int ihr = 2;
127 static int reset_phy = 0;
128 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129
130 /* Dprintk is used for more interesting debug events */
131 #undef Dprintk
132 #define Dprintk dprintk
133
134 /* tunables */
135 #define RX_BUF_SIZE 1500 /* 8192 */
136 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
137 #define NS83820_VLAN_ACCEL_SUPPORT
138 #endif
139
140 /* Must not exceed ~65000. */
141 #define NR_RX_DESC 64
142 #define NR_TX_DESC 128
143
144 /* not tunable */
145 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
146
147 #define MIN_TX_DESC_FREE 8
148
149 /* register defines */
150 #define CFGCS 0x04
151
152 #define CR_TXE 0x00000001
153 #define CR_TXD 0x00000002
154 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157 #define CR_RXE 0x00000004
158 #define CR_RXD 0x00000008
159 #define CR_TXR 0x00000010
160 #define CR_RXR 0x00000020
161 #define CR_SWI 0x00000080
162 #define CR_RST 0x00000100
163
164 #define PTSCR_EEBIST_FAIL 0x00000001
165 #define PTSCR_EEBIST_EN 0x00000002
166 #define PTSCR_EELOAD_EN 0x00000004
167 #define PTSCR_RBIST_FAIL 0x000001b8
168 #define PTSCR_RBIST_DONE 0x00000200
169 #define PTSCR_RBIST_EN 0x00000400
170 #define PTSCR_RBIST_RST 0x00002000
171
172 #define MEAR_EEDI 0x00000001
173 #define MEAR_EEDO 0x00000002
174 #define MEAR_EECLK 0x00000004
175 #define MEAR_EESEL 0x00000008
176 #define MEAR_MDIO 0x00000010
177 #define MEAR_MDDIR 0x00000020
178 #define MEAR_MDC 0x00000040
179
180 #define ISR_TXDESC3 0x40000000
181 #define ISR_TXDESC2 0x20000000
182 #define ISR_TXDESC1 0x10000000
183 #define ISR_TXDESC0 0x08000000
184 #define ISR_RXDESC3 0x04000000
185 #define ISR_RXDESC2 0x02000000
186 #define ISR_RXDESC1 0x01000000
187 #define ISR_RXDESC0 0x00800000
188 #define ISR_TXRCMP 0x00400000
189 #define ISR_RXRCMP 0x00200000
190 #define ISR_DPERR 0x00100000
191 #define ISR_SSERR 0x00080000
192 #define ISR_RMABT 0x00040000
193 #define ISR_RTABT 0x00020000
194 #define ISR_RXSOVR 0x00010000
195 #define ISR_HIBINT 0x00008000
196 #define ISR_PHY 0x00004000
197 #define ISR_PME 0x00002000
198 #define ISR_SWI 0x00001000
199 #define ISR_MIB 0x00000800
200 #define ISR_TXURN 0x00000400
201 #define ISR_TXIDLE 0x00000200
202 #define ISR_TXERR 0x00000100
203 #define ISR_TXDESC 0x00000080
204 #define ISR_TXOK 0x00000040
205 #define ISR_RXORN 0x00000020
206 #define ISR_RXIDLE 0x00000010
207 #define ISR_RXEARLY 0x00000008
208 #define ISR_RXERR 0x00000004
209 #define ISR_RXDESC 0x00000002
210 #define ISR_RXOK 0x00000001
211
212 #define TXCFG_CSI 0x80000000
213 #define TXCFG_HBI 0x40000000
214 #define TXCFG_MLB 0x20000000
215 #define TXCFG_ATP 0x10000000
216 #define TXCFG_ECRETRY 0x00800000
217 #define TXCFG_BRST_DIS 0x00080000
218 #define TXCFG_MXDMA1024 0x00000000
219 #define TXCFG_MXDMA512 0x00700000
220 #define TXCFG_MXDMA256 0x00600000
221 #define TXCFG_MXDMA128 0x00500000
222 #define TXCFG_MXDMA64 0x00400000
223 #define TXCFG_MXDMA32 0x00300000
224 #define TXCFG_MXDMA16 0x00200000
225 #define TXCFG_MXDMA8 0x00100000
226
227 #define CFG_LNKSTS 0x80000000
228 #define CFG_SPDSTS 0x60000000
229 #define CFG_SPDSTS1 0x40000000
230 #define CFG_SPDSTS0 0x20000000
231 #define CFG_DUPSTS 0x10000000
232 #define CFG_TBI_EN 0x01000000
233 #define CFG_MODE_1000 0x00400000
234 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236 #define CFG_AUTO_1000 0x00200000
237 #define CFG_PINT_CTL 0x001c0000
238 #define CFG_PINT_DUPSTS 0x00100000
239 #define CFG_PINT_LNKSTS 0x00080000
240 #define CFG_PINT_SPDSTS 0x00040000
241 #define CFG_TMRTEST 0x00020000
242 #define CFG_MRM_DIS 0x00010000
243 #define CFG_MWI_DIS 0x00008000
244 #define CFG_T64ADDR 0x00004000
245 #define CFG_PCI64_DET 0x00002000
246 #define CFG_DATA64_EN 0x00001000
247 #define CFG_M64ADDR 0x00000800
248 #define CFG_PHY_RST 0x00000400
249 #define CFG_PHY_DIS 0x00000200
250 #define CFG_EXTSTS_EN 0x00000100
251 #define CFG_REQALG 0x00000080
252 #define CFG_SB 0x00000040
253 #define CFG_POW 0x00000020
254 #define CFG_EXD 0x00000010
255 #define CFG_PESEL 0x00000008
256 #define CFG_BROM_DIS 0x00000004
257 #define CFG_EXT_125 0x00000002
258 #define CFG_BEM 0x00000001
259
260 #define EXTSTS_UDPPKT 0x00200000
261 #define EXTSTS_TCPPKT 0x00080000
262 #define EXTSTS_IPPKT 0x00020000
263 #define EXTSTS_VPKT 0x00010000
264 #define EXTSTS_VTG_MASK 0x0000ffff
265
266 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268 #define MIBC_MIBS 0x00000008
269 #define MIBC_ACLR 0x00000004
270 #define MIBC_FRZ 0x00000002
271 #define MIBC_WRN 0x00000001
272
273 #define PCR_PSEN (1 << 31)
274 #define PCR_PS_MCAST (1 << 30)
275 #define PCR_PS_DA (1 << 29)
276 #define PCR_STHI_8 (3 << 23)
277 #define PCR_STLO_4 (1 << 23)
278 #define PCR_FFHI_8K (3 << 21)
279 #define PCR_FFLO_4K (1 << 21)
280 #define PCR_PAUSE_CNT 0xFFFE
281
282 #define RXCFG_AEP 0x80000000
283 #define RXCFG_ARP 0x40000000
284 #define RXCFG_STRIPCRC 0x20000000
285 #define RXCFG_RX_FD 0x10000000
286 #define RXCFG_ALP 0x08000000
287 #define RXCFG_AIRL 0x04000000
288 #define RXCFG_MXDMA512 0x00700000
289 #define RXCFG_DRTH 0x0000003e
290 #define RXCFG_DRTH0 0x00000002
291
292 #define RFCR_RFEN 0x80000000
293 #define RFCR_AAB 0x40000000
294 #define RFCR_AAM 0x20000000
295 #define RFCR_AAU 0x10000000
296 #define RFCR_APM 0x08000000
297 #define RFCR_APAT 0x07800000
298 #define RFCR_APAT3 0x04000000
299 #define RFCR_APAT2 0x02000000
300 #define RFCR_APAT1 0x01000000
301 #define RFCR_APAT0 0x00800000
302 #define RFCR_AARP 0x00400000
303 #define RFCR_MHEN 0x00200000
304 #define RFCR_UHEN 0x00100000
305 #define RFCR_ULM 0x00080000
306
307 #define VRCR_RUDPE 0x00000080
308 #define VRCR_RTCPE 0x00000040
309 #define VRCR_RIPE 0x00000020
310 #define VRCR_IPEN 0x00000010
311 #define VRCR_DUTF 0x00000008
312 #define VRCR_DVTF 0x00000004
313 #define VRCR_VTREN 0x00000002
314 #define VRCR_VTDEN 0x00000001
315
316 #define VTCR_PPCHK 0x00000008
317 #define VTCR_GCHK 0x00000004
318 #define VTCR_VPPTI 0x00000002
319 #define VTCR_VGTI 0x00000001
320
321 #define CR 0x00
322 #define CFG 0x04
323 #define MEAR 0x08
324 #define PTSCR 0x0c
325 #define ISR 0x10
326 #define IMR 0x14
327 #define IER 0x18
328 #define IHR 0x1c
329 #define TXDP 0x20
330 #define TXDP_HI 0x24
331 #define TXCFG 0x28
332 #define GPIOR 0x2c
333 #define RXDP 0x30
334 #define RXDP_HI 0x34
335 #define RXCFG 0x38
336 #define PQCR 0x3c
337 #define WCSR 0x40
338 #define PCR 0x44
339 #define RFCR 0x48
340 #define RFDR 0x4c
341
342 #define SRR 0x58
343
344 #define VRCR 0xbc
345 #define VTCR 0xc0
346 #define VDR 0xc4
347 #define CCSR 0xcc
348
349 #define TBICR 0xe0
350 #define TBISR 0xe4
351 #define TANAR 0xe8
352 #define TANLPAR 0xec
353 #define TANER 0xf0
354 #define TESR 0xf4
355
356 #define TBICR_MR_AN_ENABLE 0x00001000
357 #define TBICR_MR_RESTART_AN 0x00000200
358
359 #define TBISR_MR_LINK_STATUS 0x00000020
360 #define TBISR_MR_AN_COMPLETE 0x00000004
361
362 #define TANAR_PS2 0x00000100
363 #define TANAR_PS1 0x00000080
364 #define TANAR_HALF_DUP 0x00000040
365 #define TANAR_FULL_DUP 0x00000020
366
367 #define GPIOR_GP5_OE 0x00000200
368 #define GPIOR_GP4_OE 0x00000100
369 #define GPIOR_GP3_OE 0x00000080
370 #define GPIOR_GP2_OE 0x00000040
371 #define GPIOR_GP1_OE 0x00000020
372 #define GPIOR_GP3_OUT 0x00000004
373 #define GPIOR_GP1_OUT 0x00000001
374
375 #define LINK_AUTONEGOTIATE 0x01
376 #define LINK_DOWN 0x02
377 #define LINK_UP 0x04
378
379 #define HW_ADDR_LEN sizeof(dma_addr_t)
380 #define desc_addr_set(desc, addr) \
381 do { \
382 ((desc)[0] = cpu_to_le32(addr)); \
383 if (HW_ADDR_LEN == 8) \
384 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
385 } while(0)
386 #define desc_addr_get(desc) \
387 (le32_to_cpu((desc)[0]) | \
388 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
389
390 #define DESC_LINK 0
391 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
392 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
393 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
394
395 #define CMDSTS_OWN 0x80000000
396 #define CMDSTS_MORE 0x40000000
397 #define CMDSTS_INTR 0x20000000
398 #define CMDSTS_ERR 0x10000000
399 #define CMDSTS_OK 0x08000000
400 #define CMDSTS_RUNT 0x00200000
401 #define CMDSTS_LEN_MASK 0x0000ffff
402
403 #define CMDSTS_DEST_MASK 0x01800000
404 #define CMDSTS_DEST_SELF 0x00800000
405 #define CMDSTS_DEST_MULTI 0x01000000
406
407 #define DESC_SIZE 8 /* Should be cache line sized */
408
409 struct rx_info {
410 spinlock_t lock;
411 int up;
412 long idle;
413
414 struct sk_buff *skbs[NR_RX_DESC];
415
416 __le32 *next_rx_desc;
417 u16 next_rx, next_empty;
418
419 __le32 *descs;
420 dma_addr_t phy_descs;
421 };
422
423
424 struct ns83820 {
425 struct net_device_stats stats;
426 u8 __iomem *base;
427
428 struct pci_dev *pci_dev;
429 struct net_device *ndev;
430
431 #ifdef NS83820_VLAN_ACCEL_SUPPORT
432 struct vlan_group *vlgrp;
433 #endif
434
435 struct rx_info rx_info;
436 struct tasklet_struct rx_tasklet;
437
438 unsigned ihr;
439 struct work_struct tq_refill;
440
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock;
443
444 u32 CFG_cache;
445
446 u32 MEAR_cache;
447 u32 IMR_cache;
448
449 unsigned linkstate;
450
451 spinlock_t tx_lock;
452
453 u16 tx_done_idx;
454 u16 tx_idx;
455 volatile u16 tx_free_idx; /* idx of free desc chain */
456 u16 tx_intr_idx;
457
458 atomic_t nr_tx_skbs;
459 struct sk_buff *tx_skbs[NR_TX_DESC];
460
461 char pad[16] __attribute__((aligned(16)));
462 __le32 *tx_descs;
463 dma_addr_t tx_phy_descs;
464
465 struct timer_list tx_watchdog;
466 };
467
468 static inline struct ns83820 *PRIV(struct net_device *dev)
469 {
470 return netdev_priv(dev);
471 }
472
473 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
474
475 static inline void kick_rx(struct net_device *ndev)
476 {
477 struct ns83820 *dev = PRIV(ndev);
478 dprintk("kick_rx: maybe kicking\n");
479 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
480 dprintk("actually kicking\n");
481 writel(dev->rx_info.phy_descs +
482 (4 * DESC_SIZE * dev->rx_info.next_rx),
483 dev->base + RXDP);
484 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
485 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
486 ndev->name);
487 __kick_rx(dev);
488 }
489 }
490
491 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492 #define start_tx_okay(dev) \
493 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
494
495
496 #ifdef NS83820_VLAN_ACCEL_SUPPORT
497 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
498 {
499 struct ns83820 *dev = PRIV(ndev);
500
501 spin_lock_irq(&dev->misc_lock);
502 spin_lock(&dev->tx_lock);
503
504 dev->vlgrp = grp;
505
506 spin_unlock(&dev->tx_lock);
507 spin_unlock_irq(&dev->misc_lock);
508 }
509 #endif
510
511 /* Packet Receiver
512 *
513 * The hardware supports linked lists of receive descriptors for
514 * which ownership is transfered back and forth by means of an
515 * ownership bit. While the hardware does support the use of a
516 * ring for receive descriptors, we only make use of a chain in
517 * an attempt to reduce bus traffic under heavy load scenarios.
518 * This will also make bugs a bit more obvious. The current code
519 * only makes use of a single rx chain; I hope to implement
520 * priority based rx for version 1.0. Goal: even under overload
521 * conditions, still route realtime traffic with as low jitter as
522 * possible.
523 */
524 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
525 {
526 desc_addr_set(desc + DESC_LINK, link);
527 desc_addr_set(desc + DESC_BUFPTR, buf);
528 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
529 mb();
530 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
531 }
532
533 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
534 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
535 {
536 unsigned next_empty;
537 u32 cmdsts;
538 __le32 *sg;
539 dma_addr_t buf;
540
541 next_empty = dev->rx_info.next_empty;
542
543 /* don't overrun last rx marker */
544 if (unlikely(nr_rx_empty(dev) <= 2)) {
545 kfree_skb(skb);
546 return 1;
547 }
548
549 #if 0
550 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
551 dev->rx_info.next_empty,
552 dev->rx_info.nr_used,
553 dev->rx_info.next_rx
554 );
555 #endif
556
557 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
558 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
559 dev->rx_info.skbs[next_empty] = skb;
560
561 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
562 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
563 buf = pci_map_single(dev->pci_dev, skb->data,
564 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
565 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
566 /* update link of previous rx */
567 if (likely(next_empty != dev->rx_info.next_rx))
568 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
569
570 return 0;
571 }
572
573 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
574 {
575 struct ns83820 *dev = PRIV(ndev);
576 unsigned i;
577 unsigned long flags = 0;
578
579 if (unlikely(nr_rx_empty(dev) <= 2))
580 return 0;
581
582 dprintk("rx_refill(%p)\n", ndev);
583 if (gfp == GFP_ATOMIC)
584 spin_lock_irqsave(&dev->rx_info.lock, flags);
585 for (i=0; i<NR_RX_DESC; i++) {
586 struct sk_buff *skb;
587 long res;
588 /* extra 16 bytes for alignment */
589 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
590 if (unlikely(!skb))
591 break;
592
593 res = (long)skb->data & 0xf;
594 res = 0x10 - res;
595 res &= 0xf;
596 skb_reserve(skb, res);
597
598 if (gfp != GFP_ATOMIC)
599 spin_lock_irqsave(&dev->rx_info.lock, flags);
600 res = ns83820_add_rx_skb(dev, skb);
601 if (gfp != GFP_ATOMIC)
602 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
603 if (res) {
604 i = 1;
605 break;
606 }
607 }
608 if (gfp == GFP_ATOMIC)
609 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
610
611 return i ? 0 : -ENOMEM;
612 }
613
614 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
615 static void fastcall rx_refill_atomic(struct net_device *ndev)
616 {
617 rx_refill(ndev, GFP_ATOMIC);
618 }
619
620 /* REFILL */
621 static inline void queue_refill(struct work_struct *work)
622 {
623 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
624 struct net_device *ndev = dev->ndev;
625
626 rx_refill(ndev, GFP_KERNEL);
627 if (dev->rx_info.up)
628 kick_rx(ndev);
629 }
630
631 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
632 {
633 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
634 }
635
636 static void FASTCALL(phy_intr(struct net_device *ndev));
637 static void fastcall phy_intr(struct net_device *ndev)
638 {
639 struct ns83820 *dev = PRIV(ndev);
640 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
641 u32 cfg, new_cfg;
642 u32 tbisr, tanar, tanlpar;
643 int speed, fullduplex, newlinkstate;
644
645 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
646
647 if (dev->CFG_cache & CFG_TBI_EN) {
648 /* we have an optical transceiver */
649 tbisr = readl(dev->base + TBISR);
650 tanar = readl(dev->base + TANAR);
651 tanlpar = readl(dev->base + TANLPAR);
652 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
653 tbisr, tanar, tanlpar);
654
655 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
656 && (tanar & TANAR_FULL_DUP)) ) {
657
658 /* both of us are full duplex */
659 writel(readl(dev->base + TXCFG)
660 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
661 dev->base + TXCFG);
662 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
663 dev->base + RXCFG);
664 /* Light up full duplex LED */
665 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
666 dev->base + GPIOR);
667
668 } else if(((tanlpar & TANAR_HALF_DUP)
669 && (tanar & TANAR_HALF_DUP))
670 || ((tanlpar & TANAR_FULL_DUP)
671 && (tanar & TANAR_HALF_DUP))
672 || ((tanlpar & TANAR_HALF_DUP)
673 && (tanar & TANAR_FULL_DUP))) {
674
675 /* one or both of us are half duplex */
676 writel((readl(dev->base + TXCFG)
677 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
678 dev->base + TXCFG);
679 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
680 dev->base + RXCFG);
681 /* Turn off full duplex LED */
682 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
683 dev->base + GPIOR);
684 }
685
686 speed = 4; /* 1000F */
687
688 } else {
689 /* we have a copper transceiver */
690 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
691
692 if (cfg & CFG_SPDSTS1)
693 new_cfg |= CFG_MODE_1000;
694 else
695 new_cfg &= ~CFG_MODE_1000;
696
697 speed = ((cfg / CFG_SPDSTS0) & 3);
698 fullduplex = (cfg & CFG_DUPSTS);
699
700 if (fullduplex) {
701 new_cfg |= CFG_SB;
702 writel(readl(dev->base + TXCFG)
703 | TXCFG_CSI | TXCFG_HBI,
704 dev->base + TXCFG);
705 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
706 dev->base + RXCFG);
707 } else {
708 writel(readl(dev->base + TXCFG)
709 & ~(TXCFG_CSI | TXCFG_HBI),
710 dev->base + TXCFG);
711 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
712 dev->base + RXCFG);
713 }
714
715 if ((cfg & CFG_LNKSTS) &&
716 ((new_cfg ^ dev->CFG_cache) != 0)) {
717 writel(new_cfg, dev->base + CFG);
718 dev->CFG_cache = new_cfg;
719 }
720
721 dev->CFG_cache &= ~CFG_SPDSTS;
722 dev->CFG_cache |= cfg & CFG_SPDSTS;
723 }
724
725 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
726
727 if (newlinkstate & LINK_UP
728 && dev->linkstate != newlinkstate) {
729 netif_start_queue(ndev);
730 netif_wake_queue(ndev);
731 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
732 ndev->name,
733 speeds[speed],
734 fullduplex ? "full" : "half");
735 } else if (newlinkstate & LINK_DOWN
736 && dev->linkstate != newlinkstate) {
737 netif_stop_queue(ndev);
738 printk(KERN_INFO "%s: link now down.\n", ndev->name);
739 }
740
741 dev->linkstate = newlinkstate;
742 }
743
744 static int ns83820_setup_rx(struct net_device *ndev)
745 {
746 struct ns83820 *dev = PRIV(ndev);
747 unsigned i;
748 int ret;
749
750 dprintk("ns83820_setup_rx(%p)\n", ndev);
751
752 dev->rx_info.idle = 1;
753 dev->rx_info.next_rx = 0;
754 dev->rx_info.next_rx_desc = dev->rx_info.descs;
755 dev->rx_info.next_empty = 0;
756
757 for (i=0; i<NR_RX_DESC; i++)
758 clear_rx_desc(dev, i);
759
760 writel(0, dev->base + RXDP_HI);
761 writel(dev->rx_info.phy_descs, dev->base + RXDP);
762
763 ret = rx_refill(ndev, GFP_KERNEL);
764 if (!ret) {
765 dprintk("starting receiver\n");
766 /* prevent the interrupt handler from stomping on us */
767 spin_lock_irq(&dev->rx_info.lock);
768
769 writel(0x0001, dev->base + CCSR);
770 writel(0, dev->base + RFCR);
771 writel(0x7fc00000, dev->base + RFCR);
772 writel(0xffc00000, dev->base + RFCR);
773
774 dev->rx_info.up = 1;
775
776 phy_intr(ndev);
777
778 /* Okay, let it rip */
779 spin_lock_irq(&dev->misc_lock);
780 dev->IMR_cache |= ISR_PHY;
781 dev->IMR_cache |= ISR_RXRCMP;
782 //dev->IMR_cache |= ISR_RXERR;
783 //dev->IMR_cache |= ISR_RXOK;
784 dev->IMR_cache |= ISR_RXORN;
785 dev->IMR_cache |= ISR_RXSOVR;
786 dev->IMR_cache |= ISR_RXDESC;
787 dev->IMR_cache |= ISR_RXIDLE;
788 dev->IMR_cache |= ISR_TXDESC;
789 dev->IMR_cache |= ISR_TXIDLE;
790
791 writel(dev->IMR_cache, dev->base + IMR);
792 writel(1, dev->base + IER);
793 spin_unlock(&dev->misc_lock);
794
795 kick_rx(ndev);
796
797 spin_unlock_irq(&dev->rx_info.lock);
798 }
799 return ret;
800 }
801
802 static void ns83820_cleanup_rx(struct ns83820 *dev)
803 {
804 unsigned i;
805 unsigned long flags;
806
807 dprintk("ns83820_cleanup_rx(%p)\n", dev);
808
809 /* disable receive interrupts */
810 spin_lock_irqsave(&dev->misc_lock, flags);
811 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
812 writel(dev->IMR_cache, dev->base + IMR);
813 spin_unlock_irqrestore(&dev->misc_lock, flags);
814
815 /* synchronize with the interrupt handler and kill it */
816 dev->rx_info.up = 0;
817 synchronize_irq(dev->pci_dev->irq);
818
819 /* touch the pci bus... */
820 readl(dev->base + IMR);
821
822 /* assumes the transmitter is already disabled and reset */
823 writel(0, dev->base + RXDP_HI);
824 writel(0, dev->base + RXDP);
825
826 for (i=0; i<NR_RX_DESC; i++) {
827 struct sk_buff *skb = dev->rx_info.skbs[i];
828 dev->rx_info.skbs[i] = NULL;
829 clear_rx_desc(dev, i);
830 if (skb)
831 kfree_skb(skb);
832 }
833 }
834
835 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
836 static void fastcall ns83820_rx_kick(struct net_device *ndev)
837 {
838 struct ns83820 *dev = PRIV(ndev);
839 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
840 if (dev->rx_info.up) {
841 rx_refill_atomic(ndev);
842 kick_rx(ndev);
843 }
844 }
845
846 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
847 schedule_work(&dev->tq_refill);
848 else
849 kick_rx(ndev);
850 if (dev->rx_info.idle)
851 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
852 }
853
854 /* rx_irq
855 *
856 */
857 static void FASTCALL(rx_irq(struct net_device *ndev));
858 static void fastcall rx_irq(struct net_device *ndev)
859 {
860 struct ns83820 *dev = PRIV(ndev);
861 struct rx_info *info = &dev->rx_info;
862 unsigned next_rx;
863 int rx_rc, len;
864 u32 cmdsts;
865 __le32 *desc;
866 unsigned long flags;
867 int nr = 0;
868
869 dprintk("rx_irq(%p)\n", ndev);
870 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
871 readl(dev->base + RXDP),
872 (long)(dev->rx_info.phy_descs),
873 (int)dev->rx_info.next_rx,
874 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
875 (int)dev->rx_info.next_empty,
876 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
877 );
878
879 spin_lock_irqsave(&info->lock, flags);
880 if (!info->up)
881 goto out;
882
883 dprintk("walking descs\n");
884 next_rx = info->next_rx;
885 desc = info->next_rx_desc;
886 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
887 (cmdsts != CMDSTS_OWN)) {
888 struct sk_buff *skb;
889 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
890 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
891
892 dprintk("cmdsts: %08x\n", cmdsts);
893 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
894 dprintk("extsts: %08x\n", extsts);
895
896 skb = info->skbs[next_rx];
897 info->skbs[next_rx] = NULL;
898 info->next_rx = (next_rx + 1) % NR_RX_DESC;
899
900 mb();
901 clear_rx_desc(dev, next_rx);
902
903 pci_unmap_single(dev->pci_dev, bufptr,
904 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
905 len = cmdsts & CMDSTS_LEN_MASK;
906 #ifdef NS83820_VLAN_ACCEL_SUPPORT
907 /* NH: As was mentioned below, this chip is kinda
908 * brain dead about vlan tag stripping. Frames
909 * that are 64 bytes with a vlan header appended
910 * like arp frames, or pings, are flagged as Runts
911 * when the tag is stripped and hardware. This
912 * also means that the OK bit in the descriptor
913 * is cleared when the frame comes in so we have
914 * to do a specific length check here to make sure
915 * the frame would have been ok, had we not stripped
916 * the tag.
917 */
918 if (likely((CMDSTS_OK & cmdsts) ||
919 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
920 #else
921 if (likely(CMDSTS_OK & cmdsts)) {
922 #endif
923 skb_put(skb, len);
924 if (unlikely(!skb))
925 goto netdev_mangle_me_harder_failed;
926 if (cmdsts & CMDSTS_DEST_MULTI)
927 dev->stats.multicast ++;
928 dev->stats.rx_packets ++;
929 dev->stats.rx_bytes += len;
930 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
931 skb->ip_summed = CHECKSUM_UNNECESSARY;
932 } else {
933 skb->ip_summed = CHECKSUM_NONE;
934 }
935 skb->protocol = eth_type_trans(skb, ndev);
936 #ifdef NS83820_VLAN_ACCEL_SUPPORT
937 if(extsts & EXTSTS_VPKT) {
938 unsigned short tag;
939 tag = ntohs(extsts & EXTSTS_VTG_MASK);
940 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
941 } else {
942 rx_rc = netif_rx(skb);
943 }
944 #else
945 rx_rc = netif_rx(skb);
946 #endif
947 if (NET_RX_DROP == rx_rc) {
948 netdev_mangle_me_harder_failed:
949 dev->stats.rx_dropped ++;
950 }
951 } else {
952 kfree_skb(skb);
953 }
954
955 nr++;
956 next_rx = info->next_rx;
957 desc = info->descs + (DESC_SIZE * next_rx);
958 }
959 info->next_rx = next_rx;
960 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
961
962 out:
963 if (0 && !nr) {
964 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
965 }
966
967 spin_unlock_irqrestore(&info->lock, flags);
968 }
969
970 static void rx_action(unsigned long _dev)
971 {
972 struct net_device *ndev = (void *)_dev;
973 struct ns83820 *dev = PRIV(ndev);
974 rx_irq(ndev);
975 writel(ihr, dev->base + IHR);
976
977 spin_lock_irq(&dev->misc_lock);
978 dev->IMR_cache |= ISR_RXDESC;
979 writel(dev->IMR_cache, dev->base + IMR);
980 spin_unlock_irq(&dev->misc_lock);
981
982 rx_irq(ndev);
983 ns83820_rx_kick(ndev);
984 }
985
986 /* Packet Transmit code
987 */
988 static inline void kick_tx(struct ns83820 *dev)
989 {
990 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
991 dev, dev->tx_idx, dev->tx_free_idx);
992 writel(CR_TXE, dev->base + CR);
993 }
994
995 /* No spinlock needed on the transmit irq path as the interrupt handler is
996 * serialized.
997 */
998 static void do_tx_done(struct net_device *ndev)
999 {
1000 struct ns83820 *dev = PRIV(ndev);
1001 u32 cmdsts, tx_done_idx;
1002 __le32 *desc;
1003
1004 dprintk("do_tx_done(%p)\n", ndev);
1005 tx_done_idx = dev->tx_done_idx;
1006 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1007
1008 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1009 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1010 while ((tx_done_idx != dev->tx_free_idx) &&
1011 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1012 struct sk_buff *skb;
1013 unsigned len;
1014 dma_addr_t addr;
1015
1016 if (cmdsts & CMDSTS_ERR)
1017 dev->stats.tx_errors ++;
1018 if (cmdsts & CMDSTS_OK)
1019 dev->stats.tx_packets ++;
1020 if (cmdsts & CMDSTS_OK)
1021 dev->stats.tx_bytes += cmdsts & 0xffff;
1022
1023 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1024 tx_done_idx, dev->tx_free_idx, cmdsts);
1025 skb = dev->tx_skbs[tx_done_idx];
1026 dev->tx_skbs[tx_done_idx] = NULL;
1027 dprintk("done(%p)\n", skb);
1028
1029 len = cmdsts & CMDSTS_LEN_MASK;
1030 addr = desc_addr_get(desc + DESC_BUFPTR);
1031 if (skb) {
1032 pci_unmap_single(dev->pci_dev,
1033 addr,
1034 len,
1035 PCI_DMA_TODEVICE);
1036 dev_kfree_skb_irq(skb);
1037 atomic_dec(&dev->nr_tx_skbs);
1038 } else
1039 pci_unmap_page(dev->pci_dev,
1040 addr,
1041 len,
1042 PCI_DMA_TODEVICE);
1043
1044 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1045 dev->tx_done_idx = tx_done_idx;
1046 desc[DESC_CMDSTS] = cpu_to_le32(0);
1047 mb();
1048 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1049 }
1050
1051 /* Allow network stack to resume queueing packets after we've
1052 * finished transmitting at least 1/4 of the packets in the queue.
1053 */
1054 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1055 dprintk("start_queue(%p)\n", ndev);
1056 netif_start_queue(ndev);
1057 netif_wake_queue(ndev);
1058 }
1059 }
1060
1061 static void ns83820_cleanup_tx(struct ns83820 *dev)
1062 {
1063 unsigned i;
1064
1065 for (i=0; i<NR_TX_DESC; i++) {
1066 struct sk_buff *skb = dev->tx_skbs[i];
1067 dev->tx_skbs[i] = NULL;
1068 if (skb) {
1069 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1070 pci_unmap_single(dev->pci_dev,
1071 desc_addr_get(desc + DESC_BUFPTR),
1072 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1073 PCI_DMA_TODEVICE);
1074 dev_kfree_skb_irq(skb);
1075 atomic_dec(&dev->nr_tx_skbs);
1076 }
1077 }
1078
1079 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1080 }
1081
1082 /* transmit routine. This code relies on the network layer serializing
1083 * its calls in, but will run happily in parallel with the interrupt
1084 * handler. This code currently has provisions for fragmenting tx buffers
1085 * while trying to track down a bug in either the zero copy code or
1086 * the tx fifo (hence the MAX_FRAG_LEN).
1087 */
1088 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1089 {
1090 struct ns83820 *dev = PRIV(ndev);
1091 u32 free_idx, cmdsts, extsts;
1092 int nr_free, nr_frags;
1093 unsigned tx_done_idx, last_idx;
1094 dma_addr_t buf;
1095 unsigned len;
1096 skb_frag_t *frag;
1097 int stopped = 0;
1098 int do_intr = 0;
1099 volatile __le32 *first_desc;
1100
1101 dprintk("ns83820_hard_start_xmit\n");
1102
1103 nr_frags = skb_shinfo(skb)->nr_frags;
1104 again:
1105 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1106 netif_stop_queue(ndev);
1107 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1108 return 1;
1109 netif_start_queue(ndev);
1110 }
1111
1112 last_idx = free_idx = dev->tx_free_idx;
1113 tx_done_idx = dev->tx_done_idx;
1114 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1115 nr_free -= 1;
1116 if (nr_free <= nr_frags) {
1117 dprintk("stop_queue - not enough(%p)\n", ndev);
1118 netif_stop_queue(ndev);
1119
1120 /* Check again: we may have raced with a tx done irq */
1121 if (dev->tx_done_idx != tx_done_idx) {
1122 dprintk("restart queue(%p)\n", ndev);
1123 netif_start_queue(ndev);
1124 goto again;
1125 }
1126 return 1;
1127 }
1128
1129 if (free_idx == dev->tx_intr_idx) {
1130 do_intr = 1;
1131 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1132 }
1133
1134 nr_free -= nr_frags;
1135 if (nr_free < MIN_TX_DESC_FREE) {
1136 dprintk("stop_queue - last entry(%p)\n", ndev);
1137 netif_stop_queue(ndev);
1138 stopped = 1;
1139 }
1140
1141 frag = skb_shinfo(skb)->frags;
1142 if (!nr_frags)
1143 frag = NULL;
1144 extsts = 0;
1145 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1146 extsts |= EXTSTS_IPPKT;
1147 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1148 extsts |= EXTSTS_TCPPKT;
1149 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1150 extsts |= EXTSTS_UDPPKT;
1151 }
1152
1153 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1154 if(vlan_tx_tag_present(skb)) {
1155 /* fetch the vlan tag info out of the
1156 * ancilliary data if the vlan code
1157 * is using hw vlan acceleration
1158 */
1159 short tag = vlan_tx_tag_get(skb);
1160 extsts |= (EXTSTS_VPKT | htons(tag));
1161 }
1162 #endif
1163
1164 len = skb->len;
1165 if (nr_frags)
1166 len -= skb->data_len;
1167 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1168
1169 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1170
1171 for (;;) {
1172 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1173
1174 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1175 (unsigned long long)buf);
1176 last_idx = free_idx;
1177 free_idx = (free_idx + 1) % NR_TX_DESC;
1178 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1179 desc_addr_set(desc + DESC_BUFPTR, buf);
1180 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1181
1182 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1183 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1184 cmdsts |= len;
1185 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1186
1187 if (!nr_frags)
1188 break;
1189
1190 buf = pci_map_page(dev->pci_dev, frag->page,
1191 frag->page_offset,
1192 frag->size, PCI_DMA_TODEVICE);
1193 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1194 (long long)buf, (long) page_to_pfn(frag->page),
1195 frag->page_offset);
1196 len = frag->size;
1197 frag++;
1198 nr_frags--;
1199 }
1200 dprintk("done pkt\n");
1201
1202 spin_lock_irq(&dev->tx_lock);
1203 dev->tx_skbs[last_idx] = skb;
1204 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1205 dev->tx_free_idx = free_idx;
1206 atomic_inc(&dev->nr_tx_skbs);
1207 spin_unlock_irq(&dev->tx_lock);
1208
1209 kick_tx(dev);
1210
1211 /* Check again: we may have raced with a tx done irq */
1212 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1213 netif_start_queue(ndev);
1214
1215 /* set the transmit start time to catch transmit timeouts */
1216 ndev->trans_start = jiffies;
1217 return 0;
1218 }
1219
1220 static void ns83820_update_stats(struct ns83820 *dev)
1221 {
1222 u8 __iomem *base = dev->base;
1223
1224 /* the DP83820 will freeze counters, so we need to read all of them */
1225 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1226 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1227 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1228 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1229 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1230 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1231 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1232 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1233 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1234 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1235 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1236 }
1237
1238 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1239 {
1240 struct ns83820 *dev = PRIV(ndev);
1241
1242 /* somewhat overkill */
1243 spin_lock_irq(&dev->misc_lock);
1244 ns83820_update_stats(dev);
1245 spin_unlock_irq(&dev->misc_lock);
1246
1247 return &dev->stats;
1248 }
1249
1250 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1251 {
1252 struct ns83820 *dev = PRIV(ndev);
1253 strcpy(info->driver, "ns83820");
1254 strcpy(info->version, VERSION);
1255 strcpy(info->bus_info, pci_name(dev->pci_dev));
1256 }
1257
1258 static u32 ns83820_get_link(struct net_device *ndev)
1259 {
1260 struct ns83820 *dev = PRIV(ndev);
1261 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1262 return cfg & CFG_LNKSTS ? 1 : 0;
1263 }
1264
1265 static const struct ethtool_ops ops = {
1266 .get_drvinfo = ns83820_get_drvinfo,
1267 .get_link = ns83820_get_link
1268 };
1269
1270 /* this function is called in irq context from the ISR */
1271 static void ns83820_mib_isr(struct ns83820 *dev)
1272 {
1273 unsigned long flags;
1274 spin_lock_irqsave(&dev->misc_lock, flags);
1275 ns83820_update_stats(dev);
1276 spin_unlock_irqrestore(&dev->misc_lock, flags);
1277 }
1278
1279 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1280 static irqreturn_t ns83820_irq(int foo, void *data)
1281 {
1282 struct net_device *ndev = data;
1283 struct ns83820 *dev = PRIV(ndev);
1284 u32 isr;
1285 dprintk("ns83820_irq(%p)\n", ndev);
1286
1287 dev->ihr = 0;
1288
1289 isr = readl(dev->base + ISR);
1290 dprintk("irq: %08x\n", isr);
1291 ns83820_do_isr(ndev, isr);
1292 return IRQ_HANDLED;
1293 }
1294
1295 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1296 {
1297 struct ns83820 *dev = PRIV(ndev);
1298 unsigned long flags;
1299
1300 #ifdef DEBUG
1301 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1302 Dprintk("odd isr? 0x%08x\n", isr);
1303 #endif
1304
1305 if (ISR_RXIDLE & isr) {
1306 dev->rx_info.idle = 1;
1307 Dprintk("oh dear, we are idle\n");
1308 ns83820_rx_kick(ndev);
1309 }
1310
1311 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1312 prefetch(dev->rx_info.next_rx_desc);
1313
1314 spin_lock_irqsave(&dev->misc_lock, flags);
1315 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1316 writel(dev->IMR_cache, dev->base + IMR);
1317 spin_unlock_irqrestore(&dev->misc_lock, flags);
1318
1319 tasklet_schedule(&dev->rx_tasklet);
1320 //rx_irq(ndev);
1321 //writel(4, dev->base + IHR);
1322 }
1323
1324 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1325 ns83820_rx_kick(ndev);
1326
1327 if (unlikely(ISR_RXSOVR & isr)) {
1328 //printk("overrun: rxsovr\n");
1329 dev->stats.rx_fifo_errors ++;
1330 }
1331
1332 if (unlikely(ISR_RXORN & isr)) {
1333 //printk("overrun: rxorn\n");
1334 dev->stats.rx_fifo_errors ++;
1335 }
1336
1337 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1338 writel(CR_RXE, dev->base + CR);
1339
1340 if (ISR_TXIDLE & isr) {
1341 u32 txdp;
1342 txdp = readl(dev->base + TXDP);
1343 dprintk("txdp: %08x\n", txdp);
1344 txdp -= dev->tx_phy_descs;
1345 dev->tx_idx = txdp / (DESC_SIZE * 4);
1346 if (dev->tx_idx >= NR_TX_DESC) {
1347 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1348 dev->tx_idx = 0;
1349 }
1350 /* The may have been a race between a pci originated read
1351 * and the descriptor update from the cpu. Just in case,
1352 * kick the transmitter if the hardware thinks it is on a
1353 * different descriptor than we are.
1354 */
1355 if (dev->tx_idx != dev->tx_free_idx)
1356 kick_tx(dev);
1357 }
1358
1359 /* Defer tx ring processing until more than a minimum amount of
1360 * work has accumulated
1361 */
1362 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1363 spin_lock_irqsave(&dev->tx_lock, flags);
1364 do_tx_done(ndev);
1365 spin_unlock_irqrestore(&dev->tx_lock, flags);
1366
1367 /* Disable TxOk if there are no outstanding tx packets.
1368 */
1369 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1370 (dev->IMR_cache & ISR_TXOK)) {
1371 spin_lock_irqsave(&dev->misc_lock, flags);
1372 dev->IMR_cache &= ~ISR_TXOK;
1373 writel(dev->IMR_cache, dev->base + IMR);
1374 spin_unlock_irqrestore(&dev->misc_lock, flags);
1375 }
1376 }
1377
1378 /* The TxIdle interrupt can come in before the transmit has
1379 * completed. Normally we reap packets off of the combination
1380 * of TxDesc and TxIdle and leave TxOk disabled (since it
1381 * occurs on every packet), but when no further irqs of this
1382 * nature are expected, we must enable TxOk.
1383 */
1384 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1385 spin_lock_irqsave(&dev->misc_lock, flags);
1386 dev->IMR_cache |= ISR_TXOK;
1387 writel(dev->IMR_cache, dev->base + IMR);
1388 spin_unlock_irqrestore(&dev->misc_lock, flags);
1389 }
1390
1391 /* MIB interrupt: one of the statistics counters is about to overflow */
1392 if (unlikely(ISR_MIB & isr))
1393 ns83820_mib_isr(dev);
1394
1395 /* PHY: Link up/down/negotiation state change */
1396 if (unlikely(ISR_PHY & isr))
1397 phy_intr(ndev);
1398
1399 #if 0 /* Still working on the interrupt mitigation strategy */
1400 if (dev->ihr)
1401 writel(dev->ihr, dev->base + IHR);
1402 #endif
1403 }
1404
1405 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1406 {
1407 Dprintk("resetting chip...\n");
1408 writel(which, dev->base + CR);
1409 do {
1410 schedule();
1411 } while (readl(dev->base + CR) & which);
1412 Dprintk("okay!\n");
1413 }
1414
1415 static int ns83820_stop(struct net_device *ndev)
1416 {
1417 struct ns83820 *dev = PRIV(ndev);
1418
1419 /* FIXME: protect against interrupt handler? */
1420 del_timer_sync(&dev->tx_watchdog);
1421
1422 /* disable interrupts */
1423 writel(0, dev->base + IMR);
1424 writel(0, dev->base + IER);
1425 readl(dev->base + IER);
1426
1427 dev->rx_info.up = 0;
1428 synchronize_irq(dev->pci_dev->irq);
1429
1430 ns83820_do_reset(dev, CR_RST);
1431
1432 synchronize_irq(dev->pci_dev->irq);
1433
1434 spin_lock_irq(&dev->misc_lock);
1435 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1436 spin_unlock_irq(&dev->misc_lock);
1437
1438 ns83820_cleanup_rx(dev);
1439 ns83820_cleanup_tx(dev);
1440
1441 return 0;
1442 }
1443
1444 static void ns83820_tx_timeout(struct net_device *ndev)
1445 {
1446 struct ns83820 *dev = PRIV(ndev);
1447 u32 tx_done_idx;
1448 __le32 *desc;
1449 unsigned long flags;
1450
1451 spin_lock_irqsave(&dev->tx_lock, flags);
1452
1453 tx_done_idx = dev->tx_done_idx;
1454 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1455
1456 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1457 ndev->name,
1458 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1459
1460 #if defined(DEBUG)
1461 {
1462 u32 isr;
1463 isr = readl(dev->base + ISR);
1464 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1465 ns83820_do_isr(ndev, isr);
1466 }
1467 #endif
1468
1469 do_tx_done(ndev);
1470
1471 tx_done_idx = dev->tx_done_idx;
1472 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1473
1474 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1475 ndev->name,
1476 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1477
1478 spin_unlock_irqrestore(&dev->tx_lock, flags);
1479 }
1480
1481 static void ns83820_tx_watch(unsigned long data)
1482 {
1483 struct net_device *ndev = (void *)data;
1484 struct ns83820 *dev = PRIV(ndev);
1485
1486 #if defined(DEBUG)
1487 printk("ns83820_tx_watch: %u %u %d\n",
1488 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1489 );
1490 #endif
1491
1492 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1493 dev->tx_done_idx != dev->tx_free_idx) {
1494 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1495 ndev->name,
1496 dev->tx_done_idx, dev->tx_free_idx,
1497 atomic_read(&dev->nr_tx_skbs));
1498 ns83820_tx_timeout(ndev);
1499 }
1500
1501 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1502 }
1503
1504 static int ns83820_open(struct net_device *ndev)
1505 {
1506 struct ns83820 *dev = PRIV(ndev);
1507 unsigned i;
1508 u32 desc;
1509 int ret;
1510
1511 dprintk("ns83820_open\n");
1512
1513 writel(0, dev->base + PQCR);
1514
1515 ret = ns83820_setup_rx(ndev);
1516 if (ret)
1517 goto failed;
1518
1519 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1520 for (i=0; i<NR_TX_DESC; i++) {
1521 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1522 = cpu_to_le32(
1523 dev->tx_phy_descs
1524 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1525 }
1526
1527 dev->tx_idx = 0;
1528 dev->tx_done_idx = 0;
1529 desc = dev->tx_phy_descs;
1530 writel(0, dev->base + TXDP_HI);
1531 writel(desc, dev->base + TXDP);
1532
1533 init_timer(&dev->tx_watchdog);
1534 dev->tx_watchdog.data = (unsigned long)ndev;
1535 dev->tx_watchdog.function = ns83820_tx_watch;
1536 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1537
1538 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1539
1540 return 0;
1541
1542 failed:
1543 ns83820_stop(ndev);
1544 return ret;
1545 }
1546
1547 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1548 {
1549 unsigned i;
1550 for (i=0; i<3; i++) {
1551 u32 data;
1552
1553 /* Read from the perfect match memory: this is loaded by
1554 * the chip from the EEPROM via the EELOAD self test.
1555 */
1556 writel(i*2, dev->base + RFCR);
1557 data = readl(dev->base + RFDR);
1558
1559 *mac++ = data;
1560 *mac++ = data >> 8;
1561 }
1562 }
1563
1564 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1565 {
1566 if (new_mtu > RX_BUF_SIZE)
1567 return -EINVAL;
1568 ndev->mtu = new_mtu;
1569 return 0;
1570 }
1571
1572 static void ns83820_set_multicast(struct net_device *ndev)
1573 {
1574 struct ns83820 *dev = PRIV(ndev);
1575 u8 __iomem *rfcr = dev->base + RFCR;
1576 u32 and_mask = 0xffffffff;
1577 u32 or_mask = 0;
1578 u32 val;
1579
1580 if (ndev->flags & IFF_PROMISC)
1581 or_mask |= RFCR_AAU | RFCR_AAM;
1582 else
1583 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1584
1585 if (ndev->flags & IFF_ALLMULTI || ndev->mc_count)
1586 or_mask |= RFCR_AAM;
1587 else
1588 and_mask &= ~RFCR_AAM;
1589
1590 spin_lock_irq(&dev->misc_lock);
1591 val = (readl(rfcr) & and_mask) | or_mask;
1592 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1593 writel(val & ~RFCR_RFEN, rfcr);
1594 writel(val, rfcr);
1595 spin_unlock_irq(&dev->misc_lock);
1596 }
1597
1598 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1599 {
1600 struct ns83820 *dev = PRIV(ndev);
1601 int timed_out = 0;
1602 unsigned long start;
1603 u32 status;
1604 int loops = 0;
1605
1606 dprintk("%s: start %s\n", ndev->name, name);
1607
1608 start = jiffies;
1609
1610 writel(enable, dev->base + PTSCR);
1611 for (;;) {
1612 loops++;
1613 status = readl(dev->base + PTSCR);
1614 if (!(status & enable))
1615 break;
1616 if (status & done)
1617 break;
1618 if (status & fail)
1619 break;
1620 if (time_after_eq(jiffies, start + HZ)) {
1621 timed_out = 1;
1622 break;
1623 }
1624 schedule_timeout_uninterruptible(1);
1625 }
1626
1627 if (status & fail)
1628 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1629 ndev->name, name, status, fail);
1630 else if (timed_out)
1631 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1632 ndev->name, name, status);
1633
1634 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1635 }
1636
1637 #ifdef PHY_CODE_IS_FINISHED
1638 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1639 {
1640 /* drive MDC low */
1641 dev->MEAR_cache &= ~MEAR_MDC;
1642 writel(dev->MEAR_cache, dev->base + MEAR);
1643 readl(dev->base + MEAR);
1644
1645 /* enable output, set bit */
1646 dev->MEAR_cache |= MEAR_MDDIR;
1647 if (bit)
1648 dev->MEAR_cache |= MEAR_MDIO;
1649 else
1650 dev->MEAR_cache &= ~MEAR_MDIO;
1651
1652 /* set the output bit */
1653 writel(dev->MEAR_cache, dev->base + MEAR);
1654 readl(dev->base + MEAR);
1655
1656 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1657 udelay(1);
1658
1659 /* drive MDC high causing the data bit to be latched */
1660 dev->MEAR_cache |= MEAR_MDC;
1661 writel(dev->MEAR_cache, dev->base + MEAR);
1662 readl(dev->base + MEAR);
1663
1664 /* Wait again... */
1665 udelay(1);
1666 }
1667
1668 static int ns83820_mii_read_bit(struct ns83820 *dev)
1669 {
1670 int bit;
1671
1672 /* drive MDC low, disable output */
1673 dev->MEAR_cache &= ~MEAR_MDC;
1674 dev->MEAR_cache &= ~MEAR_MDDIR;
1675 writel(dev->MEAR_cache, dev->base + MEAR);
1676 readl(dev->base + MEAR);
1677
1678 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1679 udelay(1);
1680
1681 /* drive MDC high causing the data bit to be latched */
1682 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1683 dev->MEAR_cache |= MEAR_MDC;
1684 writel(dev->MEAR_cache, dev->base + MEAR);
1685
1686 /* Wait again... */
1687 udelay(1);
1688
1689 return bit;
1690 }
1691
1692 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1693 {
1694 unsigned data = 0;
1695 int i;
1696
1697 /* read some garbage so that we eventually sync up */
1698 for (i=0; i<64; i++)
1699 ns83820_mii_read_bit(dev);
1700
1701 ns83820_mii_write_bit(dev, 0); /* start */
1702 ns83820_mii_write_bit(dev, 1);
1703 ns83820_mii_write_bit(dev, 1); /* opcode read */
1704 ns83820_mii_write_bit(dev, 0);
1705
1706 /* write out the phy address: 5 bits, msb first */
1707 for (i=0; i<5; i++)
1708 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1709
1710 /* write out the register address, 5 bits, msb first */
1711 for (i=0; i<5; i++)
1712 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1713
1714 ns83820_mii_read_bit(dev); /* turn around cycles */
1715 ns83820_mii_read_bit(dev);
1716
1717 /* read in the register data, 16 bits msb first */
1718 for (i=0; i<16; i++) {
1719 data <<= 1;
1720 data |= ns83820_mii_read_bit(dev);
1721 }
1722
1723 return data;
1724 }
1725
1726 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1727 {
1728 int i;
1729
1730 /* read some garbage so that we eventually sync up */
1731 for (i=0; i<64; i++)
1732 ns83820_mii_read_bit(dev);
1733
1734 ns83820_mii_write_bit(dev, 0); /* start */
1735 ns83820_mii_write_bit(dev, 1);
1736 ns83820_mii_write_bit(dev, 0); /* opcode read */
1737 ns83820_mii_write_bit(dev, 1);
1738
1739 /* write out the phy address: 5 bits, msb first */
1740 for (i=0; i<5; i++)
1741 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1742
1743 /* write out the register address, 5 bits, msb first */
1744 for (i=0; i<5; i++)
1745 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1746
1747 ns83820_mii_read_bit(dev); /* turn around cycles */
1748 ns83820_mii_read_bit(dev);
1749
1750 /* read in the register data, 16 bits msb first */
1751 for (i=0; i<16; i++)
1752 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1753
1754 return data;
1755 }
1756
1757 static void ns83820_probe_phy(struct net_device *ndev)
1758 {
1759 struct ns83820 *dev = PRIV(ndev);
1760 static int first;
1761 int i;
1762 #define MII_PHYIDR1 0x02
1763 #define MII_PHYIDR2 0x03
1764
1765 #if 0
1766 if (!first) {
1767 unsigned tmp;
1768 ns83820_mii_read_reg(dev, 1, 0x09);
1769 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1770
1771 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1772 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1773 udelay(1300);
1774 ns83820_mii_read_reg(dev, 1, 0x09);
1775 }
1776 #endif
1777 first = 1;
1778
1779 for (i=1; i<2; i++) {
1780 int j;
1781 unsigned a, b;
1782 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1783 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1784
1785 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1786 // ndev->name, i, a, b);
1787
1788 for (j=0; j<0x16; j+=4) {
1789 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1790 ndev->name, j,
1791 ns83820_mii_read_reg(dev, i, 0 + j),
1792 ns83820_mii_read_reg(dev, i, 1 + j),
1793 ns83820_mii_read_reg(dev, i, 2 + j),
1794 ns83820_mii_read_reg(dev, i, 3 + j)
1795 );
1796 }
1797 }
1798 {
1799 unsigned a, b;
1800 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1801 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1802 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1803 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1804
1805 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1806 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1807 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1808 dprintk("version: 0x%04x 0x%04x\n", a, b);
1809 }
1810 }
1811 #endif
1812
1813 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1814 {
1815 struct net_device *ndev;
1816 struct ns83820 *dev;
1817 long addr;
1818 int err;
1819 int using_dac = 0;
1820
1821 /* See if we can set the dma mask early on; failure is fatal. */
1822 if (sizeof(dma_addr_t) == 8 &&
1823 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1824 using_dac = 1;
1825 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1826 using_dac = 0;
1827 } else {
1828 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1829 return -ENODEV;
1830 }
1831
1832 ndev = alloc_etherdev(sizeof(struct ns83820));
1833 dev = PRIV(ndev);
1834
1835 err = -ENOMEM;
1836 if (!dev)
1837 goto out;
1838
1839 dev->ndev = ndev;
1840
1841 spin_lock_init(&dev->rx_info.lock);
1842 spin_lock_init(&dev->tx_lock);
1843 spin_lock_init(&dev->misc_lock);
1844 dev->pci_dev = pci_dev;
1845
1846 SET_MODULE_OWNER(ndev);
1847 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1848
1849 INIT_WORK(&dev->tq_refill, queue_refill);
1850 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1851
1852 err = pci_enable_device(pci_dev);
1853 if (err) {
1854 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1855 goto out_free;
1856 }
1857
1858 pci_set_master(pci_dev);
1859 addr = pci_resource_start(pci_dev, 1);
1860 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1861 dev->tx_descs = pci_alloc_consistent(pci_dev,
1862 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1863 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1864 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1865 err = -ENOMEM;
1866 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1867 goto out_disable;
1868
1869 dprintk("%p: %08lx %p: %08lx\n",
1870 dev->tx_descs, (long)dev->tx_phy_descs,
1871 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1872
1873 /* disable interrupts */
1874 writel(0, dev->base + IMR);
1875 writel(0, dev->base + IER);
1876 readl(dev->base + IER);
1877
1878 dev->IMR_cache = 0;
1879
1880 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1881 DRV_NAME, ndev);
1882 if (err) {
1883 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1884 pci_dev->irq, err);
1885 goto out_disable;
1886 }
1887
1888 /*
1889 * FIXME: we are holding rtnl_lock() over obscenely long area only
1890 * because some of the setup code uses dev->name. It's Wrong(tm) -
1891 * we should be using driver-specific names for all that stuff.
1892 * For now that will do, but we really need to come back and kill
1893 * most of the dev_alloc_name() users later.
1894 */
1895 rtnl_lock();
1896 err = dev_alloc_name(ndev, ndev->name);
1897 if (err < 0) {
1898 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1899 goto out_free_irq;
1900 }
1901
1902 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1903 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1904 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1905
1906 ndev->open = ns83820_open;
1907 ndev->stop = ns83820_stop;
1908 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1909 ndev->get_stats = ns83820_get_stats;
1910 ndev->change_mtu = ns83820_change_mtu;
1911 ndev->set_multicast_list = ns83820_set_multicast;
1912 SET_ETHTOOL_OPS(ndev, &ops);
1913 ndev->tx_timeout = ns83820_tx_timeout;
1914 ndev->watchdog_timeo = 5 * HZ;
1915 pci_set_drvdata(pci_dev, ndev);
1916
1917 ns83820_do_reset(dev, CR_RST);
1918
1919 /* Must reset the ram bist before running it */
1920 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1921 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1922 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1923 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1924 PTSCR_EEBIST_FAIL);
1925 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1926
1927 /* I love config registers */
1928 dev->CFG_cache = readl(dev->base + CFG);
1929
1930 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1931 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1932 ndev->name);
1933 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1934 if (!(dev->CFG_cache & CFG_DATA64_EN))
1935 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1936 ndev->name);
1937 } else
1938 dev->CFG_cache &= ~(CFG_DATA64_EN);
1939
1940 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1941 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1942 CFG_M64ADDR);
1943 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1944 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1945 dev->CFG_cache |= CFG_REQALG;
1946 dev->CFG_cache |= CFG_POW;
1947 dev->CFG_cache |= CFG_TMRTEST;
1948
1949 /* When compiled with 64 bit addressing, we must always enable
1950 * the 64 bit descriptor format.
1951 */
1952 if (sizeof(dma_addr_t) == 8)
1953 dev->CFG_cache |= CFG_M64ADDR;
1954 if (using_dac)
1955 dev->CFG_cache |= CFG_T64ADDR;
1956
1957 /* Big endian mode does not seem to do what the docs suggest */
1958 dev->CFG_cache &= ~CFG_BEM;
1959
1960 /* setup optical transceiver if we have one */
1961 if (dev->CFG_cache & CFG_TBI_EN) {
1962 printk(KERN_INFO "%s: enabling optical transceiver\n",
1963 ndev->name);
1964 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1965
1966 /* setup auto negotiation feature advertisement */
1967 writel(readl(dev->base + TANAR)
1968 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1969 dev->base + TANAR);
1970
1971 /* start auto negotiation */
1972 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1973 dev->base + TBICR);
1974 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1975 dev->linkstate = LINK_AUTONEGOTIATE;
1976
1977 dev->CFG_cache |= CFG_MODE_1000;
1978 }
1979
1980 writel(dev->CFG_cache, dev->base + CFG);
1981 dprintk("CFG: %08x\n", dev->CFG_cache);
1982
1983 if (reset_phy) {
1984 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1985 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1986 msleep(10);
1987 writel(dev->CFG_cache, dev->base + CFG);
1988 }
1989
1990 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1991 * the PCI layer. FIXME.
1992 */
1993 if (readl(dev->base + SRR))
1994 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
1995 #endif
1996
1997 /* Note! The DMA burst size interacts with packet
1998 * transmission, such that the largest packet that
1999 * can be transmitted is 8192 - FLTH - burst size.
2000 * If only the transmit fifo was larger...
2001 */
2002 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2003 * some DELL and COMPAQ SMP systems */
2004 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2005 | ((1600 / 32) * 0x100),
2006 dev->base + TXCFG);
2007
2008 /* Flush the interrupt holdoff timer */
2009 writel(0x000, dev->base + IHR);
2010 writel(0x100, dev->base + IHR);
2011 writel(0x000, dev->base + IHR);
2012
2013 /* Set Rx to full duplex, don't accept runt, errored, long or length
2014 * range errored packets. Use 512 byte DMA.
2015 */
2016 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2017 * some DELL and COMPAQ SMP systems
2018 * Turn on ALP, only we are accpeting Jumbo Packets */
2019 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2020 | RXCFG_STRIPCRC
2021 //| RXCFG_ALP
2022 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2023
2024 /* Disable priority queueing */
2025 writel(0, dev->base + PQCR);
2026
2027 /* Enable IP checksum validation and detetion of VLAN headers.
2028 * Note: do not set the reject options as at least the 0x102
2029 * revision of the chip does not properly accept IP fragments
2030 * at least for UDP.
2031 */
2032 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2033 * the MAC it calculates the packetsize AFTER stripping the VLAN
2034 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2035 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2036 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2037 * it discrards it!. These guys......
2038 * also turn on tag stripping if hardware acceleration is enabled
2039 */
2040 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2041 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2042 #else
2043 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2044 #endif
2045 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2046
2047 /* Enable per-packet TCP/UDP/IP checksumming
2048 * and per packet vlan tag insertion if
2049 * vlan hardware acceleration is enabled
2050 */
2051 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2052 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2053 #else
2054 #define VTCR_INIT_VALUE VTCR_PPCHK
2055 #endif
2056 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2057
2058 /* Ramit : Enable async and sync pause frames */
2059 /* writel(0, dev->base + PCR); */
2060 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2061 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2062 dev->base + PCR);
2063
2064 /* Disable Wake On Lan */
2065 writel(0, dev->base + WCSR);
2066
2067 ns83820_getmac(dev, ndev->dev_addr);
2068
2069 /* Yes, we support dumb IP checksum on transmit */
2070 ndev->features |= NETIF_F_SG;
2071 ndev->features |= NETIF_F_IP_CSUM;
2072
2073 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2074 /* We also support hardware vlan acceleration */
2075 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2076 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2077 #endif
2078
2079 if (using_dac) {
2080 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2081 ndev->name);
2082 ndev->features |= NETIF_F_HIGHDMA;
2083 }
2084
2085 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2086 ndev->name,
2087 (unsigned)readl(dev->base + SRR) >> 8,
2088 (unsigned)readl(dev->base + SRR) & 0xff,
2089 ndev->dev_addr[0], ndev->dev_addr[1],
2090 ndev->dev_addr[2], ndev->dev_addr[3],
2091 ndev->dev_addr[4], ndev->dev_addr[5],
2092 addr, pci_dev->irq,
2093 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2094 );
2095
2096 #ifdef PHY_CODE_IS_FINISHED
2097 ns83820_probe_phy(ndev);
2098 #endif
2099
2100 err = register_netdevice(ndev);
2101 if (err) {
2102 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2103 goto out_cleanup;
2104 }
2105 rtnl_unlock();
2106
2107 return 0;
2108
2109 out_cleanup:
2110 writel(0, dev->base + IMR); /* paranoia */
2111 writel(0, dev->base + IER);
2112 readl(dev->base + IER);
2113 out_free_irq:
2114 rtnl_unlock();
2115 free_irq(pci_dev->irq, ndev);
2116 out_disable:
2117 if (dev->base)
2118 iounmap(dev->base);
2119 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2120 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2121 pci_disable_device(pci_dev);
2122 out_free:
2123 free_netdev(ndev);
2124 pci_set_drvdata(pci_dev, NULL);
2125 out:
2126 return err;
2127 }
2128
2129 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2130 {
2131 struct net_device *ndev = pci_get_drvdata(pci_dev);
2132 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2133
2134 if (!ndev) /* paranoia */
2135 return;
2136
2137 writel(0, dev->base + IMR); /* paranoia */
2138 writel(0, dev->base + IER);
2139 readl(dev->base + IER);
2140
2141 unregister_netdev(ndev);
2142 free_irq(dev->pci_dev->irq, ndev);
2143 iounmap(dev->base);
2144 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2145 dev->tx_descs, dev->tx_phy_descs);
2146 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2147 dev->rx_info.descs, dev->rx_info.phy_descs);
2148 pci_disable_device(dev->pci_dev);
2149 free_netdev(ndev);
2150 pci_set_drvdata(pci_dev, NULL);
2151 }
2152
2153 static struct pci_device_id ns83820_pci_tbl[] = {
2154 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2155 { 0, },
2156 };
2157
2158 static struct pci_driver driver = {
2159 .name = "ns83820",
2160 .id_table = ns83820_pci_tbl,
2161 .probe = ns83820_init_one,
2162 .remove = __devexit_p(ns83820_remove_one),
2163 #if 0 /* FIXME: implement */
2164 .suspend = ,
2165 .resume = ,
2166 #endif
2167 };
2168
2169
2170 static int __init ns83820_init(void)
2171 {
2172 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2173 return pci_register_driver(&driver);
2174 }
2175
2176 static void __exit ns83820_exit(void)
2177 {
2178 pci_unregister_driver(&driver);
2179 }
2180
2181 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2182 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2183 MODULE_LICENSE("GPL");
2184
2185 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2186
2187 module_param(lnksts, int, 0);
2188 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2189
2190 module_param(ihr, int, 0);
2191 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2192
2193 module_param(reset_phy, int, 0);
2194 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2195
2196 module_init(ns83820_init);
2197 module_exit(ns83820_exit);
Stable & featurefull patchset based on Linus's git branch