2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
3 * Communications, Inc. All rights reserved.
5 * Redistribution and use in source and binary forms are permitted
6 * provided that the following conditions are met:
7 * 1. The materials contained herein are unmodified and are used
9 * 2. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following NO
11 * ''WARRANTY'' disclaimer below (''Disclaimer''), without
13 * 3. Redistributions in binary form must reproduce at minimum a
14 * disclaimer similar to the Disclaimer below and any redistribution
15 * must be conditioned upon including a substantially similar
16 * Disclaimer requirement for further binary redistribution.
17 * 4. Neither the names of the above-listed copyright holders nor the
18 * names of any contributors may be used to endorse or promote
19 * product derived from this software without specific prior written
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
26 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
28 * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * $Id: ah.h 2863 2007-11-20 17:02:12Z proski $
42 * Atheros Hardware Access Layer
44 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
45 * structure for use with the device. Hardware-related operations that
46 * follow must call back into the HAL through interface, supplying the
47 * reference as the first parameter.
51 * Bus i/o type definitions. We define a platform-independent
52 * set of types that are mapped to platform-dependent data for
53 * register read/write operations. We use types that are large
54 * enough to hold a pointer; smaller data should fit and only
55 * require type coercion to work. Larger data can be stored
56 * elsewhere and a reference passed for the bus tag and/or handle.
58 typedef void* HAL_SOFTC
; /* pointer to driver/OS state */
59 typedef void* HAL_BUS_TAG
; /* opaque bus i/o id tag */
60 typedef void* HAL_BUS_HANDLE
; /* opaque bus i/o handle */
65 * __ahdecl is analogous to _cdecl; it defines the calling
66 * convention used within the HAL. For most systems this
67 * can just default to be empty and the compiler will (should)
68 * use _cdecl. For systems where _cdecl is not compatible this
69 * must be defined. See linux/ah_osdep.h for an example.
76 * Status codes that may be returned by the HAL. Note that
77 * interfaces that return a status code set it only when an
78 * error occurs--i.e. you cannot check it for success.
81 HAL_OK
= 0, /* No error */
82 HAL_ENXIO
= 1, /* No hardware present */
83 HAL_ENOMEM
= 2, /* Memory allocation failed */
84 HAL_EIO
= 3, /* Hardware didn't respond as expected */
85 HAL_EEMAGIC
= 4, /* EEPROM magic number invalid */
86 HAL_EEVERSION
= 5, /* EEPROM version invalid */
87 HAL_EELOCKED
= 6, /* EEPROM unreadable */
88 HAL_EEBADSUM
= 7, /* EEPROM checksum invalid */
89 HAL_EEREAD
= 8, /* EEPROM read problem */
90 HAL_EEBADMAC
= 9, /* EEPROM mac address invalid */
91 HAL_EESIZE
= 10, /* EEPROM size not supported */
92 HAL_EEWRITE
= 11, /* Attempt to change write-locked EEPROM */
93 HAL_EINVAL
= 12, /* Invalid parameter to function */
94 HAL_ENOTSUPP
= 13, /* Hardware revision not supported */
95 HAL_ESELFTEST
= 14, /* Hardware self-test failed */
96 HAL_EINPROGRESS
= 15, /* Operation incomplete */
100 AH_FALSE
= 0, /* NB: lots of code assumes false is zero */
105 HAL_CAP_REG_DMN
= 0, /* current regulatory domain */
106 HAL_CAP_CIPHER
= 1, /* hardware supports cipher */
107 HAL_CAP_TKIP_MIC
= 2, /* handle TKIP MIC in hardware */
108 HAL_CAP_TKIP_SPLIT
= 3, /* hardware TKIP uses split keys */
109 HAL_CAP_PHYCOUNTERS
= 4, /* hardware PHY error counters */
110 HAL_CAP_DIVERSITY
= 5, /* hardware supports fast diversity */
111 HAL_CAP_KEYCACHE_SIZE
= 6, /* number of entries in key cache */
112 HAL_CAP_NUM_TXQUEUES
= 7, /* number of hardware xmit queues */
113 HAL_CAP_VEOL
= 9, /* hardware supports virtual EOL */
114 HAL_CAP_PSPOLL
= 10, /* hardware has working PS-Poll support */
115 HAL_CAP_DIAG
= 11, /* hardware diagnostic support */
116 HAL_CAP_COMPRESSION
= 12, /* hardware supports compression */
117 HAL_CAP_BURST
= 13, /* hardware supports packet bursting */
118 HAL_CAP_FASTFRAME
= 14, /* hardware supoprts fast frames */
119 HAL_CAP_TXPOW
= 15, /* global tx power limit */
120 HAL_CAP_TPC
= 16, /* per-packet tx power control */
121 HAL_CAP_PHYDIAG
= 17, /* hardware phy error diagnostic */
122 HAL_CAP_BSSIDMASK
= 18, /* hardware supports bssid mask */
123 HAL_CAP_MCAST_KEYSRCH
= 19, /* hardware has multicast key search */
124 HAL_CAP_TSF_ADJUST
= 20, /* hardware has beacon tsf adjust */
125 HAL_CAP_XR
= 21, /* hardware has XR support */
126 HAL_CAP_WME_TKIPMIC
= 22, /* hardware can support TKIP MIC when WMM is turned on */
127 HAL_CAP_CHAN_HALFRATE
= 23, /* hardware can support half rate channels */
128 HAL_CAP_CHAN_QUARTERRATE
= 24, /* hardware can support quarter rate channels */
129 HAL_CAP_RFSILENT
= 25, /* hardware has rfsilent support */
130 HAL_CAP_TPC_ACK
= 26, /* ack txpower with per-packet tpc */
131 HAL_CAP_TPC_CTS
= 27, /* cts txpower with per-packet tpc */
132 HAL_CAP_11D
= 28, /* 11d beacon support for changing cc */
133 HAL_CAP_INTMIT
= 29, /* interference mitigation */
134 HAL_CAP_RXORN_FATAL
= 30, /* HAL_INT_RXORN treated as fatal */
135 HAL_CAP_HT
= 31, /* hardware can support HT */
136 HAL_CAP_NUMTXCHAIN
= 32, /* # TX chains supported */
137 HAL_CAP_NUMRXCHAIN
= 33, /* # RX chains supported */
138 HAL_CAP_RXTSTAMP_PREC
= 34, /* rx desc tstamp precision (bits) */
139 } HAL_CAPABILITY_TYPE
;
142 * "States" for setting the LED. These correspond to
143 * the possible 802.11 operational states and there may
144 * be a many-to-one mapping between these states and the
145 * actual hardware state for the LED's (i.e. the hardware
146 * may have fewer states).
157 * Transmit queue types/numbers. These are used to tag
158 * each transmit queue in the hardware and to identify a set
159 * of transmit queues for operations such as start/stop dma.
162 HAL_TX_QUEUE_INACTIVE
= 0, /* queue is inactive/unused */
163 HAL_TX_QUEUE_DATA
= 1, /* data xmit q's */
164 HAL_TX_QUEUE_BEACON
= 2, /* beacon xmit q */
165 HAL_TX_QUEUE_CAB
= 3, /* "crap after beacon" xmit q */
166 HAL_TX_QUEUE_UAPSD
= 4, /* u-apsd power save xmit q */
169 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
172 * Transmit queue subtype. These map directly to
173 * WME Access Categories (except for UPSD). Refer
174 * to Table 5 of the WME spec.
177 HAL_WME_AC_BK
= 0, /* background access category */
178 HAL_WME_AC_BE
= 1, /* best effort access category*/
179 HAL_WME_AC_VI
= 2, /* video access category */
180 HAL_WME_AC_VO
= 3, /* voice access category */
181 HAL_WME_UPSD
= 4, /* uplink power save */
182 HAL_XR_DATA
= 5, /* uplink power save */
183 } HAL_TX_QUEUE_SUBTYPE
;
186 * Transmit queue flags that control various
187 * operational parameters.
191 * Per queue interrupt enables. When set the associated
192 * interrupt may be delivered for packets sent through
193 * the queue. Without these enabled no interrupts will
194 * be delivered for transmits through the queue.
196 HAL_TXQ_TXOKINT_ENABLE
= 0x0001, /* enable TXOK interrupt */
197 HAL_TXQ_TXERRINT_ENABLE
= 0x0001, /* enable TXERR interrupt */
198 HAL_TXQ_TXDESCINT_ENABLE
= 0x0002, /* enable TXDESC interrupt */
199 HAL_TXQ_TXEOLINT_ENABLE
= 0x0004, /* enable TXEOL interrupt */
200 HAL_TXQ_TXURNINT_ENABLE
= 0x0008, /* enable TXURN interrupt */
202 * Enable hardware compression for packets sent through
203 * the queue. The compression buffer must be setup and
204 * packets must have a key entry marked in the tx descriptor.
206 HAL_TXQ_COMPRESSION_ENABLE
= 0x0010, /* enable h/w compression */
208 * Disable queue when veol is hit or ready time expires.
209 * By default the queue is disabled only on reaching the
210 * physical end of queue (i.e. a null link ptr in the
213 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE
= 0x0020,
215 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
216 * event. Frames will be transmitted only when this timer
217 * fires, e.g to transmit a beacon in ap or adhoc modes.
219 HAL_TXQ_DBA_GATED
= 0x0040, /* schedule based on DBA */
221 * Each transmit queue has a counter that is incremented
222 * each time the queue is enabled and decremented when
223 * the list of frames to transmit is traversed (or when
224 * the ready time for the queue expires). This counter
225 * must be non-zero for frames to be scheduled for
226 * transmission. The following controls disable bumping
227 * this counter under certain conditions. Typically this
228 * is used to gate frames based on the contents of another
229 * queue (e.g. CAB traffic may only follow a beacon frame).
230 * These are meaningful only when frames are scheduled
231 * with a non-ASAP policy (e.g. DBA-gated).
233 HAL_TXQ_CBR_DIS_QEMPTY
= 0x0080, /* disable on this q empty */
234 HAL_TXQ_CBR_DIS_BEMPTY
= 0x0100, /* disable on beacon q empty */
237 * Fragment burst backoff policy. Normally the no backoff
238 * is done after a successful transmission, the next fragment
239 * is sent at SIFS. If this flag is set backoff is done
240 * after each fragment, regardless whether it was ack'd or
241 * not, after the backoff count reaches zero a normal channel
242 * access procedure is done before the next transmit (i.e.
243 * wait AIFS instead of SIFS).
245 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE
= 0x00800000,
247 * Disable post-tx backoff following each frame.
249 HAL_TXQ_BACKOFF_DISABLE
= 0x00010000, /* disable post backoff */
251 * DCU arbiter lockout control. This controls how
252 * lower priority tx queues are handled with respect to
253 * to a specific queue when multiple queues have frames
254 * to send. No lockout means lower priority queues arbitrate
255 * concurrently with this queue. Intra-frame lockout
256 * means lower priority queues are locked out until the
257 * current frame transmits (e.g. including backoffs and bursting).
258 * Global lockout means nothing lower can arbitrary so
259 * long as there is traffic activity on this queue (frames,
262 HAL_TXQ_ARB_LOCKOUT_INTRA
= 0x00020000, /* intra-frame lockout */
263 HAL_TXQ_ARB_LOCKOUT_GLOBAL
= 0x00040000, /* full lockout s */
265 HAL_TXQ_IGNORE_VIRTCOL
= 0x00080000, /* ignore virt collisions */
266 HAL_TXQ_SEQNUM_INC_DIS
= 0x00100000, /* disable seqnum increment */
267 } HAL_TX_QUEUE_FLAGS
;
270 u_int32_t tqi_ver
; /* hal TXQ version */
271 HAL_TX_QUEUE_SUBTYPE tqi_subtype
; /* subtype if applicable */
272 HAL_TX_QUEUE_FLAGS tqi_qflags
; /* flags (see above) */
273 u_int32_t tqi_priority
; /* (not used) */
274 u_int32_t tqi_aifs
; /* aifs */
275 u_int32_t tqi_cwmin
; /* cwMin */
276 u_int32_t tqi_cwmax
; /* cwMax */
277 u_int16_t tqi_shretry
; /* rts retry limit */
278 u_int16_t tqi_lgretry
; /* long retry limit (not used)*/
279 u_int32_t tqi_cbrPeriod
; /* CBR period (us) */
280 u_int32_t tqi_cbrOverflowLimit
; /* threshold for CBROVF int */
281 u_int32_t tqi_burstTime
; /* max burst duration (us) */
282 u_int32_t tqi_readyTime
; /* frame schedule time (us) */
283 u_int32_t tqi_compBuf
; /* comp buffer phys addr */
286 #define HAL_TQI_NONVAL 0xffff
288 /* token to use for aifs, cwmin, cwmax */
289 #define HAL_TXQ_USEDEFAULT ((u_int32_t) -1)
291 /* compression definitions */
292 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
293 #define HAL_COMP_BUF_ALIGN_SIZE 512
296 * Transmit packet types. This belongs in ah_desc.h, but
297 * is here so we can give a proper type to various parameters
298 * (and not require everyone include the file).
300 * NB: These values are intentionally assigned for
301 * direct use when setting up h/w descriptors.
304 HAL_PKT_TYPE_NORMAL
= 0,
305 HAL_PKT_TYPE_ATIM
= 1,
306 HAL_PKT_TYPE_PSPOLL
= 2,
307 HAL_PKT_TYPE_BEACON
= 3,
308 HAL_PKT_TYPE_PROBE_RESP
= 4,
309 HAL_PKT_TYPE_CHIRP
= 5,
310 HAL_PKT_TYPE_GRP_POLL
= 6,
311 HAL_PKT_TYPE_AMPDU
= 7,
314 /* Rx Filter Frame Types */
316 HAL_RX_FILTER_UCAST
= 0x00000001, /* Allow unicast frames */
317 HAL_RX_FILTER_MCAST
= 0x00000002, /* Allow multicast frames */
318 HAL_RX_FILTER_BCAST
= 0x00000004, /* Allow broadcast frames */
319 HAL_RX_FILTER_CONTROL
= 0x00000008, /* Allow control frames */
320 HAL_RX_FILTER_BEACON
= 0x00000010, /* Allow beacon frames */
321 HAL_RX_FILTER_PROM
= 0x00000020, /* Promiscuous mode */
322 HAL_RX_FILTER_XRPOLL
= 0x00000040, /* Allow XR poll frmae */
323 HAL_RX_FILTER_PROBEREQ
= 0x00000080, /* Allow probe request frames */
324 HAL_RX_FILTER_PHYERR
= 0x00000100, /* Allow phy errors */
325 HAL_RX_FILTER_PHYRADAR
= 0x00000200, /* Allow phy radar errors*/
330 HAL_PM_FULL_SLEEP
= 1,
331 HAL_PM_NETWORK_SLEEP
= 2,
337 * These are mapped to take advantage of the common locations for many of
338 * the bits on all of the currently supported MAC chips. This is to make
339 * the ISR as efficient as possible, while still abstracting HW differences.
340 * When new hardware breaks this commonality this enumerated type, as well
341 * as the HAL functions using it, must be modified. All values are directly
342 * mapped unless commented otherwise.
345 HAL_INT_RX
= 0x00000001, /* Non-common mapping */
346 HAL_INT_RXDESC
= 0x00000002,
347 HAL_INT_RXNOFRM
= 0x00000008,
348 HAL_INT_RXEOL
= 0x00000010,
349 HAL_INT_RXORN
= 0x00000020,
350 HAL_INT_TX
= 0x00000040, /* Non-common mapping */
351 HAL_INT_TXDESC
= 0x00000080,
352 HAL_INT_TXURN
= 0x00000800,
353 HAL_INT_MIB
= 0x00001000,
354 HAL_INT_RXPHY
= 0x00004000,
355 HAL_INT_RXKCM
= 0x00008000,
356 HAL_INT_SWBA
= 0x00010000,
357 HAL_INT_BMISS
= 0x00040000,
358 HAL_INT_BNR
= 0x00100000, /* Non-common mapping */
359 HAL_INT_TIM
= 0x00200000, /* Non-common mapping */
360 HAL_INT_DTIM
= 0x00400000, /* Non-common mapping */
361 HAL_INT_DTIMSYNC
= 0x00800000, /* Non-common mapping */
362 HAL_INT_GPIO
= 0x01000000,
363 HAL_INT_CABEND
= 0x02000000, /* Non-common mapping */
364 HAL_INT_CST
= 0x10000000, /* Non-common mapping */
365 HAL_INT_GTT
= 0x20000000, /* Non-common mapping */
366 HAL_INT_FATAL
= 0x40000000, /* Non-common mapping */
367 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
368 HAL_INT_BMISC
= HAL_INT_TIM
373 /* Interrupt bits that map directly to ISR/IMR bits */
374 HAL_INT_COMMON
= HAL_INT_RXNOFRM
389 HAL_RFGAIN_INACTIVE
= 0,
390 HAL_RFGAIN_READ_REQUESTED
= 1,
391 HAL_RFGAIN_NEED_CHANGE
= 2
395 * Channels are specified by frequency.
398 u_int32_t channelFlags
; /* see below */
399 u_int16_t channel
; /* setting in MHz */
401 int8_t maxRegTxPower
; /* max regulatory tx power in dBm */
402 int8_t maxTxPower
; /* max true tx power in 0.5 dBm */
403 int8_t minTxPower
; /* min true tx power in 0.5 dBm */
407 #define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */
408 #define CHANNEL_TURBO 0x00010 /* Turbo Channel */
409 #define CHANNEL_CCK 0x00020 /* CCK channel */
410 #define CHANNEL_OFDM 0x00040 /* OFDM channel */
411 #define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel */
412 #define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */
413 #define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */
414 #define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */
415 #define CHANNEL_XR 0x00800 /* XR channel */
416 #define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */
417 #define CHANNEL_HALF 0x04000 /* Half rate channel */
418 #define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */
419 #define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */
420 #define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ channel w/ ext chan above */
421 #define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ channel w/ ext chan below */
424 #define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference
425 used for as AR as well as RADAR
426 interference detection */
427 #define CHANNEL_DFS 0x02 /* DFS required on channel */
428 #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
429 #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
431 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
432 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
433 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
435 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN)
437 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
439 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
440 #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
441 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
442 #define CHANNEL_108A CHANNEL_T
443 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
444 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_OFDM | CHANNEL_HT20)
445 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_OFDM | CHANNEL_HT20)
446 #define CHANNEL_G_HT40PLUS (CHANNEL_G_HT20|CHANNEL_HT40PLUS)
447 #define CHANNEL_G_HT40MINUS (CHANNEL_G_HT20|CHANNEL_HT40MINUS)
448 #define CHANNEL_A_HT40PLUS (CHANNEL_A_HT20|CHANNEL_HT40PLUS)
449 #define CHANNEL_A_HT40MINUS (CHANNEL_A_HT20|CHANNEL_HT40MINUS)
450 #define CHANNEL_ALL \
451 (CHANNEL_OFDM | CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | \
452 CHANNEL_TURBO | CHANNEL_HT20 | CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)
453 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
455 #define HAL_ANTENNA_MIN_MODE 0
456 #define HAL_ANTENNA_FIXED_A 1
457 #define HAL_ANTENNA_FIXED_B 2
458 #define HAL_ANTENNA_MAX_MODE 3
461 u_int32_t ackrcv_bad
;
468 typedef u_int16_t HAL_CTRY_CODE
; /* country code */
469 typedef u_int16_t HAL_REG_DOMAIN
; /* regulatory domain code */
472 CTRY_DEBUG
= 0x1ff, /* debug country code */
473 CTRY_DEFAULT
= 0 /* default country code */
477 HAL_MODE_11A
= 0x001, /* 11a channels */
478 HAL_MODE_TURBO
= 0x002, /* 11a turbo-only channels */
479 HAL_MODE_11B
= 0x004, /* 11b channels */
480 HAL_MODE_PUREG
= 0x008, /* 11g channels (OFDM only) */
482 HAL_MODE_11G
= 0x010, /* 11g channels (OFDM/CCK) */
484 HAL_MODE_11G
= 0x008, /* XXX historical */
486 HAL_MODE_108G
= 0x020, /* 11a+Turbo channels */
487 HAL_MODE_108A
= 0x040, /* 11g+Turbo channels */
488 HAL_MODE_XR
= 0x100, /* XR channels */
489 HAL_MODE_11A_HALF_RATE
= 0x200, /* 11A half rate channels */
490 HAL_MODE_11A_QUARTER_RATE
= 0x400, /* 11A quarter rate channels */
491 HAL_MODE_11NG_HT20
= 0x8000,
492 HAL_MODE_11NA_HT20
= 0x10000,
493 HAL_MODE_11NG_HT40PLUS
= 0x20000,
494 HAL_MODE_11NG_HT40MINUS
= 0x40000,
495 HAL_MODE_11NA_HT40PLUS
= 0x80000,
496 HAL_MODE_11NA_HT40MINUS
= 0x100000,
501 int rateCount
; /* NB: for proper padding */
502 u_int8_t rateCodeToIndex
[32]; /* back mapping */
504 u_int8_t valid
; /* valid for rate control use */
505 u_int8_t phy
; /* CCK/OFDM/XR */
506 u_int32_t rateKbps
; /* transfer rate in kbs */
507 u_int8_t rateCode
; /* rate for h/w descriptors */
508 u_int8_t shortPreamble
; /* mask for enabling short
509 * preamble in CCK rate code */
510 u_int8_t dot11Rate
; /* value for supported rates
511 * info element of MLME */
512 u_int8_t controlRate
; /* index of next lower basic
513 * rate; used for dur. calcs */
514 u_int16_t lpAckDuration
; /* long preamble ACK duration */
515 u_int16_t spAckDuration
; /* short preamble ACK duration*/
520 u_int rs_count
; /* number of valid entries */
521 u_int8_t rs_rates
[32]; /* rates */
525 * 802.11n specific structures and enums
528 HAL_CHAINTYPE_TX
= 1, /* Tx chain type */
529 HAL_CHAINTYPE_RX
= 2, /* RX chain type */
538 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
539 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
540 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
541 } HAL_11N_RATE_SERIES
;
544 HAL_HT_MACMODE_20
= 0, /* 20 MHz operation */
545 HAL_HT_MACMODE_2040
= 1, /* 20/40 MHz operation */
549 HAL_HT_PHYMODE_20
= 0, /* 20 MHz operation */
550 HAL_HT_PHYMODE_2040
= 1, /* 20/40 MHz operation */
554 HAL_HT_EXTPROTSPACING_20
= 0, /* 20 MHz spacing */
555 HAL_HT_EXTPROTSPACING_25
= 1, /* 25 MHz spacing */
556 } HAL_HT_EXTPROTSPACING
;
560 HAL_RX_CLEAR_CTL_LOW
= 0x1, /* force control channel to appear busy */
561 HAL_RX_CLEAR_EXT_LOW
= 0x2, /* force extension channel to appear busy */
565 * Antenna switch control. By default antenna selection
566 * enables multiple (2) antenna use. To force use of the
567 * A or B antenna only specify a fixed setting. Fixing
568 * the antenna will also disable any diversity support.
571 HAL_ANT_VARIABLE
= 0, /* variable by programming */
572 HAL_ANT_FIXED_A
= 1, /* fixed antenna A */
573 HAL_ANT_FIXED_B
= 2, /* fixed antenna B */
577 HAL_M_STA
= 1, /* infrastructure station */
578 HAL_M_IBSS
= 0, /* IBSS (adhoc) station */
579 HAL_M_HOSTAP
= 6, /* Software Access Point */
580 HAL_M_MONITOR
= 8 /* Monitor mode */
584 u_int8_t kv_type
; /* one of HAL_CIPHER */
586 u_int16_t kv_len
; /* length in bits */
587 u_int8_t kv_val
[16]; /* enough for 128-bit keys */
588 u_int8_t kv_mic
[8]; /* TKIP MIC key */
589 u_int8_t kv_txmic
[8]; /* TKIP TX MIC key (optional) */
594 HAL_CIPHER_AES_OCB
= 1,
595 HAL_CIPHER_AES_CCM
= 2,
598 HAL_CIPHER_CLR
= 5, /* no encryption */
600 HAL_CIPHER_MIC
= 127 /* TKIP-MIC, not a cipher */
604 HAL_SLOT_TIME_6
= 6, /* NB: for turbo mode */
606 HAL_SLOT_TIME_20
= 20,
610 * Per-station beacon timer state. Note that the specified
611 * beacon interval (given in TU's) can also include flags
612 * to force a TSF reset and to enable the beacon xmit logic.
613 * If bs_cfpmaxduration is non-zero the hardware is setup to
614 * coexist with a PCF-capable AP.
617 u_int32_t bs_nexttbtt
; /* next beacon in TU */
618 u_int32_t bs_nextdtim
; /* next DTIM in TU */
619 u_int32_t bs_intval
; /* beacon interval+flags */
620 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
621 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
622 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
623 u_int32_t bs_dtimperiod
;
624 u_int16_t bs_cfpperiod
; /* CFP period in TU */
625 u_int16_t bs_cfpmaxduration
; /* max CFP duration in TU */
626 u_int32_t bs_cfpnext
; /* next CFP in TU */
627 u_int16_t bs_timoffset
; /* byte offset to TIM bitmap */
628 u_int16_t bs_bmissthreshold
; /* beacon miss threshold */
629 u_int32_t bs_sleepduration
; /* max sleep duration */
633 * Like HAL_BEACON_STATE but for non-station mode setup.
634 * NB: see above flag definitions for bt_intval.
637 u_int32_t bt_intval
; /* beacon interval+flags */
638 u_int32_t bt_nexttbtt
; /* next beacon in TU */
639 u_int32_t bt_nextatim
; /* next ATIM in TU */
640 u_int32_t bt_nextdba
; /* next DBA in 1/8th TU */
641 u_int32_t bt_nextswba
; /* next SWBA in 1/8th TU */
642 u_int32_t bt_flags
; /* timer enables */
643 #define HAL_BEACON_TBTT_EN 0x00000001
644 #define HAL_BEACON_DBA_EN 0x00000002
645 #define HAL_BEACON_SWBA_EN 0x00000004
649 * Per-node statistics maintained by the driver for use in
650 * optimizing signal quality and other operational aspects.
653 u_int32_t ns_avgbrssi
; /* average beacon rssi */
654 u_int32_t ns_avgrssi
; /* average data rssi */
655 u_int32_t ns_avgtxrssi
; /* average tx rssi */
658 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
661 struct ath_tx_status
;
662 struct ath_rx_status
;
665 * Hardware Access Layer (HAL) API.
667 * Clients of the HAL call ath_hal_attach to obtain a reference to an
668 * ath_hal structure for use with the device. Hardware-related operations
669 * that follow must call back into the HAL through interface, supplying
670 * the reference as the first parameter. Note that before using the
671 * reference returned by ath_hal_attach the caller should verify the
672 * ABI version number.
675 u_int32_t ah_magic
; /* consistency check magic number */
676 u_int32_t ah_abi
; /* HAL ABI version */
677 #define HAL_ABI_VERSION 0x07013100 /* YYMMDDnn */
678 u_int16_t ah_devid
; /* PCI device ID */
679 u_int16_t ah_subvendorid
; /* PCI subvendor ID */
680 HAL_SOFTC ah_sc
; /* back pointer to driver/os state */
681 HAL_BUS_TAG ah_st
; /* params for register r+w */
682 HAL_BUS_HANDLE ah_sh
;
683 HAL_CTRY_CODE ah_countryCode
;
685 u_int32_t ah_macVersion
; /* MAC version id */
686 u_int16_t ah_macRev
; /* MAC revision */
687 u_int16_t ah_phyRev
; /* PHY revision */
688 /* NB: when only one radio is present the rev is in 5Ghz */
689 u_int16_t ah_analog5GhzRev
;/* 5GHz radio revision */
690 u_int16_t ah_analog2GhzRev
;/* 2GHz radio revision */
692 const HAL_RATE_TABLE
*__ahdecl(*ah_getRateTable
)(struct ath_hal
*,
694 void __ahdecl(*ah_detach
)(struct ath_hal
*);
696 /* Reset functions */
697 HAL_BOOL
__ahdecl(*ah_reset
)(struct ath_hal
*, HAL_OPMODE
,
698 HAL_CHANNEL
*, HAL_BOOL bChannelChange
,
700 HAL_BOOL
__ahdecl(*ah_phyDisable
)(struct ath_hal
*);
701 HAL_BOOL
__ahdecl(*ah_disable
)(struct ath_hal
*);
702 void __ahdecl(*ah_setPCUConfig
)(struct ath_hal
*);
703 HAL_BOOL
__ahdecl(*ah_perCalibration
)(struct ath_hal
*, HAL_CHANNEL
*, HAL_BOOL
*);
704 HAL_BOOL
__ahdecl(*ah_setTxPowerLimit
)(struct ath_hal
*, u_int32_t
);
707 HAL_BOOL
__ahdecl(*ah_radarWait
)(struct ath_hal
*, HAL_CHANNEL
*);
709 /* Transmit functions */
710 HAL_BOOL
__ahdecl(*ah_updateTxTrigLevel
)(struct ath_hal
*,
711 HAL_BOOL incTrigLevel
);
712 int __ahdecl(*ah_setupTxQueue
)(struct ath_hal
*, HAL_TX_QUEUE
,
713 const HAL_TXQ_INFO
*qInfo
);
714 HAL_BOOL
__ahdecl(*ah_setTxQueueProps
)(struct ath_hal
*, int q
,
715 const HAL_TXQ_INFO
*qInfo
);
716 HAL_BOOL
__ahdecl(*ah_getTxQueueProps
)(struct ath_hal
*, int q
,
717 HAL_TXQ_INFO
*qInfo
);
718 HAL_BOOL
__ahdecl(*ah_releaseTxQueue
)(struct ath_hal
*ah
, u_int q
);
719 HAL_BOOL
__ahdecl(*ah_resetTxQueue
)(struct ath_hal
*ah
, u_int q
);
720 u_int32_t
__ahdecl(*ah_getTxDP
)(struct ath_hal
*, u_int
);
721 HAL_BOOL
__ahdecl(*ah_setTxDP
)(struct ath_hal
*, u_int
, u_int32_t txdp
);
722 u_int32_t
__ahdecl(*ah_numTxPending
)(struct ath_hal
*, u_int q
);
723 HAL_BOOL
__ahdecl(*ah_startTxDma
)(struct ath_hal
*, u_int
);
724 HAL_BOOL
__ahdecl(*ah_stopTxDma
)(struct ath_hal
*, u_int
);
725 HAL_BOOL
__ahdecl(*ah_setupTxDesc
)(struct ath_hal
*, struct ath_desc
*,
726 u_int pktLen
, u_int hdrLen
,
727 HAL_PKT_TYPE type
, u_int txPower
,
728 u_int txRate0
, u_int txTries0
,
729 u_int keyIx
, u_int antMode
, u_int flags
,
730 u_int rtsctsRate
, u_int rtsctsDuration
,
731 u_int compicvLen
, u_int compivLen
,
733 HAL_BOOL
__ahdecl(*ah_setupXTxDesc
)(struct ath_hal
*, struct ath_desc
*,
734 u_int txRate1
, u_int txTries1
,
735 u_int txRate2
, u_int txTries2
,
736 u_int txRate3
, u_int txTries3
);
737 HAL_BOOL
__ahdecl(*ah_fillTxDesc
)(struct ath_hal
*, struct ath_desc
*,
738 u_int segLen
, HAL_BOOL firstSeg
,
739 HAL_BOOL lastSeg
, const struct ath_desc
*);
740 HAL_STATUS
__ahdecl(*ah_procTxDesc
)(struct ath_hal
*,
741 struct ath_desc
*, struct ath_tx_status
*);
742 void __ahdecl(*ah_getTxIntrQueue
)(struct ath_hal
*, u_int32_t
*);
743 void __ahdecl(*ah_reqTxIntrDesc
)(struct ath_hal
*, struct ath_desc
*);
745 /* Receive Functions */
746 u_int32_t
__ahdecl(*ah_getRxDP
)(struct ath_hal
*);
747 void __ahdecl(*ah_setRxDP
)(struct ath_hal
*, u_int32_t rxdp
);
748 void __ahdecl(*ah_enableReceive
)(struct ath_hal
*);
749 HAL_BOOL
__ahdecl(*ah_stopDmaReceive
)(struct ath_hal
*);
750 void __ahdecl(*ah_startPcuReceive
)(struct ath_hal
*);
751 void __ahdecl(*ah_stopPcuReceive
)(struct ath_hal
*);
752 void __ahdecl(*ah_setMulticastFilter
)(struct ath_hal
*,
753 u_int32_t filter0
, u_int32_t filter1
);
754 HAL_BOOL
__ahdecl(*ah_setMulticastFilterIndex
)(struct ath_hal
*,
756 HAL_BOOL
__ahdecl(*ah_clrMulticastFilterIndex
)(struct ath_hal
*,
758 u_int32_t
__ahdecl(*ah_getRxFilter
)(struct ath_hal
*);
759 void __ahdecl(*ah_setRxFilter
)(struct ath_hal
*, u_int32_t
);
760 HAL_BOOL
__ahdecl(*ah_setupRxDesc
)(struct ath_hal
*, struct ath_desc
*,
761 u_int32_t size
, u_int flags
);
762 HAL_STATUS
__ahdecl(*ah_procRxDesc
)(struct ath_hal
*,
763 struct ath_desc
*, u_int32_t phyAddr
,
764 struct ath_desc
*next
, u_int64_t tsf
,
765 struct ath_rx_status
*);
766 void __ahdecl(*ah_rxMonitor
)(struct ath_hal
*,
767 const HAL_NODE_STATS
*, HAL_CHANNEL
*);
768 void __ahdecl(*ah_procMibEvent
)(struct ath_hal
*,
769 const HAL_NODE_STATS
*);
772 HAL_STATUS
__ahdecl(*ah_getCapability
)(struct ath_hal
*,
773 HAL_CAPABILITY_TYPE
, u_int32_t capability
,
775 HAL_BOOL
__ahdecl(*ah_setCapability
)(struct ath_hal
*,
776 HAL_CAPABILITY_TYPE
, u_int32_t capability
,
777 u_int32_t setting
, HAL_STATUS
*);
778 HAL_BOOL
__ahdecl(*ah_getDiagState
)(struct ath_hal
*, int request
,
779 const void *args
, u_int32_t argsize
,
780 void **result
, u_int32_t
*resultsize
);
781 void __ahdecl(*ah_getMacAddress
)(struct ath_hal
*, u_int8_t
*);
782 HAL_BOOL
__ahdecl(*ah_setMacAddress
)(struct ath_hal
*, const u_int8_t
*);
783 void __ahdecl(*ah_getBssIdMask
)(struct ath_hal
*, u_int8_t
*);
784 HAL_BOOL
__ahdecl(*ah_setBssIdMask
)(struct ath_hal
*, const u_int8_t
*);
785 HAL_BOOL
__ahdecl(*ah_setRegulatoryDomain
)(struct ath_hal
*,
786 u_int16_t
, HAL_STATUS
*);
787 void __ahdecl(*ah_setLedState
)(struct ath_hal
*, HAL_LED_STATE
);
788 void __ahdecl(*ah_writeAssocid
)(struct ath_hal
*,
789 const u_int8_t
*bssid
, u_int16_t assocId
);
790 HAL_BOOL
__ahdecl(*ah_gpioCfgOutput
)(struct ath_hal
*, u_int32_t gpio
);
791 HAL_BOOL
__ahdecl(*ah_gpioCfgInput
)(struct ath_hal
*, u_int32_t gpio
);
792 u_int32_t
__ahdecl(*ah_gpioGet
)(struct ath_hal
*, u_int32_t gpio
);
793 HAL_BOOL
__ahdecl(*ah_gpioSet
)(struct ath_hal
*,
794 u_int32_t gpio
, u_int32_t val
);
795 void __ahdecl(*ah_gpioSetIntr
)(struct ath_hal
*, u_int
, u_int32_t
);
796 u_int32_t
__ahdecl(*ah_getTsf32
)(struct ath_hal
*);
797 u_int64_t
__ahdecl(*ah_getTsf64
)(struct ath_hal
*);
798 void __ahdecl(*ah_resetTsf
)(struct ath_hal
*);
799 HAL_BOOL
__ahdecl(*ah_detectCardPresent
)(struct ath_hal
*);
800 void __ahdecl(*ah_updateMibCounters
)(struct ath_hal
*,
802 HAL_RFGAIN
__ahdecl(*ah_getRfGain
)(struct ath_hal
*);
803 u_int
__ahdecl(*ah_getDefAntenna
)(struct ath_hal
*);
804 void __ahdecl(*ah_setDefAntenna
)(struct ath_hal
*, u_int
);
805 HAL_ANT_SETTING
__ahdecl(*ah_getAntennaSwitch
)(struct ath_hal
*);
806 HAL_BOOL
__ahdecl(*ah_setAntennaSwitch
)(struct ath_hal
*,
808 HAL_BOOL
__ahdecl(*ah_setSlotTime
)(struct ath_hal
*, u_int
);
809 u_int
__ahdecl(*ah_getSlotTime
)(struct ath_hal
*);
810 HAL_BOOL
__ahdecl(*ah_setAckTimeout
)(struct ath_hal
*, u_int
);
811 u_int
__ahdecl(*ah_getAckTimeout
)(struct ath_hal
*);
812 HAL_BOOL
__ahdecl(*ah_setAckCTSRate
)(struct ath_hal
*, u_int
);
813 u_int
__ahdecl(*ah_getAckCTSRate
)(struct ath_hal
*);
814 HAL_BOOL
__ahdecl(*ah_setCTSTimeout
)(struct ath_hal
*, u_int
);
815 u_int
__ahdecl(*ah_getCTSTimeout
)(struct ath_hal
*);
816 HAL_BOOL
__ahdecl(*ah_setDecompMask
)(struct ath_hal
*, u_int16_t
, int);
817 void __ahdecl(*ah_setCoverageClass
)(struct ath_hal
*, u_int8_t
, int);
819 /* Key Cache Functions */
820 u_int32_t
__ahdecl(*ah_getKeyCacheSize
)(struct ath_hal
*);
821 HAL_BOOL
__ahdecl(*ah_resetKeyCacheEntry
)(struct ath_hal
*, u_int16_t
);
822 HAL_BOOL
__ahdecl(*ah_isKeyCacheEntryValid
)(struct ath_hal
*,
824 HAL_BOOL
__ahdecl(*ah_setKeyCacheEntry
)(struct ath_hal
*,
825 u_int16_t
, const HAL_KEYVAL
*,
826 const u_int8_t
*, int);
827 HAL_BOOL
__ahdecl(*ah_setKeyCacheEntryMac
)(struct ath_hal
*,
828 u_int16_t
, const u_int8_t
*);
830 /* Power Management Functions */
831 HAL_BOOL
__ahdecl(*ah_setPowerMode
)(struct ath_hal
*,
832 HAL_POWER_MODE mode
, int setChip
);
833 HAL_POWER_MODE
__ahdecl(*ah_getPowerMode
)(struct ath_hal
*);
834 int16_t __ahdecl(*ah_getChanNoise
)(struct ath_hal
*, HAL_CHANNEL
*);
836 /* Beacon Management Functions */
837 void __ahdecl(*ah_setBeaconTimers
)(struct ath_hal
*,
838 const HAL_BEACON_TIMERS
*);
839 /* NB: deprecated, use ah_setBeaconTimers instead */
840 void __ahdecl(*ah_beaconInit
)(struct ath_hal
*,
841 u_int32_t nexttbtt
, u_int32_t intval
);
842 void __ahdecl(*ah_setStationBeaconTimers
)(struct ath_hal
*,
843 const HAL_BEACON_STATE
*);
844 void __ahdecl(*ah_resetStationBeaconTimers
)(struct ath_hal
*);
846 /* Interrupt functions */
847 HAL_BOOL
__ahdecl(*ah_isInterruptPending
)(struct ath_hal
*);
848 HAL_BOOL
__ahdecl(*ah_getPendingInterrupts
)(struct ath_hal
*, HAL_INT
*);
849 HAL_INT
__ahdecl(*ah_getInterrupts
)(struct ath_hal
*);
850 HAL_INT
__ahdecl(*ah_setInterrupts
)(struct ath_hal
*, HAL_INT
);
854 * Check the PCI vendor ID and device ID against Atheros' values
855 * and return a printable description for any Atheros hardware.
856 * AH_NULL is returned if the ID's do not describe Atheros hardware.
858 extern const char *__ahdecl
ath_hal_probe(u_int16_t vendorid
, u_int16_t devid
);
861 * Attach the HAL for use with the specified device. The device is
862 * defined by the PCI device ID. The caller provides an opaque pointer
863 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
864 * HAL state block for later use. Hardware register accesses are done
865 * using the specified bus tag and handle. On successful return a
866 * reference to a state block is returned that must be supplied in all
867 * subsequent HAL calls. Storage associated with this reference is
868 * dynamically allocated and must be freed by calling the ah_detach
869 * method when the client is done. If the attach operation fails a
870 * null (AH_NULL) reference will be returned and a status code will
871 * be returned if the status parameter is non-zero.
873 extern struct ath_hal
* __ahdecl
ath_hal_attach(u_int16_t devid
, HAL_SOFTC
,
874 HAL_BUS_TAG
, HAL_BUS_HANDLE
, HAL_STATUS
* status
);
877 * Set the Vendor ID for Vendor SKU's which can modify the
878 * channel properties returned by ath_hal_init_channels.
880 extern HAL_BOOL __ahdecl
ath_hal_setvendor(struct ath_hal
*, u_int32_t
);
883 * Return a list of channels available for use with the hardware.
884 * The list is based on what the hardware is capable of, the specified
885 * country code, the modeSelect mask, and whether or not outdoor
886 * channels are to be permitted.
888 * The channel list is returned in the supplied array. maxchans
889 * defines the maximum size of this array. nchans contains the actual
890 * number of channels returned. If a problem occurred or there were
891 * no channels that met the criteria then AH_FALSE is returned.
893 extern HAL_BOOL __ahdecl
ath_hal_init_channels(struct ath_hal
*,
894 HAL_CHANNEL
*chans
, u_int maxchans
, u_int
*nchans
,
895 u_int8_t
*regclassids
, u_int maxregids
, u_int
*nregids
,
896 HAL_CTRY_CODE cc
, u_int modeSelect
,
897 HAL_BOOL enableOutdoor
, HAL_BOOL enableExtendedChannels
);
900 * Calibrate noise floor data following a channel scan or similar.
901 * This must be called prior retrieving noise floor data.
903 extern void __ahdecl
ath_hal_process_noisefloor(struct ath_hal
*ah
);
906 * Return bit mask of wireless modes supported by the hardware.
908 extern u_int __ahdecl
ath_hal_getwirelessmodes(struct ath_hal
*, HAL_CTRY_CODE
);
911 * Calculate the transmit duration of a frame.
913 extern u_int16_t __ahdecl
ath_hal_computetxtime(struct ath_hal
*,
914 const HAL_RATE_TABLE
*rates
, u_int32_t frameLen
,
915 u_int16_t rateix
, HAL_BOOL shortPreamble
);
918 * Return if device is public safety.
920 extern HAL_BOOL __ahdecl
ath_hal_ispublicsafetysku(struct ath_hal
*);
923 * Return if device is operating in 900 MHz band.
925 extern HAL_BOOL
ath_hal_isgsmsku(struct ath_hal
*);
928 * Convert between IEEE channel number and channel frequency
929 * using the specified channel flags; e.g. CHANNEL_2GHZ.
931 extern int __ahdecl
ath_hal_mhz2ieee(struct ath_hal
*, u_int mhz
, u_int flags
);
934 * Return a version string for the HAL release.
936 extern char ath_hal_version
[];
938 * Return a NULL-terminated array of build/configuration options.
940 extern const char* ath_hal_buildopts
[];
941 #endif /* _ATH_AH_H_ */