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[PATCH] sata_promise: PHYMODE4 fixup
[linux-2.6/zen-sources.git] / drivers / ata / sata_promise.c
bloba2778cf016bc2e8866423775416a48621a17433c
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.05"
50
51
52 enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_FLASH_CTL = 0x44, /* Flash control register */
56 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
57 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
58 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
59 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
60 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
62
63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
65
66 board_2037x = 0, /* FastTrak S150 TX2plus */
67 board_20319 = 1, /* FastTrak S150 TX4 */
68 board_20619 = 2, /* FastTrak TX4000 */
69 board_20771 = 3, /* FastTrak TX2300 */
70 board_2057x = 4, /* SATAII150 Tx2plus */
71 board_40518 = 5, /* SATAII150 Tx4 */
72
73 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
74
75 PDC_RESET = (1 << 11), /* HDMA reset */
76
77 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
78 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
79 ATA_FLAG_PIO_POLLING,
80
81 /* hp->flags bits */
82 PDC_FLAG_GEN_II = (1 << 0),
83 };
84
85
86 struct pdc_port_priv {
87 u8 *pkt;
88 dma_addr_t pkt_dma;
89 };
90
91 struct pdc_host_priv {
92 unsigned long flags;
93 int hotplug_offset;
94 };
95
96 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
97 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
98 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
99 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
100 static void pdc_eng_timeout(struct ata_port *ap);
101 static int pdc_port_start(struct ata_port *ap);
102 static void pdc_port_stop(struct ata_port *ap);
103 static void pdc_pata_phy_reset(struct ata_port *ap);
104 static void pdc_sata_phy_reset(struct ata_port *ap);
105 static void pdc_qc_prep(struct ata_queued_cmd *qc);
106 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
107 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
108 static void pdc_irq_clear(struct ata_port *ap);
109 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
110 static void pdc_host_stop(struct ata_host *host);
111
112
113 static struct scsi_host_template pdc_ata_sht = {
114 .module = THIS_MODULE,
115 .name = DRV_NAME,
116 .ioctl = ata_scsi_ioctl,
117 .queuecommand = ata_scsi_queuecmd,
118 .can_queue = ATA_DEF_QUEUE,
119 .this_id = ATA_SHT_THIS_ID,
120 .sg_tablesize = LIBATA_MAX_PRD,
121 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
122 .emulated = ATA_SHT_EMULATED,
123 .use_clustering = ATA_SHT_USE_CLUSTERING,
124 .proc_name = DRV_NAME,
125 .dma_boundary = ATA_DMA_BOUNDARY,
126 .slave_configure = ata_scsi_slave_config,
127 .slave_destroy = ata_scsi_slave_destroy,
128 .bios_param = ata_std_bios_param,
129 };
130
131 static const struct ata_port_operations pdc_sata_ops = {
132 .port_disable = ata_port_disable,
133 .tf_load = pdc_tf_load_mmio,
134 .tf_read = ata_tf_read,
135 .check_status = ata_check_status,
136 .exec_command = pdc_exec_command_mmio,
137 .dev_select = ata_std_dev_select,
138
139 .phy_reset = pdc_sata_phy_reset,
140
141 .qc_prep = pdc_qc_prep,
142 .qc_issue = pdc_qc_issue_prot,
143 .eng_timeout = pdc_eng_timeout,
144 .data_xfer = ata_mmio_data_xfer,
145 .irq_handler = pdc_interrupt,
146 .irq_clear = pdc_irq_clear,
147
148 .scr_read = pdc_sata_scr_read,
149 .scr_write = pdc_sata_scr_write,
150 .port_start = pdc_port_start,
151 .port_stop = pdc_port_stop,
152 .host_stop = pdc_host_stop,
153 };
154
155 static const struct ata_port_operations pdc_pata_ops = {
156 .port_disable = ata_port_disable,
157 .tf_load = pdc_tf_load_mmio,
158 .tf_read = ata_tf_read,
159 .check_status = ata_check_status,
160 .exec_command = pdc_exec_command_mmio,
161 .dev_select = ata_std_dev_select,
162
163 .phy_reset = pdc_pata_phy_reset,
164
165 .qc_prep = pdc_qc_prep,
166 .qc_issue = pdc_qc_issue_prot,
167 .data_xfer = ata_mmio_data_xfer,
168 .eng_timeout = pdc_eng_timeout,
169 .irq_handler = pdc_interrupt,
170 .irq_clear = pdc_irq_clear,
171
172 .port_start = pdc_port_start,
173 .port_stop = pdc_port_stop,
174 .host_stop = pdc_host_stop,
175 };
176
177 static const struct ata_port_info pdc_port_info[] = {
178 /* board_2037x */
179 {
180 .sht = &pdc_ata_sht,
181 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
182 .pio_mask = 0x1f, /* pio0-4 */
183 .mwdma_mask = 0x07, /* mwdma0-2 */
184 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
185 .port_ops = &pdc_sata_ops,
186 },
187
188 /* board_20319 */
189 {
190 .sht = &pdc_ata_sht,
191 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
192 .pio_mask = 0x1f, /* pio0-4 */
193 .mwdma_mask = 0x07, /* mwdma0-2 */
194 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
195 .port_ops = &pdc_sata_ops,
196 },
197
198 /* board_20619 */
199 {
200 .sht = &pdc_ata_sht,
201 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
202 .pio_mask = 0x1f, /* pio0-4 */
203 .mwdma_mask = 0x07, /* mwdma0-2 */
204 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
205 .port_ops = &pdc_pata_ops,
206 },
207
208 /* board_20771 */
209 {
210 .sht = &pdc_ata_sht,
211 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
212 .pio_mask = 0x1f, /* pio0-4 */
213 .mwdma_mask = 0x07, /* mwdma0-2 */
214 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
215 .port_ops = &pdc_sata_ops,
216 },
217
218 /* board_2057x */
219 {
220 .sht = &pdc_ata_sht,
221 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
222 .pio_mask = 0x1f, /* pio0-4 */
223 .mwdma_mask = 0x07, /* mwdma0-2 */
224 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
225 .port_ops = &pdc_sata_ops,
226 },
227
228 /* board_40518 */
229 {
230 .sht = &pdc_ata_sht,
231 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
232 .pio_mask = 0x1f, /* pio0-4 */
233 .mwdma_mask = 0x07, /* mwdma0-2 */
234 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
235 .port_ops = &pdc_sata_ops,
236 },
237 };
238
239 static const struct pci_device_id pdc_ata_pci_tbl[] = {
240 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
241 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
242 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
243 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
244 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
245 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
246 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
247 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
248 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
249
250 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
251 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
252 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
253 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
254 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
255 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
256
257 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
258
259 /* TODO: remove all associated board_20771 code, as it completely
260 * duplicates board_2037x code, unless reason for separation can be
261 * divined.
262 */
263 #if 0
264 { PCI_VDEVICE(PROMISE, 0x3570), board_20771 },
265 #endif
266 { PCI_VDEVICE(PROMISE, 0x3577), board_20771 },
267
268 { } /* terminate list */
269 };
270
271
272 static struct pci_driver pdc_ata_pci_driver = {
273 .name = DRV_NAME,
274 .id_table = pdc_ata_pci_tbl,
275 .probe = pdc_ata_init_one,
276 .remove = ata_pci_remove_one,
277 };
278
279
280 static int pdc_port_start(struct ata_port *ap)
281 {
282 struct device *dev = ap->host->dev;
283 struct pdc_host_priv *hp = ap->host->private_data;
284 struct pdc_port_priv *pp;
285 int rc;
286
287 rc = ata_port_start(ap);
288 if (rc)
289 return rc;
290
291 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
292 if (!pp) {
293 rc = -ENOMEM;
294 goto err_out;
295 }
296
297 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
298 if (!pp->pkt) {
299 rc = -ENOMEM;
300 goto err_out_kfree;
301 }
302
303 ap->private_data = pp;
304
305 /* fix up PHYMODE4 align timing */
306 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
307 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
308 unsigned int tmp;
309
310 tmp = readl(mmio + 0x014);
311 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
312 writel(tmp, mmio + 0x014);
313 }
314
315 return 0;
316
317 err_out_kfree:
318 kfree(pp);
319 err_out:
320 ata_port_stop(ap);
321 return rc;
322 }
323
324
325 static void pdc_port_stop(struct ata_port *ap)
326 {
327 struct device *dev = ap->host->dev;
328 struct pdc_port_priv *pp = ap->private_data;
329
330 ap->private_data = NULL;
331 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
332 kfree(pp);
333 ata_port_stop(ap);
334 }
335
336
337 static void pdc_host_stop(struct ata_host *host)
338 {
339 struct pdc_host_priv *hp = host->private_data;
340
341 ata_pci_host_stop(host);
342
343 kfree(hp);
344 }
345
346
347 static void pdc_reset_port(struct ata_port *ap)
348 {
349 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
350 unsigned int i;
351 u32 tmp;
352
353 for (i = 11; i > 0; i--) {
354 tmp = readl(mmio);
355 if (tmp & PDC_RESET)
356 break;
357
358 udelay(100);
359
360 tmp |= PDC_RESET;
361 writel(tmp, mmio);
362 }
363
364 tmp &= ~PDC_RESET;
365 writel(tmp, mmio);
366 readl(mmio); /* flush */
367 }
368
369 static void pdc_sata_phy_reset(struct ata_port *ap)
370 {
371 pdc_reset_port(ap);
372 sata_phy_reset(ap);
373 }
374
375 static void pdc_pata_cbl_detect(struct ata_port *ap)
376 {
377 u8 tmp;
378 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
379
380 tmp = readb(mmio);
381
382 if (tmp & 0x01) {
383 ap->cbl = ATA_CBL_PATA40;
384 ap->udma_mask &= ATA_UDMA_MASK_40C;
385 } else
386 ap->cbl = ATA_CBL_PATA80;
387 }
388
389 static void pdc_pata_phy_reset(struct ata_port *ap)
390 {
391 pdc_pata_cbl_detect(ap);
392 pdc_reset_port(ap);
393 ata_port_probe(ap);
394 ata_bus_reset(ap);
395 }
396
397 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
398 {
399 if (sc_reg > SCR_CONTROL)
400 return 0xffffffffU;
401 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
402 }
403
404
405 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
406 u32 val)
407 {
408 if (sc_reg > SCR_CONTROL)
409 return;
410 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
411 }
412
413 static void pdc_qc_prep(struct ata_queued_cmd *qc)
414 {
415 struct pdc_port_priv *pp = qc->ap->private_data;
416 unsigned int i;
417
418 VPRINTK("ENTER\n");
419
420 switch (qc->tf.protocol) {
421 case ATA_PROT_DMA:
422 ata_qc_prep(qc);
423 /* fall through */
424
425 case ATA_PROT_NODATA:
426 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
427 qc->dev->devno, pp->pkt);
428
429 if (qc->tf.flags & ATA_TFLAG_LBA48)
430 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
431 else
432 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
433
434 pdc_pkt_footer(&qc->tf, pp->pkt, i);
435 break;
436
437 default:
438 break;
439 }
440 }
441
442 static void pdc_eng_timeout(struct ata_port *ap)
443 {
444 struct ata_host *host = ap->host;
445 u8 drv_stat;
446 struct ata_queued_cmd *qc;
447 unsigned long flags;
448
449 DPRINTK("ENTER\n");
450
451 spin_lock_irqsave(&host->lock, flags);
452
453 qc = ata_qc_from_tag(ap, ap->active_tag);
454
455 switch (qc->tf.protocol) {
456 case ATA_PROT_DMA:
457 case ATA_PROT_NODATA:
458 ata_port_printk(ap, KERN_ERR, "command timeout\n");
459 drv_stat = ata_wait_idle(ap);
460 qc->err_mask |= __ac_err_mask(drv_stat);
461 break;
462
463 default:
464 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
465
466 ata_port_printk(ap, KERN_ERR,
467 "unknown timeout, cmd 0x%x stat 0x%x\n",
468 qc->tf.command, drv_stat);
469
470 qc->err_mask |= ac_err_mask(drv_stat);
471 break;
472 }
473
474 spin_unlock_irqrestore(&host->lock, flags);
475 ata_eh_qc_complete(qc);
476 DPRINTK("EXIT\n");
477 }
478
479 static inline unsigned int pdc_host_intr( struct ata_port *ap,
480 struct ata_queued_cmd *qc)
481 {
482 unsigned int handled = 0;
483 u32 tmp;
484 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
485
486 tmp = readl(mmio);
487 if (tmp & PDC_ERR_MASK) {
488 qc->err_mask |= AC_ERR_DEV;
489 pdc_reset_port(ap);
490 }
491
492 switch (qc->tf.protocol) {
493 case ATA_PROT_DMA:
494 case ATA_PROT_NODATA:
495 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
496 ata_qc_complete(qc);
497 handled = 1;
498 break;
499
500 default:
501 ap->stats.idle_irq++;
502 break;
503 }
504
505 return handled;
506 }
507
508 static void pdc_irq_clear(struct ata_port *ap)
509 {
510 struct ata_host *host = ap->host;
511 void __iomem *mmio = host->mmio_base;
512
513 readl(mmio + PDC_INT_SEQMASK);
514 }
515
516 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
517 {
518 struct ata_host *host = dev_instance;
519 struct ata_port *ap;
520 u32 mask = 0;
521 unsigned int i, tmp;
522 unsigned int handled = 0;
523 void __iomem *mmio_base;
524
525 VPRINTK("ENTER\n");
526
527 if (!host || !host->mmio_base) {
528 VPRINTK("QUICK EXIT\n");
529 return IRQ_NONE;
530 }
531
532 mmio_base = host->mmio_base;
533
534 /* reading should also clear interrupts */
535 mask = readl(mmio_base + PDC_INT_SEQMASK);
536
537 if (mask == 0xffffffff) {
538 VPRINTK("QUICK EXIT 2\n");
539 return IRQ_NONE;
540 }
541
542 spin_lock(&host->lock);
543
544 mask &= 0xffff; /* only 16 tags possible */
545 if (!mask) {
546 VPRINTK("QUICK EXIT 3\n");
547 goto done_irq;
548 }
549
550 writel(mask, mmio_base + PDC_INT_SEQMASK);
551
552 for (i = 0; i < host->n_ports; i++) {
553 VPRINTK("port %u\n", i);
554 ap = host->ports[i];
555 tmp = mask & (1 << (i + 1));
556 if (tmp && ap &&
557 !(ap->flags & ATA_FLAG_DISABLED)) {
558 struct ata_queued_cmd *qc;
559
560 qc = ata_qc_from_tag(ap, ap->active_tag);
561 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
562 handled += pdc_host_intr(ap, qc);
563 }
564 }
565
566 VPRINTK("EXIT\n");
567
568 done_irq:
569 spin_unlock(&host->lock);
570 return IRQ_RETVAL(handled);
571 }
572
573 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
574 {
575 struct ata_port *ap = qc->ap;
576 struct pdc_port_priv *pp = ap->private_data;
577 unsigned int port_no = ap->port_no;
578 u8 seq = (u8) (port_no + 1);
579
580 VPRINTK("ENTER, ap %p\n", ap);
581
582 writel(0x00000001, ap->host->mmio_base + (seq * 4));
583 readl(ap->host->mmio_base + (seq * 4)); /* flush */
584
585 pp->pkt[2] = seq;
586 wmb(); /* flush PRD, pkt writes */
587 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
588 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
589 }
590
591 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
592 {
593 switch (qc->tf.protocol) {
594 case ATA_PROT_DMA:
595 case ATA_PROT_NODATA:
596 pdc_packet_start(qc);
597 return 0;
598
599 case ATA_PROT_ATAPI_DMA:
600 BUG();
601 break;
602
603 default:
604 break;
605 }
606
607 return ata_qc_issue_prot(qc);
608 }
609
610 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
611 {
612 WARN_ON (tf->protocol == ATA_PROT_DMA ||
613 tf->protocol == ATA_PROT_NODATA);
614 ata_tf_load(ap, tf);
615 }
616
617
618 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
619 {
620 WARN_ON (tf->protocol == ATA_PROT_DMA ||
621 tf->protocol == ATA_PROT_NODATA);
622 ata_exec_command(ap, tf);
623 }
624
625
626 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
627 {
628 port->cmd_addr = base;
629 port->data_addr = base;
630 port->feature_addr =
631 port->error_addr = base + 0x4;
632 port->nsect_addr = base + 0x8;
633 port->lbal_addr = base + 0xc;
634 port->lbam_addr = base + 0x10;
635 port->lbah_addr = base + 0x14;
636 port->device_addr = base + 0x18;
637 port->command_addr =
638 port->status_addr = base + 0x1c;
639 port->altstatus_addr =
640 port->ctl_addr = base + 0x38;
641 }
642
643
644 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
645 {
646 void __iomem *mmio = pe->mmio_base;
647 struct pdc_host_priv *hp = pe->private_data;
648 int hotplug_offset = hp->hotplug_offset;
649 u32 tmp;
650
651 /*
652 * Except for the hotplug stuff, this is voodoo from the
653 * Promise driver. Label this entire section
654 * "TODO: figure out why we do this"
655 */
656
657 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
658 tmp = readl(mmio + PDC_FLASH_CTL);
659 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
660 if (!(hp->flags & PDC_FLAG_GEN_II))
661 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
662 writel(tmp, mmio + PDC_FLASH_CTL);
663
664 /* clear plug/unplug flags for all ports */
665 tmp = readl(mmio + hotplug_offset);
666 writel(tmp | 0xff, mmio + hotplug_offset);
667
668 /* mask plug/unplug ints */
669 tmp = readl(mmio + hotplug_offset);
670 writel(tmp | 0xff0000, mmio + hotplug_offset);
671
672 /* don't initialise TBG or SLEW on 2nd generation chips */
673 if (hp->flags & PDC_FLAG_GEN_II)
674 return;
675
676 /* reduce TBG clock to 133 Mhz. */
677 tmp = readl(mmio + PDC_TBG_MODE);
678 tmp &= ~0x30000; /* clear bit 17, 16*/
679 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
680 writel(tmp, mmio + PDC_TBG_MODE);
681
682 readl(mmio + PDC_TBG_MODE); /* flush */
683 msleep(10);
684
685 /* adjust slew rate control register. */
686 tmp = readl(mmio + PDC_SLEW_CTL);
687 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
688 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
689 writel(tmp, mmio + PDC_SLEW_CTL);
690 }
691
692 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
693 {
694 static int printed_version;
695 struct ata_probe_ent *probe_ent = NULL;
696 struct pdc_host_priv *hp;
697 unsigned long base;
698 void __iomem *mmio_base;
699 unsigned int board_idx = (unsigned int) ent->driver_data;
700 int pci_dev_busy = 0;
701 int rc;
702
703 if (!printed_version++)
704 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
705
706 rc = pci_enable_device(pdev);
707 if (rc)
708 return rc;
709
710 rc = pci_request_regions(pdev, DRV_NAME);
711 if (rc) {
712 pci_dev_busy = 1;
713 goto err_out;
714 }
715
716 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
717 if (rc)
718 goto err_out_regions;
719 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
720 if (rc)
721 goto err_out_regions;
722
723 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
724 if (probe_ent == NULL) {
725 rc = -ENOMEM;
726 goto err_out_regions;
727 }
728
729 probe_ent->dev = pci_dev_to_dev(pdev);
730 INIT_LIST_HEAD(&probe_ent->node);
731
732 mmio_base = pci_iomap(pdev, 3, 0);
733 if (mmio_base == NULL) {
734 rc = -ENOMEM;
735 goto err_out_free_ent;
736 }
737 base = (unsigned long) mmio_base;
738
739 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
740 if (hp == NULL) {
741 rc = -ENOMEM;
742 goto err_out_free_ent;
743 }
744
745 /* Set default hotplug offset */
746 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
747 probe_ent->private_data = hp;
748
749 probe_ent->sht = pdc_port_info[board_idx].sht;
750 probe_ent->port_flags = pdc_port_info[board_idx].flags;
751 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
752 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
753 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
754 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
755
756 probe_ent->irq = pdev->irq;
757 probe_ent->irq_flags = IRQF_SHARED;
758 probe_ent->mmio_base = mmio_base;
759
760 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
761 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
762
763 probe_ent->port[0].scr_addr = base + 0x400;
764 probe_ent->port[1].scr_addr = base + 0x500;
765
766 /* notice 4-port boards */
767 switch (board_idx) {
768 case board_40518:
769 hp->flags |= PDC_FLAG_GEN_II;
770 /* Override hotplug offset for SATAII150 */
771 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
772 /* Fall through */
773 case board_20319:
774 probe_ent->n_ports = 4;
775
776 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
777 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
778
779 probe_ent->port[2].scr_addr = base + 0x600;
780 probe_ent->port[3].scr_addr = base + 0x700;
781 break;
782 case board_2057x:
783 case board_20771:
784 hp->flags |= PDC_FLAG_GEN_II;
785 /* Override hotplug offset for SATAII150 */
786 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
787 /* Fall through */
788 case board_2037x:
789 probe_ent->n_ports = 2;
790 break;
791 case board_20619:
792 probe_ent->n_ports = 4;
793
794 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
795 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
796
797 probe_ent->port[2].scr_addr = base + 0x600;
798 probe_ent->port[3].scr_addr = base + 0x700;
799 break;
800 default:
801 BUG();
802 break;
803 }
804
805 pci_set_master(pdev);
806
807 /* initialize adapter */
808 pdc_host_init(board_idx, probe_ent);
809
810 /* FIXME: Need any other frees than hp? */
811 if (!ata_device_add(probe_ent))
812 kfree(hp);
813
814 kfree(probe_ent);
815
816 return 0;
817
818 err_out_free_ent:
819 kfree(probe_ent);
820 err_out_regions:
821 pci_release_regions(pdev);
822 err_out:
823 if (!pci_dev_busy)
824 pci_disable_device(pdev);
825 return rc;
826 }
827
828
829 static int __init pdc_ata_init(void)
830 {
831 return pci_register_driver(&pdc_ata_pci_driver);
832 }
833
834
835 static void __exit pdc_ata_exit(void)
836 {
837 pci_unregister_driver(&pdc_ata_pci_driver);
838 }
839
840
841 MODULE_AUTHOR("Jeff Garzik");
842 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
843 MODULE_LICENSE("GPL");
844 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
845 MODULE_VERSION(DRV_VERSION);
846
847 module_init(pdc_ata_init);
848 module_exit(pdc_ata_exit);
Stable & featurefull patchset based on Linus's git branch