drivers/media/dvb/frontends/mt352.c

   1 /*
   2  *  Driver for Zarlink DVB-T MT352 demodulator
   3  *
   4  *  Written by Holger Waechtler <holger@qanu.de>
   5  *       and Daniel Mack <daniel@qanu.de>
   6  *
   7  *  AVerMedia AVerTV DVB-T 771 support by
   8  *       Wolfram Joost <dbox2@frokaschwei.de>
   9  *
  10  *  Support for Samsung TDTC9251DH01C(M) tuner
  11  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
  12  *                     Amauri  Celani  <acelani@essegi.net>
  13  *
  14  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
  15  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *
  26  *  GNU General Public License for more details.
  27  *
  28  *  You should have received a copy of the GNU General Public License
  29  *  along with this program; if not, write to the Free Software
  30  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/init.h>
  37 #include <linux/delay.h>
  38
  39 #include "dvb_frontend.h"
  40 #include "mt352_priv.h"
  41 #include "mt352.h"
  42
  43 struct mt352_state {
  44         struct i2c_adapter* i2c;
  45         struct dvb_frontend frontend;
  46         struct dvb_frontend_ops ops;
  47
  48         /* configuration settings */
  49         struct mt352_config config;
  50 };
  51
  52 static int debug;
  53 #define dprintk(args...) \
  54         do { \
  55                 if (debug) printk(KERN_DEBUG "mt352: " args); \
  56         } while (0)
  57
  58 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
  59 {
  60         struct mt352_state* state = fe->demodulator_priv;
  61         u8 buf[2] = { reg, val };
  62         struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
  63                                .buf = buf, .len = 2 };
  64         int err = i2c_transfer(state->i2c, &msg, 1);
  65         if (err != 1) {
  66                 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
  67                 return err;
  68         }
  69         return 0;
  70 }
  71
  72 int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
  73 {
  74         int err,i;
  75         for (i=0; i < ilen-1; i++)
  76                 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
  77                         return err;
  78
  79         return 0;
  80 }
  81
  82 static int mt352_read_register(struct mt352_state* state, u8 reg)
  83 {
  84         int ret;
  85         u8 b0 [] = { reg };
  86         u8 b1 [] = { 0 };
  87         struct i2c_msg msg [] = { { .addr = state->config.demod_address,
  88                                     .flags = 0,
  89                                     .buf = b0, .len = 1 },
  90                                   { .addr = state->config.demod_address,
  91                                     .flags = I2C_M_RD,
  92                                     .buf = b1, .len = 1 } };
  93
  94         ret = i2c_transfer(state->i2c, msg, 2);
  95
  96         if (ret != 2) {
  97                 printk("%s: readreg error (reg=%d, ret==%i)\n",
  98                        __FUNCTION__, reg, ret);
  99                 return ret;
 100         }
 101
 102         return b1[0];
 103 }
 104
 105 static int mt352_sleep(struct dvb_frontend* fe)
 106 {
 107         static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
 108
 109         mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
 110         return 0;
 111 }
 112
 113 static void mt352_calc_nominal_rate(struct mt352_state* state,
 114                                     enum fe_bandwidth bandwidth,
 115                                     unsigned char *buf)
 116 {
 117         u32 adc_clock = 20480; /* 20.340 MHz */
 118         u32 bw,value;
 119
 120         switch (bandwidth) {
 121         case BANDWIDTH_6_MHZ:
 122                 bw = 6;
 123                 break;
 124         case BANDWIDTH_7_MHZ:
 125                 bw = 7;
 126                 break;
 127         case BANDWIDTH_8_MHZ:
 128         default:
 129                 bw = 8;
 130                 break;
 131         }
 132         if (state->config.adc_clock)
 133                 adc_clock = state->config.adc_clock;
 134
 135         value = 64 * bw * (1<<16) / (7 * 8);
 136         value = value * 1000 / adc_clock;
 137         dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
 138                 __FUNCTION__, bw, adc_clock, value);
 139         buf[0] = msb(value);
 140         buf[1] = lsb(value);
 141 }
 142
 143 static void mt352_calc_input_freq(struct mt352_state* state,
 144                                   unsigned char *buf)
 145 {
 146         int adc_clock = 20480; /* 20.480000 MHz */
 147         int if2       = 36167; /* 36.166667 MHz */
 148         int ife,value;
 149
 150         if (state->config.adc_clock)
 151                 adc_clock = state->config.adc_clock;
 152         if (state->config.if2)
 153                 if2 = state->config.if2;
 154
 155         ife = (2*adc_clock - if2);
 156         value = -16374 * ife / adc_clock;
 157         dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
 158                 __FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
 159         buf[0] = msb(value);
 160         buf[1] = lsb(value);
 161 }
 162
 163 static int mt352_set_parameters(struct dvb_frontend* fe,
 164                                 struct dvb_frontend_parameters *param)
 165 {
 166         struct mt352_state* state = fe->demodulator_priv;
 167         unsigned char buf[13];
 168         static unsigned char tuner_go[] = { 0x5d, 0x01 };
 169         static unsigned char fsm_go[]   = { 0x5e, 0x01 };
 170         unsigned int tps = 0;
 171         struct dvb_ofdm_parameters *op = &param->u.ofdm;
 172
 173         switch (op->code_rate_HP) {
 174                 case FEC_2_3:
 175                         tps |= (1 << 7);
 176                         break;
 177                 case FEC_3_4:
 178                         tps |= (2 << 7);
 179                         break;
 180                 case FEC_5_6:
 181                         tps |= (3 << 7);
 182                         break;
 183                 case FEC_7_8:
 184                         tps |= (4 << 7);
 185                         break;
 186                 case FEC_1_2:
 187                 case FEC_AUTO:
 188                         break;
 189                 default:
 190                         return -EINVAL;
 191         }
 192
 193         switch (op->code_rate_LP) {
 194                 case FEC_2_3:
 195                         tps |= (1 << 4);
 196                         break;
 197                 case FEC_3_4:
 198                         tps |= (2 << 4);
 199                         break;
 200                 case FEC_5_6:
 201                         tps |= (3 << 4);
 202                         break;
 203                 case FEC_7_8:
 204                         tps |= (4 << 4);
 205                         break;
 206                 case FEC_1_2:
 207                 case FEC_AUTO:
 208                         break;
 209                 case FEC_NONE:
 210                         if (op->hierarchy_information == HIERARCHY_AUTO ||
 211                             op->hierarchy_information == HIERARCHY_NONE)
 212                                 break;
 213                 default:
 214                         return -EINVAL;
 215         }
 216
 217         switch (op->constellation) {
 218                 case QPSK:
 219                         break;
 220                 case QAM_AUTO:
 221                 case QAM_16:
 222                         tps |= (1 << 13);
 223                         break;
 224                 case QAM_64:
 225                         tps |= (2 << 13);
 226                         break;
 227                 default:
 228                         return -EINVAL;
 229         }
 230
 231         switch (op->transmission_mode) {
 232                 case TRANSMISSION_MODE_2K:
 233                 case TRANSMISSION_MODE_AUTO:
 234                         break;
 235                 case TRANSMISSION_MODE_8K:
 236                         tps |= (1 << 0);
 237                         break;
 238                 default:
 239                         return -EINVAL;
 240         }
 241
 242         switch (op->guard_interval) {
 243                 case GUARD_INTERVAL_1_32:
 244                 case GUARD_INTERVAL_AUTO:
 245                         break;
 246                 case GUARD_INTERVAL_1_16:
 247                         tps |= (1 << 2);
 248                         break;
 249                 case GUARD_INTERVAL_1_8:
 250                         tps |= (2 << 2);
 251                         break;
 252                 case GUARD_INTERVAL_1_4:
 253                         tps |= (3 << 2);
 254                         break;
 255                 default:
 256                         return -EINVAL;
 257         }
 258
 259         switch (op->hierarchy_information) {
 260                 case HIERARCHY_AUTO:
 261                 case HIERARCHY_NONE:
 262                         break;
 263                 case HIERARCHY_1:
 264                         tps |= (1 << 10);
 265                         break;
 266                 case HIERARCHY_2:
 267                         tps |= (2 << 10);
 268                         break;
 269                 case HIERARCHY_4:
 270                         tps |= (3 << 10);
 271                         break;
 272                 default:
 273                         return -EINVAL;
 274         }
 275
 276
 277         buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
 278
 279         buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
 280         buf[2] = lsb(tps);
 281
 282         buf[3] = 0x50;  // old
 283 //      buf[3] = 0xf4;  // pinnacle
 284
 285         mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
 286         mt352_calc_input_freq(state, buf+6);
 287         state->config.pll_set(fe, param, buf+8);
 288
 289         mt352_write(fe, buf, sizeof(buf));
 290         if (state->config.no_tuner) {
 291                 /* start decoding */
 292                 mt352_write(fe, fsm_go, 2);
 293         } else {
 294                 /* start tuning */
 295                 mt352_write(fe, tuner_go, 2);
 296         }
 297         return 0;
 298 }
 299
 300 static int mt352_get_parameters(struct dvb_frontend* fe,
 301                                 struct dvb_frontend_parameters *param)
 302 {
 303         struct mt352_state* state = fe->demodulator_priv;
 304         u16 tps;
 305         u16 div;
 306         u8 trl;
 307         struct dvb_ofdm_parameters *op = &param->u.ofdm;
 308         static const u8 tps_fec_to_api[8] =
 309         {
 310                 FEC_1_2,
 311                 FEC_2_3,
 312                 FEC_3_4,
 313                 FEC_5_6,
 314                 FEC_7_8,
 315                 FEC_AUTO,
 316                 FEC_AUTO,
 317                 FEC_AUTO
 318         };
 319
 320         if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
 321                 return -EINVAL;
 322
 323         /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
 324          * the mt352 sometimes works with the wrong parameters
 325          */
 326         tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
 327         div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
 328         trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
 329
 330         op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
 331         op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
 332
 333         switch ( (tps >> 13) & 3)
 334         {
 335                 case 0:
 336                         op->constellation = QPSK;
 337                         break;
 338                 case 1:
 339                         op->constellation = QAM_16;
 340                         break;
 341                 case 2:
 342                         op->constellation = QAM_64;
 343                         break;
 344                 default:
 345                         op->constellation = QAM_AUTO;
 346                         break;
 347         }
 348
 349         op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
 350
 351         switch ( (tps >> 2) & 3)
 352         {
 353                 case 0:
 354                         op->guard_interval = GUARD_INTERVAL_1_32;
 355                         break;
 356                 case 1:
 357                         op->guard_interval = GUARD_INTERVAL_1_16;
 358                         break;
 359                 case 2:
 360                         op->guard_interval = GUARD_INTERVAL_1_8;
 361                         break;
 362                 case 3:
 363                         op->guard_interval = GUARD_INTERVAL_1_4;
 364                         break;
 365                 default:
 366                         op->guard_interval = GUARD_INTERVAL_AUTO;
 367                         break;
 368         }
 369
 370         switch ( (tps >> 10) & 7)
 371         {
 372                 case 0:
 373                         op->hierarchy_information = HIERARCHY_NONE;
 374                         break;
 375                 case 1:
 376                         op->hierarchy_information = HIERARCHY_1;
 377                         break;
 378                 case 2:
 379                         op->hierarchy_information = HIERARCHY_2;
 380                         break;
 381                 case 3:
 382                         op->hierarchy_information = HIERARCHY_4;
 383                         break;
 384                 default:
 385                         op->hierarchy_information = HIERARCHY_AUTO;
 386                         break;
 387         }
 388
 389         param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
 390
 391         if (trl == 0x72)
 392                 op->bandwidth = BANDWIDTH_8_MHZ;
 393         else if (trl == 0x64)
 394                 op->bandwidth = BANDWIDTH_7_MHZ;
 395         else
 396                 op->bandwidth = BANDWIDTH_6_MHZ;
 397
 398
 399         if (mt352_read_register(state, STATUS_2) & 0x02)
 400                 param->inversion = INVERSION_OFF;
 401         else
 402                 param->inversion = INVERSION_ON;
 403
 404         return 0;
 405 }
 406
 407 static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
 408 {
 409         struct mt352_state* state = fe->demodulator_priv;
 410         int s0, s1, s3;
 411
 412         /* FIXME:
 413          *
 414          * The MT352 design manual from Zarlink states (page 46-47):
 415          *
 416          * Notes about the TUNER_GO register:
 417          *
 418          * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
 419          * byte is copied from the tuner to the STATUS_3 register and
 420          * completion of the read operation is indicated by bit-5 of the
 421          * INTERRUPT_3 register.
 422          */
 423
 424         if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
 425                 return -EREMOTEIO;
 426         if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
 427                 return -EREMOTEIO;
 428         if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
 429                 return -EREMOTEIO;
 430
 431         *status = 0;
 432         if (s0 & (1 << 4))
 433                 *status |= FE_HAS_CARRIER;
 434         if (s0 & (1 << 1))
 435                 *status |= FE_HAS_VITERBI;
 436         if (s0 & (1 << 5))
 437                 *status |= FE_HAS_LOCK;
 438         if (s1 & (1 << 1))
 439                 *status |= FE_HAS_SYNC;
 440         if (s3 & (1 << 6))
 441                 *status |= FE_HAS_SIGNAL;
 442
 443         if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
 444                       (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
 445                 *status &= ~FE_HAS_LOCK;
 446
 447         return 0;
 448 }
 449
 450 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
 451 {
 452         struct mt352_state* state = fe->demodulator_priv;
 453
 454         *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
 455                (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
 456                (mt352_read_register (state, RS_ERR_CNT_0));
 457
 458         return 0;
 459 }
 460
 461 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 462 {
 463         struct mt352_state* state = fe->demodulator_priv;
 464
 465         /* align the 12 bit AGC gain with the most significant bits */
 466         u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
 467                 (mt352_read_register(state, AGC_GAIN_0) << 4);
 468
 469         /* inverse of gain is signal strength */
 470         *strength = ~signal;
 471         return 0;
 472 }
 473
 474 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
 475 {
 476         struct mt352_state* state = fe->demodulator_priv;
 477
 478         u8 _snr = mt352_read_register (state, SNR);
 479         *snr = (_snr << 8) | _snr;
 480
 481         return 0;
 482 }
 483
 484 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 485 {
 486         struct mt352_state* state = fe->demodulator_priv;
 487
 488         *ucblocks = (mt352_read_register (state,  RS_UBC_1) << 8) |
 489                     (mt352_read_register (state,  RS_UBC_0));
 490
 491         return 0;
 492 }
 493
 494 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
 495 {
 496         fe_tune_settings->min_delay_ms = 800;
 497         fe_tune_settings->step_size = 0;
 498         fe_tune_settings->max_drift = 0;
 499
 500         return 0;
 501 }
 502
 503 static int mt352_init(struct dvb_frontend* fe)
 504 {
 505         struct mt352_state* state = fe->demodulator_priv;
 506
 507         static u8 mt352_reset_attach [] = { RESET, 0xC0 };
 508
 509         dprintk("%s: hello\n",__FUNCTION__);
 510
 511         if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
 512             (mt352_read_register(state, CONFIG) & 0x20) == 0) {
 513
 514                 /* Do a "hard" reset */
 515                 mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
 516                 return state->config.demod_init(fe);
 517         }
 518
 519         return 0;
 520 }
 521
 522 static void mt352_release(struct dvb_frontend* fe)
 523 {
 524         struct mt352_state* state = fe->demodulator_priv;
 525         kfree(state);
 526 }
 527
 528 static struct dvb_frontend_ops mt352_ops;
 529
 530 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
 531                                   struct i2c_adapter* i2c)
 532 {
 533         struct mt352_state* state = NULL;
 534
 535         /* allocate memory for the internal state */
 536         state = kmalloc(sizeof(struct mt352_state), GFP_KERNEL);
 537         if (state == NULL) goto error;
 538         memset(state,0,sizeof(*state));
 539
 540         /* setup the state */
 541         state->i2c = i2c;
 542         memcpy(&state->config,config,sizeof(struct mt352_config));
 543         memcpy(&state->ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
 544
 545         /* check if the demod is there */
 546         if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
 547
 548         /* create dvb_frontend */
 549         state->frontend.ops = &state->ops;
 550         state->frontend.demodulator_priv = state;
 551         return &state->frontend;
 552
 553 error:
 554         kfree(state);
 555         return NULL;
 556 }
 557
 558 static struct dvb_frontend_ops mt352_ops = {
 559
 560         .info = {
 561                 .name                   = "Zarlink MT352 DVB-T",
 562                 .type                   = FE_OFDM,
 563                 .frequency_min          = 174000000,
 564                 .frequency_max          = 862000000,
 565                 .frequency_stepsize     = 166667,
 566                 .frequency_tolerance    = 0,
 567                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 568                         FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 569                         FE_CAN_FEC_AUTO |
 570                         FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 571                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
 572                         FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
 573                         FE_CAN_MUTE_TS
 574         },
 575
 576         .release = mt352_release,
 577
 578         .init = mt352_init,
 579         .sleep = mt352_sleep,
 580
 581         .set_frontend = mt352_set_parameters,
 582         .get_frontend = mt352_get_parameters,
 583         .get_tune_settings = mt352_get_tune_settings,
 584
 585         .read_status = mt352_read_status,
 586         .read_ber = mt352_read_ber,
 587         .read_signal_strength = mt352_read_signal_strength,
 588         .read_snr = mt352_read_snr,
 589         .read_ucblocks = mt352_read_ucblocks,
 590 };
 591
 592 module_param(debug, int, 0644);
 593 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 594
 595 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
 596 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
 597 MODULE_LICENSE("GPL");
 598
 599 EXPORT_SYMBOL(mt352_attach);
 600 EXPORT_SYMBOL(mt352_write);