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Merge git://git.infradead.org/mtd-2.6
[linux-2.6/zen-sources.git] / drivers / net / r6040.c
blob34fe7ef8e5edf637c1f3c5f301c944e08f598076
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/mii.h>
41 #include <linux/ethtool.h>
42 #include <linux/crc32.h>
43 #include <linux/spinlock.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/irq.h>
47 #include <linux/uaccess.h>
48
49 #include <asm/processor.h>
50
51 #define DRV_NAME "r6040"
52 #define DRV_VERSION "0.18"
53 #define DRV_RELDATE "13Jul2008"
54
55 /* PHY CHIP Address */
56 #define PHY1_ADDR 1 /* For MAC1 */
57 #define PHY2_ADDR 2 /* For MAC2 */
58 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61 /* Time in jiffies before concluding the transmitter is hung. */
62 #define TX_TIMEOUT (6000 * HZ / 1000)
63
64 /* RDC MAC I/O Size */
65 #define R6040_IO_SIZE 256
66
67 /* MAX RDC MAC */
68 #define MAX_MAC 2
69
70 /* MAC registers */
71 #define MCR0 0x00 /* Control register 0 */
72 #define MCR1 0x04 /* Control register 1 */
73 #define MAC_RST 0x0001 /* Reset the MAC */
74 #define MBCR 0x08 /* Bus control */
75 #define MT_ICR 0x0C /* TX interrupt control */
76 #define MR_ICR 0x10 /* RX interrupt control */
77 #define MTPR 0x14 /* TX poll command register */
78 #define MR_BSR 0x18 /* RX buffer size */
79 #define MR_DCR 0x1A /* RX descriptor control */
80 #define MLSR 0x1C /* Last status */
81 #define MMDIO 0x20 /* MDIO control register */
82 #define MDIO_WRITE 0x4000 /* MDIO write */
83 #define MDIO_READ 0x2000 /* MDIO read */
84 #define MMRD 0x24 /* MDIO read data register */
85 #define MMWD 0x28 /* MDIO write data register */
86 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
87 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
88 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
89 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
90 #define MISR 0x3C /* Status register */
91 #define MIER 0x40 /* INT enable register */
92 #define MSK_INT 0x0000 /* Mask off interrupts */
93 #define RX_FINISH 0x0001 /* RX finished */
94 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
95 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
96 #define RX_EARLY 0x0008 /* RX early */
97 #define TX_FINISH 0x0010 /* TX finished */
98 #define TX_EARLY 0x0080 /* TX early */
99 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
100 #define LINK_CHANGED 0x0200 /* PHY link changed */
101 #define ME_CISR 0x44 /* Event counter INT status */
102 #define ME_CIER 0x48 /* Event counter INT enable */
103 #define MR_CNT 0x50 /* Successfully received packet counter */
104 #define ME_CNT0 0x52 /* Event counter 0 */
105 #define ME_CNT1 0x54 /* Event counter 1 */
106 #define ME_CNT2 0x56 /* Event counter 2 */
107 #define ME_CNT3 0x58 /* Event counter 3 */
108 #define MT_CNT 0x5A /* Successfully transmit packet counter */
109 #define ME_CNT4 0x5C /* Event counter 4 */
110 #define MP_CNT 0x5E /* Pause frame counter register */
111 #define MAR0 0x60 /* Hash table 0 */
112 #define MAR1 0x62 /* Hash table 1 */
113 #define MAR2 0x64 /* Hash table 2 */
114 #define MAR3 0x66 /* Hash table 3 */
115 #define MID_0L 0x68 /* Multicast address MID0 Low */
116 #define MID_0M 0x6A /* Multicast address MID0 Medium */
117 #define MID_0H 0x6C /* Multicast address MID0 High */
118 #define MID_1L 0x70 /* MID1 Low */
119 #define MID_1M 0x72 /* MID1 Medium */
120 #define MID_1H 0x74 /* MID1 High */
121 #define MID_2L 0x78 /* MID2 Low */
122 #define MID_2M 0x7A /* MID2 Medium */
123 #define MID_2H 0x7C /* MID2 High */
124 #define MID_3L 0x80 /* MID3 Low */
125 #define MID_3M 0x82 /* MID3 Medium */
126 #define MID_3H 0x84 /* MID3 High */
127 #define PHY_CC 0x88 /* PHY status change configuration register */
128 #define PHY_ST 0x8A /* PHY status register */
129 #define MAC_SM 0xAC /* MAC status machine */
130 #define MAC_ID 0xBE /* Identifier register */
131
132 #define TX_DCNT 0x80 /* TX descriptor count */
133 #define RX_DCNT 0x80 /* RX descriptor count */
134 #define MAX_BUF_SIZE 0x600
135 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
137 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
138 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
139
140 /* Descriptor status */
141 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142 #define DSC_RX_OK 0x4000 /* RX was successful */
143 #define DSC_RX_ERR 0x0800 /* RX PHY error */
144 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
155 /* PHY settings */
156 #define ICPLUS_PHY_ID 0x0243
157
158 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
159 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
160 "Florian Fainelli <florian@openwrt.org>");
161 MODULE_LICENSE("GPL");
162 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
163
164 /* RX and TX interrupts that we handle */
165 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
166 #define TX_INTS (TX_FINISH)
167 #define INT_MASK (RX_INTS | TX_INTS)
168
169 struct r6040_descriptor {
170 u16 status, len; /* 0-3 */
171 __le32 buf; /* 4-7 */
172 __le32 ndesc; /* 8-B */
173 u32 rev1; /* C-F */
174 char *vbufp; /* 10-13 */
175 struct r6040_descriptor *vndescp; /* 14-17 */
176 struct sk_buff *skb_ptr; /* 18-1B */
177 u32 rev2; /* 1C-1F */
178 } __attribute__((aligned(32)));
179
180 struct r6040_private {
181 spinlock_t lock; /* driver lock */
182 struct timer_list timer;
183 struct pci_dev *pdev;
184 struct r6040_descriptor *rx_insert_ptr;
185 struct r6040_descriptor *rx_remove_ptr;
186 struct r6040_descriptor *tx_insert_ptr;
187 struct r6040_descriptor *tx_remove_ptr;
188 struct r6040_descriptor *rx_ring;
189 struct r6040_descriptor *tx_ring;
190 dma_addr_t rx_ring_dma;
191 dma_addr_t tx_ring_dma;
192 u16 tx_free_desc, phy_addr, phy_mode;
193 u16 mcr0, mcr1;
194 u16 switch_sig;
195 struct net_device *dev;
196 struct mii_if_info mii_if;
197 struct napi_struct napi;
198 void __iomem *base;
199 };
200
201 static char version[] __devinitdata = KERN_INFO DRV_NAME
202 ": RDC R6040 NAPI net driver,"
203 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
204
205 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
206
207 /* Read a word data from PHY Chip */
208 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
209 {
210 int limit = 2048;
211 u16 cmd;
212
213 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
214 /* Wait for the read bit to be cleared */
215 while (limit--) {
216 cmd = ioread16(ioaddr + MMDIO);
217 if (cmd & MDIO_READ)
218 break;
219 }
220
221 return ioread16(ioaddr + MMRD);
222 }
223
224 /* Write a word data from PHY Chip */
225 static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
226 {
227 int limit = 2048;
228 u16 cmd;
229
230 iowrite16(val, ioaddr + MMWD);
231 /* Write the command to the MDIO bus */
232 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
233 /* Wait for the write bit to be cleared */
234 while (limit--) {
235 cmd = ioread16(ioaddr + MMDIO);
236 if (cmd & MDIO_WRITE)
237 break;
238 }
239 }
240
241 static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
242 {
243 struct r6040_private *lp = netdev_priv(dev);
244 void __iomem *ioaddr = lp->base;
245
246 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
247 }
248
249 static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
250 {
251 struct r6040_private *lp = netdev_priv(dev);
252 void __iomem *ioaddr = lp->base;
253
254 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
255 }
256
257 static void r6040_free_txbufs(struct net_device *dev)
258 {
259 struct r6040_private *lp = netdev_priv(dev);
260 int i;
261
262 for (i = 0; i < TX_DCNT; i++) {
263 if (lp->tx_insert_ptr->skb_ptr) {
264 pci_unmap_single(lp->pdev,
265 le32_to_cpu(lp->tx_insert_ptr->buf),
266 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
267 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
268 lp->tx_insert_ptr->skb_ptr = NULL;
269 }
270 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
271 }
272 }
273
274 static void r6040_free_rxbufs(struct net_device *dev)
275 {
276 struct r6040_private *lp = netdev_priv(dev);
277 int i;
278
279 for (i = 0; i < RX_DCNT; i++) {
280 if (lp->rx_insert_ptr->skb_ptr) {
281 pci_unmap_single(lp->pdev,
282 le32_to_cpu(lp->rx_insert_ptr->buf),
283 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
284 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
285 lp->rx_insert_ptr->skb_ptr = NULL;
286 }
287 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
288 }
289 }
290
291 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
292 dma_addr_t desc_dma, int size)
293 {
294 struct r6040_descriptor *desc = desc_ring;
295 dma_addr_t mapping = desc_dma;
296
297 while (size-- > 0) {
298 mapping += sizeof(*desc);
299 desc->ndesc = cpu_to_le32(mapping);
300 desc->vndescp = desc + 1;
301 desc++;
302 }
303 desc--;
304 desc->ndesc = cpu_to_le32(desc_dma);
305 desc->vndescp = desc_ring;
306 }
307
308 static void r6040_init_txbufs(struct net_device *dev)
309 {
310 struct r6040_private *lp = netdev_priv(dev);
311
312 lp->tx_free_desc = TX_DCNT;
313
314 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
315 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
316 }
317
318 static int r6040_alloc_rxbufs(struct net_device *dev)
319 {
320 struct r6040_private *lp = netdev_priv(dev);
321 struct r6040_descriptor *desc;
322 struct sk_buff *skb;
323 int rc;
324
325 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
326 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
327
328 /* Allocate skbs for the rx descriptors */
329 desc = lp->rx_ring;
330 do {
331 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
332 if (!skb) {
333 printk(KERN_ERR "%s: failed to alloc skb for rx\n", dev->name);
334 rc = -ENOMEM;
335 goto err_exit;
336 }
337 desc->skb_ptr = skb;
338 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
339 desc->skb_ptr->data,
340 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
341 desc->status = DSC_OWNER_MAC;
342 desc = desc->vndescp;
343 } while (desc != lp->rx_ring);
344
345 return 0;
346
347 err_exit:
348 /* Deallocate all previously allocated skbs */
349 r6040_free_rxbufs(dev);
350 return rc;
351 }
352
353 static void r6040_init_mac_regs(struct net_device *dev)
354 {
355 struct r6040_private *lp = netdev_priv(dev);
356 void __iomem *ioaddr = lp->base;
357 int limit = 2048;
358 u16 cmd;
359
360 /* Mask Off Interrupt */
361 iowrite16(MSK_INT, ioaddr + MIER);
362
363 /* Reset RDC MAC */
364 iowrite16(MAC_RST, ioaddr + MCR1);
365 while (limit--) {
366 cmd = ioread16(ioaddr + MCR1);
367 if (cmd & 0x1)
368 break;
369 }
370 /* Reset internal state machine */
371 iowrite16(2, ioaddr + MAC_SM);
372 iowrite16(0, ioaddr + MAC_SM);
373 mdelay(5);
374
375 /* MAC Bus Control Register */
376 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
377
378 /* Buffer Size Register */
379 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
380
381 /* Write TX ring start address */
382 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
383 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
384
385 /* Write RX ring start address */
386 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
387 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
388
389 /* Set interrupt waiting time and packet numbers */
390 iowrite16(0, ioaddr + MT_ICR);
391 iowrite16(0, ioaddr + MR_ICR);
392
393 /* Enable interrupts */
394 iowrite16(INT_MASK, ioaddr + MIER);
395
396 /* Enable TX and RX */
397 iowrite16(lp->mcr0 | 0x0002, ioaddr);
398
399 /* Let TX poll the descriptors
400 * we may got called by r6040_tx_timeout which has left
401 * some unsent tx buffers */
402 iowrite16(0x01, ioaddr + MTPR);
403 }
404
405 static void r6040_tx_timeout(struct net_device *dev)
406 {
407 struct r6040_private *priv = netdev_priv(dev);
408 void __iomem *ioaddr = priv->base;
409
410 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
411 "status %4.4x, PHY status %4.4x\n",
412 dev->name, ioread16(ioaddr + MIER),
413 ioread16(ioaddr + MISR),
414 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
415
416 dev->stats.tx_errors++;
417
418 /* Reset MAC and re-init all registers */
419 r6040_init_mac_regs(dev);
420 }
421
422 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
423 {
424 struct r6040_private *priv = netdev_priv(dev);
425 void __iomem *ioaddr = priv->base;
426 unsigned long flags;
427
428 spin_lock_irqsave(&priv->lock, flags);
429 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
430 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
431 spin_unlock_irqrestore(&priv->lock, flags);
432
433 return &dev->stats;
434 }
435
436 /* Stop RDC MAC and Free the allocated resource */
437 static void r6040_down(struct net_device *dev)
438 {
439 struct r6040_private *lp = netdev_priv(dev);
440 void __iomem *ioaddr = lp->base;
441 struct pci_dev *pdev = lp->pdev;
442 int limit = 2048;
443 u16 *adrp;
444 u16 cmd;
445
446 /* Stop MAC */
447 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
448 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
449 while (limit--) {
450 cmd = ioread16(ioaddr + MCR1);
451 if (cmd & 0x1)
452 break;
453 }
454
455 /* Restore MAC Address to MIDx */
456 adrp = (u16 *) dev->dev_addr;
457 iowrite16(adrp[0], ioaddr + MID_0L);
458 iowrite16(adrp[1], ioaddr + MID_0M);
459 iowrite16(adrp[2], ioaddr + MID_0H);
460 free_irq(dev->irq, dev);
461
462 /* Free RX buffer */
463 r6040_free_rxbufs(dev);
464
465 /* Free TX buffer */
466 r6040_free_txbufs(dev);
467
468 /* Free Descriptor memory */
469 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
470 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
471 }
472
473 static int r6040_close(struct net_device *dev)
474 {
475 struct r6040_private *lp = netdev_priv(dev);
476
477 /* deleted timer */
478 del_timer_sync(&lp->timer);
479
480 spin_lock_irq(&lp->lock);
481 napi_disable(&lp->napi);
482 netif_stop_queue(dev);
483 r6040_down(dev);
484 spin_unlock_irq(&lp->lock);
485
486 return 0;
487 }
488
489 /* Status of PHY CHIP */
490 static int r6040_phy_mode_chk(struct net_device *dev)
491 {
492 struct r6040_private *lp = netdev_priv(dev);
493 void __iomem *ioaddr = lp->base;
494 int phy_dat;
495
496 /* PHY Link Status Check */
497 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
498 if (!(phy_dat & 0x4))
499 phy_dat = 0x8000; /* Link Failed, full duplex */
500
501 /* PHY Chip Auto-Negotiation Status */
502 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
503 if (phy_dat & 0x0020) {
504 /* Auto Negotiation Mode */
505 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
506 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
507 if (phy_dat & 0x140)
508 /* Force full duplex */
509 phy_dat = 0x8000;
510 else
511 phy_dat = 0;
512 } else {
513 /* Force Mode */
514 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
515 if (phy_dat & 0x100)
516 phy_dat = 0x8000;
517 else
518 phy_dat = 0x0000;
519 }
520
521 return phy_dat;
522 };
523
524 static void r6040_set_carrier(struct mii_if_info *mii)
525 {
526 if (r6040_phy_mode_chk(mii->dev)) {
527 /* autoneg is off: Link is always assumed to be up */
528 if (!netif_carrier_ok(mii->dev))
529 netif_carrier_on(mii->dev);
530 } else
531 r6040_phy_mode_chk(mii->dev);
532 }
533
534 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
535 {
536 struct r6040_private *lp = netdev_priv(dev);
537 struct mii_ioctl_data *data = if_mii(rq);
538 int rc;
539
540 if (!netif_running(dev))
541 return -EINVAL;
542 spin_lock_irq(&lp->lock);
543 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
544 spin_unlock_irq(&lp->lock);
545 r6040_set_carrier(&lp->mii_if);
546 return rc;
547 }
548
549 static int r6040_rx(struct net_device *dev, int limit)
550 {
551 struct r6040_private *priv = netdev_priv(dev);
552 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
553 struct sk_buff *skb_ptr, *new_skb;
554 int count = 0;
555 u16 err;
556
557 /* Limit not reached and the descriptor belongs to the CPU */
558 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
559 /* Read the descriptor status */
560 err = descptr->status;
561 /* Global error status set */
562 if (err & DSC_RX_ERR) {
563 /* RX dribble */
564 if (err & DSC_RX_ERR_DRI)
565 dev->stats.rx_frame_errors++;
566 /* Buffer lenght exceeded */
567 if (err & DSC_RX_ERR_BUF)
568 dev->stats.rx_length_errors++;
569 /* Packet too long */
570 if (err & DSC_RX_ERR_LONG)
571 dev->stats.rx_length_errors++;
572 /* Packet < 64 bytes */
573 if (err & DSC_RX_ERR_RUNT)
574 dev->stats.rx_length_errors++;
575 /* CRC error */
576 if (err & DSC_RX_ERR_CRC) {
577 spin_lock(&priv->lock);
578 dev->stats.rx_crc_errors++;
579 spin_unlock(&priv->lock);
580 }
581 goto next_descr;
582 }
583
584 /* Packet successfully received */
585 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
586 if (!new_skb) {
587 dev->stats.rx_dropped++;
588 goto next_descr;
589 }
590 skb_ptr = descptr->skb_ptr;
591 skb_ptr->dev = priv->dev;
592
593 /* Do not count the CRC */
594 skb_put(skb_ptr, descptr->len - 4);
595 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
596 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
597 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
598
599 /* Send to upper layer */
600 netif_receive_skb(skb_ptr);
601 dev->last_rx = jiffies;
602 dev->stats.rx_packets++;
603 dev->stats.rx_bytes += descptr->len - 4;
604
605 /* put new skb into descriptor */
606 descptr->skb_ptr = new_skb;
607 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
608 descptr->skb_ptr->data,
609 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
610
611 next_descr:
612 /* put the descriptor back to the MAC */
613 descptr->status = DSC_OWNER_MAC;
614 descptr = descptr->vndescp;
615 count++;
616 }
617 priv->rx_remove_ptr = descptr;
618
619 return count;
620 }
621
622 static void r6040_tx(struct net_device *dev)
623 {
624 struct r6040_private *priv = netdev_priv(dev);
625 struct r6040_descriptor *descptr;
626 void __iomem *ioaddr = priv->base;
627 struct sk_buff *skb_ptr;
628 u16 err;
629
630 spin_lock(&priv->lock);
631 descptr = priv->tx_remove_ptr;
632 while (priv->tx_free_desc < TX_DCNT) {
633 /* Check for errors */
634 err = ioread16(ioaddr + MLSR);
635
636 if (err & 0x0200)
637 dev->stats.rx_fifo_errors++;
638 if (err & (0x2000 | 0x4000))
639 dev->stats.tx_carrier_errors++;
640
641 if (descptr->status & DSC_OWNER_MAC)
642 break; /* Not complete */
643 skb_ptr = descptr->skb_ptr;
644 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
645 skb_ptr->len, PCI_DMA_TODEVICE);
646 /* Free buffer */
647 dev_kfree_skb_irq(skb_ptr);
648 descptr->skb_ptr = NULL;
649 /* To next descriptor */
650 descptr = descptr->vndescp;
651 priv->tx_free_desc++;
652 }
653 priv->tx_remove_ptr = descptr;
654
655 if (priv->tx_free_desc)
656 netif_wake_queue(dev);
657 spin_unlock(&priv->lock);
658 }
659
660 static int r6040_poll(struct napi_struct *napi, int budget)
661 {
662 struct r6040_private *priv =
663 container_of(napi, struct r6040_private, napi);
664 struct net_device *dev = priv->dev;
665 void __iomem *ioaddr = priv->base;
666 int work_done;
667
668 work_done = r6040_rx(dev, budget);
669
670 if (work_done < budget) {
671 netif_rx_complete(dev, napi);
672 /* Enable RX interrupt */
673 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
674 }
675 return work_done;
676 }
677
678 /* The RDC interrupt handler. */
679 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
680 {
681 struct net_device *dev = dev_id;
682 struct r6040_private *lp = netdev_priv(dev);
683 void __iomem *ioaddr = lp->base;
684 u16 status;
685
686 /* Mask off RDC MAC interrupt */
687 iowrite16(MSK_INT, ioaddr + MIER);
688 /* Read MISR status and clear */
689 status = ioread16(ioaddr + MISR);
690
691 if (status == 0x0000 || status == 0xffff)
692 return IRQ_NONE;
693
694 /* RX interrupt request */
695 if (status & RX_INTS) {
696 if (status & RX_NO_DESC) {
697 /* RX descriptor unavailable */
698 dev->stats.rx_dropped++;
699 dev->stats.rx_missed_errors++;
700 }
701 if (status & RX_FIFO_FULL)
702 dev->stats.rx_fifo_errors++;
703
704 /* Mask off RX interrupt */
705 iowrite16(ioread16(ioaddr + MIER) & ~RX_INTS, ioaddr + MIER);
706 netif_rx_schedule(dev, &lp->napi);
707 }
708
709 /* TX interrupt request */
710 if (status & TX_INTS)
711 r6040_tx(dev);
712
713 return IRQ_HANDLED;
714 }
715
716 #ifdef CONFIG_NET_POLL_CONTROLLER
717 static void r6040_poll_controller(struct net_device *dev)
718 {
719 disable_irq(dev->irq);
720 r6040_interrupt(dev->irq, dev);
721 enable_irq(dev->irq);
722 }
723 #endif
724
725 /* Init RDC MAC */
726 static int r6040_up(struct net_device *dev)
727 {
728 struct r6040_private *lp = netdev_priv(dev);
729 void __iomem *ioaddr = lp->base;
730 int ret;
731
732 /* Initialise and alloc RX/TX buffers */
733 r6040_init_txbufs(dev);
734 ret = r6040_alloc_rxbufs(dev);
735 if (ret)
736 return ret;
737
738 /* Read the PHY ID */
739 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
740
741 if (lp->switch_sig == ICPLUS_PHY_ID) {
742 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
743 lp->phy_mode = 0x8000;
744 } else {
745 /* PHY Mode Check */
746 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
747 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
748
749 if (PHY_MODE == 0x3100)
750 lp->phy_mode = r6040_phy_mode_chk(dev);
751 else
752 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
753 }
754
755 /* Set duplex mode */
756 lp->mcr0 |= lp->phy_mode;
757
758 /* improve performance (by RDC guys) */
759 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
760 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
761 r6040_phy_write(ioaddr, 0, 19, 0x0000);
762 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
763
764 /* Initialize all MAC registers */
765 r6040_init_mac_regs(dev);
766
767 return 0;
768 }
769
770 /*
771 A periodic timer routine
772 Polling PHY Chip Link Status
773 */
774 static void r6040_timer(unsigned long data)
775 {
776 struct net_device *dev = (struct net_device *)data;
777 struct r6040_private *lp = netdev_priv(dev);
778 void __iomem *ioaddr = lp->base;
779 u16 phy_mode;
780
781 /* Polling PHY Chip Status */
782 if (PHY_MODE == 0x3100)
783 phy_mode = r6040_phy_mode_chk(dev);
784 else
785 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
786
787 if (phy_mode != lp->phy_mode) {
788 lp->phy_mode = phy_mode;
789 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
790 iowrite16(lp->mcr0, ioaddr);
791 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
792 }
793
794 /* Timer active again */
795 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
796 }
797
798 /* Read/set MAC address routines */
799 static void r6040_mac_address(struct net_device *dev)
800 {
801 struct r6040_private *lp = netdev_priv(dev);
802 void __iomem *ioaddr = lp->base;
803 u16 *adrp;
804
805 /* MAC operation register */
806 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
807 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
808 iowrite16(0, ioaddr + MAC_SM);
809 mdelay(5);
810
811 /* Restore MAC Address */
812 adrp = (u16 *) dev->dev_addr;
813 iowrite16(adrp[0], ioaddr + MID_0L);
814 iowrite16(adrp[1], ioaddr + MID_0M);
815 iowrite16(adrp[2], ioaddr + MID_0H);
816 }
817
818 static int r6040_open(struct net_device *dev)
819 {
820 struct r6040_private *lp = netdev_priv(dev);
821 int ret;
822
823 /* Request IRQ and Register interrupt handler */
824 ret = request_irq(dev->irq, &r6040_interrupt,
825 IRQF_SHARED, dev->name, dev);
826 if (ret)
827 return ret;
828
829 /* Set MAC address */
830 r6040_mac_address(dev);
831
832 /* Allocate Descriptor memory */
833 lp->rx_ring =
834 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
835 if (!lp->rx_ring)
836 return -ENOMEM;
837
838 lp->tx_ring =
839 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
840 if (!lp->tx_ring) {
841 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
842 lp->rx_ring_dma);
843 return -ENOMEM;
844 }
845
846 ret = r6040_up(dev);
847 if (ret) {
848 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
849 lp->tx_ring_dma);
850 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
851 lp->rx_ring_dma);
852 return ret;
853 }
854
855 napi_enable(&lp->napi);
856 netif_start_queue(dev);
857
858 /* set and active a timer process */
859 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
860 if (lp->switch_sig != ICPLUS_PHY_ID)
861 mod_timer(&lp->timer, jiffies + HZ);
862 return 0;
863 }
864
865 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
866 {
867 struct r6040_private *lp = netdev_priv(dev);
868 struct r6040_descriptor *descptr;
869 void __iomem *ioaddr = lp->base;
870 unsigned long flags;
871 int ret = NETDEV_TX_OK;
872
873 /* Critical Section */
874 spin_lock_irqsave(&lp->lock, flags);
875
876 /* TX resource check */
877 if (!lp->tx_free_desc) {
878 spin_unlock_irqrestore(&lp->lock, flags);
879 netif_stop_queue(dev);
880 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
881 ret = NETDEV_TX_BUSY;
882 return ret;
883 }
884
885 /* Statistic Counter */
886 dev->stats.tx_packets++;
887 dev->stats.tx_bytes += skb->len;
888 /* Set TX descriptor & Transmit it */
889 lp->tx_free_desc--;
890 descptr = lp->tx_insert_ptr;
891 if (skb->len < MISR)
892 descptr->len = MISR;
893 else
894 descptr->len = skb->len;
895
896 descptr->skb_ptr = skb;
897 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
898 skb->data, skb->len, PCI_DMA_TODEVICE));
899 descptr->status = DSC_OWNER_MAC;
900 /* Trigger the MAC to check the TX descriptor */
901 iowrite16(0x01, ioaddr + MTPR);
902 lp->tx_insert_ptr = descptr->vndescp;
903
904 /* If no tx resource, stop */
905 if (!lp->tx_free_desc)
906 netif_stop_queue(dev);
907
908 dev->trans_start = jiffies;
909 spin_unlock_irqrestore(&lp->lock, flags);
910 return ret;
911 }
912
913 static void r6040_multicast_list(struct net_device *dev)
914 {
915 struct r6040_private *lp = netdev_priv(dev);
916 void __iomem *ioaddr = lp->base;
917 u16 *adrp;
918 u16 reg;
919 unsigned long flags;
920 struct dev_mc_list *dmi = dev->mc_list;
921 int i;
922
923 /* MAC Address */
924 adrp = (u16 *)dev->dev_addr;
925 iowrite16(adrp[0], ioaddr + MID_0L);
926 iowrite16(adrp[1], ioaddr + MID_0M);
927 iowrite16(adrp[2], ioaddr + MID_0H);
928
929 /* Promiscous Mode */
930 spin_lock_irqsave(&lp->lock, flags);
931
932 /* Clear AMCP & PROM bits */
933 reg = ioread16(ioaddr) & ~0x0120;
934 if (dev->flags & IFF_PROMISC) {
935 reg |= 0x0020;
936 lp->mcr0 |= 0x0020;
937 }
938 /* Too many multicast addresses
939 * accept all traffic */
940 else if ((dev->mc_count > MCAST_MAX)
941 || (dev->flags & IFF_ALLMULTI))
942 reg |= 0x0020;
943
944 iowrite16(reg, ioaddr);
945 spin_unlock_irqrestore(&lp->lock, flags);
946
947 /* Build the hash table */
948 if (dev->mc_count > MCAST_MAX) {
949 u16 hash_table[4];
950 u32 crc;
951
952 for (i = 0; i < 4; i++)
953 hash_table[i] = 0;
954
955 for (i = 0; i < dev->mc_count; i++) {
956 char *addrs = dmi->dmi_addr;
957
958 dmi = dmi->next;
959
960 if (!(*addrs & 1))
961 continue;
962
963 crc = ether_crc_le(6, addrs);
964 crc >>= 26;
965 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
966 }
967 /* Write the index of the hash table */
968 for (i = 0; i < 4; i++)
969 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
970 /* Fill the MAC hash tables with their values */
971 iowrite16(hash_table[0], ioaddr + MAR0);
972 iowrite16(hash_table[1], ioaddr + MAR1);
973 iowrite16(hash_table[2], ioaddr + MAR2);
974 iowrite16(hash_table[3], ioaddr + MAR3);
975 }
976 /* Multicast Address 1~4 case */
977 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
978 adrp = (u16 *)dmi->dmi_addr;
979 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
980 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
981 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
982 dmi = dmi->next;
983 }
984 for (i = dev->mc_count; i < MCAST_MAX; i++) {
985 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
986 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
987 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
988 }
989 }
990
991 static void netdev_get_drvinfo(struct net_device *dev,
992 struct ethtool_drvinfo *info)
993 {
994 struct r6040_private *rp = netdev_priv(dev);
995
996 strcpy(info->driver, DRV_NAME);
997 strcpy(info->version, DRV_VERSION);
998 strcpy(info->bus_info, pci_name(rp->pdev));
999 }
1000
1001 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1002 {
1003 struct r6040_private *rp = netdev_priv(dev);
1004 int rc;
1005
1006 spin_lock_irq(&rp->lock);
1007 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1008 spin_unlock_irq(&rp->lock);
1009
1010 return rc;
1011 }
1012
1013 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1014 {
1015 struct r6040_private *rp = netdev_priv(dev);
1016 int rc;
1017
1018 spin_lock_irq(&rp->lock);
1019 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1020 spin_unlock_irq(&rp->lock);
1021 r6040_set_carrier(&rp->mii_if);
1022
1023 return rc;
1024 }
1025
1026 static u32 netdev_get_link(struct net_device *dev)
1027 {
1028 struct r6040_private *rp = netdev_priv(dev);
1029
1030 return mii_link_ok(&rp->mii_if);
1031 }
1032
1033 static struct ethtool_ops netdev_ethtool_ops = {
1034 .get_drvinfo = netdev_get_drvinfo,
1035 .get_settings = netdev_get_settings,
1036 .set_settings = netdev_set_settings,
1037 .get_link = netdev_get_link,
1038 };
1039
1040 static int __devinit r6040_init_one(struct pci_dev *pdev,
1041 const struct pci_device_id *ent)
1042 {
1043 struct net_device *dev;
1044 struct r6040_private *lp;
1045 void __iomem *ioaddr;
1046 int err, io_size = R6040_IO_SIZE;
1047 static int card_idx = -1;
1048 int bar = 0;
1049 long pioaddr;
1050 u16 *adrp;
1051
1052 printk(KERN_INFO "%s\n", version);
1053
1054 err = pci_enable_device(pdev);
1055 if (err)
1056 goto err_out;
1057
1058 /* this should always be supported */
1059 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1060 if (err) {
1061 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1062 "not supported by the card\n");
1063 goto err_out;
1064 }
1065 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1066 if (err) {
1067 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1068 "not supported by the card\n");
1069 goto err_out;
1070 }
1071
1072 /* IO Size check */
1073 if (pci_resource_len(pdev, 0) < io_size) {
1074 printk(KERN_ERR DRV_NAME "Insufficient PCI resources, aborting\n");
1075 err = -EIO;
1076 goto err_out;
1077 }
1078
1079 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1080 pci_set_master(pdev);
1081
1082 dev = alloc_etherdev(sizeof(struct r6040_private));
1083 if (!dev) {
1084 printk(KERN_ERR DRV_NAME "Failed to allocate etherdev\n");
1085 err = -ENOMEM;
1086 goto err_out;
1087 }
1088 SET_NETDEV_DEV(dev, &pdev->dev);
1089 lp = netdev_priv(dev);
1090
1091 err = pci_request_regions(pdev, DRV_NAME);
1092
1093 if (err) {
1094 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1095 goto err_out_free_dev;
1096 }
1097
1098 ioaddr = pci_iomap(pdev, bar, io_size);
1099 if (!ioaddr) {
1100 printk(KERN_ERR "ioremap failed for device %s\n",
1101 pci_name(pdev));
1102 err = -EIO;
1103 goto err_out_free_res;
1104 }
1105
1106 /* Init system & device */
1107 lp->base = ioaddr;
1108 dev->irq = pdev->irq;
1109
1110 spin_lock_init(&lp->lock);
1111 pci_set_drvdata(pdev, dev);
1112
1113 /* Set MAC address */
1114 card_idx++;
1115
1116 adrp = (u16 *)dev->dev_addr;
1117 adrp[0] = ioread16(ioaddr + MID_0L);
1118 adrp[1] = ioread16(ioaddr + MID_0M);
1119 adrp[2] = ioread16(ioaddr + MID_0H);
1120
1121 /* Link new device into r6040_root_dev */
1122 lp->pdev = pdev;
1123 lp->dev = dev;
1124
1125 /* Init RDC private data */
1126 lp->mcr0 = 0x1002;
1127 lp->phy_addr = phy_table[card_idx];
1128 lp->switch_sig = 0;
1129
1130 /* The RDC-specific entries in the device structure. */
1131 dev->open = &r6040_open;
1132 dev->hard_start_xmit = &r6040_start_xmit;
1133 dev->stop = &r6040_close;
1134 dev->get_stats = r6040_get_stats;
1135 dev->set_multicast_list = &r6040_multicast_list;
1136 dev->do_ioctl = &r6040_ioctl;
1137 dev->ethtool_ops = &netdev_ethtool_ops;
1138 dev->tx_timeout = &r6040_tx_timeout;
1139 dev->watchdog_timeo = TX_TIMEOUT;
1140 #ifdef CONFIG_NET_POLL_CONTROLLER
1141 dev->poll_controller = r6040_poll_controller;
1142 #endif
1143 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1144 lp->mii_if.dev = dev;
1145 lp->mii_if.mdio_read = r6040_mdio_read;
1146 lp->mii_if.mdio_write = r6040_mdio_write;
1147 lp->mii_if.phy_id = lp->phy_addr;
1148 lp->mii_if.phy_id_mask = 0x1f;
1149 lp->mii_if.reg_num_mask = 0x1f;
1150
1151 /* Register net device. After this dev->name assign */
1152 err = register_netdev(dev);
1153 if (err) {
1154 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1155 goto err_out_unmap;
1156 }
1157 return 0;
1158
1159 err_out_unmap:
1160 pci_iounmap(pdev, ioaddr);
1161 err_out_free_res:
1162 pci_release_regions(pdev);
1163 err_out_free_dev:
1164 free_netdev(dev);
1165 err_out:
1166 return err;
1167 }
1168
1169 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1170 {
1171 struct net_device *dev = pci_get_drvdata(pdev);
1172
1173 unregister_netdev(dev);
1174 pci_release_regions(pdev);
1175 free_netdev(dev);
1176 pci_disable_device(pdev);
1177 pci_set_drvdata(pdev, NULL);
1178 }
1179
1180
1181 static struct pci_device_id r6040_pci_tbl[] = {
1182 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1183 { 0 }
1184 };
1185 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1186
1187 static struct pci_driver r6040_driver = {
1188 .name = DRV_NAME,
1189 .id_table = r6040_pci_tbl,
1190 .probe = r6040_init_one,
1191 .remove = __devexit_p(r6040_remove_one),
1192 };
1193
1194
1195 static int __init r6040_init(void)
1196 {
1197 return pci_register_driver(&r6040_driver);
1198 }
1199
1200
1201 static void __exit r6040_cleanup(void)
1202 {
1203 pci_unregister_driver(&r6040_driver);
1204 }
1205
1206 module_init(r6040_init);
1207 module_exit(r6040_cleanup);
Stable & featurefull patchset based on Linus's git branch