2 * sata_sil.c - Silicon Image SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
33 * Other errata and documentation available under NDA.
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "0.9"
52 SIL_FLAG_MOD15WRITE
= (1 << 30),
68 SIL_MASK_IDE0_INT
= (1 << 22),
69 SIL_MASK_IDE1_INT
= (1 << 23),
70 SIL_MASK_IDE2_INT
= (1 << 24),
71 SIL_MASK_IDE3_INT
= (1 << 25),
72 SIL_MASK_2PORT
= SIL_MASK_IDE0_INT
| SIL_MASK_IDE1_INT
,
73 SIL_MASK_4PORT
= SIL_MASK_2PORT
|
74 SIL_MASK_IDE2_INT
| SIL_MASK_IDE3_INT
,
76 SIL_IDE2_BMDMA
= 0x200,
78 SIL_INTR_STEERING
= (1 << 1),
79 SIL_QUIRK_MOD15WRITE
= (1 << 0),
80 SIL_QUIRK_UDMA5MAX
= (1 << 1),
83 static int sil_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
84 static void sil_dev_config(struct ata_port
*ap
, struct ata_device
*dev
);
85 static u32
sil_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
86 static void sil_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
87 static void sil_post_set_mode (struct ata_port
*ap
);
90 static const struct pci_device_id sil_pci_tbl
[] = {
91 { 0x1095, 0x3112, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112_m15w
},
92 { 0x1095, 0x0240, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112_m15w
},
93 { 0x1095, 0x3512, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
94 { 0x1095, 0x3114, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3114
},
95 { 0x1002, 0x436e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112_m15w
},
96 { 0x1002, 0x4379, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112_m15w
},
97 { 0x1002, 0x437a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112_m15w
},
98 { } /* terminate list */
102 /* TODO firmware versions should be added - eric */
103 static const struct sil_drivelist
{
104 const char * product
;
106 } sil_blacklist
[] = {
107 { "ST320012AS", SIL_QUIRK_MOD15WRITE
},
108 { "ST330013AS", SIL_QUIRK_MOD15WRITE
},
109 { "ST340017AS", SIL_QUIRK_MOD15WRITE
},
110 { "ST360015AS", SIL_QUIRK_MOD15WRITE
},
111 { "ST380013AS", SIL_QUIRK_MOD15WRITE
},
112 { "ST380023AS", SIL_QUIRK_MOD15WRITE
},
113 { "ST3120023AS", SIL_QUIRK_MOD15WRITE
},
114 { "ST3160023AS", SIL_QUIRK_MOD15WRITE
},
115 { "ST3120026AS", SIL_QUIRK_MOD15WRITE
},
116 { "ST3200822AS", SIL_QUIRK_MOD15WRITE
},
117 { "ST340014ASL", SIL_QUIRK_MOD15WRITE
},
118 { "ST360014ASL", SIL_QUIRK_MOD15WRITE
},
119 { "ST380011ASL", SIL_QUIRK_MOD15WRITE
},
120 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE
},
121 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE
},
122 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX
},
126 static struct pci_driver sil_pci_driver
= {
128 .id_table
= sil_pci_tbl
,
129 .probe
= sil_init_one
,
130 .remove
= ata_pci_remove_one
,
133 static struct scsi_host_template sil_sht
= {
134 .module
= THIS_MODULE
,
136 .ioctl
= ata_scsi_ioctl
,
137 .queuecommand
= ata_scsi_queuecmd
,
138 .eh_timed_out
= ata_scsi_timed_out
,
139 .eh_strategy_handler
= ata_scsi_error
,
140 .can_queue
= ATA_DEF_QUEUE
,
141 .this_id
= ATA_SHT_THIS_ID
,
142 .sg_tablesize
= LIBATA_MAX_PRD
,
143 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
144 .emulated
= ATA_SHT_EMULATED
,
145 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
146 .proc_name
= DRV_NAME
,
147 .dma_boundary
= ATA_DMA_BOUNDARY
,
148 .slave_configure
= ata_scsi_slave_config
,
149 .bios_param
= ata_std_bios_param
,
152 static const struct ata_port_operations sil_ops
= {
153 .port_disable
= ata_port_disable
,
154 .dev_config
= sil_dev_config
,
155 .tf_load
= ata_tf_load
,
156 .tf_read
= ata_tf_read
,
157 .check_status
= ata_check_status
,
158 .exec_command
= ata_exec_command
,
159 .dev_select
= ata_std_dev_select
,
160 .probe_reset
= ata_std_probe_reset
,
161 .post_set_mode
= sil_post_set_mode
,
162 .bmdma_setup
= ata_bmdma_setup
,
163 .bmdma_start
= ata_bmdma_start
,
164 .bmdma_stop
= ata_bmdma_stop
,
165 .bmdma_status
= ata_bmdma_status
,
166 .qc_prep
= ata_qc_prep
,
167 .qc_issue
= ata_qc_issue_prot
,
168 .eng_timeout
= ata_eng_timeout
,
169 .irq_handler
= ata_interrupt
,
170 .irq_clear
= ata_bmdma_irq_clear
,
171 .scr_read
= sil_scr_read
,
172 .scr_write
= sil_scr_write
,
173 .port_start
= ata_port_start
,
174 .port_stop
= ata_port_stop
,
175 .host_stop
= ata_pci_host_stop
,
178 static const struct ata_port_info sil_port_info
[] = {
182 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
184 .pio_mask
= 0x1f, /* pio0-4 */
185 .mwdma_mask
= 0x07, /* mwdma0-2 */
186 .udma_mask
= 0x3f, /* udma0-5 */
187 .port_ops
= &sil_ops
,
188 }, /* sil_3112_15w - keep it sync'd w/ sil_3112 */
191 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
192 ATA_FLAG_MMIO
| SIL_FLAG_MOD15WRITE
,
193 .pio_mask
= 0x1f, /* pio0-4 */
194 .mwdma_mask
= 0x07, /* mwdma0-2 */
195 .udma_mask
= 0x3f, /* udma0-5 */
196 .port_ops
= &sil_ops
,
200 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
202 .pio_mask
= 0x1f, /* pio0-4 */
203 .mwdma_mask
= 0x07, /* mwdma0-2 */
204 .udma_mask
= 0x3f, /* udma0-5 */
205 .port_ops
= &sil_ops
,
209 /* per-port register offsets */
210 /* TODO: we can probably calculate rather than use a table */
211 static const struct {
212 unsigned long tf
; /* ATA taskfile register block */
213 unsigned long ctl
; /* ATA control/altstatus register block */
214 unsigned long bmdma
; /* DMA register block */
215 unsigned long scr
; /* SATA control register block */
216 unsigned long sien
; /* SATA Interrupt Enable register */
217 unsigned long xfer_mode
;/* data transfer mode register */
220 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
221 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
222 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
223 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
227 MODULE_AUTHOR("Jeff Garzik");
228 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
229 MODULE_LICENSE("GPL");
230 MODULE_DEVICE_TABLE(pci
, sil_pci_tbl
);
231 MODULE_VERSION(DRV_VERSION
);
233 static int slow_down
= 0;
234 module_param(slow_down
, int, 0444);
235 MODULE_PARM_DESC(slow_down
, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
238 static unsigned char sil_get_device_cache_line(struct pci_dev
*pdev
)
241 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &cache_line
);
245 static void sil_post_set_mode (struct ata_port
*ap
)
247 struct ata_host_set
*host_set
= ap
->host_set
;
248 struct ata_device
*dev
;
250 host_set
->mmio_base
+ sil_port
[ap
->port_no
].xfer_mode
;
251 u32 tmp
, dev_mode
[2];
254 for (i
= 0; i
< 2; i
++) {
255 dev
= &ap
->device
[i
];
256 if (!ata_dev_present(dev
))
257 dev_mode
[i
] = 0; /* PIO0/1/2 */
258 else if (dev
->flags
& ATA_DFLAG_PIO
)
259 dev_mode
[i
] = 1; /* PIO3/4 */
261 dev_mode
[i
] = 3; /* UDMA */
262 /* value 2 indicates MDMA */
266 tmp
&= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
268 tmp
|= (dev_mode
[1] << 4);
270 readl(addr
); /* flush */
273 static inline unsigned long sil_scr_addr(struct ata_port
*ap
, unsigned int sc_reg
)
275 unsigned long offset
= ap
->ioaddr
.scr_addr
;
292 static u32
sil_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
294 void __iomem
*mmio
= (void __iomem
*) sil_scr_addr(ap
, sc_reg
);
300 static void sil_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
302 void *mmio
= (void __iomem
*) sil_scr_addr(ap
, sc_reg
);
308 * sil_dev_config - Apply device/host-specific errata fixups
309 * @ap: Port containing device to be examined
310 * @dev: Device to be examined
312 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
313 * device is known to be present, this function is called.
314 * We apply two errata fixups which are specific to Silicon Image,
315 * a Seagate and a Maxtor fixup.
317 * For certain Seagate devices, we must limit the maximum sectors
320 * For certain Maxtor devices, we must not program the drive
323 * Both fixups are unfairly pessimistic. As soon as I get more
324 * information on these errata, I will create a more exhaustive
325 * list, and apply the fixups to only the specific
326 * devices/hosts/firmwares that need it.
328 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
329 * The Maxtor quirk is in the blacklist, but I'm keeping the original
330 * pessimistic fix for the following reasons...
331 * - There seems to be less info on it, only one device gleaned off the
332 * Windows driver, maybe only one is affected. More info would be greatly
334 * - But then again UDMA5 is hardly anything to complain about
336 static void sil_dev_config(struct ata_port
*ap
, struct ata_device
*dev
)
338 unsigned int n
, quirks
= 0;
339 unsigned char model_num
[41];
341 ata_dev_id_c_string(dev
->id
, model_num
, ATA_ID_PROD_OFS
,
344 for (n
= 0; sil_blacklist
[n
].product
; n
++)
345 if (!strcmp(sil_blacklist
[n
].product
, model_num
)) {
346 quirks
= sil_blacklist
[n
].quirk
;
350 /* limit requests to 15 sectors */
352 ((ap
->flags
& SIL_FLAG_MOD15WRITE
) &&
353 (quirks
& SIL_QUIRK_MOD15WRITE
))) {
354 printk(KERN_INFO
"ata%u(%u): applying Seagate errata fix (mod15write workaround)\n",
356 dev
->max_sectors
= 15;
361 if (quirks
& SIL_QUIRK_UDMA5MAX
) {
362 printk(KERN_INFO
"ata%u(%u): applying Maxtor errata fix %s\n",
363 ap
->id
, dev
->devno
, model_num
);
364 ap
->udma_mask
&= ATA_UDMA5
;
369 static int sil_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
371 static int printed_version
;
372 struct ata_probe_ent
*probe_ent
= NULL
;
374 void __iomem
*mmio_base
;
377 int pci_dev_busy
= 0;
381 if (!printed_version
++)
382 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
385 * If this driver happens to only be useful on Apple's K2, then
386 * we should check that here as it has a normal Serverworks ID
388 rc
= pci_enable_device(pdev
);
392 rc
= pci_request_regions(pdev
, DRV_NAME
);
398 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
400 goto err_out_regions
;
401 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
403 goto err_out_regions
;
405 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
406 if (probe_ent
== NULL
) {
408 goto err_out_regions
;
411 memset(probe_ent
, 0, sizeof(*probe_ent
));
412 INIT_LIST_HEAD(&probe_ent
->node
);
413 probe_ent
->dev
= pci_dev_to_dev(pdev
);
414 probe_ent
->port_ops
= sil_port_info
[ent
->driver_data
].port_ops
;
415 probe_ent
->sht
= sil_port_info
[ent
->driver_data
].sht
;
416 probe_ent
->n_ports
= (ent
->driver_data
== sil_3114
) ? 4 : 2;
417 probe_ent
->pio_mask
= sil_port_info
[ent
->driver_data
].pio_mask
;
418 probe_ent
->mwdma_mask
= sil_port_info
[ent
->driver_data
].mwdma_mask
;
419 probe_ent
->udma_mask
= sil_port_info
[ent
->driver_data
].udma_mask
;
420 probe_ent
->irq
= pdev
->irq
;
421 probe_ent
->irq_flags
= SA_SHIRQ
;
422 probe_ent
->host_flags
= sil_port_info
[ent
->driver_data
].host_flags
;
424 mmio_base
= pci_iomap(pdev
, 5, 0);
425 if (mmio_base
== NULL
) {
427 goto err_out_free_ent
;
430 probe_ent
->mmio_base
= mmio_base
;
432 base
= (unsigned long) mmio_base
;
434 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
435 probe_ent
->port
[i
].cmd_addr
= base
+ sil_port
[i
].tf
;
436 probe_ent
->port
[i
].altstatus_addr
=
437 probe_ent
->port
[i
].ctl_addr
= base
+ sil_port
[i
].ctl
;
438 probe_ent
->port
[i
].bmdma_addr
= base
+ sil_port
[i
].bmdma
;
439 probe_ent
->port
[i
].scr_addr
= base
+ sil_port
[i
].scr
;
440 ata_std_ports(&probe_ent
->port
[i
]);
443 /* Initialize FIFO PCI bus arbitration */
444 cls
= sil_get_device_cache_line(pdev
);
447 cls
++; /* cls = (line_size/8)+1 */
448 writeb(cls
, mmio_base
+ SIL_FIFO_R0
);
449 writeb(cls
, mmio_base
+ SIL_FIFO_W0
);
450 writeb(cls
, mmio_base
+ SIL_FIFO_R1
);
451 writeb(cls
, mmio_base
+ SIL_FIFO_W1
);
452 if (ent
->driver_data
== sil_3114
) {
453 writeb(cls
, mmio_base
+ SIL_FIFO_R2
);
454 writeb(cls
, mmio_base
+ SIL_FIFO_W2
);
455 writeb(cls
, mmio_base
+ SIL_FIFO_R3
);
456 writeb(cls
, mmio_base
+ SIL_FIFO_W3
);
459 dev_printk(KERN_WARNING
, &pdev
->dev
,
460 "cache line size not set. Driver may not function\n");
462 if (ent
->driver_data
== sil_3114
) {
463 irq_mask
= SIL_MASK_4PORT
;
465 /* flip the magic "make 4 ports work" bit */
466 tmp
= readl(mmio_base
+ SIL_IDE2_BMDMA
);
467 if ((tmp
& SIL_INTR_STEERING
) == 0)
468 writel(tmp
| SIL_INTR_STEERING
,
469 mmio_base
+ SIL_IDE2_BMDMA
);
472 irq_mask
= SIL_MASK_2PORT
;
475 /* make sure IDE0/1/2/3 interrupts are not masked */
476 tmp
= readl(mmio_base
+ SIL_SYSCFG
);
477 if (tmp
& irq_mask
) {
479 writel(tmp
, mmio_base
+ SIL_SYSCFG
);
480 readl(mmio_base
+ SIL_SYSCFG
); /* flush */
483 /* mask all SATA phy-related interrupts */
484 /* TODO: unmask bit 6 (SError N bit) for hotplug */
485 for (i
= 0; i
< probe_ent
->n_ports
; i
++)
486 writel(0, mmio_base
+ sil_port
[i
].sien
);
488 pci_set_master(pdev
);
490 /* FIXME: check ata_device_add return value */
491 ata_device_add(probe_ent
);
499 pci_release_regions(pdev
);
502 pci_disable_device(pdev
);
506 static int __init
sil_init(void)
508 return pci_module_init(&sil_pci_driver
);
511 static void __exit
sil_exit(void)
513 pci_unregister_driver(&sil_pci_driver
);
517 module_init(sil_init
);
518 module_exit(sil_exit
);