2 * sata_sx4.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_sx4"
49 #define DRV_VERSION "0.8"
53 PDC_PRD_TBL
= 0x44, /* Direct command DMA table addr */
55 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
56 PDC_HDMA_PKT_SUBMIT
= 0x100, /* Host DMA packet pointer addr */
57 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
58 PDC_HDMA_CTLSTAT
= 0x12C, /* Host DMA control / status */
60 PDC_20621_SEQCTL
= 0x400,
61 PDC_20621_SEQMASK
= 0x480,
62 PDC_20621_GENERAL_CTL
= 0x484,
63 PDC_20621_PAGE_SIZE
= (32 * 1024),
65 /* chosen, not constant, values; we design our own DIMM mem map */
66 PDC_20621_DIMM_WINDOW
= 0x0C, /* page# for 32K DIMM window */
67 PDC_20621_DIMM_BASE
= 0x00200000,
68 PDC_20621_DIMM_DATA
= (64 * 1024),
69 PDC_DIMM_DATA_STEP
= (256 * 1024),
70 PDC_DIMM_WINDOW_STEP
= (8 * 1024),
71 PDC_DIMM_HOST_PRD
= (6 * 1024),
72 PDC_DIMM_HOST_PKT
= (128 * 0),
73 PDC_DIMM_HPKT_PRD
= (128 * 1),
74 PDC_DIMM_ATA_PKT
= (128 * 2),
75 PDC_DIMM_APKT_PRD
= (128 * 3),
76 PDC_DIMM_HEADER_SZ
= PDC_DIMM_APKT_PRD
+ 128,
77 PDC_PAGE_WINDOW
= 0x40,
78 PDC_PAGE_DATA
= PDC_PAGE_WINDOW
+
79 (PDC_20621_DIMM_DATA
/ PDC_20621_PAGE_SIZE
),
80 PDC_PAGE_SET
= PDC_DIMM_DATA_STEP
/ PDC_20621_PAGE_SIZE
,
82 PDC_CHIP0_OFS
= 0xC0000, /* offset of chip #0 */
84 PDC_20621_ERR_MASK
= (1<<19) | (1<<20) | (1<<21) | (1<<22) |
87 board_20621
= 0, /* FastTrak S150 SX4 */
89 PDC_RESET
= (1 << 11), /* HDMA reset */
92 PDC_HDMA_Q_MASK
= (PDC_MAX_HDMA
- 1),
94 PDC_DIMM0_SPD_DEV_ADDRESS
= 0x50,
95 PDC_DIMM1_SPD_DEV_ADDRESS
= 0x51,
96 PDC_MAX_DIMM_MODULE
= 0x02,
97 PDC_I2C_CONTROL_OFFSET
= 0x48,
98 PDC_I2C_ADDR_DATA_OFFSET
= 0x4C,
99 PDC_DIMM0_CONTROL_OFFSET
= 0x80,
100 PDC_DIMM1_CONTROL_OFFSET
= 0x84,
101 PDC_SDRAM_CONTROL_OFFSET
= 0x88,
102 PDC_I2C_WRITE
= 0x00000000,
103 PDC_I2C_READ
= 0x00000040,
104 PDC_I2C_START
= 0x00000080,
105 PDC_I2C_MASK_INT
= 0x00000020,
106 PDC_I2C_COMPLETE
= 0x00010000,
107 PDC_I2C_NO_ACK
= 0x00100000,
108 PDC_DIMM_SPD_SUBADDRESS_START
= 0x00,
109 PDC_DIMM_SPD_SUBADDRESS_END
= 0x7F,
110 PDC_DIMM_SPD_ROW_NUM
= 3,
111 PDC_DIMM_SPD_COLUMN_NUM
= 4,
112 PDC_DIMM_SPD_MODULE_ROW
= 5,
113 PDC_DIMM_SPD_TYPE
= 11,
114 PDC_DIMM_SPD_FRESH_RATE
= 12,
115 PDC_DIMM_SPD_BANK_NUM
= 17,
116 PDC_DIMM_SPD_CAS_LATENCY
= 18,
117 PDC_DIMM_SPD_ATTRIBUTE
= 21,
118 PDC_DIMM_SPD_ROW_PRE_CHARGE
= 27,
119 PDC_DIMM_SPD_ROW_ACTIVE_DELAY
= 28,
120 PDC_DIMM_SPD_RAS_CAS_DELAY
= 29,
121 PDC_DIMM_SPD_ACTIVE_PRECHARGE
= 30,
122 PDC_DIMM_SPD_SYSTEM_FREQ
= 126,
123 PDC_CTL_STATUS
= 0x08,
124 PDC_DIMM_WINDOW_CTLR
= 0x0C,
125 PDC_TIME_CONTROL
= 0x3C,
126 PDC_TIME_PERIOD
= 0x40,
127 PDC_TIME_COUNTER
= 0x44,
128 PDC_GENERAL_CTLR
= 0x484,
129 PCI_PLL_INIT
= 0x8A531824,
130 PCI_X_TCOUNT
= 0xEE1E5CFF
134 struct pdc_port_priv
{
135 u8 dimm_buf
[(ATA_PRD_SZ
* ATA_MAX_PRD
) + 512];
140 struct pdc_host_priv
{
141 void __iomem
*dimm_mmio
;
143 unsigned int doing_hdma
;
144 unsigned int hdma_prod
;
145 unsigned int hdma_cons
;
147 struct ata_queued_cmd
*qc
;
149 unsigned long pkt_ofs
;
154 static int pdc_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
155 static irqreturn_t
pdc20621_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
156 static void pdc_eng_timeout(struct ata_port
*ap
);
157 static void pdc_20621_phy_reset (struct ata_port
*ap
);
158 static int pdc_port_start(struct ata_port
*ap
);
159 static void pdc_port_stop(struct ata_port
*ap
);
160 static void pdc20621_qc_prep(struct ata_queued_cmd
*qc
);
161 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
162 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
163 static void pdc20621_host_stop(struct ata_host_set
*host_set
);
164 static unsigned int pdc20621_dimm_init(struct ata_probe_ent
*pe
);
165 static int pdc20621_detect_dimm(struct ata_probe_ent
*pe
);
166 static unsigned int pdc20621_i2c_read(struct ata_probe_ent
*pe
,
167 u32 device
, u32 subaddr
, u32
*pdata
);
168 static int pdc20621_prog_dimm0(struct ata_probe_ent
*pe
);
169 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent
*pe
);
170 #ifdef ATA_VERBOSE_DEBUG
171 static void pdc20621_get_from_dimm(struct ata_probe_ent
*pe
,
172 void *psource
, u32 offset
, u32 size
);
174 static void pdc20621_put_to_dimm(struct ata_probe_ent
*pe
,
175 void *psource
, u32 offset
, u32 size
);
176 static void pdc20621_irq_clear(struct ata_port
*ap
);
177 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd
*qc
);
180 static struct scsi_host_template pdc_sata_sht
= {
181 .module
= THIS_MODULE
,
183 .ioctl
= ata_scsi_ioctl
,
184 .queuecommand
= ata_scsi_queuecmd
,
185 .eh_timed_out
= ata_scsi_timed_out
,
186 .eh_strategy_handler
= ata_scsi_error
,
187 .can_queue
= ATA_DEF_QUEUE
,
188 .this_id
= ATA_SHT_THIS_ID
,
189 .sg_tablesize
= LIBATA_MAX_PRD
,
190 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
191 .emulated
= ATA_SHT_EMULATED
,
192 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
193 .proc_name
= DRV_NAME
,
194 .dma_boundary
= ATA_DMA_BOUNDARY
,
195 .slave_configure
= ata_scsi_slave_config
,
196 .bios_param
= ata_std_bios_param
,
199 static const struct ata_port_operations pdc_20621_ops
= {
200 .port_disable
= ata_port_disable
,
201 .tf_load
= pdc_tf_load_mmio
,
202 .tf_read
= ata_tf_read
,
203 .check_status
= ata_check_status
,
204 .exec_command
= pdc_exec_command_mmio
,
205 .dev_select
= ata_std_dev_select
,
206 .phy_reset
= pdc_20621_phy_reset
,
207 .qc_prep
= pdc20621_qc_prep
,
208 .qc_issue
= pdc20621_qc_issue_prot
,
209 .eng_timeout
= pdc_eng_timeout
,
210 .irq_handler
= pdc20621_interrupt
,
211 .irq_clear
= pdc20621_irq_clear
,
212 .port_start
= pdc_port_start
,
213 .port_stop
= pdc_port_stop
,
214 .host_stop
= pdc20621_host_stop
,
217 static const struct ata_port_info pdc_port_info
[] = {
220 .sht
= &pdc_sata_sht
,
221 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
222 ATA_FLAG_SRST
| ATA_FLAG_MMIO
|
223 ATA_FLAG_PIO_POLLING
,
224 .pio_mask
= 0x1f, /* pio0-4 */
225 .mwdma_mask
= 0x07, /* mwdma0-2 */
226 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
227 .port_ops
= &pdc_20621_ops
,
232 static const struct pci_device_id pdc_sata_pci_tbl
[] = {
233 { PCI_VENDOR_ID_PROMISE
, 0x6622, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
235 { } /* terminate list */
239 static struct pci_driver pdc_sata_pci_driver
= {
241 .id_table
= pdc_sata_pci_tbl
,
242 .probe
= pdc_sata_init_one
,
243 .remove
= ata_pci_remove_one
,
247 static void pdc20621_host_stop(struct ata_host_set
*host_set
)
249 struct pci_dev
*pdev
= to_pci_dev(host_set
->dev
);
250 struct pdc_host_priv
*hpriv
= host_set
->private_data
;
251 void __iomem
*dimm_mmio
= hpriv
->dimm_mmio
;
253 pci_iounmap(pdev
, dimm_mmio
);
256 pci_iounmap(pdev
, host_set
->mmio_base
);
259 static int pdc_port_start(struct ata_port
*ap
)
261 struct device
*dev
= ap
->host_set
->dev
;
262 struct pdc_port_priv
*pp
;
265 rc
= ata_port_start(ap
);
269 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
274 memset(pp
, 0, sizeof(*pp
));
276 pp
->pkt
= dma_alloc_coherent(dev
, 128, &pp
->pkt_dma
, GFP_KERNEL
);
282 ap
->private_data
= pp
;
294 static void pdc_port_stop(struct ata_port
*ap
)
296 struct device
*dev
= ap
->host_set
->dev
;
297 struct pdc_port_priv
*pp
= ap
->private_data
;
299 ap
->private_data
= NULL
;
300 dma_free_coherent(dev
, 128, pp
->pkt
, pp
->pkt_dma
);
306 static void pdc_20621_phy_reset (struct ata_port
*ap
)
309 ap
->cbl
= ATA_CBL_SATA
;
314 static inline void pdc20621_ata_sg(struct ata_taskfile
*tf
, u8
*buf
,
316 unsigned int total_len
)
319 unsigned int dw
= PDC_DIMM_APKT_PRD
>> 2;
320 u32
*buf32
= (u32
*) buf
;
322 /* output ATA packet S/G table */
323 addr
= PDC_20621_DIMM_BASE
+ PDC_20621_DIMM_DATA
+
324 (PDC_DIMM_DATA_STEP
* portno
);
325 VPRINTK("ATA sg addr 0x%x, %d\n", addr
, addr
);
326 buf32
[dw
] = cpu_to_le32(addr
);
327 buf32
[dw
+ 1] = cpu_to_le32(total_len
| ATA_PRD_EOT
);
329 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
330 PDC_20621_DIMM_BASE
+
331 (PDC_DIMM_WINDOW_STEP
* portno
) +
333 buf32
[dw
], buf32
[dw
+ 1]);
336 static inline void pdc20621_host_sg(struct ata_taskfile
*tf
, u8
*buf
,
338 unsigned int total_len
)
341 unsigned int dw
= PDC_DIMM_HPKT_PRD
>> 2;
342 u32
*buf32
= (u32
*) buf
;
344 /* output Host DMA packet S/G table */
345 addr
= PDC_20621_DIMM_BASE
+ PDC_20621_DIMM_DATA
+
346 (PDC_DIMM_DATA_STEP
* portno
);
348 buf32
[dw
] = cpu_to_le32(addr
);
349 buf32
[dw
+ 1] = cpu_to_le32(total_len
| ATA_PRD_EOT
);
351 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
352 PDC_20621_DIMM_BASE
+
353 (PDC_DIMM_WINDOW_STEP
* portno
) +
355 buf32
[dw
], buf32
[dw
+ 1]);
358 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile
*tf
,
359 unsigned int devno
, u8
*buf
,
363 u32
*buf32
= (u32
*) buf
;
366 unsigned int dimm_sg
= PDC_20621_DIMM_BASE
+
367 (PDC_DIMM_WINDOW_STEP
* portno
) +
369 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg
, dimm_sg
);
371 i
= PDC_DIMM_ATA_PKT
;
376 if ((tf
->protocol
== ATA_PROT_DMA
) && (!(tf
->flags
& ATA_TFLAG_WRITE
)))
377 buf
[i
++] = PDC_PKT_READ
;
378 else if (tf
->protocol
== ATA_PROT_NODATA
)
379 buf
[i
++] = PDC_PKT_NODATA
;
382 buf
[i
++] = 0; /* reserved */
383 buf
[i
++] = portno
+ 1; /* seq. id */
384 buf
[i
++] = 0xff; /* delay seq. id */
386 /* dimm dma S/G, and next-pkt */
388 if (tf
->protocol
== ATA_PROT_NODATA
)
391 buf32
[dw
] = cpu_to_le32(dimm_sg
);
396 dev_reg
= ATA_DEVICE_OBS
;
398 dev_reg
= ATA_DEVICE_OBS
| ATA_DEV1
;
401 buf
[i
++] = (1 << 5) | PDC_PKT_CLEAR_BSY
| ATA_REG_DEVICE
;
404 /* device control register */
405 buf
[i
++] = (1 << 5) | PDC_REG_DEVCTL
;
411 static inline void pdc20621_host_pkt(struct ata_taskfile
*tf
, u8
*buf
,
415 u32 tmp
, *buf32
= (u32
*) buf
;
417 unsigned int host_sg
= PDC_20621_DIMM_BASE
+
418 (PDC_DIMM_WINDOW_STEP
* portno
) +
420 unsigned int dimm_sg
= PDC_20621_DIMM_BASE
+
421 (PDC_DIMM_WINDOW_STEP
* portno
) +
423 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg
, dimm_sg
);
424 VPRINTK("host_sg == 0x%x, %d\n", host_sg
, host_sg
);
426 dw
= PDC_DIMM_HOST_PKT
>> 2;
429 * Set up Host DMA packet
431 if ((tf
->protocol
== ATA_PROT_DMA
) && (!(tf
->flags
& ATA_TFLAG_WRITE
)))
435 tmp
|= ((portno
+ 1 + 4) << 16); /* seq. id */
436 tmp
|= (0xff << 24); /* delay seq. id */
437 buf32
[dw
+ 0] = cpu_to_le32(tmp
);
438 buf32
[dw
+ 1] = cpu_to_le32(host_sg
);
439 buf32
[dw
+ 2] = cpu_to_le32(dimm_sg
);
442 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
443 PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* portno
) +
451 static void pdc20621_dma_prep(struct ata_queued_cmd
*qc
)
453 struct scatterlist
*sg
;
454 struct ata_port
*ap
= qc
->ap
;
455 struct pdc_port_priv
*pp
= ap
->private_data
;
456 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
457 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
458 void __iomem
*dimm_mmio
= hpriv
->dimm_mmio
;
459 unsigned int portno
= ap
->port_no
;
460 unsigned int i
, idx
, total_len
= 0, sgt_len
;
461 u32
*buf
= (u32
*) &pp
->dimm_buf
[PDC_DIMM_HEADER_SZ
];
463 WARN_ON(!(qc
->flags
& ATA_QCFLAG_DMAMAP
));
465 VPRINTK("ata%u: ENTER\n", ap
->id
);
467 /* hard-code chip #0 */
468 mmio
+= PDC_CHIP0_OFS
;
474 ata_for_each_sg(sg
, qc
) {
475 buf
[idx
++] = cpu_to_le32(sg_dma_address(sg
));
476 buf
[idx
++] = cpu_to_le32(sg_dma_len(sg
));
477 total_len
+= sg_dma_len(sg
);
479 buf
[idx
- 1] |= cpu_to_le32(ATA_PRD_EOT
);
483 * Build ATA, host DMA packets
485 pdc20621_host_sg(&qc
->tf
, &pp
->dimm_buf
[0], portno
, total_len
);
486 pdc20621_host_pkt(&qc
->tf
, &pp
->dimm_buf
[0], portno
);
488 pdc20621_ata_sg(&qc
->tf
, &pp
->dimm_buf
[0], portno
, total_len
);
489 i
= pdc20621_ata_pkt(&qc
->tf
, qc
->dev
->devno
, &pp
->dimm_buf
[0], portno
);
491 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
492 i
= pdc_prep_lba48(&qc
->tf
, &pp
->dimm_buf
[0], i
);
494 i
= pdc_prep_lba28(&qc
->tf
, &pp
->dimm_buf
[0], i
);
496 pdc_pkt_footer(&qc
->tf
, &pp
->dimm_buf
[0], i
);
498 /* copy three S/G tables and two packets to DIMM MMIO window */
499 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
),
500 &pp
->dimm_buf
, PDC_DIMM_HEADER_SZ
);
501 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
) +
503 &pp
->dimm_buf
[PDC_DIMM_HEADER_SZ
], sgt_len
);
505 /* force host FIFO dump */
506 writel(0x00000001, mmio
+ PDC_20621_GENERAL_CTL
);
508 readl(dimm_mmio
); /* MMIO PCI posting flush */
510 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i
, sgt_len
);
513 static void pdc20621_nodata_prep(struct ata_queued_cmd
*qc
)
515 struct ata_port
*ap
= qc
->ap
;
516 struct pdc_port_priv
*pp
= ap
->private_data
;
517 void __iomem
*mmio
= ap
->host_set
->mmio_base
;
518 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
519 void __iomem
*dimm_mmio
= hpriv
->dimm_mmio
;
520 unsigned int portno
= ap
->port_no
;
523 VPRINTK("ata%u: ENTER\n", ap
->id
);
525 /* hard-code chip #0 */
526 mmio
+= PDC_CHIP0_OFS
;
528 i
= pdc20621_ata_pkt(&qc
->tf
, qc
->dev
->devno
, &pp
->dimm_buf
[0], portno
);
530 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
531 i
= pdc_prep_lba48(&qc
->tf
, &pp
->dimm_buf
[0], i
);
533 i
= pdc_prep_lba28(&qc
->tf
, &pp
->dimm_buf
[0], i
);
535 pdc_pkt_footer(&qc
->tf
, &pp
->dimm_buf
[0], i
);
537 /* copy three S/G tables and two packets to DIMM MMIO window */
538 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
),
539 &pp
->dimm_buf
, PDC_DIMM_HEADER_SZ
);
541 /* force host FIFO dump */
542 writel(0x00000001, mmio
+ PDC_20621_GENERAL_CTL
);
544 readl(dimm_mmio
); /* MMIO PCI posting flush */
546 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i
);
549 static void pdc20621_qc_prep(struct ata_queued_cmd
*qc
)
551 switch (qc
->tf
.protocol
) {
553 pdc20621_dma_prep(qc
);
555 case ATA_PROT_NODATA
:
556 pdc20621_nodata_prep(qc
);
563 static void __pdc20621_push_hdma(struct ata_queued_cmd
*qc
,
567 struct ata_port
*ap
= qc
->ap
;
568 struct ata_host_set
*host_set
= ap
->host_set
;
569 void __iomem
*mmio
= host_set
->mmio_base
;
571 /* hard-code chip #0 */
572 mmio
+= PDC_CHIP0_OFS
;
574 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
575 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4)); /* flush */
577 writel(pkt_ofs
, mmio
+ PDC_HDMA_PKT_SUBMIT
);
578 readl(mmio
+ PDC_HDMA_PKT_SUBMIT
); /* flush */
581 static void pdc20621_push_hdma(struct ata_queued_cmd
*qc
,
585 struct ata_port
*ap
= qc
->ap
;
586 struct pdc_host_priv
*pp
= ap
->host_set
->private_data
;
587 unsigned int idx
= pp
->hdma_prod
& PDC_HDMA_Q_MASK
;
589 if (!pp
->doing_hdma
) {
590 __pdc20621_push_hdma(qc
, seq
, pkt_ofs
);
595 pp
->hdma
[idx
].qc
= qc
;
596 pp
->hdma
[idx
].seq
= seq
;
597 pp
->hdma
[idx
].pkt_ofs
= pkt_ofs
;
601 static void pdc20621_pop_hdma(struct ata_queued_cmd
*qc
)
603 struct ata_port
*ap
= qc
->ap
;
604 struct pdc_host_priv
*pp
= ap
->host_set
->private_data
;
605 unsigned int idx
= pp
->hdma_cons
& PDC_HDMA_Q_MASK
;
607 /* if nothing on queue, we're done */
608 if (pp
->hdma_prod
== pp
->hdma_cons
) {
613 __pdc20621_push_hdma(pp
->hdma
[idx
].qc
, pp
->hdma
[idx
].seq
,
614 pp
->hdma
[idx
].pkt_ofs
);
618 #ifdef ATA_VERBOSE_DEBUG
619 static void pdc20621_dump_hdma(struct ata_queued_cmd
*qc
)
621 struct ata_port
*ap
= qc
->ap
;
622 unsigned int port_no
= ap
->port_no
;
623 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
624 void *dimm_mmio
= hpriv
->dimm_mmio
;
626 dimm_mmio
+= (port_no
* PDC_DIMM_WINDOW_STEP
);
627 dimm_mmio
+= PDC_DIMM_HOST_PKT
;
629 printk(KERN_ERR
"HDMA[0] == 0x%08X\n", readl(dimm_mmio
));
630 printk(KERN_ERR
"HDMA[1] == 0x%08X\n", readl(dimm_mmio
+ 4));
631 printk(KERN_ERR
"HDMA[2] == 0x%08X\n", readl(dimm_mmio
+ 8));
632 printk(KERN_ERR
"HDMA[3] == 0x%08X\n", readl(dimm_mmio
+ 12));
635 static inline void pdc20621_dump_hdma(struct ata_queued_cmd
*qc
) { }
636 #endif /* ATA_VERBOSE_DEBUG */
638 static void pdc20621_packet_start(struct ata_queued_cmd
*qc
)
640 struct ata_port
*ap
= qc
->ap
;
641 struct ata_host_set
*host_set
= ap
->host_set
;
642 unsigned int port_no
= ap
->port_no
;
643 void __iomem
*mmio
= host_set
->mmio_base
;
644 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
645 u8 seq
= (u8
) (port_no
+ 1);
646 unsigned int port_ofs
;
648 /* hard-code chip #0 */
649 mmio
+= PDC_CHIP0_OFS
;
651 VPRINTK("ata%u: ENTER\n", ap
->id
);
653 wmb(); /* flush PRD, pkt writes */
655 port_ofs
= PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* port_no
);
657 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
658 if (rw
&& qc
->tf
.protocol
== ATA_PROT_DMA
) {
661 pdc20621_dump_hdma(qc
);
662 pdc20621_push_hdma(qc
, seq
, port_ofs
+ PDC_DIMM_HOST_PKT
);
663 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
664 port_ofs
+ PDC_DIMM_HOST_PKT
,
665 port_ofs
+ PDC_DIMM_HOST_PKT
,
668 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
669 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4)); /* flush */
671 writel(port_ofs
+ PDC_DIMM_ATA_PKT
,
672 (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
673 readl((void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
674 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
675 port_ofs
+ PDC_DIMM_ATA_PKT
,
676 port_ofs
+ PDC_DIMM_ATA_PKT
,
681 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd
*qc
)
683 switch (qc
->tf
.protocol
) {
685 case ATA_PROT_NODATA
:
686 pdc20621_packet_start(qc
);
689 case ATA_PROT_ATAPI_DMA
:
697 return ata_qc_issue_prot(qc
);
700 static inline unsigned int pdc20621_host_intr( struct ata_port
*ap
,
701 struct ata_queued_cmd
*qc
,
702 unsigned int doing_hdma
,
705 unsigned int port_no
= ap
->port_no
;
706 unsigned int port_ofs
=
707 PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* port_no
);
709 unsigned int handled
= 0;
713 if ((qc
->tf
.protocol
== ATA_PROT_DMA
) && /* read */
714 (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))) {
716 /* step two - DMA from DIMM to host */
718 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap
->id
,
719 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
720 /* get drive status; clear intr; complete txn */
721 qc
->err_mask
|= ac_err_mask(ata_wait_idle(ap
));
723 pdc20621_pop_hdma(qc
);
726 /* step one - exec ATA command */
728 u8 seq
= (u8
) (port_no
+ 1 + 4);
729 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap
->id
,
730 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
732 /* submit hdma pkt */
733 pdc20621_dump_hdma(qc
);
734 pdc20621_push_hdma(qc
, seq
,
735 port_ofs
+ PDC_DIMM_HOST_PKT
);
739 } else if (qc
->tf
.protocol
== ATA_PROT_DMA
) { /* write */
741 /* step one - DMA from host to DIMM */
743 u8 seq
= (u8
) (port_no
+ 1);
744 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap
->id
,
745 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
748 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
749 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
750 writel(port_ofs
+ PDC_DIMM_ATA_PKT
,
751 (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
752 readl((void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
755 /* step two - execute ATA command */
757 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap
->id
,
758 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
759 /* get drive status; clear intr; complete txn */
760 qc
->err_mask
|= ac_err_mask(ata_wait_idle(ap
));
762 pdc20621_pop_hdma(qc
);
766 /* command completion, but no data xfer */
767 } else if (qc
->tf
.protocol
== ATA_PROT_NODATA
) {
769 status
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
770 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status
);
771 qc
->err_mask
|= ac_err_mask(status
);
776 ap
->stats
.idle_irq
++;
782 static void pdc20621_irq_clear(struct ata_port
*ap
)
784 struct ata_host_set
*host_set
= ap
->host_set
;
785 void __iomem
*mmio
= host_set
->mmio_base
;
787 mmio
+= PDC_CHIP0_OFS
;
789 readl(mmio
+ PDC_20621_SEQMASK
);
792 static irqreturn_t
pdc20621_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
794 struct ata_host_set
*host_set
= dev_instance
;
797 unsigned int i
, tmp
, port_no
;
798 unsigned int handled
= 0;
799 void __iomem
*mmio_base
;
803 if (!host_set
|| !host_set
->mmio_base
) {
804 VPRINTK("QUICK EXIT\n");
808 mmio_base
= host_set
->mmio_base
;
810 /* reading should also clear interrupts */
811 mmio_base
+= PDC_CHIP0_OFS
;
812 mask
= readl(mmio_base
+ PDC_20621_SEQMASK
);
813 VPRINTK("mask == 0x%x\n", mask
);
815 if (mask
== 0xffffffff) {
816 VPRINTK("QUICK EXIT 2\n");
819 mask
&= 0xffff; /* only 16 tags possible */
821 VPRINTK("QUICK EXIT 3\n");
825 spin_lock(&host_set
->lock
);
827 for (i
= 1; i
< 9; i
++) {
831 if (port_no
>= host_set
->n_ports
)
834 ap
= host_set
->ports
[port_no
];
835 tmp
= mask
& (1 << i
);
836 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i
, port_no
, ap
, tmp
);
838 !(ap
->flags
& ATA_FLAG_PORT_DISABLED
)) {
839 struct ata_queued_cmd
*qc
;
841 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
842 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
)))
843 handled
+= pdc20621_host_intr(ap
, qc
, (i
> 4),
848 spin_unlock(&host_set
->lock
);
850 VPRINTK("mask == 0x%x\n", mask
);
854 return IRQ_RETVAL(handled
);
857 static void pdc_eng_timeout(struct ata_port
*ap
)
860 struct ata_host_set
*host_set
= ap
->host_set
;
861 struct ata_queued_cmd
*qc
;
866 spin_lock_irqsave(&host_set
->lock
, flags
);
868 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
870 switch (qc
->tf
.protocol
) {
872 case ATA_PROT_NODATA
:
873 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
874 qc
->err_mask
|= __ac_err_mask(ata_wait_idle(ap
));
878 drv_stat
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
880 printk(KERN_ERR
"ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
881 ap
->id
, qc
->tf
.command
, drv_stat
);
883 qc
->err_mask
|= ac_err_mask(drv_stat
);
887 spin_unlock_irqrestore(&host_set
->lock
, flags
);
888 ata_eh_qc_complete(qc
);
892 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
894 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
895 tf
->protocol
== ATA_PROT_NODATA
);
900 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
902 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
903 tf
->protocol
== ATA_PROT_NODATA
);
904 ata_exec_command(ap
, tf
);
908 static void pdc_sata_setup_port(struct ata_ioports
*port
, unsigned long base
)
910 port
->cmd_addr
= base
;
911 port
->data_addr
= base
;
913 port
->error_addr
= base
+ 0x4;
914 port
->nsect_addr
= base
+ 0x8;
915 port
->lbal_addr
= base
+ 0xc;
916 port
->lbam_addr
= base
+ 0x10;
917 port
->lbah_addr
= base
+ 0x14;
918 port
->device_addr
= base
+ 0x18;
920 port
->status_addr
= base
+ 0x1c;
921 port
->altstatus_addr
=
922 port
->ctl_addr
= base
+ 0x38;
926 #ifdef ATA_VERBOSE_DEBUG
927 static void pdc20621_get_from_dimm(struct ata_probe_ent
*pe
, void *psource
,
928 u32 offset
, u32 size
)
934 void __iomem
*mmio
= pe
->mmio_base
;
935 struct pdc_host_priv
*hpriv
= pe
->private_data
;
936 void __iomem
*dimm_mmio
= hpriv
->dimm_mmio
;
938 /* hard-code chip #0 */
939 mmio
+= PDC_CHIP0_OFS
;
942 window_size
= 0x2000 * 4; /* 32K byte uchar size */
943 idx
= (u16
) (offset
/ window_size
);
945 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
946 readl(mmio
+ PDC_GENERAL_CTLR
);
947 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
948 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
950 offset
-= (idx
* window_size
);
952 dist
= ((long) (window_size
- (offset
+ size
))) >= 0 ? size
:
953 (long) (window_size
- offset
);
954 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
+ offset
/ 4),
959 for (; (long) size
>= (long) window_size
;) {
960 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
961 readl(mmio
+ PDC_GENERAL_CTLR
);
962 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
963 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
964 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
),
966 psource
+= window_size
;
972 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
973 readl(mmio
+ PDC_GENERAL_CTLR
);
974 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
975 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
976 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
),
983 static void pdc20621_put_to_dimm(struct ata_probe_ent
*pe
, void *psource
,
984 u32 offset
, u32 size
)
990 void __iomem
*mmio
= pe
->mmio_base
;
991 struct pdc_host_priv
*hpriv
= pe
->private_data
;
992 void __iomem
*dimm_mmio
= hpriv
->dimm_mmio
;
994 /* hard-code chip #0 */
995 mmio
+= PDC_CHIP0_OFS
;
998 window_size
= 0x2000 * 4; /* 32K byte uchar size */
999 idx
= (u16
) (offset
/ window_size
);
1001 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1002 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1003 offset
-= (idx
* window_size
);
1005 dist
= ((long)(s32
)(window_size
- (offset
+ size
))) >= 0 ? size
:
1006 (long) (window_size
- offset
);
1007 memcpy_toio(dimm_mmio
+ offset
/ 4, psource
, dist
);
1008 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1009 readl(mmio
+ PDC_GENERAL_CTLR
);
1013 for (; (long) size
>= (long) window_size
;) {
1014 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1015 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1016 memcpy_toio(dimm_mmio
, psource
, window_size
/ 4);
1017 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1018 readl(mmio
+ PDC_GENERAL_CTLR
);
1019 psource
+= window_size
;
1020 size
-= window_size
;
1025 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1026 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1027 memcpy_toio(dimm_mmio
, psource
, size
/ 4);
1028 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1029 readl(mmio
+ PDC_GENERAL_CTLR
);
1034 static unsigned int pdc20621_i2c_read(struct ata_probe_ent
*pe
, u32 device
,
1035 u32 subaddr
, u32
*pdata
)
1037 void __iomem
*mmio
= pe
->mmio_base
;
1042 /* hard-code chip #0 */
1043 mmio
+= PDC_CHIP0_OFS
;
1045 i2creg
|= device
<< 24;
1046 i2creg
|= subaddr
<< 16;
1048 /* Set the device and subaddress */
1049 writel(i2creg
, mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1050 readl(mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1052 /* Write Control to perform read operation, mask int */
1053 writel(PDC_I2C_READ
| PDC_I2C_START
| PDC_I2C_MASK_INT
,
1054 mmio
+ PDC_I2C_CONTROL_OFFSET
);
1056 for (count
= 0; count
<= 1000; count
++) {
1057 status
= readl(mmio
+ PDC_I2C_CONTROL_OFFSET
);
1058 if (status
& PDC_I2C_COMPLETE
) {
1059 status
= readl(mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1061 } else if (count
== 1000)
1065 *pdata
= (status
>> 8) & 0x000000ff;
1070 static int pdc20621_detect_dimm(struct ata_probe_ent
*pe
)
1073 if (pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1074 PDC_DIMM_SPD_SYSTEM_FREQ
, &data
)) {
1080 if (pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
, 9, &data
)) {
1090 static int pdc20621_prog_dimm0(struct ata_probe_ent
*pe
)
1096 void __iomem
*mmio
= pe
->mmio_base
;
1097 static const struct {
1100 } pdc_i2c_read_data
[] = {
1101 { PDC_DIMM_SPD_TYPE
, 11 },
1102 { PDC_DIMM_SPD_FRESH_RATE
, 12 },
1103 { PDC_DIMM_SPD_COLUMN_NUM
, 4 },
1104 { PDC_DIMM_SPD_ATTRIBUTE
, 21 },
1105 { PDC_DIMM_SPD_ROW_NUM
, 3 },
1106 { PDC_DIMM_SPD_BANK_NUM
, 17 },
1107 { PDC_DIMM_SPD_MODULE_ROW
, 5 },
1108 { PDC_DIMM_SPD_ROW_PRE_CHARGE
, 27 },
1109 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY
, 28 },
1110 { PDC_DIMM_SPD_RAS_CAS_DELAY
, 29 },
1111 { PDC_DIMM_SPD_ACTIVE_PRECHARGE
, 30 },
1112 { PDC_DIMM_SPD_CAS_LATENCY
, 18 },
1115 /* hard-code chip #0 */
1116 mmio
+= PDC_CHIP0_OFS
;
1118 for(i
=0; i
<ARRAY_SIZE(pdc_i2c_read_data
); i
++)
1119 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1120 pdc_i2c_read_data
[i
].reg
,
1121 &spd0
[pdc_i2c_read_data
[i
].ofs
]);
1123 data
|= (spd0
[4] - 8) | ((spd0
[21] != 0) << 3) | ((spd0
[3]-11) << 4);
1124 data
|= ((spd0
[17] / 4) << 6) | ((spd0
[5] / 2) << 7) |
1125 ((((spd0
[27] + 9) / 10) - 1) << 8) ;
1126 data
|= (((((spd0
[29] > spd0
[28])
1127 ? spd0
[29] : spd0
[28]) + 9) / 10) - 1) << 10;
1128 data
|= ((spd0
[30] - spd0
[29] + 9) / 10 - 2) << 12;
1130 if (spd0
[18] & 0x08)
1131 data
|= ((0x03) << 14);
1132 else if (spd0
[18] & 0x04)
1133 data
|= ((0x02) << 14);
1134 else if (spd0
[18] & 0x01)
1135 data
|= ((0x01) << 14);
1140 Calculate the size of bDIMMSize (power of 2) and
1141 merge the DIMM size by program start/end address.
1144 bdimmsize
= spd0
[4] + (spd0
[5] / 2) + spd0
[3] + (spd0
[17] / 2) + 3;
1145 size
= (1 << bdimmsize
) >> 20; /* size = xxx(MB) */
1146 data
|= (((size
/ 16) - 1) << 16);
1149 writel(data
, mmio
+ PDC_DIMM0_CONTROL_OFFSET
);
1150 readl(mmio
+ PDC_DIMM0_CONTROL_OFFSET
);
1155 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent
*pe
)
1159 void __iomem
*mmio
= pe
->mmio_base
;
1161 /* hard-code chip #0 */
1162 mmio
+= PDC_CHIP0_OFS
;
1165 Set To Default : DIMM Module Global Control Register (0x022259F1)
1166 DIMM Arbitration Disable (bit 20)
1167 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1168 Refresh Enable (bit 17)
1172 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1173 readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1175 /* Turn on for ECC */
1176 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1177 PDC_DIMM_SPD_TYPE
, &spd0
);
1179 data
|= (0x01 << 16);
1180 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1181 readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1182 printk(KERN_ERR
"Local DIMM ECC Enabled\n");
1185 /* DIMM Initialization Select/Enable (bit 18/19) */
1188 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1191 for (i
= 1; i
<= 10; i
++) { /* polling ~5 secs */
1192 data
= readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1193 if (!(data
& (1<<19))) {
1203 static unsigned int pdc20621_dimm_init(struct ata_probe_ent
*pe
)
1205 int speed
, size
, length
;
1206 u32 addr
,spd0
,pci_status
;
1213 void __iomem
*mmio
= pe
->mmio_base
;
1215 /* hard-code chip #0 */
1216 mmio
+= PDC_CHIP0_OFS
;
1218 /* Initialize PLL based upon PCI Bus Frequency */
1220 /* Initialize Time Period Register */
1221 writel(0xffffffff, mmio
+ PDC_TIME_PERIOD
);
1222 time_period
= readl(mmio
+ PDC_TIME_PERIOD
);
1223 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period
);
1226 writel(0x00001a0, mmio
+ PDC_TIME_CONTROL
);
1227 readl(mmio
+ PDC_TIME_CONTROL
);
1229 /* Wait 3 seconds */
1233 When timer is enabled, counter is decreased every internal
1237 tcount
= readl(mmio
+ PDC_TIME_COUNTER
);
1238 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount
);
1241 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1242 register should be >= (0xffffffff - 3x10^8).
1244 if(tcount
>= PCI_X_TCOUNT
) {
1245 ticks
= (time_period
- tcount
);
1246 VPRINTK("Num counters 0x%x (%d)\n", ticks
, ticks
);
1248 clock
= (ticks
/ 300000);
1249 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock
, clock
);
1251 clock
= (clock
* 33);
1252 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock
, clock
);
1254 /* PLL F Param (bit 22:16) */
1255 fparam
= (1400000 / clock
) - 2;
1256 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam
, fparam
);
1258 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1259 pci_status
= (0x8a001824 | (fparam
<< 16));
1261 pci_status
= PCI_PLL_INIT
;
1263 /* Initialize PLL. */
1264 VPRINTK("pci_status: 0x%x\n", pci_status
);
1265 writel(pci_status
, mmio
+ PDC_CTL_STATUS
);
1266 readl(mmio
+ PDC_CTL_STATUS
);
1269 Read SPD of DIMM by I2C interface,
1270 and program the DIMM Module Controller.
1272 if (!(speed
= pdc20621_detect_dimm(pe
))) {
1273 printk(KERN_ERR
"Detect Local DIMM Fail\n");
1274 return 1; /* DIMM error */
1276 VPRINTK("Local DIMM Speed = %d\n", speed
);
1278 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1279 size
= pdc20621_prog_dimm0(pe
);
1280 VPRINTK("Local DIMM Size = %dMB\n",size
);
1282 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1283 if (pdc20621_prog_dimm_global(pe
)) {
1284 printk(KERN_ERR
"Programming DIMM Module Global Control Register Fail\n");
1288 #ifdef ATA_VERBOSE_DEBUG
1290 u8 test_parttern1
[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1291 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1293 '9','8','0','3','1','6','1','2',0,0};
1294 u8 test_parttern2
[40] = {0};
1296 pdc20621_put_to_dimm(pe
, (void *) test_parttern2
, 0x10040, 40);
1297 pdc20621_put_to_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1299 pdc20621_put_to_dimm(pe
, (void *) test_parttern1
, 0x10040, 40);
1300 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1301 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1302 test_parttern2
[1], &(test_parttern2
[2]));
1303 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x10040,
1305 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1306 test_parttern2
[1], &(test_parttern2
[2]));
1308 pdc20621_put_to_dimm(pe
, (void *) test_parttern1
, 0x40, 40);
1309 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1310 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1311 test_parttern2
[1], &(test_parttern2
[2]));
1315 /* ECC initiliazation. */
1317 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1318 PDC_DIMM_SPD_TYPE
, &spd0
);
1320 VPRINTK("Start ECC initialization\n");
1322 length
= size
* 1024 * 1024;
1323 while (addr
< length
) {
1324 pdc20621_put_to_dimm(pe
, (void *) &tmp
, addr
,
1326 addr
+= sizeof(u32
);
1328 VPRINTK("Finish ECC initialization\n");
1334 static void pdc_20621_init(struct ata_probe_ent
*pe
)
1337 void __iomem
*mmio
= pe
->mmio_base
;
1339 /* hard-code chip #0 */
1340 mmio
+= PDC_CHIP0_OFS
;
1343 * Select page 0x40 for our 32k DIMM window
1345 tmp
= readl(mmio
+ PDC_20621_DIMM_WINDOW
) & 0xffff0000;
1346 tmp
|= PDC_PAGE_WINDOW
; /* page 40h; arbitrarily selected */
1347 writel(tmp
, mmio
+ PDC_20621_DIMM_WINDOW
);
1352 tmp
= readl(mmio
+ PDC_HDMA_CTLSTAT
);
1354 writel(tmp
, mmio
+ PDC_HDMA_CTLSTAT
);
1355 readl(mmio
+ PDC_HDMA_CTLSTAT
); /* flush */
1359 tmp
= readl(mmio
+ PDC_HDMA_CTLSTAT
);
1361 writel(tmp
, mmio
+ PDC_HDMA_CTLSTAT
);
1362 readl(mmio
+ PDC_HDMA_CTLSTAT
); /* flush */
1365 static int pdc_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1367 static int printed_version
;
1368 struct ata_probe_ent
*probe_ent
= NULL
;
1370 void __iomem
*mmio_base
;
1371 void __iomem
*dimm_mmio
= NULL
;
1372 struct pdc_host_priv
*hpriv
= NULL
;
1373 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1374 int pci_dev_busy
= 0;
1377 if (!printed_version
++)
1378 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1381 * If this driver happens to only be useful on Apple's K2, then
1382 * we should check that here as it has a normal Serverworks ID
1384 rc
= pci_enable_device(pdev
);
1388 rc
= pci_request_regions(pdev
, DRV_NAME
);
1394 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
1396 goto err_out_regions
;
1397 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
1399 goto err_out_regions
;
1401 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1402 if (probe_ent
== NULL
) {
1404 goto err_out_regions
;
1407 memset(probe_ent
, 0, sizeof(*probe_ent
));
1408 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1409 INIT_LIST_HEAD(&probe_ent
->node
);
1411 mmio_base
= pci_iomap(pdev
, 3, 0);
1412 if (mmio_base
== NULL
) {
1414 goto err_out_free_ent
;
1416 base
= (unsigned long) mmio_base
;
1418 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1421 goto err_out_iounmap
;
1423 memset(hpriv
, 0, sizeof(*hpriv
));
1425 dimm_mmio
= pci_iomap(pdev
, 4, 0);
1429 goto err_out_iounmap
;
1432 hpriv
->dimm_mmio
= dimm_mmio
;
1434 probe_ent
->sht
= pdc_port_info
[board_idx
].sht
;
1435 probe_ent
->host_flags
= pdc_port_info
[board_idx
].host_flags
;
1436 probe_ent
->pio_mask
= pdc_port_info
[board_idx
].pio_mask
;
1437 probe_ent
->mwdma_mask
= pdc_port_info
[board_idx
].mwdma_mask
;
1438 probe_ent
->udma_mask
= pdc_port_info
[board_idx
].udma_mask
;
1439 probe_ent
->port_ops
= pdc_port_info
[board_idx
].port_ops
;
1441 probe_ent
->irq
= pdev
->irq
;
1442 probe_ent
->irq_flags
= SA_SHIRQ
;
1443 probe_ent
->mmio_base
= mmio_base
;
1445 probe_ent
->private_data
= hpriv
;
1446 base
+= PDC_CHIP0_OFS
;
1448 probe_ent
->n_ports
= 4;
1449 pdc_sata_setup_port(&probe_ent
->port
[0], base
+ 0x200);
1450 pdc_sata_setup_port(&probe_ent
->port
[1], base
+ 0x280);
1451 pdc_sata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
1452 pdc_sata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
1454 pci_set_master(pdev
);
1456 /* initialize adapter */
1457 /* initialize local dimm */
1458 if (pdc20621_dimm_init(probe_ent
)) {
1460 goto err_out_iounmap_dimm
;
1462 pdc_20621_init(probe_ent
);
1464 /* FIXME: check ata_device_add return value */
1465 ata_device_add(probe_ent
);
1470 err_out_iounmap_dimm
: /* only get to this label if 20621 */
1472 pci_iounmap(pdev
, dimm_mmio
);
1474 pci_iounmap(pdev
, mmio_base
);
1478 pci_release_regions(pdev
);
1481 pci_disable_device(pdev
);
1486 static int __init
pdc_sata_init(void)
1488 return pci_module_init(&pdc_sata_pci_driver
);
1492 static void __exit
pdc_sata_exit(void)
1494 pci_unregister_driver(&pdc_sata_pci_driver
);
1498 MODULE_AUTHOR("Jeff Garzik");
1499 MODULE_DESCRIPTION("Promise SATA low-level driver");
1500 MODULE_LICENSE("GPL");
1501 MODULE_DEVICE_TABLE(pci
, pdc_sata_pci_tbl
);
1502 MODULE_VERSION(DRV_VERSION
);
1504 module_init(pdc_sata_init
);
1505 module_exit(pdc_sata_exit
);