drivers/net/mv643xx_eth.h

   1 #ifndef __MV643XX_ETH_H__
   2 #define __MV643XX_ETH_H__
   3
   4 #include <linux/module.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/workqueue.h>
   8 #include <linux/mii.h>
   9
  10 #include <linux/mv643xx.h>
  11
  12 #define BIT0    0x00000001
  13 #define BIT1    0x00000002
  14 #define BIT2    0x00000004
  15 #define BIT3    0x00000008
  16 #define BIT4    0x00000010
  17 #define BIT5    0x00000020
  18 #define BIT6    0x00000040
  19 #define BIT7    0x00000080
  20 #define BIT8    0x00000100
  21 #define BIT9    0x00000200
  22 #define BIT10   0x00000400
  23 #define BIT11   0x00000800
  24 #define BIT12   0x00001000
  25 #define BIT13   0x00002000
  26 #define BIT14   0x00004000
  27 #define BIT15   0x00008000
  28 #define BIT16   0x00010000
  29 #define BIT17   0x00020000
  30 #define BIT18   0x00040000
  31 #define BIT19   0x00080000
  32 #define BIT20   0x00100000
  33 #define BIT21   0x00200000
  34 #define BIT22   0x00400000
  35 #define BIT23   0x00800000
  36 #define BIT24   0x01000000
  37 #define BIT25   0x02000000
  38 #define BIT26   0x04000000
  39 #define BIT27   0x08000000
  40 #define BIT28   0x10000000
  41 #define BIT29   0x20000000
  42 #define BIT30   0x40000000
  43 #define BIT31   0x80000000
  44
  45 /*
  46  *  The first part is the high level driver of the gigE ethernet ports.
  47  */
  48
  49 /* Checksum offload for Tx works for most packets, but
  50  * fails if previous packet sent did not use hw csum
  51  */
  52 #define MV643XX_CHECKSUM_OFFLOAD_TX
  53 #define MV643XX_NAPI
  54 #define MV643XX_TX_FAST_REFILL
  55 #undef  MV643XX_RX_QUEUE_FILL_ON_TASK   /* Does not work, yet */
  56 #undef  MV643XX_COAL
  57
  58 /*
  59  * Number of RX / TX descriptors on RX / TX rings.
  60  * Note that allocating RX descriptors is done by allocating the RX
  61  * ring AND a preallocated RX buffers (skb's) for each descriptor.
  62  * The TX descriptors only allocates the TX descriptors ring,
  63  * with no pre allocated TX buffers (skb's are allocated by higher layers.
  64  */
  65
  66 /* Default TX ring size is 1000 descriptors */
  67 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
  68
  69 /* Default RX ring size is 400 descriptors */
  70 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
  71
  72 #define MV643XX_TX_COAL 100
  73 #ifdef MV643XX_COAL
  74 #define MV643XX_RX_COAL 100
  75 #endif
  76
  77 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
  78 #define MAX_DESCS_PER_SKB       (MAX_SKB_FRAGS + 1)
  79 #else
  80 #define MAX_DESCS_PER_SKB       1
  81 #endif
  82
  83 #define ETH_VLAN_HLEN           4
  84 #define ETH_FCS_LEN             4
  85 #define ETH_DMA_ALIGN           8       /* hw requires 8-byte alignment */
  86 #define ETH_HW_IP_ALIGN         2       /* hw aligns IP header */
  87 #define ETH_WRAPPER_LEN         (ETH_HW_IP_ALIGN + ETH_HLEN + \
  88                                 ETH_VLAN_HLEN + ETH_FCS_LEN)
  89 #define ETH_RX_SKB_SIZE         ((dev->mtu + ETH_WRAPPER_LEN + 7) & ~0x7)
  90
  91 #define ETH_RX_QUEUES_ENABLED   (1 << 0)        /* use only Q0 for receive */
  92 #define ETH_TX_QUEUES_ENABLED   (1 << 0)        /* use only Q0 for transmit */
  93
  94 #define ETH_INT_CAUSE_RX_DONE   (ETH_RX_QUEUES_ENABLED << 2)
  95 #define ETH_INT_CAUSE_RX_ERROR  (ETH_RX_QUEUES_ENABLED << 9)
  96 #define ETH_INT_CAUSE_RX        (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
  97 #define ETH_INT_CAUSE_EXT       0x00000002
  98 #define ETH_INT_UNMASK_ALL      (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
  99
 100 #define ETH_INT_CAUSE_TX_DONE   (ETH_TX_QUEUES_ENABLED << 0)
 101 #define ETH_INT_CAUSE_TX_ERROR  (ETH_TX_QUEUES_ENABLED << 8)
 102 #define ETH_INT_CAUSE_TX        (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
 103 #define ETH_INT_CAUSE_PHY       0x00010000
 104 #define ETH_INT_UNMASK_ALL_EXT  (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
 105
 106 #define ETH_INT_MASK_ALL        0x00000000
 107 #define ETH_INT_MASK_ALL_EXT    0x00000000
 108
 109 #define PHY_WAIT_ITERATIONS     1000    /* 1000 iterations * 10uS = 10mS max */
 110 #define PHY_WAIT_MICRO_SECONDS  10
 111
 112 /* Buffer offset from buffer pointer */
 113 #define RX_BUF_OFFSET                           0x2
 114
 115 /* Gigabit Ethernet Unit Global Registers */
 116
 117 /* MIB Counters register definitions */
 118 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW        0x0
 119 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH       0x4
 120 #define ETH_MIB_BAD_OCTETS_RECEIVED             0x8
 121 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR       0xc
 122 #define ETH_MIB_GOOD_FRAMES_RECEIVED            0x10
 123 #define ETH_MIB_BAD_FRAMES_RECEIVED             0x14
 124 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED       0x18
 125 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED       0x1c
 126 #define ETH_MIB_FRAMES_64_OCTETS                0x20
 127 #define ETH_MIB_FRAMES_65_TO_127_OCTETS         0x24
 128 #define ETH_MIB_FRAMES_128_TO_255_OCTETS        0x28
 129 #define ETH_MIB_FRAMES_256_TO_511_OCTETS        0x2c
 130 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS       0x30
 131 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS       0x34
 132 #define ETH_MIB_GOOD_OCTETS_SENT_LOW            0x38
 133 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH           0x3c
 134 #define ETH_MIB_GOOD_FRAMES_SENT                0x40
 135 #define ETH_MIB_EXCESSIVE_COLLISION             0x44
 136 #define ETH_MIB_MULTICAST_FRAMES_SENT           0x48
 137 #define ETH_MIB_BROADCAST_FRAMES_SENT           0x4c
 138 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED      0x50
 139 #define ETH_MIB_FC_SENT                         0x54
 140 #define ETH_MIB_GOOD_FC_RECEIVED                0x58
 141 #define ETH_MIB_BAD_FC_RECEIVED                 0x5c
 142 #define ETH_MIB_UNDERSIZE_RECEIVED              0x60
 143 #define ETH_MIB_FRAGMENTS_RECEIVED              0x64
 144 #define ETH_MIB_OVERSIZE_RECEIVED               0x68
 145 #define ETH_MIB_JABBER_RECEIVED                 0x6c
 146 #define ETH_MIB_MAC_RECEIVE_ERROR               0x70
 147 #define ETH_MIB_BAD_CRC_EVENT                   0x74
 148 #define ETH_MIB_COLLISION                       0x78
 149 #define ETH_MIB_LATE_COLLISION                  0x7c
 150
 151 /* Port serial status reg (PSR) */
 152 #define ETH_INTERFACE_GMII_MII                  0
 153 #define ETH_INTERFACE_PCM                       BIT0
 154 #define ETH_LINK_IS_DOWN                        0
 155 #define ETH_LINK_IS_UP                          BIT1
 156 #define ETH_PORT_AT_HALF_DUPLEX                 0
 157 #define ETH_PORT_AT_FULL_DUPLEX                 BIT2
 158 #define ETH_RX_FLOW_CTRL_DISABLED               0
 159 #define ETH_RX_FLOW_CTRL_ENBALED                BIT3
 160 #define ETH_GMII_SPEED_100_10                   0
 161 #define ETH_GMII_SPEED_1000                     BIT4
 162 #define ETH_MII_SPEED_10                        0
 163 #define ETH_MII_SPEED_100                       BIT5
 164 #define ETH_NO_TX                               0
 165 #define ETH_TX_IN_PROGRESS                      BIT7
 166 #define ETH_BYPASS_NO_ACTIVE                    0
 167 #define ETH_BYPASS_ACTIVE                       BIT8
 168 #define ETH_PORT_NOT_AT_PARTITION_STATE         0
 169 #define ETH_PORT_AT_PARTITION_STATE             BIT9
 170 #define ETH_PORT_TX_FIFO_NOT_EMPTY              0
 171 #define ETH_PORT_TX_FIFO_EMPTY                  BIT10
 172
 173 #define ETH_DEFAULT_RX_BPDU_QUEUE_3             (BIT23 | BIT22)
 174 #define ETH_DEFAULT_RX_BPDU_QUEUE_4             BIT24
 175 #define ETH_DEFAULT_RX_BPDU_QUEUE_5             (BIT24 | BIT22)
 176 #define ETH_DEFAULT_RX_BPDU_QUEUE_6             (BIT24 | BIT23)
 177 #define ETH_DEFAULT_RX_BPDU_QUEUE_7             (BIT24 | BIT23 | BIT22)
 178
 179 /* SMI reg */
 180 #define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
 181 #define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
 182 #define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
 183 #define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress     */
 184
 185 /* SDMA command status fields macros */
 186
 187 /* Tx & Rx descriptors status */
 188 #define ETH_ERROR_SUMMARY                       (BIT0)
 189
 190 /* Tx & Rx descriptors command */
 191 #define ETH_BUFFER_OWNED_BY_DMA                 (BIT31)
 192
 193 /* Tx descriptors status */
 194 #define ETH_LC_ERROR                            (0    )
 195 #define ETH_UR_ERROR                            (BIT1 )
 196 #define ETH_RL_ERROR                            (BIT2 )
 197 #define ETH_LLC_SNAP_FORMAT                     (BIT9 )
 198
 199 /* Rx descriptors status */
 200 #define ETH_CRC_ERROR                           (0    )
 201 #define ETH_OVERRUN_ERROR                       (BIT1 )
 202 #define ETH_MAX_FRAME_LENGTH_ERROR              (BIT2 )
 203 #define ETH_RESOURCE_ERROR                      ((BIT2 | BIT1))
 204 #define ETH_VLAN_TAGGED                         (BIT19)
 205 #define ETH_BPDU_FRAME                          (BIT20)
 206 #define ETH_TCP_FRAME_OVER_IP_V_4               (0    )
 207 #define ETH_UDP_FRAME_OVER_IP_V_4               (BIT21)
 208 #define ETH_OTHER_FRAME_TYPE                    (BIT22)
 209 #define ETH_LAYER_2_IS_ETH_V_2                  (BIT23)
 210 #define ETH_FRAME_TYPE_IP_V_4                   (BIT24)
 211 #define ETH_FRAME_HEADER_OK                     (BIT25)
 212 #define ETH_RX_LAST_DESC                        (BIT26)
 213 #define ETH_RX_FIRST_DESC                       (BIT27)
 214 #define ETH_UNKNOWN_DESTINATION_ADDR            (BIT28)
 215 #define ETH_RX_ENABLE_INTERRUPT                 (BIT29)
 216 #define ETH_LAYER_4_CHECKSUM_OK                 (BIT30)
 217
 218 /* Rx descriptors byte count */
 219 #define ETH_FRAME_FRAGMENTED                    (BIT2)
 220
 221 /* Tx descriptors command */
 222 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
 223 #define ETH_FRAME_SET_TO_VLAN                   (BIT15)
 224 #define ETH_TCP_FRAME                           (0    )
 225 #define ETH_UDP_FRAME                           (BIT16)
 226 #define ETH_GEN_TCP_UDP_CHECKSUM                (BIT17)
 227 #define ETH_GEN_IP_V_4_CHECKSUM                 (BIT18)
 228 #define ETH_ZERO_PADDING                        (BIT19)
 229 #define ETH_TX_LAST_DESC                        (BIT20)
 230 #define ETH_TX_FIRST_DESC                       (BIT21)
 231 #define ETH_GEN_CRC                             (BIT22)
 232 #define ETH_TX_ENABLE_INTERRUPT                 (BIT23)
 233 #define ETH_AUTO_MODE                           (BIT30)
 234
 235 #define ETH_TX_IHL_SHIFT                        11
 236
 237 /* typedefs */
 238
 239 typedef enum _eth_func_ret_status {
 240         ETH_OK,                 /* Returned as expected.                */
 241         ETH_ERROR,              /* Fundamental error.                   */
 242         ETH_RETRY,              /* Could not process request. Try later.*/
 243         ETH_END_OF_JOB,         /* Ring has nothing to process.         */
 244         ETH_QUEUE_FULL,         /* Ring resource error.                 */
 245         ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust.     */
 246 } ETH_FUNC_RET_STATUS;
 247
 248 typedef enum _eth_target {
 249         ETH_TARGET_DRAM,
 250         ETH_TARGET_DEVICE,
 251         ETH_TARGET_CBS,
 252         ETH_TARGET_PCI0,
 253         ETH_TARGET_PCI1
 254 } ETH_TARGET;
 255
 256 /* These are for big-endian machines.  Little endian needs different
 257  * definitions.
 258  */
 259 #if defined(__BIG_ENDIAN)
 260 struct eth_rx_desc {
 261         u16 byte_cnt;           /* Descriptor buffer byte count         */
 262         u16 buf_size;           /* Buffer size                          */
 263         u32 cmd_sts;            /* Descriptor command status            */
 264         u32 next_desc_ptr;      /* Next descriptor pointer              */
 265         u32 buf_ptr;            /* Descriptor buffer pointer            */
 266 };
 267
 268 struct eth_tx_desc {
 269         u16 byte_cnt;           /* buffer byte count                    */
 270         u16 l4i_chk;            /* CPU provided TCP checksum            */
 271         u32 cmd_sts;            /* Command/status field                 */
 272         u32 next_desc_ptr;      /* Pointer to next descriptor           */
 273         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
 274 };
 275
 276 #elif defined(__LITTLE_ENDIAN)
 277 struct eth_rx_desc {
 278         u32 cmd_sts;            /* Descriptor command status            */
 279         u16 buf_size;           /* Buffer size                          */
 280         u16 byte_cnt;           /* Descriptor buffer byte count         */
 281         u32 buf_ptr;            /* Descriptor buffer pointer            */
 282         u32 next_desc_ptr;      /* Next descriptor pointer              */
 283 };
 284
 285 struct eth_tx_desc {
 286         u32 cmd_sts;            /* Command/status field                 */
 287         u16 l4i_chk;            /* CPU provided TCP checksum            */
 288         u16 byte_cnt;           /* buffer byte count                    */
 289         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
 290         u32 next_desc_ptr;      /* Pointer to next descriptor           */
 291 };
 292 #else
 293 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
 294 #endif
 295
 296 /* Unified struct for Rx and Tx operations. The user is not required to */
 297 /* be familier with neither Tx nor Rx descriptors.                      */
 298 struct pkt_info {
 299         unsigned short byte_cnt;        /* Descriptor buffer byte count */
 300         unsigned short l4i_chk;         /* Tx CPU provided TCP Checksum */
 301         unsigned int cmd_sts;           /* Descriptor command status    */
 302         dma_addr_t buf_ptr;             /* Descriptor buffer pointer    */
 303         struct sk_buff *return_info;    /* User resource return information */
 304 };
 305
 306 /* Ethernet port specific infomation */
 307
 308 struct mv643xx_mib_counters {
 309         u64 good_octets_received;
 310         u32 bad_octets_received;
 311         u32 internal_mac_transmit_err;
 312         u32 good_frames_received;
 313         u32 bad_frames_received;
 314         u32 broadcast_frames_received;
 315         u32 multicast_frames_received;
 316         u32 frames_64_octets;
 317         u32 frames_65_to_127_octets;
 318         u32 frames_128_to_255_octets;
 319         u32 frames_256_to_511_octets;
 320         u32 frames_512_to_1023_octets;
 321         u32 frames_1024_to_max_octets;
 322         u64 good_octets_sent;
 323         u32 good_frames_sent;
 324         u32 excessive_collision;
 325         u32 multicast_frames_sent;
 326         u32 broadcast_frames_sent;
 327         u32 unrec_mac_control_received;
 328         u32 fc_sent;
 329         u32 good_fc_received;
 330         u32 bad_fc_received;
 331         u32 undersize_received;
 332         u32 fragments_received;
 333         u32 oversize_received;
 334         u32 jabber_received;
 335         u32 mac_receive_error;
 336         u32 bad_crc_event;
 337         u32 collision;
 338         u32 late_collision;
 339 };
 340
 341 struct mv643xx_private {
 342         int port_num;                   /* User Ethernet port number    */
 343
 344         u32 rx_sram_addr;               /* Base address of rx sram area */
 345         u32 rx_sram_size;               /* Size of rx sram area         */
 346         u32 tx_sram_addr;               /* Base address of tx sram area */
 347         u32 tx_sram_size;               /* Size of tx sram area         */
 348
 349         int rx_resource_err;            /* Rx ring resource error flag */
 350
 351         /* Tx/Rx rings managment indexes fields. For driver use */
 352
 353         /* Next available and first returning Rx resource */
 354         int rx_curr_desc_q, rx_used_desc_q;
 355
 356         /* Next available and first returning Tx resource */
 357         int tx_curr_desc_q, tx_used_desc_q;
 358
 359 #ifdef MV643XX_TX_FAST_REFILL
 360         u32 tx_clean_threshold;
 361 #endif
 362
 363         struct eth_rx_desc *p_rx_desc_area;
 364         dma_addr_t rx_desc_dma;
 365         int rx_desc_area_size;
 366         struct sk_buff **rx_skb;
 367
 368         struct eth_tx_desc *p_tx_desc_area;
 369         dma_addr_t tx_desc_dma;
 370         int tx_desc_area_size;
 371         struct sk_buff **tx_skb;
 372
 373         struct work_struct tx_timeout_task;
 374
 375         struct net_device_stats stats;
 376         struct mv643xx_mib_counters mib_counters;
 377         spinlock_t lock;
 378         /* Size of Tx Ring per queue */
 379         int tx_ring_size;
 380         /* Number of tx descriptors in use */
 381         int tx_desc_count;
 382         /* Size of Rx Ring per queue */
 383         int rx_ring_size;
 384         /* Number of rx descriptors in use */
 385         int rx_desc_count;
 386
 387         /*
 388          * rx_task used to fill RX ring out of bottom half context
 389          */
 390         struct work_struct rx_task;
 391
 392         /*
 393          * Used in case RX Ring is empty, which can be caused when
 394          * system does not have resources (skb's)
 395          */
 396         struct timer_list timeout;
 397         long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
 398         unsigned rx_timer_flag;
 399
 400         u32 rx_int_coal;
 401         u32 tx_int_coal;
 402         struct mii_if_info mii;
 403 };
 404
 405 /* Port operation control routines */
 406 static void eth_port_init(struct mv643xx_private *mp);
 407 static void eth_port_reset(unsigned int eth_port_num);
 408 static void eth_port_start(struct net_device *dev);
 409
 410 /* Port MAC address routines */
 411 static void eth_port_uc_addr_set(unsigned int eth_port_num,
 412                                  unsigned char *p_addr);
 413
 414 /* PHY and MIB routines */
 415 static void ethernet_phy_reset(unsigned int eth_port_num);
 416
 417 static void eth_port_write_smi_reg(unsigned int eth_port_num,
 418                                    unsigned int phy_reg, unsigned int value);
 419
 420 static void eth_port_read_smi_reg(unsigned int eth_port_num,
 421                                   unsigned int phy_reg, unsigned int *value);
 422
 423 static void eth_clear_mib_counters(unsigned int eth_port_num);
 424
 425 /* Port data flow control routines */
 426 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
 427                                             struct pkt_info *p_pkt_info);
 428 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
 429                                               struct pkt_info *p_pkt_info);
 430
 431 #endif                          /* __MV643XX_ETH_H__ */