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sata_promise: issue ATAPI commands as normal packets
[linux-2.6/zen-sources.git] / drivers / ata / sata_promise.c
blob9d73cb9de42a5629045654e939fc6333ee4d0ab2
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include <asm/io.h>
47 #include "sata_promise.h"
48
49 #define DRV_NAME "sata_promise"
50 #define DRV_VERSION "1.05"
51
52
53 enum {
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
72
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
74 (1<<8) | (1<<9) | (1<<10),
75
76 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */
78 board_20619 = 2, /* FastTrak TX4000 */
79 board_2057x = 3, /* SATAII150 Tx2plus */
80 board_40518 = 4, /* SATAII150 Tx4 */
81
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
83
84 /* Sequence counter control registers bit definitions */
85 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
86
87 /* Feature register values */
88 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
89 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
90
91 /* Device/Head register values */
92 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
93
94 /* PDC_CTLSTAT bit definitions */
95 PDC_DMA_ENABLE = (1 << 7),
96 PDC_IRQ_DISABLE = (1 << 10),
97 PDC_RESET = (1 << 11), /* HDMA reset */
98
99 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
100 ATA_FLAG_MMIO |
101 ATA_FLAG_PIO_POLLING,
102
103 /* hp->flags bits */
104 PDC_FLAG_GEN_II = (1 << 0),
105 };
106
107
108 struct pdc_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 };
112
113 struct pdc_host_priv {
114 unsigned long flags;
115 unsigned long port_flags[ATA_MAX_PORTS];
116 };
117
118 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
122 static void pdc_eng_timeout(struct ata_port *ap);
123 static int pdc_port_start(struct ata_port *ap);
124 static void pdc_port_stop(struct ata_port *ap);
125 static void pdc_pata_phy_reset(struct ata_port *ap);
126 static void pdc_qc_prep(struct ata_queued_cmd *qc);
127 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
128 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
129 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
130 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
131 static void pdc_irq_clear(struct ata_port *ap);
132 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
133 static void pdc_host_stop(struct ata_host *host);
134 static void pdc_freeze(struct ata_port *ap);
135 static void pdc_thaw(struct ata_port *ap);
136 static void pdc_error_handler(struct ata_port *ap);
137 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
138
139
140 static struct scsi_host_template pdc_ata_sht = {
141 .module = THIS_MODULE,
142 .name = DRV_NAME,
143 .ioctl = ata_scsi_ioctl,
144 .queuecommand = ata_scsi_queuecmd,
145 .can_queue = ATA_DEF_QUEUE,
146 .this_id = ATA_SHT_THIS_ID,
147 .sg_tablesize = LIBATA_MAX_PRD,
148 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
149 .emulated = ATA_SHT_EMULATED,
150 .use_clustering = ATA_SHT_USE_CLUSTERING,
151 .proc_name = DRV_NAME,
152 .dma_boundary = ATA_DMA_BOUNDARY,
153 .slave_configure = ata_scsi_slave_config,
154 .slave_destroy = ata_scsi_slave_destroy,
155 .bios_param = ata_std_bios_param,
156 };
157
158 static const struct ata_port_operations pdc_sata_ops = {
159 .port_disable = ata_port_disable,
160 .tf_load = pdc_tf_load_mmio,
161 .tf_read = ata_tf_read,
162 .check_status = ata_check_status,
163 .exec_command = pdc_exec_command_mmio,
164 .dev_select = ata_std_dev_select,
165 .check_atapi_dma = pdc_check_atapi_dma,
166
167 .qc_prep = pdc_qc_prep,
168 .qc_issue = pdc_qc_issue_prot,
169 .freeze = pdc_freeze,
170 .thaw = pdc_thaw,
171 .error_handler = pdc_error_handler,
172 .post_internal_cmd = pdc_post_internal_cmd,
173 .data_xfer = ata_mmio_data_xfer,
174 .irq_handler = pdc_interrupt,
175 .irq_clear = pdc_irq_clear,
176
177 .scr_read = pdc_sata_scr_read,
178 .scr_write = pdc_sata_scr_write,
179 .port_start = pdc_port_start,
180 .port_stop = pdc_port_stop,
181 .host_stop = pdc_host_stop,
182 };
183
184 /* First-generation chips need a more restrictive ->check_atapi_dma op */
185 static const struct ata_port_operations pdc_old_sata_ops = {
186 .port_disable = ata_port_disable,
187 .tf_load = pdc_tf_load_mmio,
188 .tf_read = ata_tf_read,
189 .check_status = ata_check_status,
190 .exec_command = pdc_exec_command_mmio,
191 .dev_select = ata_std_dev_select,
192 .check_atapi_dma = pdc_old_check_atapi_dma,
193
194 .qc_prep = pdc_qc_prep,
195 .qc_issue = pdc_qc_issue_prot,
196 .freeze = pdc_freeze,
197 .thaw = pdc_thaw,
198 .error_handler = pdc_error_handler,
199 .post_internal_cmd = pdc_post_internal_cmd,
200 .data_xfer = ata_mmio_data_xfer,
201 .irq_handler = pdc_interrupt,
202 .irq_clear = pdc_irq_clear,
203
204 .scr_read = pdc_sata_scr_read,
205 .scr_write = pdc_sata_scr_write,
206 .port_start = pdc_port_start,
207 .port_stop = pdc_port_stop,
208 .host_stop = pdc_host_stop,
209 };
210
211 static const struct ata_port_operations pdc_pata_ops = {
212 .port_disable = ata_port_disable,
213 .tf_load = pdc_tf_load_mmio,
214 .tf_read = ata_tf_read,
215 .check_status = ata_check_status,
216 .exec_command = pdc_exec_command_mmio,
217 .dev_select = ata_std_dev_select,
218 .check_atapi_dma = pdc_check_atapi_dma,
219
220 .phy_reset = pdc_pata_phy_reset,
221
222 .qc_prep = pdc_qc_prep,
223 .qc_issue = pdc_qc_issue_prot,
224 .data_xfer = ata_mmio_data_xfer,
225 .eng_timeout = pdc_eng_timeout,
226 .irq_handler = pdc_interrupt,
227 .irq_clear = pdc_irq_clear,
228
229 .port_start = pdc_port_start,
230 .port_stop = pdc_port_stop,
231 .host_stop = pdc_host_stop,
232 };
233
234 static const struct ata_port_info pdc_port_info[] = {
235 /* board_2037x */
236 {
237 .sht = &pdc_ata_sht,
238 .flags = PDC_COMMON_FLAGS,
239 .pio_mask = 0x1f, /* pio0-4 */
240 .mwdma_mask = 0x07, /* mwdma0-2 */
241 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
242 .port_ops = &pdc_old_sata_ops,
243 },
244
245 /* board_20319 */
246 {
247 .sht = &pdc_ata_sht,
248 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
249 .pio_mask = 0x1f, /* pio0-4 */
250 .mwdma_mask = 0x07, /* mwdma0-2 */
251 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
252 .port_ops = &pdc_old_sata_ops,
253 },
254
255 /* board_20619 */
256 {
257 .sht = &pdc_ata_sht,
258 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
259 .pio_mask = 0x1f, /* pio0-4 */
260 .mwdma_mask = 0x07, /* mwdma0-2 */
261 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
262 .port_ops = &pdc_pata_ops,
263 },
264
265 /* board_2057x */
266 {
267 .sht = &pdc_ata_sht,
268 .flags = PDC_COMMON_FLAGS,
269 .pio_mask = 0x1f, /* pio0-4 */
270 .mwdma_mask = 0x07, /* mwdma0-2 */
271 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
272 .port_ops = &pdc_sata_ops,
273 },
274
275 /* board_40518 */
276 {
277 .sht = &pdc_ata_sht,
278 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
279 .pio_mask = 0x1f, /* pio0-4 */
280 .mwdma_mask = 0x07, /* mwdma0-2 */
281 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
282 .port_ops = &pdc_sata_ops,
283 },
284 };
285
286 static const struct pci_device_id pdc_ata_pci_tbl[] = {
287 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
288 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
289 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
290 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
291 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
293 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
295 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
296 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
297
298 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
299 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
300 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
301 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
302 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
303 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
304
305 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
306
307 { } /* terminate list */
308 };
309
310
311 static struct pci_driver pdc_ata_pci_driver = {
312 .name = DRV_NAME,
313 .id_table = pdc_ata_pci_tbl,
314 .probe = pdc_ata_init_one,
315 .remove = ata_pci_remove_one,
316 };
317
318
319 static int pdc_port_start(struct ata_port *ap)
320 {
321 struct device *dev = ap->host->dev;
322 struct pdc_host_priv *hp = ap->host->private_data;
323 struct pdc_port_priv *pp;
324 int rc;
325
326 /* fix up port flags and cable type for SATA+PATA chips */
327 ap->flags |= hp->port_flags[ap->port_no];
328 if (ap->flags & ATA_FLAG_SATA)
329 ap->cbl = ATA_CBL_SATA;
330
331 rc = ata_port_start(ap);
332 if (rc)
333 return rc;
334
335 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
336 if (!pp) {
337 rc = -ENOMEM;
338 goto err_out;
339 }
340
341 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
342 if (!pp->pkt) {
343 rc = -ENOMEM;
344 goto err_out_kfree;
345 }
346
347 ap->private_data = pp;
348
349 /* fix up PHYMODE4 align timing */
350 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
351 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
352 unsigned int tmp;
353
354 tmp = readl(mmio + 0x014);
355 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
356 writel(tmp, mmio + 0x014);
357 }
358
359 return 0;
360
361 err_out_kfree:
362 kfree(pp);
363 err_out:
364 ata_port_stop(ap);
365 return rc;
366 }
367
368
369 static void pdc_port_stop(struct ata_port *ap)
370 {
371 struct device *dev = ap->host->dev;
372 struct pdc_port_priv *pp = ap->private_data;
373
374 ap->private_data = NULL;
375 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
376 kfree(pp);
377 ata_port_stop(ap);
378 }
379
380
381 static void pdc_host_stop(struct ata_host *host)
382 {
383 struct pdc_host_priv *hp = host->private_data;
384
385 ata_pci_host_stop(host);
386
387 kfree(hp);
388 }
389
390
391 static void pdc_reset_port(struct ata_port *ap)
392 {
393 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
394 unsigned int i;
395 u32 tmp;
396
397 for (i = 11; i > 0; i--) {
398 tmp = readl(mmio);
399 if (tmp & PDC_RESET)
400 break;
401
402 udelay(100);
403
404 tmp |= PDC_RESET;
405 writel(tmp, mmio);
406 }
407
408 tmp &= ~PDC_RESET;
409 writel(tmp, mmio);
410 readl(mmio); /* flush */
411 }
412
413 static void pdc_pata_cbl_detect(struct ata_port *ap)
414 {
415 u8 tmp;
416 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
417
418 tmp = readb(mmio);
419
420 if (tmp & 0x01) {
421 ap->cbl = ATA_CBL_PATA40;
422 ap->udma_mask &= ATA_UDMA_MASK_40C;
423 } else
424 ap->cbl = ATA_CBL_PATA80;
425 }
426
427 static void pdc_pata_phy_reset(struct ata_port *ap)
428 {
429 pdc_pata_cbl_detect(ap);
430 pdc_reset_port(ap);
431 ata_port_probe(ap);
432 ata_bus_reset(ap);
433 }
434
435 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
436 {
437 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
438 return 0xffffffffU;
439 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
440 }
441
442
443 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
444 u32 val)
445 {
446 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
447 return;
448 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
449 }
450
451 static void pdc_atapi_dma_pkt(struct ata_queued_cmd *qc)
452 {
453 struct ata_port *ap = qc->ap;
454 dma_addr_t sg_table = ap->prd_dma;
455 unsigned int cdb_len = qc->dev->cdb_len;
456 u8 *cdb = qc->cdb;
457 struct pdc_port_priv *pp = ap->private_data;
458 u8 *buf = pp->pkt;
459 u32 *buf32 = (u32 *) buf;
460 unsigned int dev_sel, feature, nbytes;
461
462 /* set control bits (byte 0), zero delay seq id (byte 3),
463 * and seq id (byte 2)
464 */
465 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
466 buf32[0] = cpu_to_le32(PDC_PKT_READ);
467 else
468 buf32[0] = 0;
469 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
470 buf32[2] = 0; /* no next-packet */
471
472 /* select drive */
473 if (sata_scr_valid(ap)) {
474 dev_sel = PDC_DEVICE_SATA;
475 } else {
476 dev_sel = ATA_DEVICE_OBS;
477 if (qc->dev->devno != 0)
478 dev_sel |= ATA_DEV1;
479 }
480 buf[12] = (1 << 5) | ATA_REG_DEVICE;
481 buf[13] = dev_sel;
482 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
483 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
484
485 buf[16] = (1 << 5) | ATA_REG_NSECT;
486 buf[17] = 0x00;
487 buf[18] = (1 << 5) | ATA_REG_LBAL;
488 buf[19] = 0x00;
489
490 /* set feature and byte counter registers */
491 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
492 feature = PDC_FEATURE_ATAPI_PIO;
493 /* set byte counter register to real transfer byte count */
494 nbytes = qc->nbytes;
495 if (!nbytes)
496 nbytes = qc->nsect << 9;
497 if (nbytes > 0xffff)
498 nbytes = 0xffff;
499 } else {
500 feature = PDC_FEATURE_ATAPI_DMA;
501 /* set byte counter register to 0 */
502 nbytes = 0;
503 }
504 buf[20] = (1 << 5) | ATA_REG_FEATURE;
505 buf[21] = feature;
506 buf[22] = (1 << 5) | ATA_REG_BYTEL;
507 buf[23] = nbytes & 0xFF;
508 buf[24] = (1 << 5) | ATA_REG_BYTEH;
509 buf[25] = (nbytes >> 8) & 0xFF;
510
511 /* send ATAPI packet command 0xA0 */
512 buf[26] = (1 << 5) | ATA_REG_CMD;
513 buf[27] = ATA_CMD_PACKET;
514
515 /* select drive and check DRQ */
516 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
517 buf[29] = dev_sel;
518
519 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
520 BUG_ON(cdb_len & ~0x1E);
521
522 /* append the CDB as the final part */
523 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
524 memcpy(buf+31, cdb, cdb_len);
525 }
526
527 static void pdc_qc_prep(struct ata_queued_cmd *qc)
528 {
529 struct pdc_port_priv *pp = qc->ap->private_data;
530 unsigned int i;
531
532 VPRINTK("ENTER\n");
533
534 switch (qc->tf.protocol) {
535 case ATA_PROT_DMA:
536 ata_qc_prep(qc);
537 /* fall through */
538
539 case ATA_PROT_NODATA:
540 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
541 qc->dev->devno, pp->pkt);
542
543 if (qc->tf.flags & ATA_TFLAG_LBA48)
544 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
545 else
546 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
547
548 pdc_pkt_footer(&qc->tf, pp->pkt, i);
549 break;
550
551 case ATA_PROT_ATAPI:
552 case ATA_PROT_ATAPI_NODATA:
553 ata_qc_prep(qc);
554 break;
555
556 case ATA_PROT_ATAPI_DMA:
557 ata_qc_prep(qc);
558 pdc_atapi_dma_pkt(qc);
559 break;
560
561 default:
562 break;
563 }
564 }
565
566 static void pdc_freeze(struct ata_port *ap)
567 {
568 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
569 u32 tmp;
570
571 tmp = readl(mmio + PDC_CTLSTAT);
572 tmp |= PDC_IRQ_DISABLE;
573 tmp &= ~PDC_DMA_ENABLE;
574 writel(tmp, mmio + PDC_CTLSTAT);
575 readl(mmio + PDC_CTLSTAT); /* flush */
576 }
577
578 static void pdc_thaw(struct ata_port *ap)
579 {
580 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
581 u32 tmp;
582
583 /* clear IRQ */
584 readl(mmio + PDC_INT_SEQMASK);
585
586 /* turn IRQ back on */
587 tmp = readl(mmio + PDC_CTLSTAT);
588 tmp &= ~PDC_IRQ_DISABLE;
589 writel(tmp, mmio + PDC_CTLSTAT);
590 readl(mmio + PDC_CTLSTAT); /* flush */
591 }
592
593 static void pdc_error_handler(struct ata_port *ap)
594 {
595 ata_reset_fn_t hardreset;
596
597 if (!(ap->pflags & ATA_PFLAG_FROZEN))
598 pdc_reset_port(ap);
599
600 hardreset = NULL;
601 if (sata_scr_valid(ap))
602 hardreset = sata_std_hardreset;
603
604 /* perform recovery */
605 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
606 ata_std_postreset);
607 }
608
609 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
610 {
611 struct ata_port *ap = qc->ap;
612
613 if (qc->flags & ATA_QCFLAG_FAILED)
614 qc->err_mask |= AC_ERR_OTHER;
615
616 /* make DMA engine forget about the failed command */
617 if (qc->err_mask)
618 pdc_reset_port(ap);
619 }
620
621 static void pdc_eng_timeout(struct ata_port *ap)
622 {
623 struct ata_host *host = ap->host;
624 u8 drv_stat;
625 struct ata_queued_cmd *qc;
626 unsigned long flags;
627
628 DPRINTK("ENTER\n");
629
630 spin_lock_irqsave(&host->lock, flags);
631
632 qc = ata_qc_from_tag(ap, ap->active_tag);
633
634 switch (qc->tf.protocol) {
635 case ATA_PROT_DMA:
636 case ATA_PROT_NODATA:
637 ata_port_printk(ap, KERN_ERR, "command timeout\n");
638 drv_stat = ata_wait_idle(ap);
639 qc->err_mask |= __ac_err_mask(drv_stat);
640 break;
641
642 default:
643 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
644
645 ata_port_printk(ap, KERN_ERR,
646 "unknown timeout, cmd 0x%x stat 0x%x\n",
647 qc->tf.command, drv_stat);
648
649 qc->err_mask |= ac_err_mask(drv_stat);
650 break;
651 }
652
653 spin_unlock_irqrestore(&host->lock, flags);
654 ata_eh_qc_complete(qc);
655 DPRINTK("EXIT\n");
656 }
657
658 static inline unsigned int pdc_host_intr( struct ata_port *ap,
659 struct ata_queued_cmd *qc)
660 {
661 unsigned int handled = 0;
662 u32 tmp;
663 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
664
665 tmp = readl(mmio);
666 if (tmp & PDC_ERR_MASK) {
667 qc->err_mask |= AC_ERR_DEV;
668 pdc_reset_port(ap);
669 }
670
671 switch (qc->tf.protocol) {
672 case ATA_PROT_DMA:
673 case ATA_PROT_NODATA:
674 case ATA_PROT_ATAPI_DMA:
675 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
676 ata_qc_complete(qc);
677 handled = 1;
678 break;
679
680 default:
681 ap->stats.idle_irq++;
682 break;
683 }
684
685 return handled;
686 }
687
688 static void pdc_irq_clear(struct ata_port *ap)
689 {
690 struct ata_host *host = ap->host;
691 void __iomem *mmio = host->mmio_base;
692
693 readl(mmio + PDC_INT_SEQMASK);
694 }
695
696 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
697 {
698 struct ata_host *host = dev_instance;
699 struct ata_port *ap;
700 u32 mask = 0;
701 unsigned int i, tmp;
702 unsigned int handled = 0;
703 void __iomem *mmio_base;
704
705 VPRINTK("ENTER\n");
706
707 if (!host || !host->mmio_base) {
708 VPRINTK("QUICK EXIT\n");
709 return IRQ_NONE;
710 }
711
712 mmio_base = host->mmio_base;
713
714 /* reading should also clear interrupts */
715 mask = readl(mmio_base + PDC_INT_SEQMASK);
716
717 if (mask == 0xffffffff) {
718 VPRINTK("QUICK EXIT 2\n");
719 return IRQ_NONE;
720 }
721
722 spin_lock(&host->lock);
723
724 mask &= 0xffff; /* only 16 tags possible */
725 if (!mask) {
726 VPRINTK("QUICK EXIT 3\n");
727 goto done_irq;
728 }
729
730 writel(mask, mmio_base + PDC_INT_SEQMASK);
731
732 for (i = 0; i < host->n_ports; i++) {
733 VPRINTK("port %u\n", i);
734 ap = host->ports[i];
735 tmp = mask & (1 << (i + 1));
736 if (tmp && ap &&
737 !(ap->flags & ATA_FLAG_DISABLED)) {
738 struct ata_queued_cmd *qc;
739
740 qc = ata_qc_from_tag(ap, ap->active_tag);
741 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
742 handled += pdc_host_intr(ap, qc);
743 }
744 }
745
746 VPRINTK("EXIT\n");
747
748 done_irq:
749 spin_unlock(&host->lock);
750 return IRQ_RETVAL(handled);
751 }
752
753 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
754 {
755 struct ata_port *ap = qc->ap;
756 struct pdc_port_priv *pp = ap->private_data;
757 unsigned int port_no = ap->port_no;
758 u8 seq = (u8) (port_no + 1);
759
760 VPRINTK("ENTER, ap %p\n", ap);
761
762 writel(0x00000001, ap->host->mmio_base + (seq * 4));
763 readl(ap->host->mmio_base + (seq * 4)); /* flush */
764
765 pp->pkt[2] = seq;
766 wmb(); /* flush PRD, pkt writes */
767 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
768 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
769 }
770
771 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
772 {
773 switch (qc->tf.protocol) {
774 case ATA_PROT_ATAPI_DMA:
775 case ATA_PROT_DMA:
776 case ATA_PROT_NODATA:
777 pdc_packet_start(qc);
778 return 0;
779
780 default:
781 break;
782 }
783
784 return ata_qc_issue_prot(qc);
785 }
786
787 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
788 {
789 WARN_ON (tf->protocol == ATA_PROT_DMA ||
790 tf->protocol == ATA_PROT_NODATA);
791 ata_tf_load(ap, tf);
792 }
793
794
795 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
796 {
797 WARN_ON (tf->protocol == ATA_PROT_DMA ||
798 tf->protocol == ATA_PROT_NODATA);
799 ata_exec_command(ap, tf);
800 }
801
802 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
803 {
804 u8 *scsicmd = qc->scsicmd->cmnd;
805 int pio = 1; /* atapi dma off by default */
806
807 /* Whitelist commands that may use DMA. */
808 switch (scsicmd[0]) {
809 case WRITE_12:
810 case WRITE_10:
811 case WRITE_6:
812 case READ_12:
813 case READ_10:
814 case READ_6:
815 case 0xad: /* READ_DVD_STRUCTURE */
816 case 0xbe: /* READ_CD */
817 pio = 0;
818 }
819 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
820 if (scsicmd[0] == WRITE_10) {
821 unsigned int lba;
822 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
823 if (lba >= 0xFFFF4FA2)
824 pio = 1;
825 }
826 return pio;
827 }
828
829 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
830 {
831 struct ata_port *ap = qc->ap;
832
833 /* First generation chips cannot use ATAPI DMA on SATA ports */
834 if (sata_scr_valid(ap))
835 return 1;
836 return pdc_check_atapi_dma(qc);
837 }
838
839 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
840 {
841 port->cmd_addr = base;
842 port->data_addr = base;
843 port->feature_addr =
844 port->error_addr = base + 0x4;
845 port->nsect_addr = base + 0x8;
846 port->lbal_addr = base + 0xc;
847 port->lbam_addr = base + 0x10;
848 port->lbah_addr = base + 0x14;
849 port->device_addr = base + 0x18;
850 port->command_addr =
851 port->status_addr = base + 0x1c;
852 port->altstatus_addr =
853 port->ctl_addr = base + 0x38;
854 }
855
856
857 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
858 {
859 void __iomem *mmio = pe->mmio_base;
860 struct pdc_host_priv *hp = pe->private_data;
861 int hotplug_offset;
862 u32 tmp;
863
864 if (hp->flags & PDC_FLAG_GEN_II)
865 hotplug_offset = PDC2_SATA_PLUG_CSR;
866 else
867 hotplug_offset = PDC_SATA_PLUG_CSR;
868
869 /*
870 * Except for the hotplug stuff, this is voodoo from the
871 * Promise driver. Label this entire section
872 * "TODO: figure out why we do this"
873 */
874
875 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
876 tmp = readl(mmio + PDC_FLASH_CTL);
877 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
878 if (!(hp->flags & PDC_FLAG_GEN_II))
879 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
880 writel(tmp, mmio + PDC_FLASH_CTL);
881
882 /* clear plug/unplug flags for all ports */
883 tmp = readl(mmio + hotplug_offset);
884 writel(tmp | 0xff, mmio + hotplug_offset);
885
886 /* mask plug/unplug ints */
887 tmp = readl(mmio + hotplug_offset);
888 writel(tmp | 0xff0000, mmio + hotplug_offset);
889
890 /* don't initialise TBG or SLEW on 2nd generation chips */
891 if (hp->flags & PDC_FLAG_GEN_II)
892 return;
893
894 /* reduce TBG clock to 133 Mhz. */
895 tmp = readl(mmio + PDC_TBG_MODE);
896 tmp &= ~0x30000; /* clear bit 17, 16*/
897 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
898 writel(tmp, mmio + PDC_TBG_MODE);
899
900 readl(mmio + PDC_TBG_MODE); /* flush */
901 msleep(10);
902
903 /* adjust slew rate control register. */
904 tmp = readl(mmio + PDC_SLEW_CTL);
905 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
906 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
907 writel(tmp, mmio + PDC_SLEW_CTL);
908 }
909
910 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
911 {
912 static int printed_version;
913 struct ata_probe_ent *probe_ent = NULL;
914 struct pdc_host_priv *hp;
915 unsigned long base;
916 void __iomem *mmio_base;
917 unsigned int board_idx = (unsigned int) ent->driver_data;
918 int pci_dev_busy = 0;
919 int rc;
920 u8 tmp;
921
922 if (!printed_version++)
923 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
924
925 rc = pci_enable_device(pdev);
926 if (rc)
927 return rc;
928
929 rc = pci_request_regions(pdev, DRV_NAME);
930 if (rc) {
931 pci_dev_busy = 1;
932 goto err_out;
933 }
934
935 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
936 if (rc)
937 goto err_out_regions;
938 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
939 if (rc)
940 goto err_out_regions;
941
942 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
943 if (probe_ent == NULL) {
944 rc = -ENOMEM;
945 goto err_out_regions;
946 }
947
948 probe_ent->dev = pci_dev_to_dev(pdev);
949 INIT_LIST_HEAD(&probe_ent->node);
950
951 mmio_base = pci_iomap(pdev, 3, 0);
952 if (mmio_base == NULL) {
953 rc = -ENOMEM;
954 goto err_out_free_ent;
955 }
956 base = (unsigned long) mmio_base;
957
958 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
959 if (hp == NULL) {
960 rc = -ENOMEM;
961 goto err_out_free_ent;
962 }
963
964 probe_ent->private_data = hp;
965
966 probe_ent->sht = pdc_port_info[board_idx].sht;
967 probe_ent->port_flags = pdc_port_info[board_idx].flags;
968 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
969 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
970 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
971 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
972
973 probe_ent->irq = pdev->irq;
974 probe_ent->irq_flags = IRQF_SHARED;
975 probe_ent->mmio_base = mmio_base;
976
977 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
978 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
979
980 probe_ent->port[0].scr_addr = base + 0x400;
981 probe_ent->port[1].scr_addr = base + 0x500;
982
983 /* notice 4-port boards */
984 switch (board_idx) {
985 case board_40518:
986 hp->flags |= PDC_FLAG_GEN_II;
987 /* Fall through */
988 case board_20319:
989 probe_ent->n_ports = 4;
990
991 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
992 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
993
994 probe_ent->port[2].scr_addr = base + 0x600;
995 probe_ent->port[3].scr_addr = base + 0x700;
996 break;
997 case board_2057x:
998 hp->flags |= PDC_FLAG_GEN_II;
999 /* Fall through */
1000 case board_2037x:
1001 /* TX2plus boards also have a PATA port */
1002 tmp = readb(mmio_base + PDC_FLASH_CTL+1);
1003 if (!(tmp & 0x80)) {
1004 probe_ent->n_ports = 3;
1005 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1006 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
1007 printk(KERN_INFO DRV_NAME " PATA port found\n");
1008 } else
1009 probe_ent->n_ports = 2;
1010 hp->port_flags[0] = ATA_FLAG_SATA;
1011 hp->port_flags[1] = ATA_FLAG_SATA;
1012 break;
1013 case board_20619:
1014 probe_ent->n_ports = 4;
1015
1016 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
1017 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
1018
1019 probe_ent->port[2].scr_addr = base + 0x600;
1020 probe_ent->port[3].scr_addr = base + 0x700;
1021 break;
1022 default:
1023 BUG();
1024 break;
1025 }
1026
1027 pci_set_master(pdev);
1028
1029 /* initialize adapter */
1030 pdc_host_init(board_idx, probe_ent);
1031
1032 /* FIXME: Need any other frees than hp? */
1033 if (!ata_device_add(probe_ent))
1034 kfree(hp);
1035
1036 kfree(probe_ent);
1037
1038 return 0;
1039
1040 err_out_free_ent:
1041 kfree(probe_ent);
1042 err_out_regions:
1043 pci_release_regions(pdev);
1044 err_out:
1045 if (!pci_dev_busy)
1046 pci_disable_device(pdev);
1047 return rc;
1048 }
1049
1050
1051 static int __init pdc_ata_init(void)
1052 {
1053 return pci_register_driver(&pdc_ata_pci_driver);
1054 }
1055
1056
1057 static void __exit pdc_ata_exit(void)
1058 {
1059 pci_unregister_driver(&pdc_ata_pci_driver);
1060 }
1061
1062
1063 MODULE_AUTHOR("Jeff Garzik");
1064 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1065 MODULE_LICENSE("GPL");
1066 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1067 MODULE_VERSION(DRV_VERSION);
1068
1069 module_init(pdc_ata_init);
1070 module_exit(pdc_ata_exit);
Stable & featurefull patchset based on Linus's git branch