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[PATCH] S3C2410 GPIO wrappers
[linux-2.6/zen-sources.git] / arch / sparc64 / kernel / traps.c
blobad67784292db6aafe26aedc02e9deb130007da3e
1 /* $Id: traps.c,v 1.85 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/kernel/traps.c
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 /*
9 * I like traps on v9, :))))
10 */
11
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/kallsyms.h>
16 #include <linux/signal.h>
17 #include <linux/smp.h>
18 #include <linux/smp_lock.h>
19 #include <linux/mm.h>
20 #include <linux/init.h>
21
22 #include <asm/delay.h>
23 #include <asm/system.h>
24 #include <asm/ptrace.h>
25 #include <asm/oplib.h>
26 #include <asm/page.h>
27 #include <asm/pgtable.h>
28 #include <asm/unistd.h>
29 #include <asm/uaccess.h>
30 #include <asm/fpumacro.h>
31 #include <asm/lsu.h>
32 #include <asm/dcu.h>
33 #include <asm/estate.h>
34 #include <asm/chafsr.h>
35 #include <asm/sfafsr.h>
36 #include <asm/psrcompat.h>
37 #include <asm/processor.h>
38 #include <asm/timer.h>
39 #include <asm/kdebug.h>
40 #include <asm/head.h>
41 #ifdef CONFIG_KMOD
42 #include <linux/kmod.h>
43 #endif
44 #include <asm/prom.h>
45
46 ATOMIC_NOTIFIER_HEAD(sparc64die_chain);
47
48 int register_die_notifier(struct notifier_block *nb)
49 {
50 return atomic_notifier_chain_register(&sparc64die_chain, nb);
51 }
52 EXPORT_SYMBOL(register_die_notifier);
53
54 int unregister_die_notifier(struct notifier_block *nb)
55 {
56 return atomic_notifier_chain_unregister(&sparc64die_chain, nb);
57 }
58 EXPORT_SYMBOL(unregister_die_notifier);
59
60 /* When an irrecoverable trap occurs at tl > 0, the trap entry
61 * code logs the trap state registers at every level in the trap
62 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
63 * is as follows:
64 */
65 struct tl1_traplog {
66 struct {
67 unsigned long tstate;
68 unsigned long tpc;
69 unsigned long tnpc;
70 unsigned long tt;
71 } trapstack[4];
72 unsigned long tl;
73 };
74
75 static void dump_tl1_traplog(struct tl1_traplog *p)
76 {
77 int i, limit;
78
79 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
80 "dumping track stack.\n", p->tl);
81
82 limit = (tlb_type == hypervisor) ? 2 : 4;
83 for (i = 0; i < limit; i++) {
84 printk(KERN_EMERG
85 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
86 "TNPC[%016lx] TT[%lx]\n",
87 i + 1,
88 p->trapstack[i].tstate, p->trapstack[i].tpc,
89 p->trapstack[i].tnpc, p->trapstack[i].tt);
90 print_symbol("TRAPLOG: TPC<%s>\n", p->trapstack[i].tpc);
91 }
92 }
93
94 void do_call_debug(struct pt_regs *regs)
95 {
96 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
97 }
98
99 void bad_trap(struct pt_regs *regs, long lvl)
100 {
101 char buffer[32];
102 siginfo_t info;
103
104 if (notify_die(DIE_TRAP, "bad trap", regs,
105 0, lvl, SIGTRAP) == NOTIFY_STOP)
106 return;
107
108 if (lvl < 0x100) {
109 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
110 die_if_kernel(buffer, regs);
111 }
112
113 lvl -= 0x100;
114 if (regs->tstate & TSTATE_PRIV) {
115 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
116 die_if_kernel(buffer, regs);
117 }
118 if (test_thread_flag(TIF_32BIT)) {
119 regs->tpc &= 0xffffffff;
120 regs->tnpc &= 0xffffffff;
121 }
122 info.si_signo = SIGILL;
123 info.si_errno = 0;
124 info.si_code = ILL_ILLTRP;
125 info.si_addr = (void __user *)regs->tpc;
126 info.si_trapno = lvl;
127 force_sig_info(SIGILL, &info, current);
128 }
129
130 void bad_trap_tl1(struct pt_regs *regs, long lvl)
131 {
132 char buffer[32];
133
134 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
135 0, lvl, SIGTRAP) == NOTIFY_STOP)
136 return;
137
138 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
139
140 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
141 die_if_kernel (buffer, regs);
142 }
143
144 #ifdef CONFIG_DEBUG_BUGVERBOSE
145 void do_BUG(const char *file, int line)
146 {
147 bust_spinlocks(1);
148 printk("kernel BUG at %s:%d!\n", file, line);
149 }
150 #endif
151
152 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
153 {
154 siginfo_t info;
155
156 if (notify_die(DIE_TRAP, "instruction access exception", regs,
157 0, 0x8, SIGTRAP) == NOTIFY_STOP)
158 return;
159
160 if (regs->tstate & TSTATE_PRIV) {
161 printk("spitfire_insn_access_exception: SFSR[%016lx] "
162 "SFAR[%016lx], going.\n", sfsr, sfar);
163 die_if_kernel("Iax", regs);
164 }
165 if (test_thread_flag(TIF_32BIT)) {
166 regs->tpc &= 0xffffffff;
167 regs->tnpc &= 0xffffffff;
168 }
169 info.si_signo = SIGSEGV;
170 info.si_errno = 0;
171 info.si_code = SEGV_MAPERR;
172 info.si_addr = (void __user *)regs->tpc;
173 info.si_trapno = 0;
174 force_sig_info(SIGSEGV, &info, current);
175 }
176
177 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
178 {
179 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
180 0, 0x8, SIGTRAP) == NOTIFY_STOP)
181 return;
182
183 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
184 spitfire_insn_access_exception(regs, sfsr, sfar);
185 }
186
187 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
188 {
189 unsigned short type = (type_ctx >> 16);
190 unsigned short ctx = (type_ctx & 0xffff);
191 siginfo_t info;
192
193 if (notify_die(DIE_TRAP, "instruction access exception", regs,
194 0, 0x8, SIGTRAP) == NOTIFY_STOP)
195 return;
196
197 if (regs->tstate & TSTATE_PRIV) {
198 printk("sun4v_insn_access_exception: ADDR[%016lx] "
199 "CTX[%04x] TYPE[%04x], going.\n",
200 addr, ctx, type);
201 die_if_kernel("Iax", regs);
202 }
203
204 if (test_thread_flag(TIF_32BIT)) {
205 regs->tpc &= 0xffffffff;
206 regs->tnpc &= 0xffffffff;
207 }
208 info.si_signo = SIGSEGV;
209 info.si_errno = 0;
210 info.si_code = SEGV_MAPERR;
211 info.si_addr = (void __user *) addr;
212 info.si_trapno = 0;
213 force_sig_info(SIGSEGV, &info, current);
214 }
215
216 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
217 {
218 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
219 0, 0x8, SIGTRAP) == NOTIFY_STOP)
220 return;
221
222 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
223 sun4v_insn_access_exception(regs, addr, type_ctx);
224 }
225
226 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
227 {
228 siginfo_t info;
229
230 if (notify_die(DIE_TRAP, "data access exception", regs,
231 0, 0x30, SIGTRAP) == NOTIFY_STOP)
232 return;
233
234 if (regs->tstate & TSTATE_PRIV) {
235 /* Test if this comes from uaccess places. */
236 const struct exception_table_entry *entry;
237
238 entry = search_exception_tables(regs->tpc);
239 if (entry) {
240 /* Ouch, somebody is trying VM hole tricks on us... */
241 #ifdef DEBUG_EXCEPTIONS
242 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
243 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
244 regs->tpc, entry->fixup);
245 #endif
246 regs->tpc = entry->fixup;
247 regs->tnpc = regs->tpc + 4;
248 return;
249 }
250 /* Shit... */
251 printk("spitfire_data_access_exception: SFSR[%016lx] "
252 "SFAR[%016lx], going.\n", sfsr, sfar);
253 die_if_kernel("Dax", regs);
254 }
255
256 info.si_signo = SIGSEGV;
257 info.si_errno = 0;
258 info.si_code = SEGV_MAPERR;
259 info.si_addr = (void __user *)sfar;
260 info.si_trapno = 0;
261 force_sig_info(SIGSEGV, &info, current);
262 }
263
264 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
265 {
266 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
267 0, 0x30, SIGTRAP) == NOTIFY_STOP)
268 return;
269
270 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
271 spitfire_data_access_exception(regs, sfsr, sfar);
272 }
273
274 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
275 {
276 unsigned short type = (type_ctx >> 16);
277 unsigned short ctx = (type_ctx & 0xffff);
278 siginfo_t info;
279
280 if (notify_die(DIE_TRAP, "data access exception", regs,
281 0, 0x8, SIGTRAP) == NOTIFY_STOP)
282 return;
283
284 if (regs->tstate & TSTATE_PRIV) {
285 printk("sun4v_data_access_exception: ADDR[%016lx] "
286 "CTX[%04x] TYPE[%04x], going.\n",
287 addr, ctx, type);
288 die_if_kernel("Dax", regs);
289 }
290
291 if (test_thread_flag(TIF_32BIT)) {
292 regs->tpc &= 0xffffffff;
293 regs->tnpc &= 0xffffffff;
294 }
295 info.si_signo = SIGSEGV;
296 info.si_errno = 0;
297 info.si_code = SEGV_MAPERR;
298 info.si_addr = (void __user *) addr;
299 info.si_trapno = 0;
300 force_sig_info(SIGSEGV, &info, current);
301 }
302
303 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
304 {
305 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
306 0, 0x8, SIGTRAP) == NOTIFY_STOP)
307 return;
308
309 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
310 sun4v_data_access_exception(regs, addr, type_ctx);
311 }
312
313 #ifdef CONFIG_PCI
314 /* This is really pathetic... */
315 extern volatile int pci_poke_in_progress;
316 extern volatile int pci_poke_cpu;
317 extern volatile int pci_poke_faulted;
318 #endif
319
320 /* When access exceptions happen, we must do this. */
321 static void spitfire_clean_and_reenable_l1_caches(void)
322 {
323 unsigned long va;
324
325 if (tlb_type != spitfire)
326 BUG();
327
328 /* Clean 'em. */
329 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
330 spitfire_put_icache_tag(va, 0x0);
331 spitfire_put_dcache_tag(va, 0x0);
332 }
333
334 /* Re-enable in LSU. */
335 __asm__ __volatile__("flush %%g6\n\t"
336 "membar #Sync\n\t"
337 "stxa %0, [%%g0] %1\n\t"
338 "membar #Sync"
339 : /* no outputs */
340 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
341 LSU_CONTROL_IM | LSU_CONTROL_DM),
342 "i" (ASI_LSU_CONTROL)
343 : "memory");
344 }
345
346 static void spitfire_enable_estate_errors(void)
347 {
348 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
349 "membar #Sync"
350 : /* no outputs */
351 : "r" (ESTATE_ERR_ALL),
352 "i" (ASI_ESTATE_ERROR_EN));
353 }
354
355 static char ecc_syndrome_table[] = {
356 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
357 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
358 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
359 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
360 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
361 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
362 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
363 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
364 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
365 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
366 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
367 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
368 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
369 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
370 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
371 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
372 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
373 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
374 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
375 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
376 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
377 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
378 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
379 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
380 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
381 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
382 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
383 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
384 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
385 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
386 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
387 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
388 };
389
390 static char *syndrome_unknown = "<Unknown>";
391
392 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
393 {
394 unsigned short scode;
395 char memmod_str[64], *p;
396
397 if (udbl & bit) {
398 scode = ecc_syndrome_table[udbl & 0xff];
399 if (prom_getunumber(scode, afar,
400 memmod_str, sizeof(memmod_str)) == -1)
401 p = syndrome_unknown;
402 else
403 p = memmod_str;
404 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
405 "Memory Module \"%s\"\n",
406 smp_processor_id(), scode, p);
407 }
408
409 if (udbh & bit) {
410 scode = ecc_syndrome_table[udbh & 0xff];
411 if (prom_getunumber(scode, afar,
412 memmod_str, sizeof(memmod_str)) == -1)
413 p = syndrome_unknown;
414 else
415 p = memmod_str;
416 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
417 "Memory Module \"%s\"\n",
418 smp_processor_id(), scode, p);
419 }
420
421 }
422
423 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
424 {
425
426 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
427 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
428 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
429
430 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
431
432 /* We always log it, even if someone is listening for this
433 * trap.
434 */
435 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
436 0, TRAP_TYPE_CEE, SIGTRAP);
437
438 /* The Correctable ECC Error trap does not disable I/D caches. So
439 * we only have to restore the ESTATE Error Enable register.
440 */
441 spitfire_enable_estate_errors();
442 }
443
444 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
445 {
446 siginfo_t info;
447
448 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
449 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
450 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
451
452 /* XXX add more human friendly logging of the error status
453 * XXX as is implemented for cheetah
454 */
455
456 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
457
458 /* We always log it, even if someone is listening for this
459 * trap.
460 */
461 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
462 0, tt, SIGTRAP);
463
464 if (regs->tstate & TSTATE_PRIV) {
465 if (tl1)
466 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
467 die_if_kernel("UE", regs);
468 }
469
470 /* XXX need more intelligent processing here, such as is implemented
471 * XXX for cheetah errors, in fact if the E-cache still holds the
472 * XXX line with bad parity this will loop
473 */
474
475 spitfire_clean_and_reenable_l1_caches();
476 spitfire_enable_estate_errors();
477
478 if (test_thread_flag(TIF_32BIT)) {
479 regs->tpc &= 0xffffffff;
480 regs->tnpc &= 0xffffffff;
481 }
482 info.si_signo = SIGBUS;
483 info.si_errno = 0;
484 info.si_code = BUS_OBJERR;
485 info.si_addr = (void *)0;
486 info.si_trapno = 0;
487 force_sig_info(SIGBUS, &info, current);
488 }
489
490 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
491 {
492 unsigned long afsr, tt, udbh, udbl;
493 int tl1;
494
495 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
496 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
497 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
498 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
499 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
500
501 #ifdef CONFIG_PCI
502 if (tt == TRAP_TYPE_DAE &&
503 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
504 spitfire_clean_and_reenable_l1_caches();
505 spitfire_enable_estate_errors();
506
507 pci_poke_faulted = 1;
508 regs->tnpc = regs->tpc + 4;
509 return;
510 }
511 #endif
512
513 if (afsr & SFAFSR_UE)
514 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
515
516 if (tt == TRAP_TYPE_CEE) {
517 /* Handle the case where we took a CEE trap, but ACK'd
518 * only the UE state in the UDB error registers.
519 */
520 if (afsr & SFAFSR_UE) {
521 if (udbh & UDBE_CE) {
522 __asm__ __volatile__(
523 "stxa %0, [%1] %2\n\t"
524 "membar #Sync"
525 : /* no outputs */
526 : "r" (udbh & UDBE_CE),
527 "r" (0x0), "i" (ASI_UDB_ERROR_W));
528 }
529 if (udbl & UDBE_CE) {
530 __asm__ __volatile__(
531 "stxa %0, [%1] %2\n\t"
532 "membar #Sync"
533 : /* no outputs */
534 : "r" (udbl & UDBE_CE),
535 "r" (0x18), "i" (ASI_UDB_ERROR_W));
536 }
537 }
538
539 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
540 }
541 }
542
543 int cheetah_pcache_forced_on;
544
545 void cheetah_enable_pcache(void)
546 {
547 unsigned long dcr;
548
549 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
550 smp_processor_id());
551
552 __asm__ __volatile__("ldxa [%%g0] %1, %0"
553 : "=r" (dcr)
554 : "i" (ASI_DCU_CONTROL_REG));
555 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
556 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
557 "membar #Sync"
558 : /* no outputs */
559 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
560 }
561
562 /* Cheetah error trap handling. */
563 static unsigned long ecache_flush_physbase;
564 static unsigned long ecache_flush_linesize;
565 static unsigned long ecache_flush_size;
566
567 /* WARNING: The error trap handlers in assembly know the precise
568 * layout of the following structure.
569 *
570 * C-level handlers below use this information to log the error
571 * and then determine how to recover (if possible).
572 */
573 struct cheetah_err_info {
574 /*0x00*/u64 afsr;
575 /*0x08*/u64 afar;
576
577 /* D-cache state */
578 /*0x10*/u64 dcache_data[4]; /* The actual data */
579 /*0x30*/u64 dcache_index; /* D-cache index */
580 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
581 /*0x40*/u64 dcache_utag; /* D-cache microtag */
582 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
583
584 /* I-cache state */
585 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
586 /*0x90*/u64 icache_index; /* I-cache index */
587 /*0x98*/u64 icache_tag; /* I-cache phys tag */
588 /*0xa0*/u64 icache_utag; /* I-cache microtag */
589 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
590 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
591 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
592
593 /* E-cache state */
594 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
595 /*0xe0*/u64 ecache_index; /* E-cache index */
596 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
597
598 /*0xf0*/u64 __pad[32 - 30];
599 };
600 #define CHAFSR_INVALID ((u64)-1L)
601
602 /* This table is ordered in priority of errors and matches the
603 * AFAR overwrite policy as well.
604 */
605
606 struct afsr_error_table {
607 unsigned long mask;
608 const char *name;
609 };
610
611 static const char CHAFSR_PERR_msg[] =
612 "System interface protocol error";
613 static const char CHAFSR_IERR_msg[] =
614 "Internal processor error";
615 static const char CHAFSR_ISAP_msg[] =
616 "System request parity error on incoming addresss";
617 static const char CHAFSR_UCU_msg[] =
618 "Uncorrectable E-cache ECC error for ifetch/data";
619 static const char CHAFSR_UCC_msg[] =
620 "SW Correctable E-cache ECC error for ifetch/data";
621 static const char CHAFSR_UE_msg[] =
622 "Uncorrectable system bus data ECC error for read";
623 static const char CHAFSR_EDU_msg[] =
624 "Uncorrectable E-cache ECC error for stmerge/blkld";
625 static const char CHAFSR_EMU_msg[] =
626 "Uncorrectable system bus MTAG error";
627 static const char CHAFSR_WDU_msg[] =
628 "Uncorrectable E-cache ECC error for writeback";
629 static const char CHAFSR_CPU_msg[] =
630 "Uncorrectable ECC error for copyout";
631 static const char CHAFSR_CE_msg[] =
632 "HW corrected system bus data ECC error for read";
633 static const char CHAFSR_EDC_msg[] =
634 "HW corrected E-cache ECC error for stmerge/blkld";
635 static const char CHAFSR_EMC_msg[] =
636 "HW corrected system bus MTAG ECC error";
637 static const char CHAFSR_WDC_msg[] =
638 "HW corrected E-cache ECC error for writeback";
639 static const char CHAFSR_CPC_msg[] =
640 "HW corrected ECC error for copyout";
641 static const char CHAFSR_TO_msg[] =
642 "Unmapped error from system bus";
643 static const char CHAFSR_BERR_msg[] =
644 "Bus error response from system bus";
645 static const char CHAFSR_IVC_msg[] =
646 "HW corrected system bus data ECC error for ivec read";
647 static const char CHAFSR_IVU_msg[] =
648 "Uncorrectable system bus data ECC error for ivec read";
649 static struct afsr_error_table __cheetah_error_table[] = {
650 { CHAFSR_PERR, CHAFSR_PERR_msg },
651 { CHAFSR_IERR, CHAFSR_IERR_msg },
652 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
653 { CHAFSR_UCU, CHAFSR_UCU_msg },
654 { CHAFSR_UCC, CHAFSR_UCC_msg },
655 { CHAFSR_UE, CHAFSR_UE_msg },
656 { CHAFSR_EDU, CHAFSR_EDU_msg },
657 { CHAFSR_EMU, CHAFSR_EMU_msg },
658 { CHAFSR_WDU, CHAFSR_WDU_msg },
659 { CHAFSR_CPU, CHAFSR_CPU_msg },
660 { CHAFSR_CE, CHAFSR_CE_msg },
661 { CHAFSR_EDC, CHAFSR_EDC_msg },
662 { CHAFSR_EMC, CHAFSR_EMC_msg },
663 { CHAFSR_WDC, CHAFSR_WDC_msg },
664 { CHAFSR_CPC, CHAFSR_CPC_msg },
665 { CHAFSR_TO, CHAFSR_TO_msg },
666 { CHAFSR_BERR, CHAFSR_BERR_msg },
667 /* These two do not update the AFAR. */
668 { CHAFSR_IVC, CHAFSR_IVC_msg },
669 { CHAFSR_IVU, CHAFSR_IVU_msg },
670 { 0, NULL },
671 };
672 static const char CHPAFSR_DTO_msg[] =
673 "System bus unmapped error for prefetch/storequeue-read";
674 static const char CHPAFSR_DBERR_msg[] =
675 "System bus error for prefetch/storequeue-read";
676 static const char CHPAFSR_THCE_msg[] =
677 "Hardware corrected E-cache Tag ECC error";
678 static const char CHPAFSR_TSCE_msg[] =
679 "SW handled correctable E-cache Tag ECC error";
680 static const char CHPAFSR_TUE_msg[] =
681 "Uncorrectable E-cache Tag ECC error";
682 static const char CHPAFSR_DUE_msg[] =
683 "System bus uncorrectable data ECC error due to prefetch/store-fill";
684 static struct afsr_error_table __cheetah_plus_error_table[] = {
685 { CHAFSR_PERR, CHAFSR_PERR_msg },
686 { CHAFSR_IERR, CHAFSR_IERR_msg },
687 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
688 { CHAFSR_UCU, CHAFSR_UCU_msg },
689 { CHAFSR_UCC, CHAFSR_UCC_msg },
690 { CHAFSR_UE, CHAFSR_UE_msg },
691 { CHAFSR_EDU, CHAFSR_EDU_msg },
692 { CHAFSR_EMU, CHAFSR_EMU_msg },
693 { CHAFSR_WDU, CHAFSR_WDU_msg },
694 { CHAFSR_CPU, CHAFSR_CPU_msg },
695 { CHAFSR_CE, CHAFSR_CE_msg },
696 { CHAFSR_EDC, CHAFSR_EDC_msg },
697 { CHAFSR_EMC, CHAFSR_EMC_msg },
698 { CHAFSR_WDC, CHAFSR_WDC_msg },
699 { CHAFSR_CPC, CHAFSR_CPC_msg },
700 { CHAFSR_TO, CHAFSR_TO_msg },
701 { CHAFSR_BERR, CHAFSR_BERR_msg },
702 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
703 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
704 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
705 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
706 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
707 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
708 /* These two do not update the AFAR. */
709 { CHAFSR_IVC, CHAFSR_IVC_msg },
710 { CHAFSR_IVU, CHAFSR_IVU_msg },
711 { 0, NULL },
712 };
713 static const char JPAFSR_JETO_msg[] =
714 "System interface protocol error, hw timeout caused";
715 static const char JPAFSR_SCE_msg[] =
716 "Parity error on system snoop results";
717 static const char JPAFSR_JEIC_msg[] =
718 "System interface protocol error, illegal command detected";
719 static const char JPAFSR_JEIT_msg[] =
720 "System interface protocol error, illegal ADTYPE detected";
721 static const char JPAFSR_OM_msg[] =
722 "Out of range memory error has occurred";
723 static const char JPAFSR_ETP_msg[] =
724 "Parity error on L2 cache tag SRAM";
725 static const char JPAFSR_UMS_msg[] =
726 "Error due to unsupported store";
727 static const char JPAFSR_RUE_msg[] =
728 "Uncorrectable ECC error from remote cache/memory";
729 static const char JPAFSR_RCE_msg[] =
730 "Correctable ECC error from remote cache/memory";
731 static const char JPAFSR_BP_msg[] =
732 "JBUS parity error on returned read data";
733 static const char JPAFSR_WBP_msg[] =
734 "JBUS parity error on data for writeback or block store";
735 static const char JPAFSR_FRC_msg[] =
736 "Foreign read to DRAM incurring correctable ECC error";
737 static const char JPAFSR_FRU_msg[] =
738 "Foreign read to DRAM incurring uncorrectable ECC error";
739 static struct afsr_error_table __jalapeno_error_table[] = {
740 { JPAFSR_JETO, JPAFSR_JETO_msg },
741 { JPAFSR_SCE, JPAFSR_SCE_msg },
742 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
743 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
744 { CHAFSR_PERR, CHAFSR_PERR_msg },
745 { CHAFSR_IERR, CHAFSR_IERR_msg },
746 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
747 { CHAFSR_UCU, CHAFSR_UCU_msg },
748 { CHAFSR_UCC, CHAFSR_UCC_msg },
749 { CHAFSR_UE, CHAFSR_UE_msg },
750 { CHAFSR_EDU, CHAFSR_EDU_msg },
751 { JPAFSR_OM, JPAFSR_OM_msg },
752 { CHAFSR_WDU, CHAFSR_WDU_msg },
753 { CHAFSR_CPU, CHAFSR_CPU_msg },
754 { CHAFSR_CE, CHAFSR_CE_msg },
755 { CHAFSR_EDC, CHAFSR_EDC_msg },
756 { JPAFSR_ETP, JPAFSR_ETP_msg },
757 { CHAFSR_WDC, CHAFSR_WDC_msg },
758 { CHAFSR_CPC, CHAFSR_CPC_msg },
759 { CHAFSR_TO, CHAFSR_TO_msg },
760 { CHAFSR_BERR, CHAFSR_BERR_msg },
761 { JPAFSR_UMS, JPAFSR_UMS_msg },
762 { JPAFSR_RUE, JPAFSR_RUE_msg },
763 { JPAFSR_RCE, JPAFSR_RCE_msg },
764 { JPAFSR_BP, JPAFSR_BP_msg },
765 { JPAFSR_WBP, JPAFSR_WBP_msg },
766 { JPAFSR_FRC, JPAFSR_FRC_msg },
767 { JPAFSR_FRU, JPAFSR_FRU_msg },
768 /* These two do not update the AFAR. */
769 { CHAFSR_IVU, CHAFSR_IVU_msg },
770 { 0, NULL },
771 };
772 static struct afsr_error_table *cheetah_error_table;
773 static unsigned long cheetah_afsr_errors;
774
775 /* This is allocated at boot time based upon the largest hardware
776 * cpu ID in the system. We allocate two entries per cpu, one for
777 * TL==0 logging and one for TL >= 1 logging.
778 */
779 struct cheetah_err_info *cheetah_error_log;
780
781 static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
782 {
783 struct cheetah_err_info *p;
784 int cpu = smp_processor_id();
785
786 if (!cheetah_error_log)
787 return NULL;
788
789 p = cheetah_error_log + (cpu * 2);
790 if ((afsr & CHAFSR_TL1) != 0UL)
791 p++;
792
793 return p;
794 }
795
796 extern unsigned int tl0_icpe[], tl1_icpe[];
797 extern unsigned int tl0_dcpe[], tl1_dcpe[];
798 extern unsigned int tl0_fecc[], tl1_fecc[];
799 extern unsigned int tl0_cee[], tl1_cee[];
800 extern unsigned int tl0_iae[], tl1_iae[];
801 extern unsigned int tl0_dae[], tl1_dae[];
802 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
803 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
804 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
805 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
806 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
807
808 void __init cheetah_ecache_flush_init(void)
809 {
810 unsigned long largest_size, smallest_linesize, order, ver;
811 struct device_node *dp;
812 int i, instance, sz;
813
814 /* Scan all cpu device tree nodes, note two values:
815 * 1) largest E-cache size
816 * 2) smallest E-cache line size
817 */
818 largest_size = 0UL;
819 smallest_linesize = ~0UL;
820
821 instance = 0;
822 while (!cpu_find_by_instance(instance, &dp, NULL)) {
823 unsigned long val;
824
825 val = of_getintprop_default(dp, "ecache-size",
826 (2 * 1024 * 1024));
827 if (val > largest_size)
828 largest_size = val;
829 val = of_getintprop_default(dp, "ecache-line-size", 64);
830 if (val < smallest_linesize)
831 smallest_linesize = val;
832 instance++;
833 }
834
835 if (largest_size == 0UL || smallest_linesize == ~0UL) {
836 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
837 "parameters.\n");
838 prom_halt();
839 }
840
841 ecache_flush_size = (2 * largest_size);
842 ecache_flush_linesize = smallest_linesize;
843
844 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
845
846 if (ecache_flush_physbase == ~0UL) {
847 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
848 "contiguous physical memory.\n",
849 ecache_flush_size);
850 prom_halt();
851 }
852
853 /* Now allocate error trap reporting scoreboard. */
854 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
855 for (order = 0; order < MAX_ORDER; order++) {
856 if ((PAGE_SIZE << order) >= sz)
857 break;
858 }
859 cheetah_error_log = (struct cheetah_err_info *)
860 __get_free_pages(GFP_KERNEL, order);
861 if (!cheetah_error_log) {
862 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
863 "error logging scoreboard (%d bytes).\n", sz);
864 prom_halt();
865 }
866 memset(cheetah_error_log, 0, PAGE_SIZE << order);
867
868 /* Mark all AFSRs as invalid so that the trap handler will
869 * log new new information there.
870 */
871 for (i = 0; i < 2 * NR_CPUS; i++)
872 cheetah_error_log[i].afsr = CHAFSR_INVALID;
873
874 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
875 if ((ver >> 32) == __JALAPENO_ID ||
876 (ver >> 32) == __SERRANO_ID) {
877 cheetah_error_table = &__jalapeno_error_table[0];
878 cheetah_afsr_errors = JPAFSR_ERRORS;
879 } else if ((ver >> 32) == 0x003e0015) {
880 cheetah_error_table = &__cheetah_plus_error_table[0];
881 cheetah_afsr_errors = CHPAFSR_ERRORS;
882 } else {
883 cheetah_error_table = &__cheetah_error_table[0];
884 cheetah_afsr_errors = CHAFSR_ERRORS;
885 }
886
887 /* Now patch trap tables. */
888 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
889 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
890 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
891 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
892 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
893 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
894 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
895 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
896 if (tlb_type == cheetah_plus) {
897 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
898 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
899 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
900 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
901 }
902 flushi(PAGE_OFFSET);
903 }
904
905 static void cheetah_flush_ecache(void)
906 {
907 unsigned long flush_base = ecache_flush_physbase;
908 unsigned long flush_linesize = ecache_flush_linesize;
909 unsigned long flush_size = ecache_flush_size;
910
911 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
912 " bne,pt %%xcc, 1b\n\t"
913 " ldxa [%2 + %0] %3, %%g0\n\t"
914 : "=&r" (flush_size)
915 : "0" (flush_size), "r" (flush_base),
916 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
917 }
918
919 static void cheetah_flush_ecache_line(unsigned long physaddr)
920 {
921 unsigned long alias;
922
923 physaddr &= ~(8UL - 1UL);
924 physaddr = (ecache_flush_physbase +
925 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
926 alias = physaddr + (ecache_flush_size >> 1UL);
927 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
928 "ldxa [%1] %2, %%g0\n\t"
929 "membar #Sync"
930 : /* no outputs */
931 : "r" (physaddr), "r" (alias),
932 "i" (ASI_PHYS_USE_EC));
933 }
934
935 /* Unfortunately, the diagnostic access to the I-cache tags we need to
936 * use to clear the thing interferes with I-cache coherency transactions.
937 *
938 * So we must only flush the I-cache when it is disabled.
939 */
940 static void __cheetah_flush_icache(void)
941 {
942 unsigned int icache_size, icache_line_size;
943 unsigned long addr;
944
945 icache_size = local_cpu_data().icache_size;
946 icache_line_size = local_cpu_data().icache_line_size;
947
948 /* Clear the valid bits in all the tags. */
949 for (addr = 0; addr < icache_size; addr += icache_line_size) {
950 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
951 "membar #Sync"
952 : /* no outputs */
953 : "r" (addr | (2 << 3)),
954 "i" (ASI_IC_TAG));
955 }
956 }
957
958 static void cheetah_flush_icache(void)
959 {
960 unsigned long dcu_save;
961
962 /* Save current DCU, disable I-cache. */
963 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
964 "or %0, %2, %%g1\n\t"
965 "stxa %%g1, [%%g0] %1\n\t"
966 "membar #Sync"
967 : "=r" (dcu_save)
968 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
969 : "g1");
970
971 __cheetah_flush_icache();
972
973 /* Restore DCU register */
974 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
975 "membar #Sync"
976 : /* no outputs */
977 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
978 }
979
980 static void cheetah_flush_dcache(void)
981 {
982 unsigned int dcache_size, dcache_line_size;
983 unsigned long addr;
984
985 dcache_size = local_cpu_data().dcache_size;
986 dcache_line_size = local_cpu_data().dcache_line_size;
987
988 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
989 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
990 "membar #Sync"
991 : /* no outputs */
992 : "r" (addr), "i" (ASI_DCACHE_TAG));
993 }
994 }
995
996 /* In order to make the even parity correct we must do two things.
997 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
998 * Next, we clear out all 32-bytes of data for that line. Data of
999 * all-zero + tag parity value of zero == correct parity.
1000 */
1001 static void cheetah_plus_zap_dcache_parity(void)
1002 {
1003 unsigned int dcache_size, dcache_line_size;
1004 unsigned long addr;
1005
1006 dcache_size = local_cpu_data().dcache_size;
1007 dcache_line_size = local_cpu_data().dcache_line_size;
1008
1009 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1010 unsigned long tag = (addr >> 14);
1011 unsigned long line;
1012
1013 __asm__ __volatile__("membar #Sync\n\t"
1014 "stxa %0, [%1] %2\n\t"
1015 "membar #Sync"
1016 : /* no outputs */
1017 : "r" (tag), "r" (addr),
1018 "i" (ASI_DCACHE_UTAG));
1019 for (line = addr; line < addr + dcache_line_size; line += 8)
1020 __asm__ __volatile__("membar #Sync\n\t"
1021 "stxa %%g0, [%0] %1\n\t"
1022 "membar #Sync"
1023 : /* no outputs */
1024 : "r" (line),
1025 "i" (ASI_DCACHE_DATA));
1026 }
1027 }
1028
1029 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1030 * something palatable to the memory controller driver get_unumber
1031 * routine.
1032 */
1033 #define MT0 137
1034 #define MT1 138
1035 #define MT2 139
1036 #define NONE 254
1037 #define MTC0 140
1038 #define MTC1 141
1039 #define MTC2 142
1040 #define MTC3 143
1041 #define C0 128
1042 #define C1 129
1043 #define C2 130
1044 #define C3 131
1045 #define C4 132
1046 #define C5 133
1047 #define C6 134
1048 #define C7 135
1049 #define C8 136
1050 #define M2 144
1051 #define M3 145
1052 #define M4 146
1053 #define M 147
1054 static unsigned char cheetah_ecc_syntab[] = {
1055 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1056 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1057 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1058 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1059 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1060 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1061 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1062 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1063 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1064 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1065 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1066 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1067 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1068 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1069 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1070 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1071 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1072 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1073 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1074 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1075 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1076 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1077 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1078 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1079 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1080 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1081 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1082 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1083 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1084 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1085 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1086 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1087 };
1088 static unsigned char cheetah_mtag_syntab[] = {
1089 NONE, MTC0,
1090 MTC1, NONE,
1091 MTC2, NONE,
1092 NONE, MT0,
1093 MTC3, NONE,
1094 NONE, MT1,
1095 NONE, MT2,
1096 NONE, NONE
1097 };
1098
1099 /* Return the highest priority error conditon mentioned. */
1100 static __inline__ unsigned long cheetah_get_hipri(unsigned long afsr)
1101 {
1102 unsigned long tmp = 0;
1103 int i;
1104
1105 for (i = 0; cheetah_error_table[i].mask; i++) {
1106 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1107 return tmp;
1108 }
1109 return tmp;
1110 }
1111
1112 static const char *cheetah_get_string(unsigned long bit)
1113 {
1114 int i;
1115
1116 for (i = 0; cheetah_error_table[i].mask; i++) {
1117 if ((bit & cheetah_error_table[i].mask) != 0UL)
1118 return cheetah_error_table[i].name;
1119 }
1120 return "???";
1121 }
1122
1123 extern int chmc_getunumber(int, unsigned long, char *, int);
1124
1125 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1126 unsigned long afsr, unsigned long afar, int recoverable)
1127 {
1128 unsigned long hipri;
1129 char unum[256];
1130
1131 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1132 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1133 afsr, afar,
1134 (afsr & CHAFSR_TL1) ? 1 : 0);
1135 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1136 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1137 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1138 printk("%s" "ERROR(%d): ",
1139 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1140 print_symbol("TPC<%s>\n", regs->tpc);
1141 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1142 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1143 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1144 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1145 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1146 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1147 hipri = cheetah_get_hipri(afsr);
1148 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1149 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1150 hipri, cheetah_get_string(hipri));
1151
1152 /* Try to get unumber if relevant. */
1153 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1154 CHAFSR_CPC | CHAFSR_CPU | \
1155 CHAFSR_UE | CHAFSR_CE | \
1156 CHAFSR_EDC | CHAFSR_EDU | \
1157 CHAFSR_UCC | CHAFSR_UCU | \
1158 CHAFSR_WDU | CHAFSR_WDC)
1159 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1160 if (afsr & ESYND_ERRORS) {
1161 int syndrome;
1162 int ret;
1163
1164 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1165 syndrome = cheetah_ecc_syntab[syndrome];
1166 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1167 if (ret != -1)
1168 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1169 (recoverable ? KERN_WARNING : KERN_CRIT),
1170 smp_processor_id(), unum);
1171 } else if (afsr & MSYND_ERRORS) {
1172 int syndrome;
1173 int ret;
1174
1175 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1176 syndrome = cheetah_mtag_syntab[syndrome];
1177 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1178 if (ret != -1)
1179 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1180 (recoverable ? KERN_WARNING : KERN_CRIT),
1181 smp_processor_id(), unum);
1182 }
1183
1184 /* Now dump the cache snapshots. */
1185 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1186 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1187 (int) info->dcache_index,
1188 info->dcache_tag,
1189 info->dcache_utag,
1190 info->dcache_stag);
1191 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1192 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1193 info->dcache_data[0],
1194 info->dcache_data[1],
1195 info->dcache_data[2],
1196 info->dcache_data[3]);
1197 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1198 "u[%016lx] l[%016lx]\n",
1199 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1200 (int) info->icache_index,
1201 info->icache_tag,
1202 info->icache_utag,
1203 info->icache_stag,
1204 info->icache_upper,
1205 info->icache_lower);
1206 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1207 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1208 info->icache_data[0],
1209 info->icache_data[1],
1210 info->icache_data[2],
1211 info->icache_data[3]);
1212 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1213 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1214 info->icache_data[4],
1215 info->icache_data[5],
1216 info->icache_data[6],
1217 info->icache_data[7]);
1218 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1219 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1220 (int) info->ecache_index, info->ecache_tag);
1221 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1222 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1223 info->ecache_data[0],
1224 info->ecache_data[1],
1225 info->ecache_data[2],
1226 info->ecache_data[3]);
1227
1228 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1229 while (afsr != 0UL) {
1230 unsigned long bit = cheetah_get_hipri(afsr);
1231
1232 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1233 (recoverable ? KERN_WARNING : KERN_CRIT),
1234 bit, cheetah_get_string(bit));
1235
1236 afsr &= ~bit;
1237 }
1238
1239 if (!recoverable)
1240 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1241 }
1242
1243 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1244 {
1245 unsigned long afsr, afar;
1246 int ret = 0;
1247
1248 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1249 : "=r" (afsr)
1250 : "i" (ASI_AFSR));
1251 if ((afsr & cheetah_afsr_errors) != 0) {
1252 if (logp != NULL) {
1253 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1254 : "=r" (afar)
1255 : "i" (ASI_AFAR));
1256 logp->afsr = afsr;
1257 logp->afar = afar;
1258 }
1259 ret = 1;
1260 }
1261 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1262 "membar #Sync\n\t"
1263 : : "r" (afsr), "i" (ASI_AFSR));
1264
1265 return ret;
1266 }
1267
1268 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1269 {
1270 struct cheetah_err_info local_snapshot, *p;
1271 int recoverable;
1272
1273 /* Flush E-cache */
1274 cheetah_flush_ecache();
1275
1276 p = cheetah_get_error_log(afsr);
1277 if (!p) {
1278 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1279 afsr, afar);
1280 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1281 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1282 prom_halt();
1283 }
1284
1285 /* Grab snapshot of logged error. */
1286 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1287
1288 /* If the current trap snapshot does not match what the
1289 * trap handler passed along into our args, big trouble.
1290 * In such a case, mark the local copy as invalid.
1291 *
1292 * Else, it matches and we mark the afsr in the non-local
1293 * copy as invalid so we may log new error traps there.
1294 */
1295 if (p->afsr != afsr || p->afar != afar)
1296 local_snapshot.afsr = CHAFSR_INVALID;
1297 else
1298 p->afsr = CHAFSR_INVALID;
1299
1300 cheetah_flush_icache();
1301 cheetah_flush_dcache();
1302
1303 /* Re-enable I-cache/D-cache */
1304 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1305 "or %%g1, %1, %%g1\n\t"
1306 "stxa %%g1, [%%g0] %0\n\t"
1307 "membar #Sync"
1308 : /* no outputs */
1309 : "i" (ASI_DCU_CONTROL_REG),
1310 "i" (DCU_DC | DCU_IC)
1311 : "g1");
1312
1313 /* Re-enable error reporting */
1314 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1315 "or %%g1, %1, %%g1\n\t"
1316 "stxa %%g1, [%%g0] %0\n\t"
1317 "membar #Sync"
1318 : /* no outputs */
1319 : "i" (ASI_ESTATE_ERROR_EN),
1320 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1321 : "g1");
1322
1323 /* Decide if we can continue after handling this trap and
1324 * logging the error.
1325 */
1326 recoverable = 1;
1327 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1328 recoverable = 0;
1329
1330 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1331 * error was logged while we had error reporting traps disabled.
1332 */
1333 if (cheetah_recheck_errors(&local_snapshot)) {
1334 unsigned long new_afsr = local_snapshot.afsr;
1335
1336 /* If we got a new asynchronous error, die... */
1337 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1338 CHAFSR_WDU | CHAFSR_CPU |
1339 CHAFSR_IVU | CHAFSR_UE |
1340 CHAFSR_BERR | CHAFSR_TO))
1341 recoverable = 0;
1342 }
1343
1344 /* Log errors. */
1345 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1346
1347 if (!recoverable)
1348 panic("Irrecoverable Fast-ECC error trap.\n");
1349
1350 /* Flush E-cache to kick the error trap handlers out. */
1351 cheetah_flush_ecache();
1352 }
1353
1354 /* Try to fix a correctable error by pushing the line out from
1355 * the E-cache. Recheck error reporting registers to see if the
1356 * problem is intermittent.
1357 */
1358 static int cheetah_fix_ce(unsigned long physaddr)
1359 {
1360 unsigned long orig_estate;
1361 unsigned long alias1, alias2;
1362 int ret;
1363
1364 /* Make sure correctable error traps are disabled. */
1365 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1366 "andn %0, %1, %%g1\n\t"
1367 "stxa %%g1, [%%g0] %2\n\t"
1368 "membar #Sync"
1369 : "=&r" (orig_estate)
1370 : "i" (ESTATE_ERROR_CEEN),
1371 "i" (ASI_ESTATE_ERROR_EN)
1372 : "g1");
1373
1374 /* We calculate alias addresses that will force the
1375 * cache line in question out of the E-cache. Then
1376 * we bring it back in with an atomic instruction so
1377 * that we get it in some modified/exclusive state,
1378 * then we displace it again to try and get proper ECC
1379 * pushed back into the system.
1380 */
1381 physaddr &= ~(8UL - 1UL);
1382 alias1 = (ecache_flush_physbase +
1383 (physaddr & ((ecache_flush_size >> 1) - 1)));
1384 alias2 = alias1 + (ecache_flush_size >> 1);
1385 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1386 "ldxa [%1] %3, %%g0\n\t"
1387 "casxa [%2] %3, %%g0, %%g0\n\t"
1388 "membar #StoreLoad | #StoreStore\n\t"
1389 "ldxa [%0] %3, %%g0\n\t"
1390 "ldxa [%1] %3, %%g0\n\t"
1391 "membar #Sync"
1392 : /* no outputs */
1393 : "r" (alias1), "r" (alias2),
1394 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1395
1396 /* Did that trigger another error? */
1397 if (cheetah_recheck_errors(NULL)) {
1398 /* Try one more time. */
1399 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1400 "membar #Sync"
1401 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1402 if (cheetah_recheck_errors(NULL))
1403 ret = 2;
1404 else
1405 ret = 1;
1406 } else {
1407 /* No new error, intermittent problem. */
1408 ret = 0;
1409 }
1410
1411 /* Restore error enables. */
1412 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1413 "membar #Sync"
1414 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1415
1416 return ret;
1417 }
1418
1419 /* Return non-zero if PADDR is a valid physical memory address. */
1420 static int cheetah_check_main_memory(unsigned long paddr)
1421 {
1422 unsigned long vaddr = PAGE_OFFSET + paddr;
1423
1424 if (vaddr > (unsigned long) high_memory)
1425 return 0;
1426
1427 return kern_addr_valid(vaddr);
1428 }
1429
1430 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1431 {
1432 struct cheetah_err_info local_snapshot, *p;
1433 int recoverable, is_memory;
1434
1435 p = cheetah_get_error_log(afsr);
1436 if (!p) {
1437 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1438 afsr, afar);
1439 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1440 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1441 prom_halt();
1442 }
1443
1444 /* Grab snapshot of logged error. */
1445 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1446
1447 /* If the current trap snapshot does not match what the
1448 * trap handler passed along into our args, big trouble.
1449 * In such a case, mark the local copy as invalid.
1450 *
1451 * Else, it matches and we mark the afsr in the non-local
1452 * copy as invalid so we may log new error traps there.
1453 */
1454 if (p->afsr != afsr || p->afar != afar)
1455 local_snapshot.afsr = CHAFSR_INVALID;
1456 else
1457 p->afsr = CHAFSR_INVALID;
1458
1459 is_memory = cheetah_check_main_memory(afar);
1460
1461 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1462 /* XXX Might want to log the results of this operation
1463 * XXX somewhere... -DaveM
1464 */
1465 cheetah_fix_ce(afar);
1466 }
1467
1468 {
1469 int flush_all, flush_line;
1470
1471 flush_all = flush_line = 0;
1472 if ((afsr & CHAFSR_EDC) != 0UL) {
1473 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1474 flush_line = 1;
1475 else
1476 flush_all = 1;
1477 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1478 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1479 flush_line = 1;
1480 else
1481 flush_all = 1;
1482 }
1483
1484 /* Trap handler only disabled I-cache, flush it. */
1485 cheetah_flush_icache();
1486
1487 /* Re-enable I-cache */
1488 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1489 "or %%g1, %1, %%g1\n\t"
1490 "stxa %%g1, [%%g0] %0\n\t"
1491 "membar #Sync"
1492 : /* no outputs */
1493 : "i" (ASI_DCU_CONTROL_REG),
1494 "i" (DCU_IC)
1495 : "g1");
1496
1497 if (flush_all)
1498 cheetah_flush_ecache();
1499 else if (flush_line)
1500 cheetah_flush_ecache_line(afar);
1501 }
1502
1503 /* Re-enable error reporting */
1504 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1505 "or %%g1, %1, %%g1\n\t"
1506 "stxa %%g1, [%%g0] %0\n\t"
1507 "membar #Sync"
1508 : /* no outputs */
1509 : "i" (ASI_ESTATE_ERROR_EN),
1510 "i" (ESTATE_ERROR_CEEN)
1511 : "g1");
1512
1513 /* Decide if we can continue after handling this trap and
1514 * logging the error.
1515 */
1516 recoverable = 1;
1517 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1518 recoverable = 0;
1519
1520 /* Re-check AFSR/AFAR */
1521 (void) cheetah_recheck_errors(&local_snapshot);
1522
1523 /* Log errors. */
1524 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1525
1526 if (!recoverable)
1527 panic("Irrecoverable Correctable-ECC error trap.\n");
1528 }
1529
1530 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1531 {
1532 struct cheetah_err_info local_snapshot, *p;
1533 int recoverable, is_memory;
1534
1535 #ifdef CONFIG_PCI
1536 /* Check for the special PCI poke sequence. */
1537 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1538 cheetah_flush_icache();
1539 cheetah_flush_dcache();
1540
1541 /* Re-enable I-cache/D-cache */
1542 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1543 "or %%g1, %1, %%g1\n\t"
1544 "stxa %%g1, [%%g0] %0\n\t"
1545 "membar #Sync"
1546 : /* no outputs */
1547 : "i" (ASI_DCU_CONTROL_REG),
1548 "i" (DCU_DC | DCU_IC)
1549 : "g1");
1550
1551 /* Re-enable error reporting */
1552 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1553 "or %%g1, %1, %%g1\n\t"
1554 "stxa %%g1, [%%g0] %0\n\t"
1555 "membar #Sync"
1556 : /* no outputs */
1557 : "i" (ASI_ESTATE_ERROR_EN),
1558 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1559 : "g1");
1560
1561 (void) cheetah_recheck_errors(NULL);
1562
1563 pci_poke_faulted = 1;
1564 regs->tpc += 4;
1565 regs->tnpc = regs->tpc + 4;
1566 return;
1567 }
1568 #endif
1569
1570 p = cheetah_get_error_log(afsr);
1571 if (!p) {
1572 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1573 afsr, afar);
1574 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1575 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1576 prom_halt();
1577 }
1578
1579 /* Grab snapshot of logged error. */
1580 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1581
1582 /* If the current trap snapshot does not match what the
1583 * trap handler passed along into our args, big trouble.
1584 * In such a case, mark the local copy as invalid.
1585 *
1586 * Else, it matches and we mark the afsr in the non-local
1587 * copy as invalid so we may log new error traps there.
1588 */
1589 if (p->afsr != afsr || p->afar != afar)
1590 local_snapshot.afsr = CHAFSR_INVALID;
1591 else
1592 p->afsr = CHAFSR_INVALID;
1593
1594 is_memory = cheetah_check_main_memory(afar);
1595
1596 {
1597 int flush_all, flush_line;
1598
1599 flush_all = flush_line = 0;
1600 if ((afsr & CHAFSR_EDU) != 0UL) {
1601 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1602 flush_line = 1;
1603 else
1604 flush_all = 1;
1605 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1606 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1607 flush_line = 1;
1608 else
1609 flush_all = 1;
1610 }
1611
1612 cheetah_flush_icache();
1613 cheetah_flush_dcache();
1614
1615 /* Re-enable I/D caches */
1616 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1617 "or %%g1, %1, %%g1\n\t"
1618 "stxa %%g1, [%%g0] %0\n\t"
1619 "membar #Sync"
1620 : /* no outputs */
1621 : "i" (ASI_DCU_CONTROL_REG),
1622 "i" (DCU_IC | DCU_DC)
1623 : "g1");
1624
1625 if (flush_all)
1626 cheetah_flush_ecache();
1627 else if (flush_line)
1628 cheetah_flush_ecache_line(afar);
1629 }
1630
1631 /* Re-enable error reporting */
1632 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1633 "or %%g1, %1, %%g1\n\t"
1634 "stxa %%g1, [%%g0] %0\n\t"
1635 "membar #Sync"
1636 : /* no outputs */
1637 : "i" (ASI_ESTATE_ERROR_EN),
1638 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1639 : "g1");
1640
1641 /* Decide if we can continue after handling this trap and
1642 * logging the error.
1643 */
1644 recoverable = 1;
1645 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1646 recoverable = 0;
1647
1648 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1649 * error was logged while we had error reporting traps disabled.
1650 */
1651 if (cheetah_recheck_errors(&local_snapshot)) {
1652 unsigned long new_afsr = local_snapshot.afsr;
1653
1654 /* If we got a new asynchronous error, die... */
1655 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1656 CHAFSR_WDU | CHAFSR_CPU |
1657 CHAFSR_IVU | CHAFSR_UE |
1658 CHAFSR_BERR | CHAFSR_TO))
1659 recoverable = 0;
1660 }
1661
1662 /* Log errors. */
1663 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1664
1665 /* "Recoverable" here means we try to yank the page from ever
1666 * being newly used again. This depends upon a few things:
1667 * 1) Must be main memory, and AFAR must be valid.
1668 * 2) If we trapped from user, OK.
1669 * 3) Else, if we trapped from kernel we must find exception
1670 * table entry (ie. we have to have been accessing user
1671 * space).
1672 *
1673 * If AFAR is not in main memory, or we trapped from kernel
1674 * and cannot find an exception table entry, it is unacceptable
1675 * to try and continue.
1676 */
1677 if (recoverable && is_memory) {
1678 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1679 /* OK, usermode access. */
1680 recoverable = 1;
1681 } else {
1682 const struct exception_table_entry *entry;
1683
1684 entry = search_exception_tables(regs->tpc);
1685 if (entry) {
1686 /* OK, kernel access to userspace. */
1687 recoverable = 1;
1688
1689 } else {
1690 /* BAD, privileged state is corrupted. */
1691 recoverable = 0;
1692 }
1693
1694 if (recoverable) {
1695 if (pfn_valid(afar >> PAGE_SHIFT))
1696 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1697 else
1698 recoverable = 0;
1699
1700 /* Only perform fixup if we still have a
1701 * recoverable condition.
1702 */
1703 if (recoverable) {
1704 regs->tpc = entry->fixup;
1705 regs->tnpc = regs->tpc + 4;
1706 }
1707 }
1708 }
1709 } else {
1710 recoverable = 0;
1711 }
1712
1713 if (!recoverable)
1714 panic("Irrecoverable deferred error trap.\n");
1715 }
1716
1717 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1718 *
1719 * Bit0: 0=dcache,1=icache
1720 * Bit1: 0=recoverable,1=unrecoverable
1721 *
1722 * The hardware has disabled both the I-cache and D-cache in
1723 * the %dcr register.
1724 */
1725 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1726 {
1727 if (type & 0x1)
1728 __cheetah_flush_icache();
1729 else
1730 cheetah_plus_zap_dcache_parity();
1731 cheetah_flush_dcache();
1732
1733 /* Re-enable I-cache/D-cache */
1734 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1735 "or %%g1, %1, %%g1\n\t"
1736 "stxa %%g1, [%%g0] %0\n\t"
1737 "membar #Sync"
1738 : /* no outputs */
1739 : "i" (ASI_DCU_CONTROL_REG),
1740 "i" (DCU_DC | DCU_IC)
1741 : "g1");
1742
1743 if (type & 0x2) {
1744 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1745 smp_processor_id(),
1746 (type & 0x1) ? 'I' : 'D',
1747 regs->tpc);
1748 print_symbol(KERN_EMERG "TPC<%s>\n", regs->tpc);
1749 panic("Irrecoverable Cheetah+ parity error.");
1750 }
1751
1752 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1753 smp_processor_id(),
1754 (type & 0x1) ? 'I' : 'D',
1755 regs->tpc);
1756 print_symbol(KERN_WARNING "TPC<%s>\n", regs->tpc);
1757 }
1758
1759 struct sun4v_error_entry {
1760 u64 err_handle;
1761 u64 err_stick;
1762
1763 u32 err_type;
1764 #define SUN4V_ERR_TYPE_UNDEFINED 0
1765 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1766 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1767 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1768 #define SUN4V_ERR_TYPE_WARNING_RES 4
1769
1770 u32 err_attrs;
1771 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1772 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1773 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1774 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1775 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1776 #define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1777 #define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1778 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1779
1780 u64 err_raddr;
1781 u32 err_size;
1782 u16 err_cpu;
1783 u16 err_pad;
1784 };
1785
1786 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1787 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1788
1789 static const char *sun4v_err_type_to_str(u32 type)
1790 {
1791 switch (type) {
1792 case SUN4V_ERR_TYPE_UNDEFINED:
1793 return "undefined";
1794 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1795 return "uncorrected resumable";
1796 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1797 return "precise nonresumable";
1798 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1799 return "deferred nonresumable";
1800 case SUN4V_ERR_TYPE_WARNING_RES:
1801 return "warning resumable";
1802 default:
1803 return "unknown";
1804 };
1805 }
1806
1807 extern void __show_regs(struct pt_regs * regs);
1808
1809 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1810 {
1811 int cnt;
1812
1813 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1814 printk("%s: err_handle[%lx] err_stick[%lx] err_type[%08x:%s]\n",
1815 pfx,
1816 ent->err_handle, ent->err_stick,
1817 ent->err_type,
1818 sun4v_err_type_to_str(ent->err_type));
1819 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1820 pfx,
1821 ent->err_attrs,
1822 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1823 "processor" : ""),
1824 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1825 "memory" : ""),
1826 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1827 "pio" : ""),
1828 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1829 "integer-regs" : ""),
1830 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1831 "fpu-regs" : ""),
1832 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1833 "user" : ""),
1834 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1835 "privileged" : ""),
1836 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1837 "queue-full" : ""));
1838 printk("%s: err_raddr[%016lx] err_size[%u] err_cpu[%u]\n",
1839 pfx,
1840 ent->err_raddr, ent->err_size, ent->err_cpu);
1841
1842 __show_regs(regs);
1843
1844 if ((cnt = atomic_read(ocnt)) != 0) {
1845 atomic_set(ocnt, 0);
1846 wmb();
1847 printk("%s: Queue overflowed %d times.\n",
1848 pfx, cnt);
1849 }
1850 }
1851
1852 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1853 * Log the event and clear the first word of the entry.
1854 */
1855 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1856 {
1857 struct sun4v_error_entry *ent, local_copy;
1858 struct trap_per_cpu *tb;
1859 unsigned long paddr;
1860 int cpu;
1861
1862 cpu = get_cpu();
1863
1864 tb = &trap_block[cpu];
1865 paddr = tb->resum_kernel_buf_pa + offset;
1866 ent = __va(paddr);
1867
1868 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1869
1870 /* We have a local copy now, so release the entry. */
1871 ent->err_handle = 0;
1872 wmb();
1873
1874 put_cpu();
1875
1876 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1877 /* If err_type is 0x4, it's a powerdown request. Do
1878 * not do the usual resumable error log because that
1879 * makes it look like some abnormal error.
1880 */
1881 printk(KERN_INFO "Power down request...\n");
1882 kill_cad_pid(SIGINT, 1);
1883 return;
1884 }
1885
1886 sun4v_log_error(regs, &local_copy, cpu,
1887 KERN_ERR "RESUMABLE ERROR",
1888 &sun4v_resum_oflow_cnt);
1889 }
1890
1891 /* If we try to printk() we'll probably make matters worse, by trying
1892 * to retake locks this cpu already holds or causing more errors. So
1893 * just bump a counter, and we'll report these counter bumps above.
1894 */
1895 void sun4v_resum_overflow(struct pt_regs *regs)
1896 {
1897 atomic_inc(&sun4v_resum_oflow_cnt);
1898 }
1899
1900 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1901 * Log the event, clear the first word of the entry, and die.
1902 */
1903 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1904 {
1905 struct sun4v_error_entry *ent, local_copy;
1906 struct trap_per_cpu *tb;
1907 unsigned long paddr;
1908 int cpu;
1909
1910 cpu = get_cpu();
1911
1912 tb = &trap_block[cpu];
1913 paddr = tb->nonresum_kernel_buf_pa + offset;
1914 ent = __va(paddr);
1915
1916 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1917
1918 /* We have a local copy now, so release the entry. */
1919 ent->err_handle = 0;
1920 wmb();
1921
1922 put_cpu();
1923
1924 #ifdef CONFIG_PCI
1925 /* Check for the special PCI poke sequence. */
1926 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1927 pci_poke_faulted = 1;
1928 regs->tpc += 4;
1929 regs->tnpc = regs->tpc + 4;
1930 return;
1931 }
1932 #endif
1933
1934 sun4v_log_error(regs, &local_copy, cpu,
1935 KERN_EMERG "NON-RESUMABLE ERROR",
1936 &sun4v_nonresum_oflow_cnt);
1937
1938 panic("Non-resumable error.");
1939 }
1940
1941 /* If we try to printk() we'll probably make matters worse, by trying
1942 * to retake locks this cpu already holds or causing more errors. So
1943 * just bump a counter, and we'll report these counter bumps above.
1944 */
1945 void sun4v_nonresum_overflow(struct pt_regs *regs)
1946 {
1947 /* XXX Actually even this can make not that much sense. Perhaps
1948 * XXX we should just pull the plug and panic directly from here?
1949 */
1950 atomic_inc(&sun4v_nonresum_oflow_cnt);
1951 }
1952
1953 unsigned long sun4v_err_itlb_vaddr;
1954 unsigned long sun4v_err_itlb_ctx;
1955 unsigned long sun4v_err_itlb_pte;
1956 unsigned long sun4v_err_itlb_error;
1957
1958 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1959 {
1960 if (tl > 1)
1961 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1962
1963 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1964 regs->tpc, tl);
1965 print_symbol(KERN_EMERG "SUN4V-ITLB: TPC<%s>\n", regs->tpc);
1966 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1967 "pte[%lx] error[%lx]\n",
1968 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1969 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1970
1971 prom_halt();
1972 }
1973
1974 unsigned long sun4v_err_dtlb_vaddr;
1975 unsigned long sun4v_err_dtlb_ctx;
1976 unsigned long sun4v_err_dtlb_pte;
1977 unsigned long sun4v_err_dtlb_error;
1978
1979 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1980 {
1981 if (tl > 1)
1982 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1983
1984 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1985 regs->tpc, tl);
1986 print_symbol(KERN_EMERG "SUN4V-DTLB: TPC<%s>\n", regs->tpc);
1987 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1988 "pte[%lx] error[%lx]\n",
1989 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1990 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1991
1992 prom_halt();
1993 }
1994
1995 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
1996 {
1997 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
1998 err, op);
1999 }
2000
2001 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2002 {
2003 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2004 err, op);
2005 }
2006
2007 void do_fpe_common(struct pt_regs *regs)
2008 {
2009 if (regs->tstate & TSTATE_PRIV) {
2010 regs->tpc = regs->tnpc;
2011 regs->tnpc += 4;
2012 } else {
2013 unsigned long fsr = current_thread_info()->xfsr[0];
2014 siginfo_t info;
2015
2016 if (test_thread_flag(TIF_32BIT)) {
2017 regs->tpc &= 0xffffffff;
2018 regs->tnpc &= 0xffffffff;
2019 }
2020 info.si_signo = SIGFPE;
2021 info.si_errno = 0;
2022 info.si_addr = (void __user *)regs->tpc;
2023 info.si_trapno = 0;
2024 info.si_code = __SI_FAULT;
2025 if ((fsr & 0x1c000) == (1 << 14)) {
2026 if (fsr & 0x10)
2027 info.si_code = FPE_FLTINV;
2028 else if (fsr & 0x08)
2029 info.si_code = FPE_FLTOVF;
2030 else if (fsr & 0x04)
2031 info.si_code = FPE_FLTUND;
2032 else if (fsr & 0x02)
2033 info.si_code = FPE_FLTDIV;
2034 else if (fsr & 0x01)
2035 info.si_code = FPE_FLTRES;
2036 }
2037 force_sig_info(SIGFPE, &info, current);
2038 }
2039 }
2040
2041 void do_fpieee(struct pt_regs *regs)
2042 {
2043 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2044 0, 0x24, SIGFPE) == NOTIFY_STOP)
2045 return;
2046
2047 do_fpe_common(regs);
2048 }
2049
2050 extern int do_mathemu(struct pt_regs *, struct fpustate *);
2051
2052 void do_fpother(struct pt_regs *regs)
2053 {
2054 struct fpustate *f = FPUSTATE;
2055 int ret = 0;
2056
2057 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2058 0, 0x25, SIGFPE) == NOTIFY_STOP)
2059 return;
2060
2061 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2062 case (2 << 14): /* unfinished_FPop */
2063 case (3 << 14): /* unimplemented_FPop */
2064 ret = do_mathemu(regs, f);
2065 break;
2066 }
2067 if (ret)
2068 return;
2069 do_fpe_common(regs);
2070 }
2071
2072 void do_tof(struct pt_regs *regs)
2073 {
2074 siginfo_t info;
2075
2076 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2077 0, 0x26, SIGEMT) == NOTIFY_STOP)
2078 return;
2079
2080 if (regs->tstate & TSTATE_PRIV)
2081 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2082 if (test_thread_flag(TIF_32BIT)) {
2083 regs->tpc &= 0xffffffff;
2084 regs->tnpc &= 0xffffffff;
2085 }
2086 info.si_signo = SIGEMT;
2087 info.si_errno = 0;
2088 info.si_code = EMT_TAGOVF;
2089 info.si_addr = (void __user *)regs->tpc;
2090 info.si_trapno = 0;
2091 force_sig_info(SIGEMT, &info, current);
2092 }
2093
2094 void do_div0(struct pt_regs *regs)
2095 {
2096 siginfo_t info;
2097
2098 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2099 0, 0x28, SIGFPE) == NOTIFY_STOP)
2100 return;
2101
2102 if (regs->tstate & TSTATE_PRIV)
2103 die_if_kernel("TL0: Kernel divide by zero.", regs);
2104 if (test_thread_flag(TIF_32BIT)) {
2105 regs->tpc &= 0xffffffff;
2106 regs->tnpc &= 0xffffffff;
2107 }
2108 info.si_signo = SIGFPE;
2109 info.si_errno = 0;
2110 info.si_code = FPE_INTDIV;
2111 info.si_addr = (void __user *)regs->tpc;
2112 info.si_trapno = 0;
2113 force_sig_info(SIGFPE, &info, current);
2114 }
2115
2116 void instruction_dump (unsigned int *pc)
2117 {
2118 int i;
2119
2120 if ((((unsigned long) pc) & 3))
2121 return;
2122
2123 printk("Instruction DUMP:");
2124 for (i = -3; i < 6; i++)
2125 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2126 printk("\n");
2127 }
2128
2129 static void user_instruction_dump (unsigned int __user *pc)
2130 {
2131 int i;
2132 unsigned int buf[9];
2133
2134 if ((((unsigned long) pc) & 3))
2135 return;
2136
2137 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2138 return;
2139
2140 printk("Instruction DUMP:");
2141 for (i = 0; i < 9; i++)
2142 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2143 printk("\n");
2144 }
2145
2146 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2147 {
2148 unsigned long pc, fp, thread_base, ksp;
2149 void *tp = task_stack_page(tsk);
2150 struct reg_window *rw;
2151 int count = 0;
2152
2153 ksp = (unsigned long) _ksp;
2154
2155 if (tp == current_thread_info())
2156 flushw_all();
2157
2158 fp = ksp + STACK_BIAS;
2159 thread_base = (unsigned long) tp;
2160
2161 printk("Call Trace:");
2162 #ifdef CONFIG_KALLSYMS
2163 printk("\n");
2164 #endif
2165 do {
2166 /* Bogus frame pointer? */
2167 if (fp < (thread_base + sizeof(struct thread_info)) ||
2168 fp >= (thread_base + THREAD_SIZE))
2169 break;
2170 rw = (struct reg_window *)fp;
2171 pc = rw->ins[7];
2172 printk(" [%016lx] ", pc);
2173 print_symbol("%s\n", pc);
2174 fp = rw->ins[6] + STACK_BIAS;
2175 } while (++count < 16);
2176 #ifndef CONFIG_KALLSYMS
2177 printk("\n");
2178 #endif
2179 }
2180
2181 void dump_stack(void)
2182 {
2183 unsigned long *ksp;
2184
2185 __asm__ __volatile__("mov %%fp, %0"
2186 : "=r" (ksp));
2187 show_stack(current, ksp);
2188 }
2189
2190 EXPORT_SYMBOL(dump_stack);
2191
2192 static inline int is_kernel_stack(struct task_struct *task,
2193 struct reg_window *rw)
2194 {
2195 unsigned long rw_addr = (unsigned long) rw;
2196 unsigned long thread_base, thread_end;
2197
2198 if (rw_addr < PAGE_OFFSET) {
2199 if (task != &init_task)
2200 return 0;
2201 }
2202
2203 thread_base = (unsigned long) task_stack_page(task);
2204 thread_end = thread_base + sizeof(union thread_union);
2205 if (rw_addr >= thread_base &&
2206 rw_addr < thread_end &&
2207 !(rw_addr & 0x7UL))
2208 return 1;
2209
2210 return 0;
2211 }
2212
2213 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2214 {
2215 unsigned long fp = rw->ins[6];
2216
2217 if (!fp)
2218 return NULL;
2219
2220 return (struct reg_window *) (fp + STACK_BIAS);
2221 }
2222
2223 void die_if_kernel(char *str, struct pt_regs *regs)
2224 {
2225 static int die_counter;
2226 extern void smp_report_regs(void);
2227 int count = 0;
2228
2229 /* Amuse the user. */
2230 printk(
2231 " \\|/ ____ \\|/\n"
2232 " \"@'/ .. \\`@\"\n"
2233 " /_| \\__/ |_\\\n"
2234 " \\__U_/\n");
2235
2236 printk("%s(%d): %s [#%d]\n", current->comm, current->pid, str, ++die_counter);
2237 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2238 __asm__ __volatile__("flushw");
2239 __show_regs(regs);
2240 if (regs->tstate & TSTATE_PRIV) {
2241 struct reg_window *rw = (struct reg_window *)
2242 (regs->u_regs[UREG_FP] + STACK_BIAS);
2243
2244 /* Stop the back trace when we hit userland or we
2245 * find some badly aligned kernel stack.
2246 */
2247 while (rw &&
2248 count++ < 30&&
2249 is_kernel_stack(current, rw)) {
2250 printk("Caller[%016lx]", rw->ins[7]);
2251 print_symbol(": %s", rw->ins[7]);
2252 printk("\n");
2253
2254 rw = kernel_stack_up(rw);
2255 }
2256 instruction_dump ((unsigned int *) regs->tpc);
2257 } else {
2258 if (test_thread_flag(TIF_32BIT)) {
2259 regs->tpc &= 0xffffffff;
2260 regs->tnpc &= 0xffffffff;
2261 }
2262 user_instruction_dump ((unsigned int __user *) regs->tpc);
2263 }
2264 #if 0
2265 #ifdef CONFIG_SMP
2266 smp_report_regs();
2267 #endif
2268 #endif
2269 if (regs->tstate & TSTATE_PRIV)
2270 do_exit(SIGKILL);
2271 do_exit(SIGSEGV);
2272 }
2273
2274 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2275 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2276
2277 extern int handle_popc(u32 insn, struct pt_regs *regs);
2278 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2279 extern int vis_emul(struct pt_regs *, unsigned int);
2280
2281 void do_illegal_instruction(struct pt_regs *regs)
2282 {
2283 unsigned long pc = regs->tpc;
2284 unsigned long tstate = regs->tstate;
2285 u32 insn;
2286 siginfo_t info;
2287
2288 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2289 0, 0x10, SIGILL) == NOTIFY_STOP)
2290 return;
2291
2292 if (tstate & TSTATE_PRIV)
2293 die_if_kernel("Kernel illegal instruction", regs);
2294 if (test_thread_flag(TIF_32BIT))
2295 pc = (u32)pc;
2296 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2297 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2298 if (handle_popc(insn, regs))
2299 return;
2300 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2301 if (handle_ldf_stq(insn, regs))
2302 return;
2303 } else if (tlb_type == hypervisor) {
2304 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2305 if (!vis_emul(regs, insn))
2306 return;
2307 } else {
2308 struct fpustate *f = FPUSTATE;
2309
2310 /* XXX maybe verify XFSR bits like
2311 * XXX do_fpother() does?
2312 */
2313 if (do_mathemu(regs, f))
2314 return;
2315 }
2316 }
2317 }
2318 info.si_signo = SIGILL;
2319 info.si_errno = 0;
2320 info.si_code = ILL_ILLOPC;
2321 info.si_addr = (void __user *)pc;
2322 info.si_trapno = 0;
2323 force_sig_info(SIGILL, &info, current);
2324 }
2325
2326 extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2327
2328 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2329 {
2330 siginfo_t info;
2331
2332 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2333 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2334 return;
2335
2336 if (regs->tstate & TSTATE_PRIV) {
2337 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2338 return;
2339 }
2340 info.si_signo = SIGBUS;
2341 info.si_errno = 0;
2342 info.si_code = BUS_ADRALN;
2343 info.si_addr = (void __user *)sfar;
2344 info.si_trapno = 0;
2345 force_sig_info(SIGBUS, &info, current);
2346 }
2347
2348 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2349 {
2350 siginfo_t info;
2351
2352 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2353 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2354 return;
2355
2356 if (regs->tstate & TSTATE_PRIV) {
2357 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2358 return;
2359 }
2360 info.si_signo = SIGBUS;
2361 info.si_errno = 0;
2362 info.si_code = BUS_ADRALN;
2363 info.si_addr = (void __user *) addr;
2364 info.si_trapno = 0;
2365 force_sig_info(SIGBUS, &info, current);
2366 }
2367
2368 void do_privop(struct pt_regs *regs)
2369 {
2370 siginfo_t info;
2371
2372 if (notify_die(DIE_TRAP, "privileged operation", regs,
2373 0, 0x11, SIGILL) == NOTIFY_STOP)
2374 return;
2375
2376 if (test_thread_flag(TIF_32BIT)) {
2377 regs->tpc &= 0xffffffff;
2378 regs->tnpc &= 0xffffffff;
2379 }
2380 info.si_signo = SIGILL;
2381 info.si_errno = 0;
2382 info.si_code = ILL_PRVOPC;
2383 info.si_addr = (void __user *)regs->tpc;
2384 info.si_trapno = 0;
2385 force_sig_info(SIGILL, &info, current);
2386 }
2387
2388 void do_privact(struct pt_regs *regs)
2389 {
2390 do_privop(regs);
2391 }
2392
2393 /* Trap level 1 stuff or other traps we should never see... */
2394 void do_cee(struct pt_regs *regs)
2395 {
2396 die_if_kernel("TL0: Cache Error Exception", regs);
2397 }
2398
2399 void do_cee_tl1(struct pt_regs *regs)
2400 {
2401 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2402 die_if_kernel("TL1: Cache Error Exception", regs);
2403 }
2404
2405 void do_dae_tl1(struct pt_regs *regs)
2406 {
2407 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2408 die_if_kernel("TL1: Data Access Exception", regs);
2409 }
2410
2411 void do_iae_tl1(struct pt_regs *regs)
2412 {
2413 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2414 die_if_kernel("TL1: Instruction Access Exception", regs);
2415 }
2416
2417 void do_div0_tl1(struct pt_regs *regs)
2418 {
2419 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2420 die_if_kernel("TL1: DIV0 Exception", regs);
2421 }
2422
2423 void do_fpdis_tl1(struct pt_regs *regs)
2424 {
2425 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2426 die_if_kernel("TL1: FPU Disabled", regs);
2427 }
2428
2429 void do_fpieee_tl1(struct pt_regs *regs)
2430 {
2431 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2432 die_if_kernel("TL1: FPU IEEE Exception", regs);
2433 }
2434
2435 void do_fpother_tl1(struct pt_regs *regs)
2436 {
2437 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2438 die_if_kernel("TL1: FPU Other Exception", regs);
2439 }
2440
2441 void do_ill_tl1(struct pt_regs *regs)
2442 {
2443 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2444 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2445 }
2446
2447 void do_irq_tl1(struct pt_regs *regs)
2448 {
2449 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2450 die_if_kernel("TL1: IRQ Exception", regs);
2451 }
2452
2453 void do_lddfmna_tl1(struct pt_regs *regs)
2454 {
2455 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2456 die_if_kernel("TL1: LDDF Exception", regs);
2457 }
2458
2459 void do_stdfmna_tl1(struct pt_regs *regs)
2460 {
2461 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2462 die_if_kernel("TL1: STDF Exception", regs);
2463 }
2464
2465 void do_paw(struct pt_regs *regs)
2466 {
2467 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2468 }
2469
2470 void do_paw_tl1(struct pt_regs *regs)
2471 {
2472 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2473 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2474 }
2475
2476 void do_vaw(struct pt_regs *regs)
2477 {
2478 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2479 }
2480
2481 void do_vaw_tl1(struct pt_regs *regs)
2482 {
2483 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2484 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2485 }
2486
2487 void do_tof_tl1(struct pt_regs *regs)
2488 {
2489 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2490 die_if_kernel("TL1: Tag Overflow Exception", regs);
2491 }
2492
2493 void do_getpsr(struct pt_regs *regs)
2494 {
2495 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2496 regs->tpc = regs->tnpc;
2497 regs->tnpc += 4;
2498 if (test_thread_flag(TIF_32BIT)) {
2499 regs->tpc &= 0xffffffff;
2500 regs->tnpc &= 0xffffffff;
2501 }
2502 }
2503
2504 struct trap_per_cpu trap_block[NR_CPUS];
2505
2506 /* This can get invoked before sched_init() so play it super safe
2507 * and use hard_smp_processor_id().
2508 */
2509 void init_cur_cpu_trap(struct thread_info *t)
2510 {
2511 int cpu = hard_smp_processor_id();
2512 struct trap_per_cpu *p = &trap_block[cpu];
2513
2514 p->thread = t;
2515 p->pgd_paddr = 0;
2516 }
2517
2518 extern void thread_info_offsets_are_bolixed_dave(void);
2519 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2520 extern void tsb_config_offsets_are_bolixed_dave(void);
2521
2522 /* Only invoked on boot processor. */
2523 void __init trap_init(void)
2524 {
2525 /* Compile time sanity check. */
2526 if (TI_TASK != offsetof(struct thread_info, task) ||
2527 TI_FLAGS != offsetof(struct thread_info, flags) ||
2528 TI_CPU != offsetof(struct thread_info, cpu) ||
2529 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2530 TI_KSP != offsetof(struct thread_info, ksp) ||
2531 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2532 TI_KREGS != offsetof(struct thread_info, kregs) ||
2533 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2534 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2535 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2536 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2537 TI_GSR != offsetof(struct thread_info, gsr) ||
2538 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2539 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2540 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2541 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2542 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2543 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2544 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2545 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2546 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2547 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2548 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2549 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
2550 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2551 (TI_FPREGS & (64 - 1)))
2552 thread_info_offsets_are_bolixed_dave();
2553
2554 if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
2555 (TRAP_PER_CPU_PGD_PADDR !=
2556 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2557 (TRAP_PER_CPU_CPU_MONDO_PA !=
2558 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2559 (TRAP_PER_CPU_DEV_MONDO_PA !=
2560 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2561 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2562 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2563 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2564 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2565 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2566 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2567 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2568 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2569 (TRAP_PER_CPU_FAULT_INFO !=
2570 offsetof(struct trap_per_cpu, fault_info)) ||
2571 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2572 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2573 (TRAP_PER_CPU_CPU_LIST_PA !=
2574 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2575 (TRAP_PER_CPU_TSB_HUGE !=
2576 offsetof(struct trap_per_cpu, tsb_huge)) ||
2577 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2578 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2579 (TRAP_PER_CPU_IRQ_WORKLIST !=
2580 offsetof(struct trap_per_cpu, irq_worklist)))
2581 trap_per_cpu_offsets_are_bolixed_dave();
2582
2583 if ((TSB_CONFIG_TSB !=
2584 offsetof(struct tsb_config, tsb)) ||
2585 (TSB_CONFIG_RSS_LIMIT !=
2586 offsetof(struct tsb_config, tsb_rss_limit)) ||
2587 (TSB_CONFIG_NENTRIES !=
2588 offsetof(struct tsb_config, tsb_nentries)) ||
2589 (TSB_CONFIG_REG_VAL !=
2590 offsetof(struct tsb_config, tsb_reg_val)) ||
2591 (TSB_CONFIG_MAP_VADDR !=
2592 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2593 (TSB_CONFIG_MAP_PTE !=
2594 offsetof(struct tsb_config, tsb_map_pte)))
2595 tsb_config_offsets_are_bolixed_dave();
2596
2597 /* Attach to the address space of init_task. On SMP we
2598 * do this in smp.c:smp_callin for other cpus.
2599 */
2600 atomic_inc(&init_mm.mm_count);
2601 current->active_mm = &init_mm;
2602 }
Stable & featurefull patchset based on Linus's git branch