2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.1"
46 #define PFX DRV_NAME " "
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION
);
65 static const u32 default_msg
66 = NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
69 static int debug
= -1; /* defaults above */
70 module_param(debug
, int, 0);
71 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
73 static const struct pci_device_id skge_id_table
[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940
) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM
, PCI_DEVICE_ID_3COM_3C940B
) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_GE
) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_YU
) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, PCI_DEVICE_ID_DLINK_DGE510T
), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET
, PCI_DEVICE_ID_CNET_GIGACARD
) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS
, PCI_DEVICE_ID_LINKSYS_EG1064
) },
83 { PCI_VENDOR_ID_LINKSYS
, 0x1032, PCI_ANY_ID
, 0x0015, },
86 MODULE_DEVICE_TABLE(pci
, skge_id_table
);
88 static int skge_up(struct net_device
*dev
);
89 static int skge_down(struct net_device
*dev
);
90 static void skge_tx_clean(struct skge_port
*skge
);
91 static void xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
92 static void gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
);
93 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
);
94 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
);
95 static void yukon_init(struct skge_hw
*hw
, int port
);
96 static void yukon_reset(struct skge_hw
*hw
, int port
);
97 static void genesis_mac_init(struct skge_hw
*hw
, int port
);
98 static void genesis_reset(struct skge_hw
*hw
, int port
);
99 static void genesis_link_up(struct skge_port
*skge
);
101 /* Avoid conditionals by using array */
102 static const int txqaddr
[] = { Q_XA1
, Q_XA2
};
103 static const int rxqaddr
[] = { Q_R1
, Q_R2
};
104 static const u32 rxirqmask
[] = { IS_R1_F
, IS_R2_F
};
105 static const u32 txirqmask
[] = { IS_XA1_F
, IS_XA2_F
};
106 static const u32 portirqmask
[] = { IS_PORT_1
, IS_PORT_2
};
108 static int skge_get_regs_len(struct net_device
*dev
)
114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
118 static void skge_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
121 const struct skge_port
*skge
= netdev_priv(dev
);
122 const void __iomem
*io
= skge
->hw
->regs
;
125 memset(p
, 0, regs
->len
);
126 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
128 memcpy_fromio(p
+ B3_RI_WTO_R1
, io
+ B3_RI_WTO_R1
,
129 regs
->len
- B3_RI_WTO_R1
);
132 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
133 static int wol_supported(const struct skge_hw
*hw
)
135 return !((hw
->chip_id
== CHIP_ID_GENESIS
||
136 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)));
139 static void skge_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
141 struct skge_port
*skge
= netdev_priv(dev
);
143 wol
->supported
= wol_supported(skge
->hw
) ? WAKE_MAGIC
: 0;
144 wol
->wolopts
= skge
->wol
? WAKE_MAGIC
: 0;
147 static int skge_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
149 struct skge_port
*skge
= netdev_priv(dev
);
150 struct skge_hw
*hw
= skge
->hw
;
152 if (wol
->wolopts
!= WAKE_MAGIC
&& wol
->wolopts
!= 0)
155 if (wol
->wolopts
== WAKE_MAGIC
&& !wol_supported(hw
))
158 skge
->wol
= wol
->wolopts
== WAKE_MAGIC
;
161 memcpy_toio(hw
->regs
+ WOL_MAC_ADDR
, dev
->dev_addr
, ETH_ALEN
);
163 skge_write16(hw
, WOL_CTRL_STAT
,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT
|
165 WOL_CTL_ENA_MAGIC_PKT_UNIT
);
167 skge_write16(hw
, WOL_CTRL_STAT
, WOL_CTL_DEFAULT
);
172 /* Determine supported/adverised modes based on hardware.
173 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
175 static u32
skge_supported_modes(const struct skge_hw
*hw
)
180 supported
= SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
188 if (hw
->chip_id
== CHIP_ID_GENESIS
)
189 supported
&= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full
);
194 else if (hw
->chip_id
== CHIP_ID_YUKON
)
195 supported
&= ~SUPPORTED_1000baseT_Half
;
197 supported
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
203 static int skge_get_settings(struct net_device
*dev
,
204 struct ethtool_cmd
*ecmd
)
206 struct skge_port
*skge
= netdev_priv(dev
);
207 struct skge_hw
*hw
= skge
->hw
;
209 ecmd
->transceiver
= XCVR_INTERNAL
;
210 ecmd
->supported
= skge_supported_modes(hw
);
213 ecmd
->port
= PORT_TP
;
214 ecmd
->phy_address
= hw
->phy_addr
;
216 ecmd
->port
= PORT_FIBRE
;
218 ecmd
->advertising
= skge
->advertising
;
219 ecmd
->autoneg
= skge
->autoneg
;
220 ecmd
->speed
= skge
->speed
;
221 ecmd
->duplex
= skge
->duplex
;
225 static int skge_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
227 struct skge_port
*skge
= netdev_priv(dev
);
228 const struct skge_hw
*hw
= skge
->hw
;
229 u32 supported
= skge_supported_modes(hw
);
231 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
232 ecmd
->advertising
= supported
;
238 switch (ecmd
->speed
) {
240 if (ecmd
->duplex
== DUPLEX_FULL
)
241 setting
= SUPPORTED_1000baseT_Full
;
242 else if (ecmd
->duplex
== DUPLEX_HALF
)
243 setting
= SUPPORTED_1000baseT_Half
;
248 if (ecmd
->duplex
== DUPLEX_FULL
)
249 setting
= SUPPORTED_100baseT_Full
;
250 else if (ecmd
->duplex
== DUPLEX_HALF
)
251 setting
= SUPPORTED_100baseT_Half
;
257 if (ecmd
->duplex
== DUPLEX_FULL
)
258 setting
= SUPPORTED_10baseT_Full
;
259 else if (ecmd
->duplex
== DUPLEX_HALF
)
260 setting
= SUPPORTED_10baseT_Half
;
268 if ((setting
& supported
) == 0)
271 skge
->speed
= ecmd
->speed
;
272 skge
->duplex
= ecmd
->duplex
;
275 skge
->autoneg
= ecmd
->autoneg
;
276 skge
->advertising
= ecmd
->advertising
;
278 if (netif_running(dev
)) {
285 static void skge_get_drvinfo(struct net_device
*dev
,
286 struct ethtool_drvinfo
*info
)
288 struct skge_port
*skge
= netdev_priv(dev
);
290 strcpy(info
->driver
, DRV_NAME
);
291 strcpy(info
->version
, DRV_VERSION
);
292 strcpy(info
->fw_version
, "N/A");
293 strcpy(info
->bus_info
, pci_name(skge
->hw
->pdev
));
296 static const struct skge_stat
{
297 char name
[ETH_GSTRING_LEN
];
301 { "tx_bytes", XM_TXO_OK_HI
, GM_TXO_OK_HI
},
302 { "rx_bytes", XM_RXO_OK_HI
, GM_RXO_OK_HI
},
304 { "tx_broadcast", XM_TXF_BC_OK
, GM_TXF_BC_OK
},
305 { "rx_broadcast", XM_RXF_BC_OK
, GM_RXF_BC_OK
},
306 { "tx_multicast", XM_TXF_MC_OK
, GM_TXF_MC_OK
},
307 { "rx_multicast", XM_RXF_MC_OK
, GM_RXF_MC_OK
},
308 { "tx_unicast", XM_TXF_UC_OK
, GM_TXF_UC_OK
},
309 { "rx_unicast", XM_RXF_UC_OK
, GM_RXF_UC_OK
},
310 { "tx_mac_pause", XM_TXF_MPAUSE
, GM_TXF_MPAUSE
},
311 { "rx_mac_pause", XM_RXF_MPAUSE
, GM_RXF_MPAUSE
},
313 { "collisions", XM_TXF_SNG_COL
, GM_TXF_SNG_COL
},
314 { "multi_collisions", XM_TXF_MUL_COL
, GM_TXF_MUL_COL
},
315 { "aborted", XM_TXF_ABO_COL
, GM_TXF_ABO_COL
},
316 { "late_collision", XM_TXF_LAT_COL
, GM_TXF_LAT_COL
},
317 { "fifo_underrun", XM_TXE_FIFO_UR
, GM_TXE_FIFO_UR
},
318 { "fifo_overflow", XM_RXE_FIFO_OV
, GM_RXE_FIFO_OV
},
320 { "rx_toolong", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
321 { "rx_jabber", XM_RXF_JAB_PKT
, GM_RXF_JAB_PKT
},
322 { "rx_runt", XM_RXE_RUNT
, GM_RXE_FRAG
},
323 { "rx_too_long", XM_RXF_LNG_ERR
, GM_RXF_LNG_ERR
},
324 { "rx_fcs_error", XM_RXF_FCS_ERR
, GM_RXF_FCS_ERR
},
327 static int skge_get_stats_count(struct net_device
*dev
)
329 return ARRAY_SIZE(skge_stats
);
332 static void skge_get_ethtool_stats(struct net_device
*dev
,
333 struct ethtool_stats
*stats
, u64
*data
)
335 struct skge_port
*skge
= netdev_priv(dev
);
337 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
338 genesis_get_stats(skge
, data
);
340 yukon_get_stats(skge
, data
);
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
347 static struct net_device_stats
*skge_get_stats(struct net_device
*dev
)
349 struct skge_port
*skge
= netdev_priv(dev
);
350 u64 data
[ARRAY_SIZE(skge_stats
)];
352 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
)
353 genesis_get_stats(skge
, data
);
355 yukon_get_stats(skge
, data
);
357 skge
->net_stats
.tx_bytes
= data
[0];
358 skge
->net_stats
.rx_bytes
= data
[1];
359 skge
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
360 skge
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
361 skge
->net_stats
.multicast
= data
[5] + data
[7];
362 skge
->net_stats
.collisions
= data
[10];
363 skge
->net_stats
.tx_aborted_errors
= data
[12];
365 return &skge
->net_stats
;
368 static void skge_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
374 for (i
= 0; i
< ARRAY_SIZE(skge_stats
); i
++)
375 memcpy(data
+ i
* ETH_GSTRING_LEN
,
376 skge_stats
[i
].name
, ETH_GSTRING_LEN
);
381 static void skge_get_ring_param(struct net_device
*dev
,
382 struct ethtool_ringparam
*p
)
384 struct skge_port
*skge
= netdev_priv(dev
);
386 p
->rx_max_pending
= MAX_RX_RING_SIZE
;
387 p
->tx_max_pending
= MAX_TX_RING_SIZE
;
388 p
->rx_mini_max_pending
= 0;
389 p
->rx_jumbo_max_pending
= 0;
391 p
->rx_pending
= skge
->rx_ring
.count
;
392 p
->tx_pending
= skge
->tx_ring
.count
;
393 p
->rx_mini_pending
= 0;
394 p
->rx_jumbo_pending
= 0;
397 static int skge_set_ring_param(struct net_device
*dev
,
398 struct ethtool_ringparam
*p
)
400 struct skge_port
*skge
= netdev_priv(dev
);
402 if (p
->rx_pending
== 0 || p
->rx_pending
> MAX_RX_RING_SIZE
||
403 p
->tx_pending
== 0 || p
->tx_pending
> MAX_TX_RING_SIZE
)
406 skge
->rx_ring
.count
= p
->rx_pending
;
407 skge
->tx_ring
.count
= p
->tx_pending
;
409 if (netif_running(dev
)) {
417 static u32
skge_get_msglevel(struct net_device
*netdev
)
419 struct skge_port
*skge
= netdev_priv(netdev
);
420 return skge
->msg_enable
;
423 static void skge_set_msglevel(struct net_device
*netdev
, u32 value
)
425 struct skge_port
*skge
= netdev_priv(netdev
);
426 skge
->msg_enable
= value
;
429 static int skge_nway_reset(struct net_device
*dev
)
431 struct skge_port
*skge
= netdev_priv(dev
);
432 struct skge_hw
*hw
= skge
->hw
;
433 int port
= skge
->port
;
435 if (skge
->autoneg
!= AUTONEG_ENABLE
|| !netif_running(dev
))
438 spin_lock_bh(&hw
->phy_lock
);
439 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
440 genesis_reset(hw
, port
);
441 genesis_mac_init(hw
, port
);
443 yukon_reset(hw
, port
);
444 yukon_init(hw
, port
);
446 spin_unlock_bh(&hw
->phy_lock
);
450 static int skge_set_sg(struct net_device
*dev
, u32 data
)
452 struct skge_port
*skge
= netdev_priv(dev
);
453 struct skge_hw
*hw
= skge
->hw
;
455 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
457 return ethtool_op_set_sg(dev
, data
);
460 static int skge_set_tx_csum(struct net_device
*dev
, u32 data
)
462 struct skge_port
*skge
= netdev_priv(dev
);
463 struct skge_hw
*hw
= skge
->hw
;
465 if (hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
468 return ethtool_op_set_tx_csum(dev
, data
);
471 static u32
skge_get_rx_csum(struct net_device
*dev
)
473 struct skge_port
*skge
= netdev_priv(dev
);
475 return skge
->rx_csum
;
478 /* Only Yukon supports checksum offload. */
479 static int skge_set_rx_csum(struct net_device
*dev
, u32 data
)
481 struct skge_port
*skge
= netdev_priv(dev
);
483 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
&& data
)
486 skge
->rx_csum
= data
;
490 static void skge_get_pauseparam(struct net_device
*dev
,
491 struct ethtool_pauseparam
*ecmd
)
493 struct skge_port
*skge
= netdev_priv(dev
);
495 ecmd
->tx_pause
= (skge
->flow_control
== FLOW_MODE_LOC_SEND
)
496 || (skge
->flow_control
== FLOW_MODE_SYMMETRIC
);
497 ecmd
->rx_pause
= (skge
->flow_control
== FLOW_MODE_REM_SEND
)
498 || (skge
->flow_control
== FLOW_MODE_SYMMETRIC
);
500 ecmd
->autoneg
= skge
->autoneg
;
503 static int skge_set_pauseparam(struct net_device
*dev
,
504 struct ethtool_pauseparam
*ecmd
)
506 struct skge_port
*skge
= netdev_priv(dev
);
508 skge
->autoneg
= ecmd
->autoneg
;
509 if (ecmd
->rx_pause
&& ecmd
->tx_pause
)
510 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
511 else if (ecmd
->rx_pause
&& !ecmd
->tx_pause
)
512 skge
->flow_control
= FLOW_MODE_REM_SEND
;
513 else if (!ecmd
->rx_pause
&& ecmd
->tx_pause
)
514 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
516 skge
->flow_control
= FLOW_MODE_NONE
;
518 if (netif_running(dev
)) {
525 /* Chip internal frequency for clock calculations */
526 static inline u32
hwkhz(const struct skge_hw
*hw
)
528 if (hw
->chip_id
== CHIP_ID_GENESIS
)
529 return 53215; /* or: 53.125 MHz */
531 return 78215; /* or: 78.125 MHz */
534 /* Chip hz to microseconds */
535 static inline u32
skge_clk2usec(const struct skge_hw
*hw
, u32 ticks
)
537 return (ticks
* 1000) / hwkhz(hw
);
540 /* Microseconds to chip hz */
541 static inline u32
skge_usecs2clk(const struct skge_hw
*hw
, u32 usec
)
543 return hwkhz(hw
) * usec
/ 1000;
546 static int skge_get_coalesce(struct net_device
*dev
,
547 struct ethtool_coalesce
*ecmd
)
549 struct skge_port
*skge
= netdev_priv(dev
);
550 struct skge_hw
*hw
= skge
->hw
;
551 int port
= skge
->port
;
553 ecmd
->rx_coalesce_usecs
= 0;
554 ecmd
->tx_coalesce_usecs
= 0;
556 if (skge_read32(hw
, B2_IRQM_CTRL
) & TIM_START
) {
557 u32 delay
= skge_clk2usec(hw
, skge_read32(hw
, B2_IRQM_INI
));
558 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
560 if (msk
& rxirqmask
[port
])
561 ecmd
->rx_coalesce_usecs
= delay
;
562 if (msk
& txirqmask
[port
])
563 ecmd
->tx_coalesce_usecs
= delay
;
569 /* Note: interrupt timer is per board, but can turn on/off per port */
570 static int skge_set_coalesce(struct net_device
*dev
,
571 struct ethtool_coalesce
*ecmd
)
573 struct skge_port
*skge
= netdev_priv(dev
);
574 struct skge_hw
*hw
= skge
->hw
;
575 int port
= skge
->port
;
576 u32 msk
= skge_read32(hw
, B2_IRQM_MSK
);
579 if (ecmd
->rx_coalesce_usecs
== 0)
580 msk
&= ~rxirqmask
[port
];
581 else if (ecmd
->rx_coalesce_usecs
< 25 ||
582 ecmd
->rx_coalesce_usecs
> 33333)
585 msk
|= rxirqmask
[port
];
586 delay
= ecmd
->rx_coalesce_usecs
;
589 if (ecmd
->tx_coalesce_usecs
== 0)
590 msk
&= ~txirqmask
[port
];
591 else if (ecmd
->tx_coalesce_usecs
< 25 ||
592 ecmd
->tx_coalesce_usecs
> 33333)
595 msk
|= txirqmask
[port
];
596 delay
= min(delay
, ecmd
->rx_coalesce_usecs
);
599 skge_write32(hw
, B2_IRQM_MSK
, msk
);
601 skge_write32(hw
, B2_IRQM_CTRL
, TIM_STOP
);
603 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, delay
));
604 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
609 enum led_mode
{ LED_MODE_OFF
, LED_MODE_ON
, LED_MODE_TST
};
610 static void skge_led(struct skge_port
*skge
, enum led_mode mode
)
612 struct skge_hw
*hw
= skge
->hw
;
613 int port
= skge
->port
;
615 spin_lock_bh(&hw
->phy_lock
);
616 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
619 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_OFF
);
620 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
621 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 0);
622 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_T_OFF
);
626 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_ON
);
627 skge_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_LINKSYNC_ON
);
629 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
630 skge_write8(hw
, SK_REG(port
, TX_LED_CTRL
), LED_START
);
635 skge_write8(hw
, SK_REG(port
, RX_LED_TST
), LED_T_ON
);
636 skge_write32(hw
, SK_REG(port
, RX_LED_VAL
), 100);
637 skge_write8(hw
, SK_REG(port
, RX_LED_CTRL
), LED_START
);
639 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, PHY_B_PEC_LED_ON
);
645 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
646 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
647 PHY_M_LED_MO_DUP(MO_LED_OFF
) |
648 PHY_M_LED_MO_10(MO_LED_OFF
) |
649 PHY_M_LED_MO_100(MO_LED_OFF
) |
650 PHY_M_LED_MO_1000(MO_LED_OFF
) |
651 PHY_M_LED_MO_RX(MO_LED_OFF
));
654 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
,
655 PHY_M_LED_PULS_DUR(PULS_170MS
) |
656 PHY_M_LED_BLINK_RT(BLINK_84MS
) |
660 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
661 PHY_M_LED_MO_RX(MO_LED_OFF
) |
662 (skge
->speed
== SPEED_100
?
663 PHY_M_LED_MO_100(MO_LED_ON
) : 0));
666 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
667 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
668 PHY_M_LED_MO_DUP(MO_LED_ON
) |
669 PHY_M_LED_MO_10(MO_LED_ON
) |
670 PHY_M_LED_MO_100(MO_LED_ON
) |
671 PHY_M_LED_MO_1000(MO_LED_ON
) |
672 PHY_M_LED_MO_RX(MO_LED_ON
));
675 spin_unlock_bh(&hw
->phy_lock
);
678 /* blink LED's for finding board */
679 static int skge_phys_id(struct net_device
*dev
, u32 data
)
681 struct skge_port
*skge
= netdev_priv(dev
);
683 enum led_mode mode
= LED_MODE_TST
;
685 if (!data
|| data
> (u32
)(MAX_SCHEDULE_TIMEOUT
/ HZ
))
686 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
/ HZ
) * 1000;
691 skge_led(skge
, mode
);
692 mode
^= LED_MODE_TST
;
694 if (msleep_interruptible(BLINK_MS
))
699 /* back to regular LED state */
700 skge_led(skge
, netif_running(dev
) ? LED_MODE_ON
: LED_MODE_OFF
);
705 static struct ethtool_ops skge_ethtool_ops
= {
706 .get_settings
= skge_get_settings
,
707 .set_settings
= skge_set_settings
,
708 .get_drvinfo
= skge_get_drvinfo
,
709 .get_regs_len
= skge_get_regs_len
,
710 .get_regs
= skge_get_regs
,
711 .get_wol
= skge_get_wol
,
712 .set_wol
= skge_set_wol
,
713 .get_msglevel
= skge_get_msglevel
,
714 .set_msglevel
= skge_set_msglevel
,
715 .nway_reset
= skge_nway_reset
,
716 .get_link
= ethtool_op_get_link
,
717 .get_ringparam
= skge_get_ring_param
,
718 .set_ringparam
= skge_set_ring_param
,
719 .get_pauseparam
= skge_get_pauseparam
,
720 .set_pauseparam
= skge_set_pauseparam
,
721 .get_coalesce
= skge_get_coalesce
,
722 .set_coalesce
= skge_set_coalesce
,
723 .get_sg
= ethtool_op_get_sg
,
724 .set_sg
= skge_set_sg
,
725 .get_tx_csum
= ethtool_op_get_tx_csum
,
726 .set_tx_csum
= skge_set_tx_csum
,
727 .get_rx_csum
= skge_get_rx_csum
,
728 .set_rx_csum
= skge_set_rx_csum
,
729 .get_strings
= skge_get_strings
,
730 .phys_id
= skge_phys_id
,
731 .get_stats_count
= skge_get_stats_count
,
732 .get_ethtool_stats
= skge_get_ethtool_stats
,
736 * Allocate ring elements and chain them together
737 * One-to-one association of board descriptors with ring elements
739 static int skge_ring_alloc(struct skge_ring
*ring
, void *vaddr
, u64 base
)
741 struct skge_tx_desc
*d
;
742 struct skge_element
*e
;
745 ring
->start
= kmalloc(sizeof(*e
)*ring
->count
, GFP_KERNEL
);
749 for (i
= 0, e
= ring
->start
, d
= vaddr
; i
< ring
->count
; i
++, e
++, d
++) {
752 if (i
== ring
->count
- 1) {
753 e
->next
= ring
->start
;
754 d
->next_offset
= base
;
757 d
->next_offset
= base
+ (i
+1) * sizeof(*d
);
760 ring
->to_use
= ring
->to_clean
= ring
->start
;
765 /* Allocate and setup a new buffer for receiving */
766 static void skge_rx_setup(struct skge_port
*skge
, struct skge_element
*e
,
767 struct sk_buff
*skb
, unsigned int bufsize
)
769 struct skge_rx_desc
*rd
= e
->desc
;
772 map
= pci_map_single(skge
->hw
->pdev
, skb
->data
, bufsize
,
776 rd
->dma_hi
= map
>> 32;
778 rd
->csum1_start
= ETH_HLEN
;
779 rd
->csum2_start
= ETH_HLEN
;
785 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| bufsize
;
786 pci_unmap_addr_set(e
, mapaddr
, map
);
787 pci_unmap_len_set(e
, maplen
, bufsize
);
790 /* Resume receiving using existing skb,
791 * Note: DMA address is not changed by chip.
792 * MTU not changed while receiver active.
794 static void skge_rx_reuse(struct skge_element
*e
, unsigned int size
)
796 struct skge_rx_desc
*rd
= e
->desc
;
799 rd
->csum2_start
= ETH_HLEN
;
803 rd
->control
= BMU_OWN
| BMU_STF
| BMU_IRQ_EOF
| BMU_TCP_CHECK
| size
;
807 /* Free all buffers in receive ring, assumes receiver stopped */
808 static void skge_rx_clean(struct skge_port
*skge
)
810 struct skge_hw
*hw
= skge
->hw
;
811 struct skge_ring
*ring
= &skge
->rx_ring
;
812 struct skge_element
*e
;
816 struct skge_rx_desc
*rd
= e
->desc
;
819 pci_unmap_single(hw
->pdev
,
820 pci_unmap_addr(e
, mapaddr
),
821 pci_unmap_len(e
, maplen
),
823 dev_kfree_skb(e
->skb
);
826 } while ((e
= e
->next
) != ring
->start
);
830 /* Allocate buffers for receive ring
831 * For receive: to_clean is next received frame.
833 static int skge_rx_fill(struct skge_port
*skge
)
835 struct skge_ring
*ring
= &skge
->rx_ring
;
836 struct skge_element
*e
;
842 skb
= dev_alloc_skb(skge
->rx_buf_size
+ NET_IP_ALIGN
);
846 skb_reserve(skb
, NET_IP_ALIGN
);
847 skge_rx_setup(skge
, e
, skb
, skge
->rx_buf_size
);
848 } while ( (e
= e
->next
) != ring
->start
);
850 ring
->to_clean
= ring
->start
;
854 static void skge_link_up(struct skge_port
*skge
)
856 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
),
857 LED_BLK_OFF
|LED_SYNC_OFF
|LED_ON
);
859 netif_carrier_on(skge
->netdev
);
860 if (skge
->tx_avail
> MAX_SKB_FRAGS
+ 1)
861 netif_wake_queue(skge
->netdev
);
863 if (netif_msg_link(skge
))
865 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
866 skge
->netdev
->name
, skge
->speed
,
867 skge
->duplex
== DUPLEX_FULL
? "full" : "half",
868 (skge
->flow_control
== FLOW_MODE_NONE
) ? "none" :
869 (skge
->flow_control
== FLOW_MODE_LOC_SEND
) ? "tx only" :
870 (skge
->flow_control
== FLOW_MODE_REM_SEND
) ? "rx only" :
871 (skge
->flow_control
== FLOW_MODE_SYMMETRIC
) ? "tx and rx" :
875 static void skge_link_down(struct skge_port
*skge
)
877 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
878 netif_carrier_off(skge
->netdev
);
879 netif_stop_queue(skge
->netdev
);
881 if (netif_msg_link(skge
))
882 printk(KERN_INFO PFX
"%s: Link is down.\n", skge
->netdev
->name
);
885 static u16
xm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
890 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
891 v
= xm_read16(hw
, port
, XM_PHY_DATA
);
893 /* Need to wait for external PHY */
894 for (i
= 0; i
< PHY_RETRIES
; i
++) {
896 if (xm_read16(hw
, port
, XM_MMU_CMD
)
901 printk(KERN_WARNING PFX
"%s: phy read timed out\n",
902 hw
->dev
[port
]->name
);
905 v
= xm_read16(hw
, port
, XM_PHY_DATA
);
910 static void xm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
914 xm_write16(hw
, port
, XM_PHY_ADDR
, reg
| hw
->phy_addr
);
915 for (i
= 0; i
< PHY_RETRIES
; i
++) {
916 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
920 printk(KERN_WARNING PFX
"%s: phy write failed to come ready\n",
921 hw
->dev
[port
]->name
);
925 xm_write16(hw
, port
, XM_PHY_DATA
, val
);
926 for (i
= 0; i
< PHY_RETRIES
; i
++) {
928 if (!(xm_read16(hw
, port
, XM_MMU_CMD
) & XM_MMU_PHY_BUSY
))
931 printk(KERN_WARNING PFX
"%s: phy write timed out\n",
932 hw
->dev
[port
]->name
);
935 static void genesis_init(struct skge_hw
*hw
)
937 /* set blink source counter */
938 skge_write32(hw
, B2_BSC_INI
, (SK_BLK_DUR
* SK_FACT_53
) / 100);
939 skge_write8(hw
, B2_BSC_CTRL
, BSC_START
);
941 /* configure mac arbiter */
942 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
944 /* configure mac arbiter timeout values */
945 skge_write8(hw
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
946 skge_write8(hw
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
947 skge_write8(hw
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
948 skge_write8(hw
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
950 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
951 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
952 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
953 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
955 /* configure packet arbiter timeout */
956 skge_write16(hw
, B3_PA_CTRL
, PA_RST_CLR
);
957 skge_write16(hw
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
958 skge_write16(hw
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
959 skge_write16(hw
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
960 skge_write16(hw
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
963 static void genesis_reset(struct skge_hw
*hw
, int port
)
965 const u8 zero
[8] = { 0 };
967 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
969 /* reset the statistics module */
970 xm_write32(hw
, port
, XM_GP_PORT
, XM_GP_RES_STAT
);
971 xm_write16(hw
, port
, XM_IMSK
, 0xffff); /* disable XMAC IRQs */
972 xm_write32(hw
, port
, XM_MODE
, 0); /* clear Mode Reg */
973 xm_write16(hw
, port
, XM_TX_CMD
, 0); /* reset TX CMD Reg */
974 xm_write16(hw
, port
, XM_RX_CMD
, 0); /* reset RX CMD Reg */
976 /* disable Broadcom PHY IRQ */
977 xm_write16(hw
, port
, PHY_BCOM_INT_MASK
, 0xffff);
979 xm_outhash(hw
, port
, XM_HSM
, zero
);
983 /* Convert mode to MII values */
984 static const u16 phy_pause_map
[] = {
985 [FLOW_MODE_NONE
] = 0,
986 [FLOW_MODE_LOC_SEND
] = PHY_AN_PAUSE_ASYM
,
987 [FLOW_MODE_SYMMETRIC
] = PHY_AN_PAUSE_CAP
,
988 [FLOW_MODE_REM_SEND
] = PHY_AN_PAUSE_CAP
| PHY_AN_PAUSE_ASYM
,
992 /* Check status of Broadcom phy link */
993 static void bcom_check_link(struct skge_hw
*hw
, int port
)
995 struct net_device
*dev
= hw
->dev
[port
];
996 struct skge_port
*skge
= netdev_priv(dev
);
999 /* read twice because of latch */
1000 (void) xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1001 status
= xm_phy_read(hw
, port
, PHY_BCOM_STAT
);
1003 if ((status
& PHY_ST_LSYNC
) == 0) {
1004 u16 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1005 cmd
&= ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1006 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1007 /* dummy read to ensure writing */
1008 (void) xm_read16(hw
, port
, XM_MMU_CMD
);
1010 if (netif_carrier_ok(dev
))
1011 skge_link_down(skge
);
1013 if (skge
->autoneg
== AUTONEG_ENABLE
&&
1014 (status
& PHY_ST_AN_OVER
)) {
1015 u16 lpa
= xm_phy_read(hw
, port
, PHY_BCOM_AUNE_LP
);
1016 u16 aux
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_STAT
);
1018 if (lpa
& PHY_B_AN_RF
) {
1019 printk(KERN_NOTICE PFX
"%s: remote fault\n",
1024 /* Check Duplex mismatch */
1025 switch (aux
& PHY_B_AS_AN_RES_MSK
) {
1026 case PHY_B_RES_1000FD
:
1027 skge
->duplex
= DUPLEX_FULL
;
1029 case PHY_B_RES_1000HD
:
1030 skge
->duplex
= DUPLEX_HALF
;
1033 printk(KERN_NOTICE PFX
"%s: duplex mismatch\n",
1039 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1040 switch (aux
& PHY_B_AS_PAUSE_MSK
) {
1041 case PHY_B_AS_PAUSE_MSK
:
1042 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
1045 skge
->flow_control
= FLOW_MODE_REM_SEND
;
1048 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
1051 skge
->flow_control
= FLOW_MODE_NONE
;
1054 skge
->speed
= SPEED_1000
;
1057 if (!netif_carrier_ok(dev
))
1058 genesis_link_up(skge
);
1062 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1063 * Phy on for 100 or 10Mbit operation
1065 static void bcom_phy_init(struct skge_port
*skge
, int jumbo
)
1067 struct skge_hw
*hw
= skge
->hw
;
1068 int port
= skge
->port
;
1070 u16 id1
, r
, ext
, ctl
;
1072 /* magic workaround patterns for Broadcom */
1073 static const struct {
1077 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1078 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1079 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1080 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1082 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1083 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1086 /* read Id from external PHY (all have the same address) */
1087 id1
= xm_phy_read(hw
, port
, PHY_XMAC_ID1
);
1089 /* Optimize MDIO transfer by suppressing preamble. */
1090 r
= xm_read16(hw
, port
, XM_MMU_CMD
);
1092 xm_write16(hw
, port
, XM_MMU_CMD
,r
);
1095 case PHY_BCOM_ID1_C0
:
1097 * Workaround BCOM Errata for the C0 type.
1098 * Write magic patterns to reserved registers.
1100 for (i
= 0; i
< ARRAY_SIZE(C0hack
); i
++)
1101 xm_phy_write(hw
, port
,
1102 C0hack
[i
].reg
, C0hack
[i
].val
);
1105 case PHY_BCOM_ID1_A1
:
1107 * Workaround BCOM Errata for the A1 type.
1108 * Write magic patterns to reserved registers.
1110 for (i
= 0; i
< ARRAY_SIZE(A1hack
); i
++)
1111 xm_phy_write(hw
, port
,
1112 A1hack
[i
].reg
, A1hack
[i
].val
);
1117 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1118 * Disable Power Management after reset.
1120 r
= xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
);
1121 r
|= PHY_B_AC_DIS_PM
;
1122 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
, r
);
1125 xm_read16(hw
, port
, XM_ISRC
);
1127 ext
= PHY_B_PEC_EN_LTR
; /* enable tx led */
1128 ctl
= PHY_CT_SP1000
; /* always 1000mbit */
1130 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1132 * Workaround BCOM Errata #1 for the C5 type.
1133 * 1000Base-T Link Acquisition Failure in Slave Mode
1134 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1136 u16 adv
= PHY_B_1000C_RD
;
1137 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1138 adv
|= PHY_B_1000C_AHD
;
1139 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1140 adv
|= PHY_B_1000C_AFD
;
1141 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, adv
);
1143 ctl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1145 if (skge
->duplex
== DUPLEX_FULL
)
1146 ctl
|= PHY_CT_DUP_MD
;
1147 /* Force to slave */
1148 xm_phy_write(hw
, port
, PHY_BCOM_1000T_CTRL
, PHY_B_1000C_MSE
);
1151 /* Set autonegotiation pause parameters */
1152 xm_phy_write(hw
, port
, PHY_BCOM_AUNE_ADV
,
1153 phy_pause_map
[skge
->flow_control
] | PHY_AN_CSMA
);
1155 /* Handle Jumbo frames */
1157 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1158 PHY_B_AC_TX_TST
| PHY_B_AC_LONG_PACK
);
1160 ext
|= PHY_B_PEC_HIGH_LA
;
1164 xm_phy_write(hw
, port
, PHY_BCOM_P_EXT_CTRL
, ext
);
1165 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
, ctl
);
1167 /* Use link status change interrrupt */
1168 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1170 bcom_check_link(hw
, port
);
1173 static void genesis_mac_init(struct skge_hw
*hw
, int port
)
1175 struct net_device
*dev
= hw
->dev
[port
];
1176 struct skge_port
*skge
= netdev_priv(dev
);
1177 int jumbo
= hw
->dev
[port
]->mtu
> ETH_DATA_LEN
;
1180 const u8 zero
[6] = { 0 };
1182 /* Clear MIB counters */
1183 xm_write16(hw
, port
, XM_STAT_CMD
,
1184 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1185 /* Clear two times according to Errata #3 */
1186 xm_write16(hw
, port
, XM_STAT_CMD
,
1187 XM_SC_CLR_RXC
| XM_SC_CLR_TXC
);
1189 /* Unreset the XMAC. */
1190 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_CLR_MAC_RST
);
1193 * Perform additional initialization for external PHYs,
1194 * namely for the 1000baseTX cards that use the XMAC's
1197 /* Take external Phy out of reset */
1198 r
= skge_read32(hw
, B2_GP_IO
);
1200 r
|= GP_DIR_0
|GP_IO_0
;
1202 r
|= GP_DIR_2
|GP_IO_2
;
1204 skge_write32(hw
, B2_GP_IO
, r
);
1205 skge_read32(hw
, B2_GP_IO
);
1207 /* Enable GMII interfac */
1208 xm_write16(hw
, port
, XM_HW_CFG
, XM_HW_GMII_MD
);
1210 bcom_phy_init(skge
, jumbo
);
1212 /* Set Station Address */
1213 xm_outaddr(hw
, port
, XM_SA
, dev
->dev_addr
);
1215 /* We don't use match addresses so clear */
1216 for (i
= 1; i
< 16; i
++)
1217 xm_outaddr(hw
, port
, XM_EXM(i
), zero
);
1219 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1220 xm_write16(hw
, port
, XM_RX_HI_WM
, 1450);
1222 /* We don't need the FCS appended to the packet. */
1223 r
= XM_RX_LENERR_OK
| XM_RX_STRIP_FCS
;
1225 r
|= XM_RX_BIG_PK_OK
;
1227 if (skge
->duplex
== DUPLEX_HALF
) {
1229 * If in manual half duplex mode the other side might be in
1230 * full duplex mode, so ignore if a carrier extension is not seen
1231 * on frames received
1233 r
|= XM_RX_DIS_CEXT
;
1235 xm_write16(hw
, port
, XM_RX_CMD
, r
);
1238 /* We want short frames padded to 60 bytes. */
1239 xm_write16(hw
, port
, XM_TX_CMD
, XM_TX_AUTO_PAD
);
1242 * Bump up the transmit threshold. This helps hold off transmit
1243 * underruns when we're blasting traffic from both ports at once.
1245 xm_write16(hw
, port
, XM_TX_THR
, 512);
1248 * Enable the reception of all error frames. This is is
1249 * a necessary evil due to the design of the XMAC. The
1250 * XMAC's receive FIFO is only 8K in size, however jumbo
1251 * frames can be up to 9000 bytes in length. When bad
1252 * frame filtering is enabled, the XMAC's RX FIFO operates
1253 * in 'store and forward' mode. For this to work, the
1254 * entire frame has to fit into the FIFO, but that means
1255 * that jumbo frames larger than 8192 bytes will be
1256 * truncated. Disabling all bad frame filtering causes
1257 * the RX FIFO to operate in streaming mode, in which
1258 * case the XMAC will start transfering frames out of the
1259 * RX FIFO as soon as the FIFO threshold is reached.
1261 xm_write32(hw
, port
, XM_MODE
, XM_DEF_MODE
);
1265 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1266 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1267 * and 'Octets Rx OK Hi Cnt Ov'.
1269 xm_write32(hw
, port
, XM_RX_EV_MSK
, XMR_DEF_MSK
);
1272 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1273 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1274 * and 'Octets Tx OK Hi Cnt Ov'.
1276 xm_write32(hw
, port
, XM_TX_EV_MSK
, XMT_DEF_MSK
);
1278 /* Configure MAC arbiter */
1279 skge_write16(hw
, B3_MA_TO_CTRL
, MA_RST_CLR
);
1281 /* configure timeout values */
1282 skge_write8(hw
, B3_MA_TOINI_RX1
, 72);
1283 skge_write8(hw
, B3_MA_TOINI_RX2
, 72);
1284 skge_write8(hw
, B3_MA_TOINI_TX1
, 72);
1285 skge_write8(hw
, B3_MA_TOINI_TX2
, 72);
1287 skge_write8(hw
, B3_MA_RCINI_RX1
, 0);
1288 skge_write8(hw
, B3_MA_RCINI_RX2
, 0);
1289 skge_write8(hw
, B3_MA_RCINI_TX1
, 0);
1290 skge_write8(hw
, B3_MA_RCINI_TX2
, 0);
1292 /* Configure Rx MAC FIFO */
1293 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
1294 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_TIM_PAT
);
1295 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1297 /* Configure Tx MAC FIFO */
1298 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
1299 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
1300 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
1303 /* Enable frame flushing if jumbo frames used */
1304 skge_write16(hw
, SK_REG(port
,RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
1306 /* enable timeout timers if normal frames */
1307 skge_write16(hw
, B3_PA_CTRL
,
1308 (port
== 0) ? PA_ENA_TO_TX1
: PA_ENA_TO_TX2
);
1312 static void genesis_stop(struct skge_port
*skge
)
1314 struct skge_hw
*hw
= skge
->hw
;
1315 int port
= skge
->port
;
1318 genesis_reset(hw
, port
);
1320 /* Clear Tx packet arbiter timeout IRQ */
1321 skge_write16(hw
, B3_PA_CTRL
,
1322 port
== 0 ? PA_CLR_TO_TX1
: PA_CLR_TO_TX2
);
1325 * If the transfer stucks at the MAC the STOP command will not
1326 * terminate if we don't flush the XMAC's transmit FIFO !
1328 xm_write32(hw
, port
, XM_MODE
,
1329 xm_read32(hw
, port
, XM_MODE
)|XM_MD_FTF
);
1333 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
), MFF_SET_MAC_RST
);
1335 /* For external PHYs there must be special handling */
1336 reg
= skge_read32(hw
, B2_GP_IO
);
1344 skge_write32(hw
, B2_GP_IO
, reg
);
1345 skge_read32(hw
, B2_GP_IO
);
1347 xm_write16(hw
, port
, XM_MMU_CMD
,
1348 xm_read16(hw
, port
, XM_MMU_CMD
)
1349 & ~(XM_MMU_ENA_RX
| XM_MMU_ENA_TX
));
1351 xm_read16(hw
, port
, XM_MMU_CMD
);
1355 static void genesis_get_stats(struct skge_port
*skge
, u64
*data
)
1357 struct skge_hw
*hw
= skge
->hw
;
1358 int port
= skge
->port
;
1360 unsigned long timeout
= jiffies
+ HZ
;
1362 xm_write16(hw
, port
,
1363 XM_STAT_CMD
, XM_SC_SNP_TXC
| XM_SC_SNP_RXC
);
1365 /* wait for update to complete */
1366 while (xm_read16(hw
, port
, XM_STAT_CMD
)
1367 & (XM_SC_SNP_TXC
| XM_SC_SNP_RXC
)) {
1368 if (time_after(jiffies
, timeout
))
1373 /* special case for 64 bit octet counter */
1374 data
[0] = (u64
) xm_read32(hw
, port
, XM_TXO_OK_HI
) << 32
1375 | xm_read32(hw
, port
, XM_TXO_OK_LO
);
1376 data
[1] = (u64
) xm_read32(hw
, port
, XM_RXO_OK_HI
) << 32
1377 | xm_read32(hw
, port
, XM_RXO_OK_LO
);
1379 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
1380 data
[i
] = xm_read32(hw
, port
, skge_stats
[i
].xmac_offset
);
1383 static void genesis_mac_intr(struct skge_hw
*hw
, int port
)
1385 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1386 u16 status
= xm_read16(hw
, port
, XM_ISRC
);
1388 if (netif_msg_intr(skge
))
1389 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
1390 skge
->netdev
->name
, status
);
1392 if (status
& XM_IS_TXF_UR
) {
1393 xm_write32(hw
, port
, XM_MODE
, XM_MD_FTF
);
1394 ++skge
->net_stats
.tx_fifo_errors
;
1396 if (status
& XM_IS_RXF_OV
) {
1397 xm_write32(hw
, port
, XM_MODE
, XM_MD_FRF
);
1398 ++skge
->net_stats
.rx_fifo_errors
;
1402 static void gm_phy_write(struct skge_hw
*hw
, int port
, u16 reg
, u16 val
)
1406 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
1407 gma_write16(hw
, port
, GM_SMI_CTRL
,
1408 GM_SMI_CT_PHY_AD(hw
->phy_addr
) | GM_SMI_CT_REG_AD(reg
));
1409 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1412 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
1417 static u16
gm_phy_read(struct skge_hw
*hw
, int port
, u16 reg
)
1421 gma_write16(hw
, port
, GM_SMI_CTRL
,
1422 GM_SMI_CT_PHY_AD(hw
->phy_addr
)
1423 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
1425 for (i
= 0; i
< PHY_RETRIES
; i
++) {
1427 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
)
1431 printk(KERN_WARNING PFX
"%s: phy read timeout\n",
1432 hw
->dev
[port
]->name
);
1435 return gma_read16(hw
, port
, GM_SMI_DATA
);
1438 static void genesis_link_up(struct skge_port
*skge
)
1440 struct skge_hw
*hw
= skge
->hw
;
1441 int port
= skge
->port
;
1445 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1448 * enabling pause frame reception is required for 1000BT
1449 * because the XMAC is not reset if the link is going down
1451 if (skge
->flow_control
== FLOW_MODE_NONE
||
1452 skge
->flow_control
== FLOW_MODE_LOC_SEND
)
1453 /* Disable Pause Frame Reception */
1454 cmd
|= XM_MMU_IGN_PF
;
1456 /* Enable Pause Frame Reception */
1457 cmd
&= ~XM_MMU_IGN_PF
;
1459 xm_write16(hw
, port
, XM_MMU_CMD
, cmd
);
1461 mode
= xm_read32(hw
, port
, XM_MODE
);
1462 if (skge
->flow_control
== FLOW_MODE_SYMMETRIC
||
1463 skge
->flow_control
== FLOW_MODE_LOC_SEND
) {
1465 * Configure Pause Frame Generation
1466 * Use internal and external Pause Frame Generation.
1467 * Sending pause frames is edge triggered.
1468 * Send a Pause frame with the maximum pause time if
1469 * internal oder external FIFO full condition occurs.
1470 * Send a zero pause time frame to re-start transmission.
1472 /* XM_PAUSE_DA = '010000C28001' (default) */
1473 /* XM_MAC_PTIME = 0xffff (maximum) */
1474 /* remember this value is defined in big endian (!) */
1475 xm_write16(hw
, port
, XM_MAC_PTIME
, 0xffff);
1477 mode
|= XM_PAUSE_MODE
;
1478 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_ENA_PAUSE
);
1481 * disable pause frame generation is required for 1000BT
1482 * because the XMAC is not reset if the link is going down
1484 /* Disable Pause Mode in Mode Register */
1485 mode
&= ~XM_PAUSE_MODE
;
1487 skge_write16(hw
, SK_REG(port
, RX_MFF_CTRL1
), MFF_DIS_PAUSE
);
1490 xm_write32(hw
, port
, XM_MODE
, mode
);
1493 /* disable GP0 interrupt bit for external Phy */
1494 msk
|= XM_IS_INP_ASS
;
1496 xm_write16(hw
, port
, XM_IMSK
, msk
);
1497 xm_read16(hw
, port
, XM_ISRC
);
1499 /* get MMU Command Reg. */
1500 cmd
= xm_read16(hw
, port
, XM_MMU_CMD
);
1501 if (skge
->duplex
== DUPLEX_FULL
)
1502 cmd
|= XM_MMU_GMII_FD
;
1505 * Workaround BCOM Errata (#10523) for all BCom Phys
1506 * Enable Power Management after link up
1508 xm_phy_write(hw
, port
, PHY_BCOM_AUX_CTRL
,
1509 xm_phy_read(hw
, port
, PHY_BCOM_AUX_CTRL
)
1510 & ~PHY_B_AC_DIS_PM
);
1511 xm_phy_write(hw
, port
, PHY_BCOM_INT_MASK
, PHY_B_DEF_MSK
);
1514 xm_write16(hw
, port
, XM_MMU_CMD
,
1515 cmd
| XM_MMU_ENA_RX
| XM_MMU_ENA_TX
);
1520 static inline void bcom_phy_intr(struct skge_port
*skge
)
1522 struct skge_hw
*hw
= skge
->hw
;
1523 int port
= skge
->port
;
1526 isrc
= xm_phy_read(hw
, port
, PHY_BCOM_INT_STAT
);
1527 if (netif_msg_intr(skge
))
1528 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x\n",
1529 skge
->netdev
->name
, isrc
);
1531 if (isrc
& PHY_B_IS_PSE
)
1532 printk(KERN_ERR PFX
"%s: uncorrectable pair swap error\n",
1533 hw
->dev
[port
]->name
);
1535 /* Workaround BCom Errata:
1536 * enable and disable loopback mode if "NO HCD" occurs.
1538 if (isrc
& PHY_B_IS_NO_HDCL
) {
1539 u16 ctrl
= xm_phy_read(hw
, port
, PHY_BCOM_CTRL
);
1540 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1541 ctrl
| PHY_CT_LOOP
);
1542 xm_phy_write(hw
, port
, PHY_BCOM_CTRL
,
1543 ctrl
& ~PHY_CT_LOOP
);
1546 if (isrc
& (PHY_B_IS_AN_PR
| PHY_B_IS_LST_CHANGE
))
1547 bcom_check_link(hw
, port
);
1551 /* Marvell Phy Initailization */
1552 static void yukon_init(struct skge_hw
*hw
, int port
)
1554 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1555 u16 ctrl
, ct1000
, adv
;
1557 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1558 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
1560 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
1561 PHY_M_EC_MAC_S_MSK
);
1562 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
1564 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1566 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
1569 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
1570 if (skge
->autoneg
== AUTONEG_DISABLE
)
1571 ctrl
&= ~PHY_CT_ANE
;
1573 ctrl
|= PHY_CT_RESET
;
1574 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1580 if (skge
->autoneg
== AUTONEG_ENABLE
) {
1582 if (skge
->advertising
& ADVERTISED_1000baseT_Full
)
1583 ct1000
|= PHY_M_1000C_AFD
;
1584 if (skge
->advertising
& ADVERTISED_1000baseT_Half
)
1585 ct1000
|= PHY_M_1000C_AHD
;
1586 if (skge
->advertising
& ADVERTISED_100baseT_Full
)
1587 adv
|= PHY_M_AN_100_FD
;
1588 if (skge
->advertising
& ADVERTISED_100baseT_Half
)
1589 adv
|= PHY_M_AN_100_HD
;
1590 if (skge
->advertising
& ADVERTISED_10baseT_Full
)
1591 adv
|= PHY_M_AN_10_FD
;
1592 if (skge
->advertising
& ADVERTISED_10baseT_Half
)
1593 adv
|= PHY_M_AN_10_HD
;
1594 } else /* special defines for FIBER (88E1011S only) */
1595 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
1597 /* Set Flow-control capabilities */
1598 adv
|= phy_pause_map
[skge
->flow_control
];
1600 /* Restart Auto-negotiation */
1601 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
1603 /* forced speed/duplex settings */
1604 ct1000
= PHY_M_1000C_MSE
;
1606 if (skge
->duplex
== DUPLEX_FULL
)
1607 ctrl
|= PHY_CT_DUP_MD
;
1609 switch (skge
->speed
) {
1611 ctrl
|= PHY_CT_SP1000
;
1614 ctrl
|= PHY_CT_SP100
;
1618 ctrl
|= PHY_CT_RESET
;
1621 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
1623 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
1624 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
1626 /* Enable phy interrupt on autonegotiation complete (or link up) */
1627 if (skge
->autoneg
== AUTONEG_ENABLE
)
1628 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_MSK
);
1630 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
1633 static void yukon_reset(struct skge_hw
*hw
, int port
)
1635 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);/* disable PHY IRQs */
1636 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
1637 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
1638 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
1639 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
1641 gma_write16(hw
, port
, GM_RX_CTRL
,
1642 gma_read16(hw
, port
, GM_RX_CTRL
)
1643 | GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
1646 static void yukon_mac_init(struct skge_hw
*hw
, int port
)
1648 struct skge_port
*skge
= netdev_priv(hw
->dev
[port
]);
1651 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
1653 /* WA code for COMA mode -- set PHY reset */
1654 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1655 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1656 reg
= skge_read32(hw
, B2_GP_IO
);
1657 reg
|= GP_DIR_9
| GP_IO_9
;
1658 skge_write32(hw
, B2_GP_IO
, reg
);
1662 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1663 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1665 /* WA code for COMA mode -- clear PHY reset */
1666 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1667 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1668 reg
= skge_read32(hw
, B2_GP_IO
);
1671 skge_write32(hw
, B2_GP_IO
, reg
);
1674 /* Set hardware config mode */
1675 reg
= GPC_INT_POL_HI
| GPC_DIS_FC
| GPC_DIS_SLEEP
|
1676 GPC_ENA_XC
| GPC_ANEG_ADV_ALL_M
| GPC_ENA_PAUSE
;
1677 reg
|= hw
->copper
? GPC_HWCFG_GMII_COP
: GPC_HWCFG_GMII_FIB
;
1679 /* Clear GMC reset */
1680 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_SET
);
1681 skge_write32(hw
, SK_REG(port
, GPHY_CTRL
), reg
| GPC_RST_CLR
);
1682 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
| GMC_RST_CLR
);
1683 if (skge
->autoneg
== AUTONEG_DISABLE
) {
1684 reg
= GM_GPCR_AU_ALL_DIS
;
1685 gma_write16(hw
, port
, GM_GP_CTRL
,
1686 gma_read16(hw
, port
, GM_GP_CTRL
) | reg
);
1688 switch (skge
->speed
) {
1690 reg
|= GM_GPCR_SPEED_1000
;
1693 reg
|= GM_GPCR_SPEED_100
;
1696 if (skge
->duplex
== DUPLEX_FULL
)
1697 reg
|= GM_GPCR_DUP_FULL
;
1699 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
1700 switch (skge
->flow_control
) {
1701 case FLOW_MODE_NONE
:
1702 skge_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1703 reg
|= GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
1705 case FLOW_MODE_LOC_SEND
:
1706 /* disable Rx flow-control */
1707 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
1710 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1711 skge_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
1713 yukon_init(hw
, port
);
1716 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
1717 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
1719 for (i
= 0; i
< GM_MIB_CNT_SIZE
; i
++)
1720 gma_read16(hw
, port
, GM_MIB_CNT_BASE
+ 8*i
);
1721 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
1723 /* transmit control */
1724 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
1726 /* receive control reg: unicast + multicast + no FCS */
1727 gma_write16(hw
, port
, GM_RX_CTRL
,
1728 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
1730 /* transmit flow control */
1731 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
1733 /* transmit parameter */
1734 gma_write16(hw
, port
, GM_TX_PARAM
,
1735 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
1736 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
1737 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
));
1739 /* serial mode register */
1740 reg
= GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1741 if (hw
->dev
[port
]->mtu
> 1500)
1742 reg
|= GM_SMOD_JUMBO_ENA
;
1744 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
1746 /* physical address: used for pause frames */
1747 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
1748 /* virtual address for data */
1749 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
1751 /* enable interrupt mask for counter overflows */
1752 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
1753 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
1754 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
1756 /* Initialize Mac Fifo */
1758 /* Configure Rx MAC FIFO */
1759 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), RX_FF_FL_DEF_MSK
);
1760 reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
1761 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1762 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
)
1763 reg
&= ~GMF_RX_F_FL_ON
;
1764 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
1765 skge_write16(hw
, SK_REG(port
, RX_GMF_CTRL_T
), reg
);
1767 * because Pause Packet Truncation in GMAC is not working
1768 * we have to increase the Flush Threshold to 64 bytes
1769 * in order to flush pause packets in Rx FIFO on Yukon-1
1771 skge_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
1773 /* Configure Tx MAC FIFO */
1774 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
1775 skge_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
1778 static void yukon_stop(struct skge_port
*skge
)
1780 struct skge_hw
*hw
= skge
->hw
;
1781 int port
= skge
->port
;
1783 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
1784 yukon_reset(hw
, port
);
1786 gma_write16(hw
, port
, GM_GP_CTRL
,
1787 gma_read16(hw
, port
, GM_GP_CTRL
)
1788 & ~(GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
));
1789 gma_read16(hw
, port
, GM_GP_CTRL
);
1791 if (hw
->chip_id
== CHIP_ID_YUKON_LITE
&&
1792 hw
->chip_rev
>= CHIP_REV_YU_LITE_A3
) {
1793 u32 io
= skge_read32(hw
, B2_GP_IO
);
1795 io
|= GP_DIR_9
| GP_IO_9
;
1796 skge_write32(hw
, B2_GP_IO
, io
);
1797 skge_read32(hw
, B2_GP_IO
);
1800 /* set GPHY Control reset */
1801 skge_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1802 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1805 static void yukon_get_stats(struct skge_port
*skge
, u64
*data
)
1807 struct skge_hw
*hw
= skge
->hw
;
1808 int port
= skge
->port
;
1811 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
1812 | gma_read32(hw
, port
, GM_TXO_OK_LO
);
1813 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
1814 | gma_read32(hw
, port
, GM_RXO_OK_LO
);
1816 for (i
= 2; i
< ARRAY_SIZE(skge_stats
); i
++)
1817 data
[i
] = gma_read32(hw
, port
,
1818 skge_stats
[i
].gma_offset
);
1821 static void yukon_mac_intr(struct skge_hw
*hw
, int port
)
1823 struct net_device
*dev
= hw
->dev
[port
];
1824 struct skge_port
*skge
= netdev_priv(dev
);
1825 u8 status
= skge_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
1827 if (netif_msg_intr(skge
))
1828 printk(KERN_DEBUG PFX
"%s: mac interrupt status 0x%x\n",
1831 if (status
& GM_IS_RX_FF_OR
) {
1832 ++skge
->net_stats
.rx_fifo_errors
;
1833 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
1836 if (status
& GM_IS_TX_FF_UR
) {
1837 ++skge
->net_stats
.tx_fifo_errors
;
1838 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
1843 static u16
yukon_speed(const struct skge_hw
*hw
, u16 aux
)
1845 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1846 case PHY_M_PS_SPEED_1000
:
1848 case PHY_M_PS_SPEED_100
:
1855 static void yukon_link_up(struct skge_port
*skge
)
1857 struct skge_hw
*hw
= skge
->hw
;
1858 int port
= skge
->port
;
1861 /* Enable Transmit FIFO Underrun */
1862 skge_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1864 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1865 if (skge
->duplex
== DUPLEX_FULL
|| skge
->autoneg
== AUTONEG_ENABLE
)
1866 reg
|= GM_GPCR_DUP_FULL
;
1869 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1870 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1872 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_DEF_MSK
);
1876 static void yukon_link_down(struct skge_port
*skge
)
1878 struct skge_hw
*hw
= skge
->hw
;
1879 int port
= skge
->port
;
1882 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1884 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1885 ctrl
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1886 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1888 if (skge
->flow_control
== FLOW_MODE_REM_SEND
) {
1889 /* restore Asymmetric Pause bit */
1890 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1891 gm_phy_read(hw
, port
,
1897 yukon_reset(hw
, port
);
1898 skge_link_down(skge
);
1900 yukon_init(hw
, port
);
1903 static void yukon_phy_intr(struct skge_port
*skge
)
1905 struct skge_hw
*hw
= skge
->hw
;
1906 int port
= skge
->port
;
1907 const char *reason
= NULL
;
1908 u16 istatus
, phystat
;
1910 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1911 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1913 if (netif_msg_intr(skge
))
1914 printk(KERN_DEBUG PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1915 skge
->netdev
->name
, istatus
, phystat
);
1917 if (istatus
& PHY_M_IS_AN_COMPL
) {
1918 if (gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
)
1920 reason
= "remote fault";
1924 if (gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1925 reason
= "master/slave fault";
1929 if (!(phystat
& PHY_M_PS_SPDUP_RES
)) {
1930 reason
= "speed/duplex";
1934 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
)
1935 ? DUPLEX_FULL
: DUPLEX_HALF
;
1936 skge
->speed
= yukon_speed(hw
, phystat
);
1938 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1939 switch (phystat
& PHY_M_PS_PAUSE_MSK
) {
1940 case PHY_M_PS_PAUSE_MSK
:
1941 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
1943 case PHY_M_PS_RX_P_EN
:
1944 skge
->flow_control
= FLOW_MODE_REM_SEND
;
1946 case PHY_M_PS_TX_P_EN
:
1947 skge
->flow_control
= FLOW_MODE_LOC_SEND
;
1950 skge
->flow_control
= FLOW_MODE_NONE
;
1953 if (skge
->flow_control
== FLOW_MODE_NONE
||
1954 (skge
->speed
< SPEED_1000
&& skge
->duplex
== DUPLEX_HALF
))
1955 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1957 skge_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1958 yukon_link_up(skge
);
1962 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1963 skge
->speed
= yukon_speed(hw
, phystat
);
1965 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1966 skge
->duplex
= (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1967 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1968 if (phystat
& PHY_M_PS_LINK_UP
)
1969 yukon_link_up(skge
);
1971 yukon_link_down(skge
);
1975 printk(KERN_ERR PFX
"%s: autonegotiation failed (%s)\n",
1976 skge
->netdev
->name
, reason
);
1978 /* XXX restart autonegotiation? */
1981 static void skge_ramset(struct skge_hw
*hw
, u16 q
, u32 start
, size_t len
)
1987 end
= start
+ len
- 1;
1989 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
1990 skge_write32(hw
, RB_ADDR(q
, RB_START
), start
);
1991 skge_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
1992 skge_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
1993 skge_write32(hw
, RB_ADDR(q
, RB_END
), end
);
1995 if (q
== Q_R1
|| q
== Q_R2
) {
1996 /* Set thresholds on receive queue's */
1997 skge_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
),
1999 skge_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
),
2002 /* Enable store & forward on Tx queue's because
2003 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2005 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
2008 skge_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
2011 /* Setup Bus Memory Interface */
2012 static void skge_qset(struct skge_port
*skge
, u16 q
,
2013 const struct skge_element
*e
)
2015 struct skge_hw
*hw
= skge
->hw
;
2016 u32 watermark
= 0x600;
2017 u64 base
= skge
->dma
+ (e
->desc
- skge
->mem
);
2019 /* optimization to reduce window on 32bit/33mhz */
2020 if ((skge_read16(hw
, B0_CTST
) & (CS_BUS_CLOCK
| CS_BUS_SLOT_SZ
)) == 0)
2023 skge_write32(hw
, Q_ADDR(q
, Q_CSR
), CSR_CLR_RESET
);
2024 skge_write32(hw
, Q_ADDR(q
, Q_F
), watermark
);
2025 skge_write32(hw
, Q_ADDR(q
, Q_DA_H
), (u32
)(base
>> 32));
2026 skge_write32(hw
, Q_ADDR(q
, Q_DA_L
), (u32
)base
);
2029 static int skge_up(struct net_device
*dev
)
2031 struct skge_port
*skge
= netdev_priv(dev
);
2032 struct skge_hw
*hw
= skge
->hw
;
2033 int port
= skge
->port
;
2034 u32 chunk
, ram_addr
;
2035 size_t rx_size
, tx_size
;
2038 if (netif_msg_ifup(skge
))
2039 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
2041 if (dev
->mtu
> RX_BUF_SIZE
)
2042 skge
->rx_buf_size
= dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
;
2044 skge
->rx_buf_size
= RX_BUF_SIZE
;
2047 rx_size
= skge
->rx_ring
.count
* sizeof(struct skge_rx_desc
);
2048 tx_size
= skge
->tx_ring
.count
* sizeof(struct skge_tx_desc
);
2049 skge
->mem_size
= tx_size
+ rx_size
;
2050 skge
->mem
= pci_alloc_consistent(hw
->pdev
, skge
->mem_size
, &skge
->dma
);
2054 memset(skge
->mem
, 0, skge
->mem_size
);
2056 if ((err
= skge_ring_alloc(&skge
->rx_ring
, skge
->mem
, skge
->dma
)))
2059 err
= skge_rx_fill(skge
);
2063 if ((err
= skge_ring_alloc(&skge
->tx_ring
, skge
->mem
+ rx_size
,
2064 skge
->dma
+ rx_size
)))
2067 skge
->tx_avail
= skge
->tx_ring
.count
- 1;
2069 /* Enable IRQ from port */
2070 hw
->intr_mask
|= portirqmask
[port
];
2071 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2074 spin_lock_bh(&hw
->phy_lock
);
2075 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2076 genesis_mac_init(hw
, port
);
2078 yukon_mac_init(hw
, port
);
2079 spin_unlock_bh(&hw
->phy_lock
);
2081 /* Configure RAMbuffers */
2082 chunk
= hw
->ram_size
/ ((hw
->ports
+ 1)*2);
2083 ram_addr
= hw
->ram_offset
+ 2 * chunk
* port
;
2085 skge_ramset(hw
, rxqaddr
[port
], ram_addr
, chunk
);
2086 skge_qset(skge
, rxqaddr
[port
], skge
->rx_ring
.to_clean
);
2088 BUG_ON(skge
->tx_ring
.to_use
!= skge
->tx_ring
.to_clean
);
2089 skge_ramset(hw
, txqaddr
[port
], ram_addr
+chunk
, chunk
);
2090 skge_qset(skge
, txqaddr
[port
], skge
->tx_ring
.to_use
);
2092 /* Start receiver BMU */
2094 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_START
| CSR_IRQ_CL_F
);
2095 skge_led(skge
, LED_MODE_ON
);
2100 skge_rx_clean(skge
);
2101 kfree(skge
->rx_ring
.start
);
2103 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2108 static int skge_down(struct net_device
*dev
)
2110 struct skge_port
*skge
= netdev_priv(dev
);
2111 struct skge_hw
*hw
= skge
->hw
;
2112 int port
= skge
->port
;
2114 if (netif_msg_ifdown(skge
))
2115 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
2117 netif_stop_queue(dev
);
2119 skge_write8(skge
->hw
, SK_REG(skge
->port
, LNK_LED_REG
), LED_OFF
);
2120 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2125 hw
->intr_mask
&= ~portirqmask
[skge
->port
];
2126 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2128 /* Stop transmitter */
2129 skge_write8(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_STOP
);
2130 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
2131 RB_RST_SET
|RB_DIS_OP_MD
);
2134 /* Disable Force Sync bit and Enable Alloc bit */
2135 skge_write8(hw
, SK_REG(port
, TXA_CTRL
),
2136 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
2138 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2139 skge_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
2140 skge_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
2142 /* Reset PCI FIFO */
2143 skge_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2144 skge_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
2146 /* Reset the RAM Buffer async Tx queue */
2147 skge_write8(hw
, RB_ADDR(port
== 0 ? Q_XA1
: Q_XA2
, RB_CTRL
), RB_RST_SET
);
2149 skge_write8(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_STOP
);
2150 skge_write32(hw
, RB_ADDR(port
? Q_R2
: Q_R1
, RB_CTRL
),
2151 RB_RST_SET
|RB_DIS_OP_MD
);
2152 skge_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), CSR_SET_RESET
);
2154 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2155 skge_write8(hw
, SK_REG(port
, TX_MFF_CTRL2
), MFF_RST_SET
);
2156 skge_write8(hw
, SK_REG(port
, RX_MFF_CTRL2
), MFF_RST_SET
);
2158 skge_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
2159 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
2162 skge_led(skge
, LED_MODE_OFF
);
2164 skge_tx_clean(skge
);
2165 skge_rx_clean(skge
);
2167 kfree(skge
->rx_ring
.start
);
2168 kfree(skge
->tx_ring
.start
);
2169 pci_free_consistent(hw
->pdev
, skge
->mem_size
, skge
->mem
, skge
->dma
);
2173 static int skge_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
2175 struct skge_port
*skge
= netdev_priv(dev
);
2176 struct skge_hw
*hw
= skge
->hw
;
2177 struct skge_ring
*ring
= &skge
->tx_ring
;
2178 struct skge_element
*e
;
2179 struct skge_tx_desc
*td
;
2183 unsigned long flags
;
2185 skb
= skb_padto(skb
, ETH_ZLEN
);
2187 return NETDEV_TX_OK
;
2189 local_irq_save(flags
);
2190 if (!spin_trylock(&skge
->tx_lock
)) {
2191 /* Collision - tell upper layer to requeue */
2192 local_irq_restore(flags
);
2193 return NETDEV_TX_LOCKED
;
2196 if (unlikely(skge
->tx_avail
< skb_shinfo(skb
)->nr_frags
+1)) {
2197 netif_stop_queue(dev
);
2198 spin_unlock_irqrestore(&skge
->tx_lock
, flags
);
2200 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
2202 return NETDEV_TX_BUSY
;
2208 len
= skb_headlen(skb
);
2209 map
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2210 pci_unmap_addr_set(e
, mapaddr
, map
);
2211 pci_unmap_len_set(e
, maplen
, len
);
2214 td
->dma_hi
= map
>> 32;
2216 if (skb
->ip_summed
== CHECKSUM_HW
) {
2217 const struct iphdr
*ip
2218 = (const struct iphdr
*) (skb
->data
+ ETH_HLEN
);
2219 int offset
= skb
->h
.raw
- skb
->data
;
2221 /* This seems backwards, but it is what the sk98lin
2222 * does. Looks like hardware is wrong?
2224 if (ip
->protocol
== IPPROTO_UDP
2225 && hw
->chip_rev
== 0 && hw
->chip_id
== CHIP_ID_YUKON
)
2226 control
= BMU_TCP_CHECK
;
2228 control
= BMU_UDP_CHECK
;
2231 td
->csum_start
= offset
;
2232 td
->csum_write
= offset
+ skb
->csum
;
2234 control
= BMU_CHECK
;
2236 if (!skb_shinfo(skb
)->nr_frags
) /* single buffer i.e. no fragments */
2237 control
|= BMU_EOF
| BMU_IRQ_EOF
;
2239 struct skge_tx_desc
*tf
= td
;
2241 control
|= BMU_STFWD
;
2242 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2243 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2245 map
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
2246 frag
->size
, PCI_DMA_TODEVICE
);
2252 tf
->dma_hi
= (u64
) map
>> 32;
2253 pci_unmap_addr_set(e
, mapaddr
, map
);
2254 pci_unmap_len_set(e
, maplen
, frag
->size
);
2256 tf
->control
= BMU_OWN
| BMU_SW
| control
| frag
->size
;
2258 tf
->control
|= BMU_EOF
| BMU_IRQ_EOF
;
2260 /* Make sure all the descriptors written */
2262 td
->control
= BMU_OWN
| BMU_SW
| BMU_STF
| control
| len
;
2265 skge_write8(hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_START
);
2267 if (netif_msg_tx_queued(skge
))
2268 printk(KERN_DEBUG
"%s: tx queued, slot %td, len %d\n",
2269 dev
->name
, e
- ring
->start
, skb
->len
);
2271 ring
->to_use
= e
->next
;
2272 skge
->tx_avail
-= skb_shinfo(skb
)->nr_frags
+ 1;
2273 if (skge
->tx_avail
<= MAX_SKB_FRAGS
+ 1) {
2274 pr_debug("%s: transmit queue full\n", dev
->name
);
2275 netif_stop_queue(dev
);
2278 dev
->trans_start
= jiffies
;
2279 spin_unlock_irqrestore(&skge
->tx_lock
, flags
);
2281 return NETDEV_TX_OK
;
2284 static inline void skge_tx_free(struct skge_hw
*hw
, struct skge_element
*e
)
2286 /* This ring element can be skb or fragment */
2288 pci_unmap_single(hw
->pdev
,
2289 pci_unmap_addr(e
, mapaddr
),
2290 pci_unmap_len(e
, maplen
),
2292 dev_kfree_skb_any(e
->skb
);
2295 pci_unmap_page(hw
->pdev
,
2296 pci_unmap_addr(e
, mapaddr
),
2297 pci_unmap_len(e
, maplen
),
2302 static void skge_tx_clean(struct skge_port
*skge
)
2304 struct skge_ring
*ring
= &skge
->tx_ring
;
2305 struct skge_element
*e
;
2306 unsigned long flags
;
2308 spin_lock_irqsave(&skge
->tx_lock
, flags
);
2309 for (e
= ring
->to_clean
; e
!= ring
->to_use
; e
= e
->next
) {
2311 skge_tx_free(skge
->hw
, e
);
2314 spin_unlock_irqrestore(&skge
->tx_lock
, flags
);
2317 static void skge_tx_timeout(struct net_device
*dev
)
2319 struct skge_port
*skge
= netdev_priv(dev
);
2321 if (netif_msg_timer(skge
))
2322 printk(KERN_DEBUG PFX
"%s: tx timeout\n", dev
->name
);
2324 skge_write8(skge
->hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_STOP
);
2325 skge_tx_clean(skge
);
2328 static int skge_change_mtu(struct net_device
*dev
, int new_mtu
)
2331 int running
= netif_running(dev
);
2333 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2346 static void genesis_set_multicast(struct net_device
*dev
)
2348 struct skge_port
*skge
= netdev_priv(dev
);
2349 struct skge_hw
*hw
= skge
->hw
;
2350 int port
= skge
->port
;
2351 int i
, count
= dev
->mc_count
;
2352 struct dev_mc_list
*list
= dev
->mc_list
;
2356 mode
= xm_read32(hw
, port
, XM_MODE
);
2357 mode
|= XM_MD_ENA_HASH
;
2358 if (dev
->flags
& IFF_PROMISC
)
2359 mode
|= XM_MD_ENA_PROM
;
2361 mode
&= ~XM_MD_ENA_PROM
;
2363 if (dev
->flags
& IFF_ALLMULTI
)
2364 memset(filter
, 0xff, sizeof(filter
));
2366 memset(filter
, 0, sizeof(filter
));
2367 for (i
= 0; list
&& i
< count
; i
++, list
= list
->next
) {
2369 crc
= ether_crc_le(ETH_ALEN
, list
->dmi_addr
);
2371 filter
[bit
/8] |= 1 << (bit
%8);
2375 xm_write32(hw
, port
, XM_MODE
, mode
);
2376 xm_outhash(hw
, port
, XM_HSM
, filter
);
2379 static void yukon_set_multicast(struct net_device
*dev
)
2381 struct skge_port
*skge
= netdev_priv(dev
);
2382 struct skge_hw
*hw
= skge
->hw
;
2383 int port
= skge
->port
;
2384 struct dev_mc_list
*list
= dev
->mc_list
;
2388 memset(filter
, 0, sizeof(filter
));
2390 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2391 reg
|= GM_RXCR_UCF_ENA
;
2393 if (dev
->flags
& IFF_PROMISC
) /* promiscious */
2394 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2395 else if (dev
->flags
& IFF_ALLMULTI
) /* all multicast */
2396 memset(filter
, 0xff, sizeof(filter
));
2397 else if (dev
->mc_count
== 0) /* no multicast */
2398 reg
&= ~GM_RXCR_MCF_ENA
;
2401 reg
|= GM_RXCR_MCF_ENA
;
2403 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2404 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2405 filter
[bit
/8] |= 1 << (bit
%8);
2410 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2411 (u16
)filter
[0] | ((u16
)filter
[1] << 8));
2412 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2413 (u16
)filter
[2] | ((u16
)filter
[3] << 8));
2414 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2415 (u16
)filter
[4] | ((u16
)filter
[5] << 8));
2416 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2417 (u16
)filter
[6] | ((u16
)filter
[7] << 8));
2419 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2422 static inline u16
phy_length(const struct skge_hw
*hw
, u32 status
)
2424 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2425 return status
>> XMR_FS_LEN_SHIFT
;
2427 return status
>> GMR_FS_LEN_SHIFT
;
2430 static inline int bad_phy_status(const struct skge_hw
*hw
, u32 status
)
2432 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2433 return (status
& (XMR_FS_ERR
| XMR_FS_2L_VLAN
)) != 0;
2435 return (status
& GMR_FS_ANY_ERR
) ||
2436 (status
& GMR_FS_RX_OK
) == 0;
2440 /* Get receive buffer from descriptor.
2441 * Handles copy of small buffers and reallocation failures
2443 static inline struct sk_buff
*skge_rx_get(struct skge_port
*skge
,
2444 struct skge_element
*e
,
2445 u32 control
, u32 status
, u16 csum
)
2447 struct sk_buff
*skb
;
2448 u16 len
= control
& BMU_BBC
;
2450 if (unlikely(netif_msg_rx_status(skge
)))
2451 printk(KERN_DEBUG PFX
"%s: rx slot %td status 0x%x len %d\n",
2452 skge
->netdev
->name
, e
- skge
->rx_ring
.start
,
2455 if (len
> skge
->rx_buf_size
)
2458 if ((control
& (BMU_EOF
|BMU_STF
)) != (BMU_STF
|BMU_EOF
))
2461 if (bad_phy_status(skge
->hw
, status
))
2464 if (phy_length(skge
->hw
, status
) != len
)
2467 if (len
< RX_COPY_THRESHOLD
) {
2468 skb
= dev_alloc_skb(len
+ 2);
2472 skb_reserve(skb
, 2);
2473 pci_dma_sync_single_for_cpu(skge
->hw
->pdev
,
2474 pci_unmap_addr(e
, mapaddr
),
2475 len
, PCI_DMA_FROMDEVICE
);
2476 memcpy(skb
->data
, e
->skb
->data
, len
);
2477 pci_dma_sync_single_for_device(skge
->hw
->pdev
,
2478 pci_unmap_addr(e
, mapaddr
),
2479 len
, PCI_DMA_FROMDEVICE
);
2480 skge_rx_reuse(e
, skge
->rx_buf_size
);
2482 struct sk_buff
*nskb
;
2483 nskb
= dev_alloc_skb(skge
->rx_buf_size
+ NET_IP_ALIGN
);
2487 pci_unmap_single(skge
->hw
->pdev
,
2488 pci_unmap_addr(e
, mapaddr
),
2489 pci_unmap_len(e
, maplen
),
2490 PCI_DMA_FROMDEVICE
);
2492 prefetch(skb
->data
);
2493 skge_rx_setup(skge
, e
, nskb
, skge
->rx_buf_size
);
2497 skb
->dev
= skge
->netdev
;
2498 if (skge
->rx_csum
) {
2500 skb
->ip_summed
= CHECKSUM_HW
;
2503 skb
->protocol
= eth_type_trans(skb
, skge
->netdev
);
2508 if (netif_msg_rx_err(skge
))
2509 printk(KERN_DEBUG PFX
"%s: rx err, slot %td control 0x%x status 0x%x\n",
2510 skge
->netdev
->name
, e
- skge
->rx_ring
.start
,
2513 if (skge
->hw
->chip_id
== CHIP_ID_GENESIS
) {
2514 if (status
& (XMR_FS_RUNT
|XMR_FS_LNG_ERR
))
2515 skge
->net_stats
.rx_length_errors
++;
2516 if (status
& XMR_FS_FRA_ERR
)
2517 skge
->net_stats
.rx_frame_errors
++;
2518 if (status
& XMR_FS_FCS_ERR
)
2519 skge
->net_stats
.rx_crc_errors
++;
2521 if (status
& (GMR_FS_LONG_ERR
|GMR_FS_UN_SIZE
))
2522 skge
->net_stats
.rx_length_errors
++;
2523 if (status
& GMR_FS_FRAGMENT
)
2524 skge
->net_stats
.rx_frame_errors
++;
2525 if (status
& GMR_FS_CRC_ERR
)
2526 skge
->net_stats
.rx_crc_errors
++;
2530 skge_rx_reuse(e
, skge
->rx_buf_size
);
2535 static int skge_poll(struct net_device
*dev
, int *budget
)
2537 struct skge_port
*skge
= netdev_priv(dev
);
2538 struct skge_hw
*hw
= skge
->hw
;
2539 struct skge_ring
*ring
= &skge
->rx_ring
;
2540 struct skge_element
*e
;
2541 unsigned int to_do
= min(dev
->quota
, *budget
);
2542 unsigned int work_done
= 0;
2544 for (e
= ring
->to_clean
; work_done
< to_do
; e
= e
->next
) {
2545 struct skge_rx_desc
*rd
= e
->desc
;
2546 struct sk_buff
*skb
;
2550 control
= rd
->control
;
2551 if (control
& BMU_OWN
)
2554 skb
= skge_rx_get(skge
, e
, control
, rd
->status
,
2555 le16_to_cpu(rd
->csum2
));
2557 dev
->last_rx
= jiffies
;
2558 netif_receive_skb(skb
);
2562 skge_rx_reuse(e
, skge
->rx_buf_size
);
2566 /* restart receiver */
2568 skge_write8(hw
, Q_ADDR(rxqaddr
[skge
->port
], Q_CSR
),
2569 CSR_START
| CSR_IRQ_CL_F
);
2571 *budget
-= work_done
;
2572 dev
->quota
-= work_done
;
2574 if (work_done
>= to_do
)
2575 return 1; /* not done */
2577 local_irq_disable();
2578 __netif_rx_complete(dev
);
2579 hw
->intr_mask
|= portirqmask
[skge
->port
];
2580 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2585 static inline void skge_tx_intr(struct net_device
*dev
)
2587 struct skge_port
*skge
= netdev_priv(dev
);
2588 struct skge_hw
*hw
= skge
->hw
;
2589 struct skge_ring
*ring
= &skge
->tx_ring
;
2590 struct skge_element
*e
;
2592 spin_lock(&skge
->tx_lock
);
2593 for (e
= ring
->to_clean
; e
!= ring
->to_use
; e
= e
->next
) {
2594 struct skge_tx_desc
*td
= e
->desc
;
2598 control
= td
->control
;
2599 if (control
& BMU_OWN
)
2602 if (unlikely(netif_msg_tx_done(skge
)))
2603 printk(KERN_DEBUG PFX
"%s: tx done slot %td status 0x%x\n",
2604 dev
->name
, e
- ring
->start
, td
->status
);
2606 skge_tx_free(hw
, e
);
2611 skge_write8(hw
, Q_ADDR(txqaddr
[skge
->port
], Q_CSR
), CSR_IRQ_CL_F
);
2613 if (skge
->tx_avail
> MAX_SKB_FRAGS
+ 1)
2614 netif_wake_queue(dev
);
2616 spin_unlock(&skge
->tx_lock
);
2619 /* Parity errors seem to happen when Genesis is connected to a switch
2620 * with no other ports present. Heartbeat error??
2622 static void skge_mac_parity(struct skge_hw
*hw
, int port
)
2624 struct net_device
*dev
= hw
->dev
[port
];
2627 struct skge_port
*skge
= netdev_priv(dev
);
2628 ++skge
->net_stats
.tx_heartbeat_errors
;
2631 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2632 skge_write16(hw
, SK_REG(port
, TX_MFF_CTRL1
),
2635 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2636 skge_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
2637 (hw
->chip_id
== CHIP_ID_YUKON
&& hw
->chip_rev
== 0)
2638 ? GMF_CLI_TX_FC
: GMF_CLI_TX_PE
);
2641 static void skge_pci_clear(struct skge_hw
*hw
)
2645 pci_read_config_word(hw
->pdev
, PCI_STATUS
, &status
);
2646 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2647 pci_write_config_word(hw
->pdev
, PCI_STATUS
,
2648 status
| PCI_STATUS_ERROR_BITS
);
2649 skge_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2652 static void skge_mac_intr(struct skge_hw
*hw
, int port
)
2654 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2655 genesis_mac_intr(hw
, port
);
2657 yukon_mac_intr(hw
, port
);
2660 /* Handle device specific framing and timeout interrupts */
2661 static void skge_error_irq(struct skge_hw
*hw
)
2663 u32 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
2665 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2666 /* clear xmac errors */
2667 if (hwstatus
& (IS_NO_STAT_M1
|IS_NO_TIST_M1
))
2668 skge_write16(hw
, RX_MFF_CTRL1
, MFF_CLR_INSTAT
);
2669 if (hwstatus
& (IS_NO_STAT_M2
|IS_NO_TIST_M2
))
2670 skge_write16(hw
, RX_MFF_CTRL2
, MFF_CLR_INSTAT
);
2672 /* Timestamp (unused) overflow */
2673 if (hwstatus
& IS_IRQ_TIST_OV
)
2674 skge_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2677 if (hwstatus
& IS_RAM_RD_PAR
) {
2678 printk(KERN_ERR PFX
"Ram read data parity error\n");
2679 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_RD_PERR
);
2682 if (hwstatus
& IS_RAM_WR_PAR
) {
2683 printk(KERN_ERR PFX
"Ram write data parity error\n");
2684 skge_write16(hw
, B3_RI_CTRL
, RI_CLR_WR_PERR
);
2687 if (hwstatus
& IS_M1_PAR_ERR
)
2688 skge_mac_parity(hw
, 0);
2690 if (hwstatus
& IS_M2_PAR_ERR
)
2691 skge_mac_parity(hw
, 1);
2693 if (hwstatus
& IS_R1_PAR_ERR
)
2694 skge_write32(hw
, B0_R1_CSR
, CSR_IRQ_CL_P
);
2696 if (hwstatus
& IS_R2_PAR_ERR
)
2697 skge_write32(hw
, B0_R2_CSR
, CSR_IRQ_CL_P
);
2699 if (hwstatus
& (IS_IRQ_MST_ERR
|IS_IRQ_STAT
)) {
2700 printk(KERN_ERR PFX
"hardware error detected (status 0x%x)\n",
2705 /* if error still set then just ignore it */
2706 hwstatus
= skge_read32(hw
, B0_HWE_ISRC
);
2707 if (hwstatus
& IS_IRQ_STAT
) {
2708 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2710 hw
->intr_mask
&= ~IS_HW_ERR
;
2716 * Interrrupt from PHY are handled in tasklet (soft irq)
2717 * because accessing phy registers requires spin wait which might
2718 * cause excess interrupt latency.
2720 static void skge_extirq(unsigned long data
)
2722 struct skge_hw
*hw
= (struct skge_hw
*) data
;
2725 spin_lock(&hw
->phy_lock
);
2726 for (port
= 0; port
< 2; port
++) {
2727 struct net_device
*dev
= hw
->dev
[port
];
2729 if (dev
&& netif_running(dev
)) {
2730 struct skge_port
*skge
= netdev_priv(dev
);
2732 if (hw
->chip_id
!= CHIP_ID_GENESIS
)
2733 yukon_phy_intr(skge
);
2735 bcom_phy_intr(skge
);
2738 spin_unlock(&hw
->phy_lock
);
2740 local_irq_disable();
2741 hw
->intr_mask
|= IS_EXT_REG
;
2742 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2746 static irqreturn_t
skge_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2748 struct skge_hw
*hw
= dev_id
;
2749 u32 status
= skge_read32(hw
, B0_SP_ISRC
);
2751 if (status
== 0 || status
== ~0) /* hotplug or shared irq */
2754 status
&= hw
->intr_mask
;
2755 if (status
& IS_R1_F
) {
2756 hw
->intr_mask
&= ~IS_R1_F
;
2757 netif_rx_schedule(hw
->dev
[0]);
2760 if (status
& IS_R2_F
) {
2761 hw
->intr_mask
&= ~IS_R2_F
;
2762 netif_rx_schedule(hw
->dev
[1]);
2765 if (status
& IS_XA1_F
)
2766 skge_tx_intr(hw
->dev
[0]);
2768 if (status
& IS_XA2_F
)
2769 skge_tx_intr(hw
->dev
[1]);
2771 if (status
& IS_PA_TO_RX1
) {
2772 struct skge_port
*skge
= netdev_priv(hw
->dev
[0]);
2773 ++skge
->net_stats
.rx_over_errors
;
2774 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX1
);
2777 if (status
& IS_PA_TO_RX2
) {
2778 struct skge_port
*skge
= netdev_priv(hw
->dev
[1]);
2779 ++skge
->net_stats
.rx_over_errors
;
2780 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_RX2
);
2783 if (status
& IS_PA_TO_TX1
)
2784 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX1
);
2786 if (status
& IS_PA_TO_TX2
)
2787 skge_write16(hw
, B3_PA_CTRL
, PA_CLR_TO_TX2
);
2789 if (status
& IS_MAC1
)
2790 skge_mac_intr(hw
, 0);
2792 if (status
& IS_MAC2
)
2793 skge_mac_intr(hw
, 1);
2795 if (status
& IS_HW_ERR
)
2798 if (status
& IS_EXT_REG
) {
2799 hw
->intr_mask
&= ~IS_EXT_REG
;
2800 tasklet_schedule(&hw
->ext_tasklet
);
2803 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2808 #ifdef CONFIG_NET_POLL_CONTROLLER
2809 static void skge_netpoll(struct net_device
*dev
)
2811 struct skge_port
*skge
= netdev_priv(dev
);
2813 disable_irq(dev
->irq
);
2814 skge_intr(dev
->irq
, skge
->hw
, NULL
);
2815 enable_irq(dev
->irq
);
2819 static int skge_set_mac_address(struct net_device
*dev
, void *p
)
2821 struct skge_port
*skge
= netdev_priv(dev
);
2822 struct sockaddr
*addr
= p
;
2825 if (!is_valid_ether_addr(addr
->sa_data
))
2826 return -EADDRNOTAVAIL
;
2829 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2830 memcpy_toio(skge
->hw
->regs
+ B2_MAC_1
+ skge
->port
*8,
2831 dev
->dev_addr
, ETH_ALEN
);
2832 memcpy_toio(skge
->hw
->regs
+ B2_MAC_2
+ skge
->port
*8,
2833 dev
->dev_addr
, ETH_ALEN
);
2834 if (dev
->flags
& IFF_UP
)
2839 static const struct {
2843 { CHIP_ID_GENESIS
, "Genesis" },
2844 { CHIP_ID_YUKON
, "Yukon" },
2845 { CHIP_ID_YUKON_LITE
, "Yukon-Lite"},
2846 { CHIP_ID_YUKON_LP
, "Yukon-LP"},
2849 static const char *skge_board_name(const struct skge_hw
*hw
)
2852 static char buf
[16];
2854 for (i
= 0; i
< ARRAY_SIZE(skge_chips
); i
++)
2855 if (skge_chips
[i
].id
== hw
->chip_id
)
2856 return skge_chips
[i
].name
;
2858 snprintf(buf
, sizeof buf
, "chipid 0x%x", hw
->chip_id
);
2864 * Setup the board data structure, but don't bring up
2867 static int skge_reset(struct skge_hw
*hw
)
2870 u8 t8
, mac_cfg
, pmd_type
, phy_type
;
2873 ctst
= skge_read16(hw
, B0_CTST
);
2876 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
2877 skge_write8(hw
, B0_CTST
, CS_RST_CLR
);
2879 /* clear PCI errors, if any */
2882 skge_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2884 /* restore CLK_RUN bits (for Yukon-Lite) */
2885 skge_write16(hw
, B0_CTST
,
2886 ctst
& (CS_CLK_RUN_HOT
|CS_CLK_RUN_RST
|CS_CLK_RUN_ENA
));
2888 hw
->chip_id
= skge_read8(hw
, B2_CHIP_ID
);
2889 phy_type
= skge_read8(hw
, B2_E_1
) & 0xf;
2890 pmd_type
= skge_read8(hw
, B2_PMD_TYP
);
2891 hw
->copper
= (pmd_type
== 'T' || pmd_type
== '1');
2893 switch (hw
->chip_id
) {
2894 case CHIP_ID_GENESIS
:
2897 hw
->phy_addr
= PHY_ADDR_BCOM
;
2900 printk(KERN_ERR PFX
"%s: unsupported phy type 0x%x\n",
2901 pci_name(hw
->pdev
), phy_type
);
2907 case CHIP_ID_YUKON_LITE
:
2908 case CHIP_ID_YUKON_LP
:
2909 if (phy_type
< SK_PHY_MARV_COPPER
&& pmd_type
!= 'S')
2912 hw
->phy_addr
= PHY_ADDR_MARV
;
2916 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2917 pci_name(hw
->pdev
), hw
->chip_id
);
2921 mac_cfg
= skge_read8(hw
, B2_MAC_CFG
);
2922 hw
->ports
= (mac_cfg
& CFG_SNG_MAC
) ? 1 : 2;
2923 hw
->chip_rev
= (mac_cfg
& CFG_CHIP_R_MSK
) >> 4;
2925 /* read the adapters RAM size */
2926 t8
= skge_read8(hw
, B2_E_0
);
2927 if (hw
->chip_id
== CHIP_ID_GENESIS
) {
2929 /* special case: 4 x 64k x 36, offset = 0x80000 */
2930 hw
->ram_size
= 0x100000;
2931 hw
->ram_offset
= 0x80000;
2933 hw
->ram_size
= t8
* 512;
2936 hw
->ram_size
= 0x20000;
2938 hw
->ram_size
= t8
* 4096;
2940 hw
->intr_mask
= IS_HW_ERR
| IS_EXT_REG
;
2941 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2944 /* switch power to VCC (WA for VAUX problem) */
2945 skge_write8(hw
, B0_POWER_CTRL
,
2946 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
2947 /* avoid boards with stuck Hardware error bits */
2948 if ((skge_read32(hw
, B0_ISRC
) & IS_HW_ERR
) &&
2949 (skge_read32(hw
, B0_HWE_ISRC
) & IS_IRQ_SENSOR
)) {
2950 printk(KERN_WARNING PFX
"stuck hardware sensor bit\n");
2951 hw
->intr_mask
&= ~IS_HW_ERR
;
2954 for (i
= 0; i
< hw
->ports
; i
++) {
2955 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2956 skge_write16(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2960 /* turn off hardware timer (unused) */
2961 skge_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2962 skge_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2963 skge_write8(hw
, B0_LED
, LED_STAT_ON
);
2965 /* enable the Tx Arbiters */
2966 for (i
= 0; i
< hw
->ports
; i
++)
2967 skge_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2969 /* Initialize ram interface */
2970 skge_write16(hw
, B3_RI_CTRL
, RI_RST_CLR
);
2972 skge_write8(hw
, B3_RI_WTO_R1
, SK_RI_TO_53
);
2973 skge_write8(hw
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
2974 skge_write8(hw
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
2975 skge_write8(hw
, B3_RI_RTO_R1
, SK_RI_TO_53
);
2976 skge_write8(hw
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
2977 skge_write8(hw
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
2978 skge_write8(hw
, B3_RI_WTO_R2
, SK_RI_TO_53
);
2979 skge_write8(hw
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
2980 skge_write8(hw
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
2981 skge_write8(hw
, B3_RI_RTO_R2
, SK_RI_TO_53
);
2982 skge_write8(hw
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
2983 skge_write8(hw
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
2985 skge_write32(hw
, B0_HWE_IMSK
, IS_ERR_MSK
);
2987 /* Set interrupt moderation for Transmit only
2988 * Receive interrupts avoided by NAPI
2990 skge_write32(hw
, B2_IRQM_MSK
, IS_XA1_F
|IS_XA2_F
);
2991 skge_write32(hw
, B2_IRQM_INI
, skge_usecs2clk(hw
, 100));
2992 skge_write32(hw
, B2_IRQM_CTRL
, TIM_START
);
2994 skge_write32(hw
, B0_IMSK
, hw
->intr_mask
);
2996 spin_lock_bh(&hw
->phy_lock
);
2997 for (i
= 0; i
< hw
->ports
; i
++) {
2998 if (hw
->chip_id
== CHIP_ID_GENESIS
)
2999 genesis_reset(hw
, i
);
3003 spin_unlock_bh(&hw
->phy_lock
);
3008 /* Initialize network device */
3009 static struct net_device
*skge_devinit(struct skge_hw
*hw
, int port
,
3012 struct skge_port
*skge
;
3013 struct net_device
*dev
= alloc_etherdev(sizeof(*skge
));
3016 printk(KERN_ERR
"skge etherdev alloc failed");
3020 SET_MODULE_OWNER(dev
);
3021 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3022 dev
->open
= skge_up
;
3023 dev
->stop
= skge_down
;
3024 dev
->hard_start_xmit
= skge_xmit_frame
;
3025 dev
->get_stats
= skge_get_stats
;
3026 if (hw
->chip_id
== CHIP_ID_GENESIS
)
3027 dev
->set_multicast_list
= genesis_set_multicast
;
3029 dev
->set_multicast_list
= yukon_set_multicast
;
3031 dev
->set_mac_address
= skge_set_mac_address
;
3032 dev
->change_mtu
= skge_change_mtu
;
3033 SET_ETHTOOL_OPS(dev
, &skge_ethtool_ops
);
3034 dev
->tx_timeout
= skge_tx_timeout
;
3035 dev
->watchdog_timeo
= TX_WATCHDOG
;
3036 dev
->poll
= skge_poll
;
3037 dev
->weight
= NAPI_WEIGHT
;
3038 #ifdef CONFIG_NET_POLL_CONTROLLER
3039 dev
->poll_controller
= skge_netpoll
;
3041 dev
->irq
= hw
->pdev
->irq
;
3042 dev
->features
= NETIF_F_LLTX
;
3044 dev
->features
|= NETIF_F_HIGHDMA
;
3046 skge
= netdev_priv(dev
);
3049 skge
->msg_enable
= netif_msg_init(debug
, default_msg
);
3050 skge
->tx_ring
.count
= DEFAULT_TX_RING_SIZE
;
3051 skge
->rx_ring
.count
= DEFAULT_RX_RING_SIZE
;
3053 /* Auto speed and flow control */
3054 skge
->autoneg
= AUTONEG_ENABLE
;
3055 skge
->flow_control
= FLOW_MODE_SYMMETRIC
;
3058 skge
->advertising
= skge_supported_modes(hw
);
3060 hw
->dev
[port
] = dev
;
3064 spin_lock_init(&skge
->tx_lock
);
3066 if (hw
->chip_id
!= CHIP_ID_GENESIS
) {
3067 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3071 /* read the mac address */
3072 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
*8, ETH_ALEN
);
3074 /* device is off until link detection */
3075 netif_carrier_off(dev
);
3076 netif_stop_queue(dev
);
3081 static void __devinit
skge_show_addr(struct net_device
*dev
)
3083 const struct skge_port
*skge
= netdev_priv(dev
);
3085 if (netif_msg_probe(skge
))
3086 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3088 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3089 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3092 static int __devinit
skge_probe(struct pci_dev
*pdev
,
3093 const struct pci_device_id
*ent
)
3095 struct net_device
*dev
, *dev1
;
3097 int err
, using_dac
= 0;
3099 if ((err
= pci_enable_device(pdev
))) {
3100 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3105 if ((err
= pci_request_regions(pdev
, DRV_NAME
))) {
3106 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3108 goto err_out_disable_pdev
;
3111 pci_set_master(pdev
);
3113 if (!(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)))
3115 else if (!(err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
))) {
3116 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3118 goto err_out_free_regions
;
3122 /* byte swap decriptors in hardware */
3126 pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
3127 reg
|= PCI_REV_DESC
;
3128 pci_write_config_dword(pdev
, PCI_DEV_REG2
, reg
);
3133 hw
= kmalloc(sizeof(*hw
), GFP_KERNEL
);
3135 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3137 goto err_out_free_regions
;
3140 memset(hw
, 0, sizeof(*hw
));
3142 spin_lock_init(&hw
->phy_lock
);
3143 tasklet_init(&hw
->ext_tasklet
, skge_extirq
, (unsigned long) hw
);
3145 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3147 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3149 goto err_out_free_hw
;
3152 if ((err
= request_irq(pdev
->irq
, skge_intr
, SA_SHIRQ
, DRV_NAME
, hw
))) {
3153 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3154 pci_name(pdev
), pdev
->irq
);
3155 goto err_out_iounmap
;
3157 pci_set_drvdata(pdev
, hw
);
3159 err
= skge_reset(hw
);
3161 goto err_out_free_irq
;
3163 printk(KERN_INFO PFX
"addr 0x%lx irq %d chip %s rev %d\n",
3164 pci_resource_start(pdev
, 0), pdev
->irq
,
3165 skge_board_name(hw
), hw
->chip_rev
);
3167 if ((dev
= skge_devinit(hw
, 0, using_dac
)) == NULL
)
3168 goto err_out_led_off
;
3170 if ((err
= register_netdev(dev
))) {
3171 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3173 goto err_out_free_netdev
;
3176 skge_show_addr(dev
);
3178 if (hw
->ports
> 1 && (dev1
= skge_devinit(hw
, 1, using_dac
))) {
3179 if (register_netdev(dev1
) == 0)
3180 skge_show_addr(dev1
);
3182 /* Failure to register second port need not be fatal */
3183 printk(KERN_WARNING PFX
"register of second port failed\n");
3191 err_out_free_netdev
:
3194 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3196 free_irq(pdev
->irq
, hw
);
3201 err_out_free_regions
:
3202 pci_release_regions(pdev
);
3203 err_out_disable_pdev
:
3204 pci_disable_device(pdev
);
3205 pci_set_drvdata(pdev
, NULL
);
3210 static void __devexit
skge_remove(struct pci_dev
*pdev
)
3212 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3213 struct net_device
*dev0
, *dev1
;
3218 if ((dev1
= hw
->dev
[1]))
3219 unregister_netdev(dev1
);
3221 unregister_netdev(dev0
);
3223 skge_write32(hw
, B0_IMSK
, 0);
3224 skge_write16(hw
, B0_LED
, LED_STAT_OFF
);
3226 skge_write8(hw
, B0_CTST
, CS_RST_SET
);
3228 tasklet_kill(&hw
->ext_tasklet
);
3230 free_irq(pdev
->irq
, hw
);
3231 pci_release_regions(pdev
);
3232 pci_disable_device(pdev
);
3239 pci_set_drvdata(pdev
, NULL
);
3243 static int skge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3245 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3248 for (i
= 0; i
< 2; i
++) {
3249 struct net_device
*dev
= hw
->dev
[i
];
3252 struct skge_port
*skge
= netdev_priv(dev
);
3253 if (netif_running(dev
)) {
3254 netif_carrier_off(dev
);
3256 netif_stop_queue(dev
);
3260 netif_device_detach(dev
);
3265 pci_save_state(pdev
);
3266 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
3267 pci_disable_device(pdev
);
3268 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3273 static int skge_resume(struct pci_dev
*pdev
)
3275 struct skge_hw
*hw
= pci_get_drvdata(pdev
);
3278 pci_set_power_state(pdev
, PCI_D0
);
3279 pci_restore_state(pdev
);
3280 pci_enable_wake(pdev
, PCI_D0
, 0);
3284 for (i
= 0; i
< 2; i
++) {
3285 struct net_device
*dev
= hw
->dev
[i
];
3287 netif_device_attach(dev
);
3288 if (netif_running(dev
))
3296 static struct pci_driver skge_driver
= {
3298 .id_table
= skge_id_table
,
3299 .probe
= skge_probe
,
3300 .remove
= __devexit_p(skge_remove
),
3302 .suspend
= skge_suspend
,
3303 .resume
= skge_resume
,
3307 static int __init
skge_init_module(void)
3309 return pci_module_init(&skge_driver
);
3312 static void __exit
skge_cleanup_module(void)
3314 pci_unregister_driver(&skge_driver
);
3317 module_init(skge_init_module
);
3318 module_exit(skge_cleanup_module
);