2 * AMD CPU Microcode Update Driver for Linux
3 * Copyright (C) 2008 Advanced Micro Devices Inc.
5 * Author: Peter Oruba <peter.oruba@amd.com>
8 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
10 * This driver allows to upgrade microcode on AMD
11 * family 0x10 and 0x11 processors.
13 * Licensed unter the terms of the GNU General Public
14 * License version 2. See file COPYING for details.
17 #include <linux/capability.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/cpumask.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/vmalloc.h>
25 #include <linux/miscdevice.h>
26 #include <linux/spinlock.h>
29 #include <linux/mutex.h>
30 #include <linux/cpu.h>
31 #include <linux/firmware.h>
32 #include <linux/platform_device.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
37 #include <asm/uaccess.h>
38 #include <asm/processor.h>
39 #include <asm/microcode.h>
41 MODULE_DESCRIPTION("AMD Microcode Update Driver");
42 MODULE_AUTHOR("Peter Oruba");
43 MODULE_LICENSE("GPL v2");
45 #define UCODE_MAGIC 0x00414d44
46 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
47 #define UCODE_UCODE_TYPE 0x00000001
49 struct equiv_cpu_entry
{
50 unsigned int installed_cpu
;
51 unsigned int fixed_errata_mask
;
52 unsigned int fixed_errata_compare
;
53 unsigned int equiv_cpu
;
56 struct microcode_header_amd
{
57 unsigned int data_code
;
58 unsigned int patch_id
;
59 unsigned char mc_patch_data_id
[2];
60 unsigned char mc_patch_data_len
;
61 unsigned char init_flag
;
62 unsigned int mc_patch_data_checksum
;
63 unsigned int nb_dev_id
;
64 unsigned int sb_dev_id
;
65 unsigned char processor_rev_id
[2];
66 unsigned char nb_rev_id
;
67 unsigned char sb_rev_id
;
68 unsigned char bios_api_rev
;
69 unsigned char reserved1
[3];
70 unsigned int match_reg
[8];
73 struct microcode_amd
{
74 struct microcode_header_amd hdr
;
78 #define UCODE_MAX_SIZE (2048)
79 #define DEFAULT_UCODE_DATASIZE (896)
80 #define MC_HEADER_SIZE (sizeof(struct microcode_header_amd))
81 #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
82 #define DWSIZE (sizeof(u32))
83 /* For now we support a fixed ucode total size only */
84 #define get_totalsize(mc) \
85 ((((struct microcode_amd *)mc)->hdr.mc_patch_data_len * 28) \
88 /* serialize access to the physical write */
89 static DEFINE_SPINLOCK(microcode_update_lock
);
91 static struct equiv_cpu_entry
*equiv_cpu_table
;
93 static int collect_cpu_info_amd(int cpu
, struct cpu_signature
*csig
)
95 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
97 memset(csig
, 0, sizeof(*csig
));
99 if (c
->x86_vendor
!= X86_VENDOR_AMD
|| c
->x86
< 0x10) {
100 printk(KERN_ERR
"microcode: CPU%d not a capable AMD processor\n",
105 asm volatile("movl %1, %%ecx; rdmsr"
107 : "i" (0x0000008B) : "ecx");
109 printk(KERN_INFO
"microcode: collect_cpu_info_amd : patch_id=0x%x\n",
115 static int get_matching_microcode(int cpu
, void *mc
, int rev
)
117 struct microcode_header_amd
*mc_header
= mc
;
118 struct pci_dev
*nb_pci_dev
, *sb_pci_dev
;
119 unsigned int current_cpu_id
;
120 unsigned int equiv_cpu_id
= 0x00;
123 BUG_ON(equiv_cpu_table
== NULL
);
124 current_cpu_id
= cpuid_eax(0x00000001);
126 while (equiv_cpu_table
[i
].installed_cpu
!= 0) {
127 if (current_cpu_id
== equiv_cpu_table
[i
].installed_cpu
) {
128 equiv_cpu_id
= equiv_cpu_table
[i
].equiv_cpu
;
135 printk(KERN_ERR
"microcode: CPU%d cpu_id "
136 "not found in equivalent cpu table \n", cpu
);
140 if ((mc_header
->processor_rev_id
[0]) != (equiv_cpu_id
& 0xff)) {
142 "microcode: CPU%d patch does not match "
143 "(patch is %x, cpu extended is %x) \n",
144 cpu
, mc_header
->processor_rev_id
[0],
145 (equiv_cpu_id
& 0xff));
149 if ((mc_header
->processor_rev_id
[1]) != ((equiv_cpu_id
>> 16) & 0xff)) {
150 printk(KERN_ERR
"microcode: CPU%d patch does not match "
151 "(patch is %x, cpu base id is %x) \n",
152 cpu
, mc_header
->processor_rev_id
[1],
153 ((equiv_cpu_id
>> 16) & 0xff));
158 /* ucode may be northbridge specific */
159 if (mc_header
->nb_dev_id
) {
160 nb_pci_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
161 (mc_header
->nb_dev_id
& 0xff),
164 (mc_header
->nb_rev_id
!= nb_pci_dev
->revision
)) {
165 printk(KERN_ERR
"microcode: CPU%d NB mismatch \n", cpu
);
166 pci_dev_put(nb_pci_dev
);
169 pci_dev_put(nb_pci_dev
);
172 /* ucode may be southbridge specific */
173 if (mc_header
->sb_dev_id
) {
174 sb_pci_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
175 (mc_header
->sb_dev_id
& 0xff),
178 (mc_header
->sb_rev_id
!= sb_pci_dev
->revision
)) {
179 printk(KERN_ERR
"microcode: CPU%d SB mismatch \n", cpu
);
180 pci_dev_put(sb_pci_dev
);
183 pci_dev_put(sb_pci_dev
);
186 if (mc_header
->patch_id
<= rev
)
192 static void apply_microcode_amd(int cpu
)
195 unsigned int eax
, edx
;
197 int cpu_num
= raw_smp_processor_id();
198 struct ucode_cpu_info
*uci
= ucode_cpu_info
+ cpu_num
;
199 struct microcode_amd
*mc_amd
= uci
->mc
;
202 /* We should bind the task to the CPU */
203 BUG_ON(cpu_num
!= cpu
);
208 spin_lock_irqsave(µcode_update_lock
, flags
);
210 addr
= (unsigned long)&mc_amd
->hdr
.data_code
;
211 edx
= (unsigned int)(((unsigned long)upper_32_bits(addr
)));
212 eax
= (unsigned int)(((unsigned long)lower_32_bits(addr
)));
214 asm volatile("movl %0, %%ecx; wrmsr" :
215 : "i" (0xc0010020), "a" (eax
), "d" (edx
) : "ecx");
217 /* get patch id after patching */
218 asm volatile("movl %1, %%ecx; rdmsr"
220 : "i" (0x0000008B) : "ecx");
222 spin_unlock_irqrestore(µcode_update_lock
, flags
);
224 /* check current patch id and patch's id for match */
225 if (rev
!= mc_amd
->hdr
.patch_id
) {
226 printk(KERN_ERR
"microcode: CPU%d update from revision "
227 "0x%x to 0x%x failed\n", cpu_num
,
228 mc_amd
->hdr
.patch_id
, rev
);
232 printk(KERN_INFO
"microcode: CPU%d updated from revision "
234 cpu_num
, uci
->cpu_sig
.rev
, mc_amd
->hdr
.patch_id
);
236 uci
->cpu_sig
.rev
= rev
;
239 static void * get_next_ucode(u8
*buf
, unsigned int size
,
240 int (*get_ucode_data
)(void *, const void *, size_t),
241 unsigned int *mc_size
)
243 unsigned int total_size
;
244 #define UCODE_CONTAINER_SECTION_HDR 8
245 u8 section_hdr
[UCODE_CONTAINER_SECTION_HDR
];
248 if (get_ucode_data(section_hdr
, buf
, UCODE_CONTAINER_SECTION_HDR
))
251 if (section_hdr
[0] != UCODE_UCODE_TYPE
) {
252 printk(KERN_ERR
"microcode: error! "
253 "Wrong microcode payload type field\n");
257 total_size
= (unsigned long) (section_hdr
[4] + (section_hdr
[5] << 8));
259 printk(KERN_INFO
"microcode: size %u, total_size %u\n",
262 if (total_size
> size
|| total_size
> UCODE_MAX_SIZE
) {
263 printk(KERN_ERR
"microcode: error! Bad data in microcode data file\n");
267 mc
= vmalloc(UCODE_MAX_SIZE
);
269 memset(mc
, 0, UCODE_MAX_SIZE
);
270 if (get_ucode_data(mc
, buf
+ UCODE_CONTAINER_SECTION_HDR
, total_size
)) {
274 *mc_size
= total_size
+ UCODE_CONTAINER_SECTION_HDR
;
276 #undef UCODE_CONTAINER_SECTION_HDR
281 static int install_equiv_cpu_table(u8
*buf
,
282 int (*get_ucode_data
)(void *, const void *, size_t))
284 #define UCODE_CONTAINER_HEADER_SIZE 12
285 u8
*container_hdr
[UCODE_CONTAINER_HEADER_SIZE
];
286 unsigned int *buf_pos
= (unsigned int *)container_hdr
;
289 if (get_ucode_data(&container_hdr
, buf
, UCODE_CONTAINER_HEADER_SIZE
))
294 if (buf_pos
[1] != UCODE_EQUIV_CPU_TABLE_TYPE
|| !size
) {
295 printk(KERN_ERR
"microcode: error! "
296 "Wrong microcode equivalnet cpu table\n");
300 equiv_cpu_table
= (struct equiv_cpu_entry
*) vmalloc(size
);
301 if (!equiv_cpu_table
) {
302 printk(KERN_ERR
"microcode: error, can't allocate memory for equiv CPU table\n");
306 buf
+= UCODE_CONTAINER_HEADER_SIZE
;
307 if (get_ucode_data(equiv_cpu_table
, buf
, size
)) {
308 vfree(equiv_cpu_table
);
312 return size
+ UCODE_CONTAINER_HEADER_SIZE
; /* add header length */
313 #undef UCODE_CONTAINER_HEADER_SIZE
316 static void free_equiv_cpu_table(void)
318 if (equiv_cpu_table
) {
319 vfree(equiv_cpu_table
);
320 equiv_cpu_table
= NULL
;
324 static int generic_load_microcode(int cpu
, void *data
, size_t size
,
325 int (*get_ucode_data
)(void *, const void *, size_t))
327 struct ucode_cpu_info
*uci
= ucode_cpu_info
+ cpu
;
328 u8
*ucode_ptr
= data
, *new_mc
= NULL
, *mc
;
329 int new_rev
= uci
->cpu_sig
.rev
;
330 unsigned int leftover
;
331 unsigned long offset
;
333 offset
= install_equiv_cpu_table(ucode_ptr
, get_ucode_data
);
335 printk(KERN_ERR
"microcode: installing equivalent cpu table failed\n");
340 leftover
= size
- offset
;
343 unsigned int uninitialized_var(mc_size
);
344 struct microcode_header_amd
*mc_header
;
346 mc
= get_next_ucode(ucode_ptr
, leftover
, get_ucode_data
, &mc_size
);
350 mc_header
= (struct microcode_header_amd
*)mc
;
351 if (get_matching_microcode(cpu
, mc
, new_rev
)) {
354 new_rev
= mc_header
->patch_id
;
359 ucode_ptr
+= mc_size
;
368 pr_debug("microcode: CPU%d found a matching microcode update with"
369 " version 0x%x (current=0x%x)\n",
370 cpu
, new_rev
, uci
->cpu_sig
.rev
);
375 free_equiv_cpu_table();
377 return (int)leftover
;
380 static int get_ucode_fw(void *to
, const void *from
, size_t n
)
386 static int request_microcode_fw(int cpu
, struct device
*device
)
388 const char *fw_name
= "amd-ucode/microcode_amd.bin";
389 const struct firmware
*firmware
;
392 /* We should bind the task to the CPU */
393 BUG_ON(cpu
!= raw_smp_processor_id());
395 ret
= request_firmware(&firmware
, fw_name
, device
);
397 printk(KERN_ERR
"microcode: ucode data file %s load failed\n", fw_name
);
401 ret
= generic_load_microcode(cpu
, (void*)firmware
->data
, firmware
->size
,
404 release_firmware(firmware
);
409 static int request_microcode_user(int cpu
, const void __user
*buf
, size_t size
)
411 printk(KERN_WARNING
"microcode: AMD microcode update via /dev/cpu/microcode"
412 "is not supported\n");
416 static void microcode_fini_cpu_amd(int cpu
)
418 struct ucode_cpu_info
*uci
= ucode_cpu_info
+ cpu
;
424 static struct microcode_ops microcode_amd_ops
= {
425 .request_microcode_user
= request_microcode_user
,
426 .request_microcode_fw
= request_microcode_fw
,
427 .collect_cpu_info
= collect_cpu_info_amd
,
428 .apply_microcode
= apply_microcode_amd
,
429 .microcode_fini_cpu
= microcode_fini_cpu_amd
,
432 struct microcode_ops
* __init
init_amd_microcode(void)
434 return µcode_amd_ops
;