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[PATCH] skge: cleanup ethtool mode support
[linux-2.6/zen-sources.git] / drivers / net / skge.c
blob81b8fe9581c7144c08fb6c41f2903e858cd048a8
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "0.6"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define PHY_RETRIES 1000
53 #define ETH_JUMBO_MTU 9000
54 #define TX_WATCHDOG (5 * HZ)
55 #define NAPI_WEIGHT 64
56 #define BLINK_HZ (HZ/4)
57 #define LINK_POLL_HZ (HZ/10)
58
59 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
61 MODULE_LICENSE("GPL");
62 MODULE_VERSION(DRV_VERSION);
63
64 static const u32 default_msg
65 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
66 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
67
68 static int debug = -1; /* defaults above */
69 module_param(debug, int, 0);
70 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72 static const struct pci_device_id skge_id_table[] = {
73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
75 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
84 { 0 }
85 };
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99
100 static const int txqaddr[] = { Q_XA1, Q_XA2 };
101 static const int rxqaddr[] = { Q_R1, Q_R2 };
102 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
103 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
104
105 /* Don't need to look at whole 16K.
106 * last interesting register is descriptor poll timer.
107 */
108 #define SKGE_REGS_LEN (29*128)
109
110 static int skge_get_regs_len(struct net_device *dev)
111 {
112 return SKGE_REGS_LEN;
113 }
114
115 /*
116 * Returns copy of control register region
117 * I/O region is divided into banks and certain regions are unreadable
118 */
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121 {
122 const struct skge_port *skge = netdev_priv(dev);
123 unsigned long offs;
124 const void __iomem *io = skge->hw->regs;
125 static const unsigned long bankmap
126 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
127 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
128 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
129 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
130
131 regs->version = 1;
132 for (offs = 0; offs < regs->len; offs += 128) {
133 u32 len = min_t(u32, 128, regs->len - offs);
134
135 if (bankmap & (1<<(offs/128)))
136 memcpy_fromio(p + offs, io + offs, len);
137 else
138 memset(p + offs, 0, len);
139 }
140 }
141
142 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
143 static int wol_supported(const struct skge_hw *hw)
144 {
145 return !((hw->chip_id == CHIP_ID_GENESIS ||
146 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
147 }
148
149 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150 {
151 struct skge_port *skge = netdev_priv(dev);
152
153 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
154 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
155 }
156
157 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
158 {
159 struct skge_port *skge = netdev_priv(dev);
160 struct skge_hw *hw = skge->hw;
161
162 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
163 return -EOPNOTSUPP;
164
165 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
166 return -EOPNOTSUPP;
167
168 skge->wol = wol->wolopts == WAKE_MAGIC;
169
170 if (skge->wol) {
171 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
172
173 skge_write16(hw, WOL_CTRL_STAT,
174 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
175 WOL_CTL_ENA_MAGIC_PKT_UNIT);
176 } else
177 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
178
179 return 0;
180 }
181
182 /* Determine supported/adverised modes based on hardware.
183 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
184 */
185 static u32 skge_supported_modes(const struct skge_hw *hw)
186 {
187 u32 supported;
188
189 if (iscopper(hw)) {
190 supported = SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full
194 | SUPPORTED_1000baseT_Half
195 | SUPPORTED_1000baseT_Full
196 | SUPPORTED_Autoneg| SUPPORTED_TP;
197
198 if (hw->chip_id == CHIP_ID_GENESIS)
199 supported &= ~(SUPPORTED_10baseT_Half
200 | SUPPORTED_10baseT_Full
201 | SUPPORTED_100baseT_Half
202 | SUPPORTED_100baseT_Full);
203
204 else if (hw->chip_id == CHIP_ID_YUKON)
205 supported &= ~SUPPORTED_1000baseT_Half;
206 } else
207 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
208 | SUPPORTED_Autoneg;
209
210 return supported;
211 }
212
213 static int skge_get_settings(struct net_device *dev,
214 struct ethtool_cmd *ecmd)
215 {
216 struct skge_port *skge = netdev_priv(dev);
217 struct skge_hw *hw = skge->hw;
218
219 ecmd->transceiver = XCVR_INTERNAL;
220 ecmd->supported = skge_supported_modes(hw);
221
222 if (iscopper(hw)) {
223 ecmd->port = PORT_TP;
224 ecmd->phy_address = hw->phy_addr;
225 } else
226 ecmd->port = PORT_FIBRE;
227
228 ecmd->advertising = skge->advertising;
229 ecmd->autoneg = skge->autoneg;
230 ecmd->speed = skge->speed;
231 ecmd->duplex = skge->duplex;
232 return 0;
233 }
234
235 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
236 {
237 struct skge_port *skge = netdev_priv(dev);
238 const struct skge_hw *hw = skge->hw;
239 u32 supported = skge_supported_modes(hw);
240
241 if (ecmd->autoneg == AUTONEG_ENABLE) {
242 ecmd->advertising = supported;
243 skge->duplex = -1;
244 skge->speed = -1;
245 } else {
246 u32 setting;
247
248 switch(ecmd->speed) {
249 case SPEED_1000:
250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_1000baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_1000baseT_Half;
254 else
255 return -EINVAL;
256 break;
257 case SPEED_100:
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_100baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_100baseT_Half;
262 else
263 return -EINVAL;
264 break;
265
266 case SPEED_10:
267 if (ecmd->duplex == DUPLEX_FULL)
268 setting = SUPPORTED_10baseT_Full;
269 else if (ecmd->duplex == DUPLEX_HALF)
270 setting = SUPPORTED_10baseT_Half;
271 else
272 return -EINVAL;
273 break;
274 default:
275 return -EINVAL;
276 }
277
278 if ((setting & supported) == 0)
279 return -EINVAL;
280
281 skge->speed = ecmd->speed;
282 skge->duplex = ecmd->duplex;
283 }
284
285 skge->autoneg = ecmd->autoneg;
286 skge->advertising = ecmd->advertising;
287
288 if (netif_running(dev)) {
289 skge_down(dev);
290 skge_up(dev);
291 }
292 return (0);
293 }
294
295 static void skge_get_drvinfo(struct net_device *dev,
296 struct ethtool_drvinfo *info)
297 {
298 struct skge_port *skge = netdev_priv(dev);
299
300 strcpy(info->driver, DRV_NAME);
301 strcpy(info->version, DRV_VERSION);
302 strcpy(info->fw_version, "N/A");
303 strcpy(info->bus_info, pci_name(skge->hw->pdev));
304 }
305
306 static const struct skge_stat {
307 char name[ETH_GSTRING_LEN];
308 u16 xmac_offset;
309 u16 gma_offset;
310 } skge_stats[] = {
311 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
312 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
313
314 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
315 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
316 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
317 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
318 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
319 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
320 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
321 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
322
323 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
324 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
325 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
326 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
327 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
328 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
329
330 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
331 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
332 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
333 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
335 };
336
337 static int skge_get_stats_count(struct net_device *dev)
338 {
339 return ARRAY_SIZE(skge_stats);
340 }
341
342 static void skge_get_ethtool_stats(struct net_device *dev,
343 struct ethtool_stats *stats, u64 *data)
344 {
345 struct skge_port *skge = netdev_priv(dev);
346
347 if (skge->hw->chip_id == CHIP_ID_GENESIS)
348 genesis_get_stats(skge, data);
349 else
350 yukon_get_stats(skge, data);
351 }
352
353 /* Use hardware MIB variables for critical path statistics and
354 * transmit feedback not reported at interrupt.
355 * Other errors are accounted for in interrupt handler.
356 */
357 static struct net_device_stats *skge_get_stats(struct net_device *dev)
358 {
359 struct skge_port *skge = netdev_priv(dev);
360 u64 data[ARRAY_SIZE(skge_stats)];
361
362 if (skge->hw->chip_id == CHIP_ID_GENESIS)
363 genesis_get_stats(skge, data);
364 else
365 yukon_get_stats(skge, data);
366
367 skge->net_stats.tx_bytes = data[0];
368 skge->net_stats.rx_bytes = data[1];
369 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
370 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
371 skge->net_stats.multicast = data[5] + data[7];
372 skge->net_stats.collisions = data[10];
373 skge->net_stats.tx_aborted_errors = data[12];
374
375 return &skge->net_stats;
376 }
377
378 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
379 {
380 int i;
381
382 switch (stringset) {
383 case ETH_SS_STATS:
384 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
385 memcpy(data + i * ETH_GSTRING_LEN,
386 skge_stats[i].name, ETH_GSTRING_LEN);
387 break;
388 }
389 }
390
391 static void skge_get_ring_param(struct net_device *dev,
392 struct ethtool_ringparam *p)
393 {
394 struct skge_port *skge = netdev_priv(dev);
395
396 p->rx_max_pending = MAX_RX_RING_SIZE;
397 p->tx_max_pending = MAX_TX_RING_SIZE;
398 p->rx_mini_max_pending = 0;
399 p->rx_jumbo_max_pending = 0;
400
401 p->rx_pending = skge->rx_ring.count;
402 p->tx_pending = skge->tx_ring.count;
403 p->rx_mini_pending = 0;
404 p->rx_jumbo_pending = 0;
405 }
406
407 static int skge_set_ring_param(struct net_device *dev,
408 struct ethtool_ringparam *p)
409 {
410 struct skge_port *skge = netdev_priv(dev);
411
412 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
413 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
414 return -EINVAL;
415
416 skge->rx_ring.count = p->rx_pending;
417 skge->tx_ring.count = p->tx_pending;
418
419 if (netif_running(dev)) {
420 skge_down(dev);
421 skge_up(dev);
422 }
423
424 return 0;
425 }
426
427 static u32 skge_get_msglevel(struct net_device *netdev)
428 {
429 struct skge_port *skge = netdev_priv(netdev);
430 return skge->msg_enable;
431 }
432
433 static void skge_set_msglevel(struct net_device *netdev, u32 value)
434 {
435 struct skge_port *skge = netdev_priv(netdev);
436 skge->msg_enable = value;
437 }
438
439 static int skge_nway_reset(struct net_device *dev)
440 {
441 struct skge_port *skge = netdev_priv(dev);
442 struct skge_hw *hw = skge->hw;
443 int port = skge->port;
444
445 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
446 return -EINVAL;
447
448 spin_lock_bh(&hw->phy_lock);
449 if (hw->chip_id == CHIP_ID_GENESIS) {
450 genesis_reset(hw, port);
451 genesis_mac_init(hw, port);
452 } else {
453 yukon_reset(hw, port);
454 yukon_init(hw, port);
455 }
456 spin_unlock_bh(&hw->phy_lock);
457 return 0;
458 }
459
460 static int skge_set_sg(struct net_device *dev, u32 data)
461 {
462 struct skge_port *skge = netdev_priv(dev);
463 struct skge_hw *hw = skge->hw;
464
465 if (hw->chip_id == CHIP_ID_GENESIS && data)
466 return -EOPNOTSUPP;
467 return ethtool_op_set_sg(dev, data);
468 }
469
470 static int skge_set_tx_csum(struct net_device *dev, u32 data)
471 {
472 struct skge_port *skge = netdev_priv(dev);
473 struct skge_hw *hw = skge->hw;
474
475 if (hw->chip_id == CHIP_ID_GENESIS && data)
476 return -EOPNOTSUPP;
477
478 return ethtool_op_set_tx_csum(dev, data);
479 }
480
481 static u32 skge_get_rx_csum(struct net_device *dev)
482 {
483 struct skge_port *skge = netdev_priv(dev);
484
485 return skge->rx_csum;
486 }
487
488 /* Only Yukon supports checksum offload. */
489 static int skge_set_rx_csum(struct net_device *dev, u32 data)
490 {
491 struct skge_port *skge = netdev_priv(dev);
492
493 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
494 return -EOPNOTSUPP;
495
496 skge->rx_csum = data;
497 return 0;
498 }
499
500 static void skge_get_pauseparam(struct net_device *dev,
501 struct ethtool_pauseparam *ecmd)
502 {
503 struct skge_port *skge = netdev_priv(dev);
504
505 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
506 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
507 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
508 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
509
510 ecmd->autoneg = skge->autoneg;
511 }
512
513 static int skge_set_pauseparam(struct net_device *dev,
514 struct ethtool_pauseparam *ecmd)
515 {
516 struct skge_port *skge = netdev_priv(dev);
517
518 skge->autoneg = ecmd->autoneg;
519 if (ecmd->rx_pause && ecmd->tx_pause)
520 skge->flow_control = FLOW_MODE_SYMMETRIC;
521 else if (ecmd->rx_pause && !ecmd->tx_pause)
522 skge->flow_control = FLOW_MODE_REM_SEND;
523 else if (!ecmd->rx_pause && ecmd->tx_pause)
524 skge->flow_control = FLOW_MODE_LOC_SEND;
525 else
526 skge->flow_control = FLOW_MODE_NONE;
527
528 if (netif_running(dev)) {
529 skge_down(dev);
530 skge_up(dev);
531 }
532 return 0;
533 }
534
535 /* Chip internal frequency for clock calculations */
536 static inline u32 hwkhz(const struct skge_hw *hw)
537 {
538 if (hw->chip_id == CHIP_ID_GENESIS)
539 return 53215; /* or: 53.125 MHz */
540 else
541 return 78215; /* or: 78.125 MHz */
542 }
543
544 /* Chip hz to microseconds */
545 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
546 {
547 return (ticks * 1000) / hwkhz(hw);
548 }
549
550 /* Microseconds to chip hz */
551 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
552 {
553 return hwkhz(hw) * usec / 1000;
554 }
555
556 static int skge_get_coalesce(struct net_device *dev,
557 struct ethtool_coalesce *ecmd)
558 {
559 struct skge_port *skge = netdev_priv(dev);
560 struct skge_hw *hw = skge->hw;
561 int port = skge->port;
562
563 ecmd->rx_coalesce_usecs = 0;
564 ecmd->tx_coalesce_usecs = 0;
565
566 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
567 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
568 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569
570 if (msk & rxirqmask[port])
571 ecmd->rx_coalesce_usecs = delay;
572 if (msk & txirqmask[port])
573 ecmd->tx_coalesce_usecs = delay;
574 }
575
576 return 0;
577 }
578
579 /* Note: interrupt timer is per board, but can turn on/off per port */
580 static int skge_set_coalesce(struct net_device *dev,
581 struct ethtool_coalesce *ecmd)
582 {
583 struct skge_port *skge = netdev_priv(dev);
584 struct skge_hw *hw = skge->hw;
585 int port = skge->port;
586 u32 msk = skge_read32(hw, B2_IRQM_MSK);
587 u32 delay = 25;
588
589 if (ecmd->rx_coalesce_usecs == 0)
590 msk &= ~rxirqmask[port];
591 else if (ecmd->rx_coalesce_usecs < 25 ||
592 ecmd->rx_coalesce_usecs > 33333)
593 return -EINVAL;
594 else {
595 msk |= rxirqmask[port];
596 delay = ecmd->rx_coalesce_usecs;
597 }
598
599 if (ecmd->tx_coalesce_usecs == 0)
600 msk &= ~txirqmask[port];
601 else if (ecmd->tx_coalesce_usecs < 25 ||
602 ecmd->tx_coalesce_usecs > 33333)
603 return -EINVAL;
604 else {
605 msk |= txirqmask[port];
606 delay = min(delay, ecmd->rx_coalesce_usecs);
607 }
608
609 skge_write32(hw, B2_IRQM_MSK, msk);
610 if (msk == 0)
611 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
612 else {
613 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
614 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
615 }
616 return 0;
617 }
618
619 static void skge_led_on(struct skge_hw *hw, int port)
620 {
621 if (hw->chip_id == CHIP_ID_GENESIS) {
622 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
623 skge_write8(hw, B0_LED, LED_STAT_ON);
624
625 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
626 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
627 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
628
629 /* For Broadcom Phy only */
630 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
631 } else {
632 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
633 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
634 PHY_M_LED_MO_DUP(MO_LED_ON) |
635 PHY_M_LED_MO_10(MO_LED_ON) |
636 PHY_M_LED_MO_100(MO_LED_ON) |
637 PHY_M_LED_MO_1000(MO_LED_ON) |
638 PHY_M_LED_MO_RX(MO_LED_ON));
639 }
640 }
641
642 static void skge_led_off(struct skge_hw *hw, int port)
643 {
644 if (hw->chip_id == CHIP_ID_GENESIS) {
645 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
646 skge_write8(hw, B0_LED, LED_STAT_OFF);
647
648 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
649 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
650
651 /* Broadcom only */
652 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
653 } else {
654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
655 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
656 PHY_M_LED_MO_DUP(MO_LED_OFF) |
657 PHY_M_LED_MO_10(MO_LED_OFF) |
658 PHY_M_LED_MO_100(MO_LED_OFF) |
659 PHY_M_LED_MO_1000(MO_LED_OFF) |
660 PHY_M_LED_MO_RX(MO_LED_OFF));
661 }
662 }
663
664 static void skge_blink_timer(unsigned long data)
665 {
666 struct skge_port *skge = (struct skge_port *) data;
667 struct skge_hw *hw = skge->hw;
668 unsigned long flags;
669
670 spin_lock_irqsave(&hw->phy_lock, flags);
671 if (skge->blink_on)
672 skge_led_on(hw, skge->port);
673 else
674 skge_led_off(hw, skge->port);
675 spin_unlock_irqrestore(&hw->phy_lock, flags);
676
677 skge->blink_on = !skge->blink_on;
678 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
679 }
680
681 /* blink LED's for finding board */
682 static int skge_phys_id(struct net_device *dev, u32 data)
683 {
684 struct skge_port *skge = netdev_priv(dev);
685
686 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
687 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
688
689 /* start blinking */
690 skge->blink_on = 1;
691 mod_timer(&skge->led_blink, jiffies+1);
692
693 msleep_interruptible(data * 1000);
694 del_timer_sync(&skge->led_blink);
695
696 skge_led_off(skge->hw, skge->port);
697
698 return 0;
699 }
700
701 static struct ethtool_ops skge_ethtool_ops = {
702 .get_settings = skge_get_settings,
703 .set_settings = skge_set_settings,
704 .get_drvinfo = skge_get_drvinfo,
705 .get_regs_len = skge_get_regs_len,
706 .get_regs = skge_get_regs,
707 .get_wol = skge_get_wol,
708 .set_wol = skge_set_wol,
709 .get_msglevel = skge_get_msglevel,
710 .set_msglevel = skge_set_msglevel,
711 .nway_reset = skge_nway_reset,
712 .get_link = ethtool_op_get_link,
713 .get_ringparam = skge_get_ring_param,
714 .set_ringparam = skge_set_ring_param,
715 .get_pauseparam = skge_get_pauseparam,
716 .set_pauseparam = skge_set_pauseparam,
717 .get_coalesce = skge_get_coalesce,
718 .set_coalesce = skge_set_coalesce,
719 .get_sg = ethtool_op_get_sg,
720 .set_sg = skge_set_sg,
721 .get_tx_csum = ethtool_op_get_tx_csum,
722 .set_tx_csum = skge_set_tx_csum,
723 .get_rx_csum = skge_get_rx_csum,
724 .set_rx_csum = skge_set_rx_csum,
725 .get_strings = skge_get_strings,
726 .phys_id = skge_phys_id,
727 .get_stats_count = skge_get_stats_count,
728 .get_ethtool_stats = skge_get_ethtool_stats,
729 };
730
731 /*
732 * Allocate ring elements and chain them together
733 * One-to-one association of board descriptors with ring elements
734 */
735 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
736 {
737 struct skge_tx_desc *d;
738 struct skge_element *e;
739 int i;
740
741 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
742 if (!ring->start)
743 return -ENOMEM;
744
745 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
746 e->desc = d;
747 if (i == ring->count - 1) {
748 e->next = ring->start;
749 d->next_offset = base;
750 } else {
751 e->next = e + 1;
752 d->next_offset = base + (i+1) * sizeof(*d);
753 }
754 }
755 ring->to_use = ring->to_clean = ring->start;
756
757 return 0;
758 }
759
760 /* Setup buffer for receiving */
761 static inline int skge_rx_alloc(struct skge_port *skge,
762 struct skge_element *e)
763 {
764 unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
765 struct skge_rx_desc *rd = e->desc;
766 struct sk_buff *skb;
767 u64 map;
768
769 skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
770 if (unlikely(!skb)) {
771 printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
772 skge->netdev->name);
773 return -ENOMEM;
774 }
775
776 skb->dev = skge->netdev;
777 skb_reserve(skb, NET_IP_ALIGN);
778
779 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
780 PCI_DMA_FROMDEVICE);
781
782 rd->dma_lo = map;
783 rd->dma_hi = map >> 32;
784 e->skb = skb;
785 rd->csum1_start = ETH_HLEN;
786 rd->csum2_start = ETH_HLEN;
787 rd->csum1 = 0;
788 rd->csum2 = 0;
789
790 wmb();
791
792 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
793 pci_unmap_addr_set(e, mapaddr, map);
794 pci_unmap_len_set(e, maplen, bufsize);
795 return 0;
796 }
797
798 /* Free all unused buffers in receive ring, assumes receiver stopped */
799 static void skge_rx_clean(struct skge_port *skge)
800 {
801 struct skge_hw *hw = skge->hw;
802 struct skge_ring *ring = &skge->rx_ring;
803 struct skge_element *e;
804
805 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
806 struct skge_rx_desc *rd = e->desc;
807 rd->control = 0;
808
809 pci_unmap_single(hw->pdev,
810 pci_unmap_addr(e, mapaddr),
811 pci_unmap_len(e, maplen),
812 PCI_DMA_FROMDEVICE);
813 dev_kfree_skb(e->skb);
814 e->skb = NULL;
815 }
816 ring->to_clean = e;
817 }
818
819 /* Allocate buffers for receive ring
820 * For receive: to_use is refill location
821 * to_clean is next received frame.
822 *
823 * if (to_use == to_clean)
824 * then ring all frames in ring need buffers
825 * if (to_use->next == to_clean)
826 * then ring all frames in ring have buffers
827 */
828 static int skge_rx_fill(struct skge_port *skge)
829 {
830 struct skge_ring *ring = &skge->rx_ring;
831 struct skge_element *e;
832 int ret = 0;
833
834 for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
835 if (skge_rx_alloc(skge, e)) {
836 ret = 1;
837 break;
838 }
839
840 }
841 ring->to_use = e;
842
843 return ret;
844 }
845
846 static void skge_link_up(struct skge_port *skge)
847 {
848 netif_carrier_on(skge->netdev);
849 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
850 netif_wake_queue(skge->netdev);
851
852 if (netif_msg_link(skge))
853 printk(KERN_INFO PFX
854 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
855 skge->netdev->name, skge->speed,
856 skge->duplex == DUPLEX_FULL ? "full" : "half",
857 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
858 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
859 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
860 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
861 "unknown");
862 }
863
864 static void skge_link_down(struct skge_port *skge)
865 {
866 netif_carrier_off(skge->netdev);
867 netif_stop_queue(skge->netdev);
868
869 if (netif_msg_link(skge))
870 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
871 }
872
873 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
874 {
875 int i;
876 u16 v;
877
878 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
879 v = xm_read16(hw, port, XM_PHY_DATA);
880
881 /* Need to wait for external PHY */
882 for (i = 0; i < PHY_RETRIES; i++) {
883 udelay(1);
884 if (xm_read16(hw, port, XM_MMU_CMD)
885 & XM_MMU_PHY_RDY)
886 goto ready;
887 }
888
889 printk(KERN_WARNING PFX "%s: phy read timed out\n",
890 hw->dev[port]->name);
891 return 0;
892 ready:
893 v = xm_read16(hw, port, XM_PHY_DATA);
894
895 return v;
896 }
897
898 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
899 {
900 int i;
901
902 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
903 for (i = 0; i < PHY_RETRIES; i++) {
904 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
905 goto ready;
906 udelay(1);
907 }
908 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
909 hw->dev[port]->name);
910
911
912 ready:
913 xm_write16(hw, port, XM_PHY_DATA, val);
914 for (i = 0; i < PHY_RETRIES; i++) {
915 udelay(1);
916 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
917 return;
918 }
919 printk(KERN_WARNING PFX "%s: phy write timed out\n",
920 hw->dev[port]->name);
921 }
922
923 static void genesis_init(struct skge_hw *hw)
924 {
925 /* set blink source counter */
926 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
927 skge_write8(hw, B2_BSC_CTRL, BSC_START);
928
929 /* configure mac arbiter */
930 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
931
932 /* configure mac arbiter timeout values */
933 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
934 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
935 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
937
938 skge_write8(hw, B3_MA_RCINI_RX1, 0);
939 skge_write8(hw, B3_MA_RCINI_RX2, 0);
940 skge_write8(hw, B3_MA_RCINI_TX1, 0);
941 skge_write8(hw, B3_MA_RCINI_TX2, 0);
942
943 /* configure packet arbiter timeout */
944 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
945 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
946 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
947 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
949 }
950
951 static void genesis_reset(struct skge_hw *hw, int port)
952 {
953 int i;
954 u64 zero = 0;
955
956 /* reset the statistics module */
957 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
958 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
959 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
960 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
961 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
962
963 /* disable Broadcom PHY IRQ */
964 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
965
966 xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
967 for (i = 0; i < 15; i++)
968 xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
969 xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
970 }
971
972
973 static void genesis_mac_init(struct skge_hw *hw, int port)
974 {
975 struct skge_port *skge = netdev_priv(hw->dev[port]);
976 int i;
977 u32 r;
978 u16 id1;
979 u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
980
981 /* magic workaround patterns for Broadcom */
982 static const struct {
983 u16 reg;
984 u16 val;
985 } A1hack[] = {
986 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
987 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
988 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
989 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
990 }, C0hack[] = {
991 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
992 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
993 };
994
995
996 /* initialize Rx, Tx and Link LED */
997 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
998 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
999
1000 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1001 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
1002
1003 /* Unreset the XMAC. */
1004 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1005
1006 /*
1007 * Perform additional initialization for external PHYs,
1008 * namely for the 1000baseTX cards that use the XMAC's
1009 * GMII mode.
1010 */
1011 spin_lock_bh(&hw->phy_lock);
1012
1013 /* External Phy Handling */
1014 /* Take PHY out of reset. */
1015 r = skge_read32(hw, B2_GP_IO);
1016 if (port == 0)
1017 r |= GP_DIR_0|GP_IO_0;
1018 else
1019 r |= GP_DIR_2|GP_IO_2;
1020
1021 skge_write32(hw, B2_GP_IO, r);
1022 skge_read32(hw, B2_GP_IO);
1023
1024 /* Enable GMII mode on the XMAC. */
1025 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1026
1027 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1028
1029 /* Optimize MDIO transfer by suppressing preamble. */
1030 xm_write16(hw, port, XM_MMU_CMD,
1031 xm_read16(hw, port, XM_MMU_CMD)
1032 | XM_MMU_NO_PRE);
1033
1034 if (id1 == PHY_BCOM_ID1_C0) {
1035 /*
1036 * Workaround BCOM Errata for the C0 type.
1037 * Write magic patterns to reserved registers.
1038 */
1039 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1040 xm_phy_write(hw, port,
1041 C0hack[i].reg, C0hack[i].val);
1042
1043 } else if (id1 == PHY_BCOM_ID1_A1) {
1044 /*
1045 * Workaround BCOM Errata for the A1 type.
1046 * Write magic patterns to reserved registers.
1047 */
1048 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1049 xm_phy_write(hw, port,
1050 A1hack[i].reg, A1hack[i].val);
1051 }
1052
1053 /*
1054 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1055 * Disable Power Management after reset.
1056 */
1057 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1058 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
1059
1060
1061 /* Dummy read */
1062 xm_read16(hw, port, XM_ISRC);
1063
1064 r = xm_read32(hw, port, XM_MODE);
1065 xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
1066
1067 /* We don't need the FCS appended to the packet. */
1068 r = xm_read16(hw, port, XM_RX_CMD);
1069 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
1070
1071 /* We want short frames padded to 60 bytes. */
1072 r = xm_read16(hw, port, XM_TX_CMD);
1073 xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
1074
1075 /*
1076 * Enable the reception of all error frames. This is is
1077 * a necessary evil due to the design of the XMAC. The
1078 * XMAC's receive FIFO is only 8K in size, however jumbo
1079 * frames can be up to 9000 bytes in length. When bad
1080 * frame filtering is enabled, the XMAC's RX FIFO operates
1081 * in 'store and forward' mode. For this to work, the
1082 * entire frame has to fit into the FIFO, but that means
1083 * that jumbo frames larger than 8192 bytes will be
1084 * truncated. Disabling all bad frame filtering causes
1085 * the RX FIFO to operate in streaming mode, in which
1086 * case the XMAC will start transfering frames out of the
1087 * RX FIFO as soon as the FIFO threshold is reached.
1088 */
1089 r = xm_read32(hw, port, XM_MODE);
1090 xm_write32(hw, port, XM_MODE,
1091 XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
1092 XM_MD_RX_ERR|XM_MD_RX_IRLE);
1093
1094 xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
1095 xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
1096
1097 /*
1098 * Bump up the transmit threshold. This helps hold off transmit
1099 * underruns when we're blasting traffic from both ports at once.
1100 */
1101 xm_write16(hw, port, XM_TX_THR, 512);
1102
1103 /* Configure MAC arbiter */
1104 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1105
1106 /* configure timeout values */
1107 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1108 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1109 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1110 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1111
1112 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1113 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1114 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1115 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1116
1117 /* Configure Rx MAC FIFO */
1118 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1119 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1120 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1121
1122 /* Configure Tx MAC FIFO */
1123 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1124 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1125 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1126
1127 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1128 /* Enable frame flushing if jumbo frames used */
1129 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1130 } else {
1131 /* enable timeout timers if normal frames */
1132 skge_write16(hw, B3_PA_CTRL,
1133 port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1134 }
1135
1136
1137 r = xm_read16(hw, port, XM_RX_CMD);
1138 if (hw->dev[port]->mtu > ETH_DATA_LEN)
1139 xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
1140 else
1141 xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
1142
1143 /* Broadcom phy initialization */
1144 ctrl1 = PHY_CT_SP1000;
1145 ctrl2 = 0;
1146 ctrl3 = PHY_AN_CSMA;
1147 ctrl4 = PHY_B_PEC_EN_LTR;
1148 ctrl5 = PHY_B_AC_TX_TST;
1149
1150 if (skge->autoneg == AUTONEG_ENABLE) {
1151 /*
1152 * Workaround BCOM Errata #1 for the C5 type.
1153 * 1000Base-T Link Acquisition Failure in Slave Mode
1154 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1155 */
1156 ctrl2 |= PHY_B_1000C_RD;
1157 if (skge->advertising & ADVERTISED_1000baseT_Half)
1158 ctrl2 |= PHY_B_1000C_AHD;
1159 if (skge->advertising & ADVERTISED_1000baseT_Full)
1160 ctrl2 |= PHY_B_1000C_AFD;
1161
1162 /* Set Flow-control capabilities */
1163 switch (skge->flow_control) {
1164 case FLOW_MODE_NONE:
1165 ctrl3 |= PHY_B_P_NO_PAUSE;
1166 break;
1167 case FLOW_MODE_LOC_SEND:
1168 ctrl3 |= PHY_B_P_ASYM_MD;
1169 break;
1170 case FLOW_MODE_SYMMETRIC:
1171 ctrl3 |= PHY_B_P_SYM_MD;
1172 break;
1173 case FLOW_MODE_REM_SEND:
1174 ctrl3 |= PHY_B_P_BOTH_MD;
1175 break;
1176 }
1177
1178 /* Restart Auto-negotiation */
1179 ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
1180 } else {
1181 if (skge->duplex == DUPLEX_FULL)
1182 ctrl1 |= PHY_CT_DUP_MD;
1183
1184 ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
1185 }
1186
1187 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
1188 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
1189
1190 if (skge->netdev->mtu > ETH_DATA_LEN) {
1191 ctrl4 |= PHY_B_PEC_HIGH_LA;
1192 ctrl5 |= PHY_B_AC_LONG_PACK;
1193
1194 xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
1195 }
1196
1197 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
1198 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
1199 spin_unlock_bh(&hw->phy_lock);
1200
1201 /* Clear MIB counters */
1202 xm_write16(hw, port, XM_STAT_CMD,
1203 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1204 /* Clear two times according to Errata #3 */
1205 xm_write16(hw, port, XM_STAT_CMD,
1206 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1207
1208 /* Start polling for link status */
1209 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1210 }
1211
1212 static void genesis_stop(struct skge_port *skge)
1213 {
1214 struct skge_hw *hw = skge->hw;
1215 int port = skge->port;
1216 u32 reg;
1217
1218 /* Clear Tx packet arbiter timeout IRQ */
1219 skge_write16(hw, B3_PA_CTRL,
1220 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1221
1222 /*
1223 * If the transfer stucks at the MAC the STOP command will not
1224 * terminate if we don't flush the XMAC's transmit FIFO !
1225 */
1226 xm_write32(hw, port, XM_MODE,
1227 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1228
1229
1230 /* Reset the MAC */
1231 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1232
1233 /* For external PHYs there must be special handling */
1234 reg = skge_read32(hw, B2_GP_IO);
1235 if (port == 0) {
1236 reg |= GP_DIR_0;
1237 reg &= ~GP_IO_0;
1238 } else {
1239 reg |= GP_DIR_2;
1240 reg &= ~GP_IO_2;
1241 }
1242 skge_write32(hw, B2_GP_IO, reg);
1243 skge_read32(hw, B2_GP_IO);
1244
1245 xm_write16(hw, port, XM_MMU_CMD,
1246 xm_read16(hw, port, XM_MMU_CMD)
1247 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1248
1249 xm_read16(hw, port, XM_MMU_CMD);
1250 }
1251
1252
1253 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1254 {
1255 struct skge_hw *hw = skge->hw;
1256 int port = skge->port;
1257 int i;
1258 unsigned long timeout = jiffies + HZ;
1259
1260 xm_write16(hw, port,
1261 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1262
1263 /* wait for update to complete */
1264 while (xm_read16(hw, port, XM_STAT_CMD)
1265 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1266 if (time_after(jiffies, timeout))
1267 break;
1268 udelay(10);
1269 }
1270
1271 /* special case for 64 bit octet counter */
1272 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1273 | xm_read32(hw, port, XM_TXO_OK_LO);
1274 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1275 | xm_read32(hw, port, XM_RXO_OK_LO);
1276
1277 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1278 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1279 }
1280
1281 static void genesis_mac_intr(struct skge_hw *hw, int port)
1282 {
1283 struct skge_port *skge = netdev_priv(hw->dev[port]);
1284 u16 status = xm_read16(hw, port, XM_ISRC);
1285
1286 pr_debug("genesis_intr status %x\n", status);
1287
1288 if (status & XM_IS_TXF_UR) {
1289 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1290 ++skge->net_stats.tx_fifo_errors;
1291 }
1292 if (status & XM_IS_RXF_OV) {
1293 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1294 ++skge->net_stats.rx_fifo_errors;
1295 }
1296 }
1297
1298 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1299 {
1300 int i;
1301
1302 gma_write16(hw, port, GM_SMI_DATA, val);
1303 gma_write16(hw, port, GM_SMI_CTRL,
1304 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1305 for (i = 0; i < PHY_RETRIES; i++) {
1306 udelay(1);
1307
1308 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1309 break;
1310 }
1311 }
1312
1313 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1314 {
1315 int i;
1316
1317 gma_write16(hw, port, GM_SMI_CTRL,
1318 GM_SMI_CT_PHY_AD(hw->phy_addr)
1319 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1320
1321 for (i = 0; i < PHY_RETRIES; i++) {
1322 udelay(1);
1323 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1324 goto ready;
1325 }
1326
1327 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1328 hw->dev[port]->name);
1329 return 0;
1330 ready:
1331 return gma_read16(hw, port, GM_SMI_DATA);
1332 }
1333
1334 static void genesis_link_down(struct skge_port *skge)
1335 {
1336 struct skge_hw *hw = skge->hw;
1337 int port = skge->port;
1338
1339 pr_debug("genesis_link_down\n");
1340
1341 xm_write16(hw, port, XM_MMU_CMD,
1342 xm_read16(hw, port, XM_MMU_CMD)
1343 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1344
1345 /* dummy read to ensure writing */
1346 (void) xm_read16(hw, port, XM_MMU_CMD);
1347
1348 skge_link_down(skge);
1349 }
1350
1351 static void genesis_link_up(struct skge_port *skge)
1352 {
1353 struct skge_hw *hw = skge->hw;
1354 int port = skge->port;
1355 u16 cmd;
1356 u32 mode, msk;
1357
1358 pr_debug("genesis_link_up\n");
1359 cmd = xm_read16(hw, port, XM_MMU_CMD);
1360
1361 /*
1362 * enabling pause frame reception is required for 1000BT
1363 * because the XMAC is not reset if the link is going down
1364 */
1365 if (skge->flow_control == FLOW_MODE_NONE ||
1366 skge->flow_control == FLOW_MODE_LOC_SEND)
1367 cmd |= XM_MMU_IGN_PF;
1368 else
1369 /* Enable Pause Frame Reception */
1370 cmd &= ~XM_MMU_IGN_PF;
1371
1372 xm_write16(hw, port, XM_MMU_CMD, cmd);
1373
1374 mode = xm_read32(hw, port, XM_MODE);
1375 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1376 skge->flow_control == FLOW_MODE_LOC_SEND) {
1377 /*
1378 * Configure Pause Frame Generation
1379 * Use internal and external Pause Frame Generation.
1380 * Sending pause frames is edge triggered.
1381 * Send a Pause frame with the maximum pause time if
1382 * internal oder external FIFO full condition occurs.
1383 * Send a zero pause time frame to re-start transmission.
1384 */
1385 /* XM_PAUSE_DA = '010000C28001' (default) */
1386 /* XM_MAC_PTIME = 0xffff (maximum) */
1387 /* remember this value is defined in big endian (!) */
1388 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1389
1390 mode |= XM_PAUSE_MODE;
1391 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1392 } else {
1393 /*
1394 * disable pause frame generation is required for 1000BT
1395 * because the XMAC is not reset if the link is going down
1396 */
1397 /* Disable Pause Mode in Mode Register */
1398 mode &= ~XM_PAUSE_MODE;
1399
1400 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1401 }
1402
1403 xm_write32(hw, port, XM_MODE, mode);
1404
1405 msk = XM_DEF_MSK;
1406 /* disable GP0 interrupt bit for external Phy */
1407 msk |= XM_IS_INP_ASS;
1408
1409 xm_write16(hw, port, XM_IMSK, msk);
1410 xm_read16(hw, port, XM_ISRC);
1411
1412 /* get MMU Command Reg. */
1413 cmd = xm_read16(hw, port, XM_MMU_CMD);
1414 if (skge->duplex == DUPLEX_FULL)
1415 cmd |= XM_MMU_GMII_FD;
1416
1417 /*
1418 * Workaround BCOM Errata (#10523) for all BCom Phys
1419 * Enable Power Management after link up
1420 */
1421 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1422 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1423 & ~PHY_B_AC_DIS_PM);
1424 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1425
1426 /* enable Rx/Tx */
1427 xm_write16(hw, port, XM_MMU_CMD,
1428 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1429 skge_link_up(skge);
1430 }
1431
1432
1433 static void genesis_bcom_intr(struct skge_port *skge)
1434 {
1435 struct skge_hw *hw = skge->hw;
1436 int port = skge->port;
1437 u16 stat = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1438
1439 pr_debug("genesis_bcom intr stat=%x\n", stat);
1440
1441 /* Workaround BCom Errata:
1442 * enable and disable loopback mode if "NO HCD" occurs.
1443 */
1444 if (stat & PHY_B_IS_NO_HDCL) {
1445 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1446 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1447 ctrl | PHY_CT_LOOP);
1448 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1449 ctrl & ~PHY_CT_LOOP);
1450 }
1451
1452 stat = xm_phy_read(hw, port, PHY_BCOM_STAT);
1453 if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
1454 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1455 if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
1456 genesis_link_down(skge);
1457
1458 else if (stat & PHY_B_IS_LST_CHANGE) {
1459 if (aux & PHY_B_AS_AN_C) {
1460 switch (aux & PHY_B_AS_AN_RES_MSK) {
1461 case PHY_B_RES_1000FD:
1462 skge->duplex = DUPLEX_FULL;
1463 break;
1464 case PHY_B_RES_1000HD:
1465 skge->duplex = DUPLEX_HALF;
1466 break;
1467 }
1468
1469 switch (aux & PHY_B_AS_PAUSE_MSK) {
1470 case PHY_B_AS_PAUSE_MSK:
1471 skge->flow_control = FLOW_MODE_SYMMETRIC;
1472 break;
1473 case PHY_B_AS_PRR:
1474 skge->flow_control = FLOW_MODE_REM_SEND;
1475 break;
1476 case PHY_B_AS_PRT:
1477 skge->flow_control = FLOW_MODE_LOC_SEND;
1478 break;
1479 default:
1480 skge->flow_control = FLOW_MODE_NONE;
1481 }
1482 skge->speed = SPEED_1000;
1483 }
1484 genesis_link_up(skge);
1485 }
1486 else
1487 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1488 }
1489 }
1490
1491 /* Perodic poll of phy status to check for link transistion */
1492 static void skge_link_timer(unsigned long __arg)
1493 {
1494 struct skge_port *skge = (struct skge_port *) __arg;
1495 struct skge_hw *hw = skge->hw;
1496
1497 if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
1498 return;
1499
1500 spin_lock_bh(&hw->phy_lock);
1501 genesis_bcom_intr(skge);
1502 spin_unlock_bh(&hw->phy_lock);
1503 }
1504
1505 /* Marvell Phy Initailization */
1506 static void yukon_init(struct skge_hw *hw, int port)
1507 {
1508 struct skge_port *skge = netdev_priv(hw->dev[port]);
1509 u16 ctrl, ct1000, adv;
1510 u16 ledctrl, ledover;
1511
1512 pr_debug("yukon_init\n");
1513 if (skge->autoneg == AUTONEG_ENABLE) {
1514 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1515
1516 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1517 PHY_M_EC_MAC_S_MSK);
1518 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1519
1520 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1521
1522 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1523 }
1524
1525 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1526 if (skge->autoneg == AUTONEG_DISABLE)
1527 ctrl &= ~PHY_CT_ANE;
1528
1529 ctrl |= PHY_CT_RESET;
1530 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1531
1532 ctrl = 0;
1533 ct1000 = 0;
1534 adv = PHY_AN_CSMA;
1535
1536 if (skge->autoneg == AUTONEG_ENABLE) {
1537 if (iscopper(hw)) {
1538 if (skge->advertising & ADVERTISED_1000baseT_Full)
1539 ct1000 |= PHY_M_1000C_AFD;
1540 if (skge->advertising & ADVERTISED_1000baseT_Half)
1541 ct1000 |= PHY_M_1000C_AHD;
1542 if (skge->advertising & ADVERTISED_100baseT_Full)
1543 adv |= PHY_M_AN_100_FD;
1544 if (skge->advertising & ADVERTISED_100baseT_Half)
1545 adv |= PHY_M_AN_100_HD;
1546 if (skge->advertising & ADVERTISED_10baseT_Full)
1547 adv |= PHY_M_AN_10_FD;
1548 if (skge->advertising & ADVERTISED_10baseT_Half)
1549 adv |= PHY_M_AN_10_HD;
1550
1551 /* Set Flow-control capabilities */
1552 switch (skge->flow_control) {
1553 case FLOW_MODE_NONE:
1554 adv |= PHY_B_P_NO_PAUSE;
1555 break;
1556 case FLOW_MODE_LOC_SEND:
1557 adv |= PHY_B_P_ASYM_MD;
1558 break;
1559 case FLOW_MODE_SYMMETRIC:
1560 adv |= PHY_B_P_SYM_MD;
1561 break;
1562 case FLOW_MODE_REM_SEND:
1563 adv |= PHY_B_P_BOTH_MD;
1564 break;
1565 }
1566 } else { /* special defines for FIBER (88E1011S only) */
1567 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1568
1569 /* Set Flow-control capabilities */
1570 switch (skge->flow_control) {
1571 case FLOW_MODE_NONE:
1572 adv |= PHY_M_P_NO_PAUSE_X;
1573 break;
1574 case FLOW_MODE_LOC_SEND:
1575 adv |= PHY_M_P_ASYM_MD_X;
1576 break;
1577 case FLOW_MODE_SYMMETRIC:
1578 adv |= PHY_M_P_SYM_MD_X;
1579 break;
1580 case FLOW_MODE_REM_SEND:
1581 adv |= PHY_M_P_BOTH_MD_X;
1582 break;
1583 }
1584 }
1585 /* Restart Auto-negotiation */
1586 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1587 } else {
1588 /* forced speed/duplex settings */
1589 ct1000 = PHY_M_1000C_MSE;
1590
1591 if (skge->duplex == DUPLEX_FULL)
1592 ctrl |= PHY_CT_DUP_MD;
1593
1594 switch (skge->speed) {
1595 case SPEED_1000:
1596 ctrl |= PHY_CT_SP1000;
1597 break;
1598 case SPEED_100:
1599 ctrl |= PHY_CT_SP100;
1600 break;
1601 }
1602
1603 ctrl |= PHY_CT_RESET;
1604 }
1605
1606 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1607
1608 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1609 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1610
1611 /* Setup Phy LED's */
1612 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1613 ledover = 0;
1614
1615 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1616
1617 /* turn off the Rx LED (LED_RX) */
1618 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
1619
1620 /* disable blink mode (LED_DUPLEX) on collisions */
1621 ctrl |= PHY_M_LEDC_DP_CTRL;
1622 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
1623
1624 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1625 /* turn on 100 Mbps LED (LED_LINK100) */
1626 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1627 }
1628
1629 if (ledover)
1630 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
1631
1632 /* Enable phy interrupt on autonegotiation complete (or link up) */
1633 if (skge->autoneg == AUTONEG_ENABLE)
1634 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
1635 else
1636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1637 }
1638
1639 static void yukon_reset(struct skge_hw *hw, int port)
1640 {
1641 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1642 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1643 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1644 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1645 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1646
1647 gma_write16(hw, port, GM_RX_CTRL,
1648 gma_read16(hw, port, GM_RX_CTRL)
1649 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1650 }
1651
1652 static void yukon_mac_init(struct skge_hw *hw, int port)
1653 {
1654 struct skge_port *skge = netdev_priv(hw->dev[port]);
1655 int i;
1656 u32 reg;
1657 const u8 *addr = hw->dev[port]->dev_addr;
1658
1659 /* WA code for COMA mode -- set PHY reset */
1660 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1661 hw->chip_rev == CHIP_REV_YU_LITE_A3)
1662 skge_write32(hw, B2_GP_IO,
1663 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1664
1665 /* hard reset */
1666 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1667 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1668
1669 /* WA code for COMA mode -- clear PHY reset */
1670 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1671 hw->chip_rev == CHIP_REV_YU_LITE_A3)
1672 skge_write32(hw, B2_GP_IO,
1673 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1674 & ~GP_IO_9);
1675
1676 /* Set hardware config mode */
1677 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1678 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1679 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1680
1681 /* Clear GMC reset */
1682 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1683 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1684 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1685 if (skge->autoneg == AUTONEG_DISABLE) {
1686 reg = GM_GPCR_AU_ALL_DIS;
1687 gma_write16(hw, port, GM_GP_CTRL,
1688 gma_read16(hw, port, GM_GP_CTRL) | reg);
1689
1690 switch (skge->speed) {
1691 case SPEED_1000:
1692 reg |= GM_GPCR_SPEED_1000;
1693 /* fallthru */
1694 case SPEED_100:
1695 reg |= GM_GPCR_SPEED_100;
1696 }
1697
1698 if (skge->duplex == DUPLEX_FULL)
1699 reg |= GM_GPCR_DUP_FULL;
1700 } else
1701 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1702 switch (skge->flow_control) {
1703 case FLOW_MODE_NONE:
1704 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1705 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1706 break;
1707 case FLOW_MODE_LOC_SEND:
1708 /* disable Rx flow-control */
1709 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1710 }
1711
1712 gma_write16(hw, port, GM_GP_CTRL, reg);
1713 skge_read16(hw, GMAC_IRQ_SRC);
1714
1715 spin_lock_bh(&hw->phy_lock);
1716 yukon_init(hw, port);
1717 spin_unlock_bh(&hw->phy_lock);
1718
1719 /* MIB clear */
1720 reg = gma_read16(hw, port, GM_PHY_ADDR);
1721 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1722
1723 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1724 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1725 gma_write16(hw, port, GM_PHY_ADDR, reg);
1726
1727 /* transmit control */
1728 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1729
1730 /* receive control reg: unicast + multicast + no FCS */
1731 gma_write16(hw, port, GM_RX_CTRL,
1732 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1733
1734 /* transmit flow control */
1735 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1736
1737 /* transmit parameter */
1738 gma_write16(hw, port, GM_TX_PARAM,
1739 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1740 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1741 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1742
1743 /* serial mode register */
1744 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1745 if (hw->dev[port]->mtu > 1500)
1746 reg |= GM_SMOD_JUMBO_ENA;
1747
1748 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1749
1750 /* physical address: used for pause frames */
1751 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1752 /* virtual address for data */
1753 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1754
1755 /* enable interrupt mask for counter overflows */
1756 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1757 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1758 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1759
1760 /* Initialize Mac Fifo */
1761
1762 /* Configure Rx MAC FIFO */
1763 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1764 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1765 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1766 hw->chip_rev == CHIP_REV_YU_LITE_A3)
1767 reg &= ~GMF_RX_F_FL_ON;
1768 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1769 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1770 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
1771
1772 /* Configure Tx MAC FIFO */
1773 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1774 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1775 }
1776
1777 static void yukon_stop(struct skge_port *skge)
1778 {
1779 struct skge_hw *hw = skge->hw;
1780 int port = skge->port;
1781
1782 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1783 hw->chip_rev == CHIP_REV_YU_LITE_A3) {
1784 skge_write32(hw, B2_GP_IO,
1785 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1786 }
1787
1788 gma_write16(hw, port, GM_GP_CTRL,
1789 gma_read16(hw, port, GM_GP_CTRL)
1790 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
1791 gma_read16(hw, port, GM_GP_CTRL);
1792
1793 /* set GPHY Control reset */
1794 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1795 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
1796 }
1797
1798 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1799 {
1800 struct skge_hw *hw = skge->hw;
1801 int port = skge->port;
1802 int i;
1803
1804 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1805 | gma_read32(hw, port, GM_TXO_OK_LO);
1806 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1807 | gma_read32(hw, port, GM_RXO_OK_LO);
1808
1809 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1810 data[i] = gma_read32(hw, port,
1811 skge_stats[i].gma_offset);
1812 }
1813
1814 static void yukon_mac_intr(struct skge_hw *hw, int port)
1815 {
1816 struct skge_port *skge = netdev_priv(hw->dev[port]);
1817 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1818
1819 pr_debug("yukon_intr status %x\n", status);
1820 if (status & GM_IS_RX_FF_OR) {
1821 ++skge->net_stats.rx_fifo_errors;
1822 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
1823 }
1824 if (status & GM_IS_TX_FF_UR) {
1825 ++skge->net_stats.tx_fifo_errors;
1826 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
1827 }
1828
1829 }
1830
1831 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1832 {
1833 switch (aux & PHY_M_PS_SPEED_MSK) {
1834 case PHY_M_PS_SPEED_1000:
1835 return SPEED_1000;
1836 case PHY_M_PS_SPEED_100:
1837 return SPEED_100;
1838 default:
1839 return SPEED_10;
1840 }
1841 }
1842
1843 static void yukon_link_up(struct skge_port *skge)
1844 {
1845 struct skge_hw *hw = skge->hw;
1846 int port = skge->port;
1847 u16 reg;
1848
1849 pr_debug("yukon_link_up\n");
1850
1851 /* Enable Transmit FIFO Underrun */
1852 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1853
1854 reg = gma_read16(hw, port, GM_GP_CTRL);
1855 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1856 reg |= GM_GPCR_DUP_FULL;
1857
1858 /* enable Rx/Tx */
1859 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1860 gma_write16(hw, port, GM_GP_CTRL, reg);
1861
1862 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1863 skge_link_up(skge);
1864 }
1865
1866 static void yukon_link_down(struct skge_port *skge)
1867 {
1868 struct skge_hw *hw = skge->hw;
1869 int port = skge->port;
1870
1871 pr_debug("yukon_link_down\n");
1872 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1873 gm_phy_write(hw, port, GM_GP_CTRL,
1874 gm_phy_read(hw, port, GM_GP_CTRL)
1875 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1876
1877 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1878 /* restore Asymmetric Pause bit */
1879 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1880 gm_phy_read(hw, port,
1881 PHY_MARV_AUNE_ADV)
1882 | PHY_M_AN_ASP);
1883
1884 }
1885
1886 yukon_reset(hw, port);
1887 skge_link_down(skge);
1888
1889 yukon_init(hw, port);
1890 }
1891
1892 static void yukon_phy_intr(struct skge_port *skge)
1893 {
1894 struct skge_hw *hw = skge->hw;
1895 int port = skge->port;
1896 const char *reason = NULL;
1897 u16 istatus, phystat;
1898
1899 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1900 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1901 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
1902
1903 if (istatus & PHY_M_IS_AN_COMPL) {
1904 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1905 & PHY_M_AN_RF) {
1906 reason = "remote fault";
1907 goto failed;
1908 }
1909
1910 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1911 reason = "master/slave fault";
1912 goto failed;
1913 }
1914
1915 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1916 reason = "speed/duplex";
1917 goto failed;
1918 }
1919
1920 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1921 ? DUPLEX_FULL : DUPLEX_HALF;
1922 skge->speed = yukon_speed(hw, phystat);
1923
1924 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1925 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1926 case PHY_M_PS_PAUSE_MSK:
1927 skge->flow_control = FLOW_MODE_SYMMETRIC;
1928 break;
1929 case PHY_M_PS_RX_P_EN:
1930 skge->flow_control = FLOW_MODE_REM_SEND;
1931 break;
1932 case PHY_M_PS_TX_P_EN:
1933 skge->flow_control = FLOW_MODE_LOC_SEND;
1934 break;
1935 default:
1936 skge->flow_control = FLOW_MODE_NONE;
1937 }
1938
1939 if (skge->flow_control == FLOW_MODE_NONE ||
1940 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1941 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1942 else
1943 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1944 yukon_link_up(skge);
1945 return;
1946 }
1947
1948 if (istatus & PHY_M_IS_LSP_CHANGE)
1949 skge->speed = yukon_speed(hw, phystat);
1950
1951 if (istatus & PHY_M_IS_DUP_CHANGE)
1952 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1953 if (istatus & PHY_M_IS_LST_CHANGE) {
1954 if (phystat & PHY_M_PS_LINK_UP)
1955 yukon_link_up(skge);
1956 else
1957 yukon_link_down(skge);
1958 }
1959 return;
1960 failed:
1961 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1962 skge->netdev->name, reason);
1963
1964 /* XXX restart autonegotiation? */
1965 }
1966
1967 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1968 {
1969 u32 end;
1970
1971 start /= 8;
1972 len /= 8;
1973 end = start + len - 1;
1974
1975 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1976 skge_write32(hw, RB_ADDR(q, RB_START), start);
1977 skge_write32(hw, RB_ADDR(q, RB_WP), start);
1978 skge_write32(hw, RB_ADDR(q, RB_RP), start);
1979 skge_write32(hw, RB_ADDR(q, RB_END), end);
1980
1981 if (q == Q_R1 || q == Q_R2) {
1982 /* Set thresholds on receive queue's */
1983 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
1984 start + (2*len)/3);
1985 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
1986 start + (len/3));
1987 } else {
1988 /* Enable store & forward on Tx queue's because
1989 * Tx FIFO is only 4K on Genesis and 1K on Yukon
1990 */
1991 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1992 }
1993
1994 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1995 }
1996
1997 /* Setup Bus Memory Interface */
1998 static void skge_qset(struct skge_port *skge, u16 q,
1999 const struct skge_element *e)
2000 {
2001 struct skge_hw *hw = skge->hw;
2002 u32 watermark = 0x600;
2003 u64 base = skge->dma + (e->desc - skge->mem);
2004
2005 /* optimization to reduce window on 32bit/33mhz */
2006 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2007 watermark /= 2;
2008
2009 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2010 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2011 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2012 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2013 }
2014
2015 static int skge_up(struct net_device *dev)
2016 {
2017 struct skge_port *skge = netdev_priv(dev);
2018 struct skge_hw *hw = skge->hw;
2019 int port = skge->port;
2020 u32 chunk, ram_addr;
2021 size_t rx_size, tx_size;
2022 int err;
2023
2024 if (netif_msg_ifup(skge))
2025 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2026
2027 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2028 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2029 skge->mem_size = tx_size + rx_size;
2030 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2031 if (!skge->mem)
2032 return -ENOMEM;
2033
2034 memset(skge->mem, 0, skge->mem_size);
2035
2036 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2037 goto free_pci_mem;
2038
2039 if (skge_rx_fill(skge))
2040 goto free_rx_ring;
2041
2042 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2043 skge->dma + rx_size)))
2044 goto free_rx_ring;
2045
2046 skge->tx_avail = skge->tx_ring.count - 1;
2047
2048 /* Initialze MAC */
2049 if (hw->chip_id == CHIP_ID_GENESIS)
2050 genesis_mac_init(hw, port);
2051 else
2052 yukon_mac_init(hw, port);
2053
2054 /* Configure RAMbuffers */
2055 chunk = hw->ram_size / ((hw->ports + 1)*2);
2056 ram_addr = hw->ram_offset + 2 * chunk * port;
2057
2058 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2059 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2060
2061 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2062 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2063 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2064
2065 /* Start receiver BMU */
2066 wmb();
2067 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2068
2069 pr_debug("skge_up completed\n");
2070 return 0;
2071
2072 free_rx_ring:
2073 skge_rx_clean(skge);
2074 kfree(skge->rx_ring.start);
2075 free_pci_mem:
2076 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2077
2078 return err;
2079 }
2080
2081 static int skge_down(struct net_device *dev)
2082 {
2083 struct skge_port *skge = netdev_priv(dev);
2084 struct skge_hw *hw = skge->hw;
2085 int port = skge->port;
2086
2087 if (netif_msg_ifdown(skge))
2088 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2089
2090 netif_stop_queue(dev);
2091
2092 del_timer_sync(&skge->led_blink);
2093 del_timer_sync(&skge->link_check);
2094
2095 /* Stop transmitter */
2096 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2097 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2098 RB_RST_SET|RB_DIS_OP_MD);
2099
2100 if (hw->chip_id == CHIP_ID_GENESIS)
2101 genesis_stop(skge);
2102 else
2103 yukon_stop(skge);
2104
2105 /* Disable Force Sync bit and Enable Alloc bit */
2106 skge_write8(hw, SK_REG(port, TXA_CTRL),
2107 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2108
2109 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2110 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2111 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2112
2113 /* Reset PCI FIFO */
2114 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2115 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2116
2117 /* Reset the RAM Buffer async Tx queue */
2118 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2119 /* stop receiver */
2120 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2121 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2122 RB_RST_SET|RB_DIS_OP_MD);
2123 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2124
2125 if (hw->chip_id == CHIP_ID_GENESIS) {
2126 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2127 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2128 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2129 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
2130 } else {
2131 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2132 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2133 }
2134
2135 /* turn off led's */
2136 skge_write16(hw, B0_LED, LED_STAT_OFF);
2137
2138 skge_tx_clean(skge);
2139 skge_rx_clean(skge);
2140
2141 kfree(skge->rx_ring.start);
2142 kfree(skge->tx_ring.start);
2143 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2144 return 0;
2145 }
2146
2147 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2148 {
2149 struct skge_port *skge = netdev_priv(dev);
2150 struct skge_hw *hw = skge->hw;
2151 struct skge_ring *ring = &skge->tx_ring;
2152 struct skge_element *e;
2153 struct skge_tx_desc *td;
2154 int i;
2155 u32 control, len;
2156 u64 map;
2157 unsigned long flags;
2158
2159 skb = skb_padto(skb, ETH_ZLEN);
2160 if (!skb)
2161 return NETDEV_TX_OK;
2162
2163 local_irq_save(flags);
2164 if (!spin_trylock(&skge->tx_lock)) {
2165 /* Collision - tell upper layer to requeue */
2166 local_irq_restore(flags);
2167 return NETDEV_TX_LOCKED;
2168 }
2169
2170 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2171 netif_stop_queue(dev);
2172 spin_unlock_irqrestore(&skge->tx_lock, flags);
2173
2174 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2175 dev->name);
2176 return NETDEV_TX_BUSY;
2177 }
2178
2179 e = ring->to_use;
2180 td = e->desc;
2181 e->skb = skb;
2182 len = skb_headlen(skb);
2183 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2184 pci_unmap_addr_set(e, mapaddr, map);
2185 pci_unmap_len_set(e, maplen, len);
2186
2187 td->dma_lo = map;
2188 td->dma_hi = map >> 32;
2189
2190 if (skb->ip_summed == CHECKSUM_HW) {
2191 const struct iphdr *ip
2192 = (const struct iphdr *) (skb->data + ETH_HLEN);
2193 int offset = skb->h.raw - skb->data;
2194
2195 /* This seems backwards, but it is what the sk98lin
2196 * does. Looks like hardware is wrong?
2197 */
2198 if (ip->protocol == IPPROTO_UDP
2199 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2200 control = BMU_TCP_CHECK;
2201 else
2202 control = BMU_UDP_CHECK;
2203
2204 td->csum_offs = 0;
2205 td->csum_start = offset;
2206 td->csum_write = offset + skb->csum;
2207 } else
2208 control = BMU_CHECK;
2209
2210 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2211 control |= BMU_EOF| BMU_IRQ_EOF;
2212 else {
2213 struct skge_tx_desc *tf = td;
2214
2215 control |= BMU_STFWD;
2216 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2217 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2218
2219 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2220 frag->size, PCI_DMA_TODEVICE);
2221
2222 e = e->next;
2223 e->skb = NULL;
2224 tf = e->desc;
2225 tf->dma_lo = map;
2226 tf->dma_hi = (u64) map >> 32;
2227 pci_unmap_addr_set(e, mapaddr, map);
2228 pci_unmap_len_set(e, maplen, frag->size);
2229
2230 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2231 }
2232 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2233 }
2234 /* Make sure all the descriptors written */
2235 wmb();
2236 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2237 wmb();
2238
2239 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2240
2241 if (netif_msg_tx_queued(skge))
2242 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2243 dev->name, e - ring->start, skb->len);
2244
2245 ring->to_use = e->next;
2246 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2247 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2248 pr_debug("%s: transmit queue full\n", dev->name);
2249 netif_stop_queue(dev);
2250 }
2251
2252 dev->trans_start = jiffies;
2253 spin_unlock_irqrestore(&skge->tx_lock, flags);
2254
2255 return NETDEV_TX_OK;
2256 }
2257
2258 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2259 {
2260 if (e->skb) {
2261 pci_unmap_single(hw->pdev,
2262 pci_unmap_addr(e, mapaddr),
2263 pci_unmap_len(e, maplen),
2264 PCI_DMA_TODEVICE);
2265 dev_kfree_skb_any(e->skb);
2266 e->skb = NULL;
2267 } else {
2268 pci_unmap_page(hw->pdev,
2269 pci_unmap_addr(e, mapaddr),
2270 pci_unmap_len(e, maplen),
2271 PCI_DMA_TODEVICE);
2272 }
2273 }
2274
2275 static void skge_tx_clean(struct skge_port *skge)
2276 {
2277 struct skge_ring *ring = &skge->tx_ring;
2278 struct skge_element *e;
2279 unsigned long flags;
2280
2281 spin_lock_irqsave(&skge->tx_lock, flags);
2282 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2283 ++skge->tx_avail;
2284 skge_tx_free(skge->hw, e);
2285 }
2286 ring->to_clean = e;
2287 spin_unlock_irqrestore(&skge->tx_lock, flags);
2288 }
2289
2290 static void skge_tx_timeout(struct net_device *dev)
2291 {
2292 struct skge_port *skge = netdev_priv(dev);
2293
2294 if (netif_msg_timer(skge))
2295 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2296
2297 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2298 skge_tx_clean(skge);
2299 }
2300
2301 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2302 {
2303 int err = 0;
2304
2305 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2306 return -EINVAL;
2307
2308 dev->mtu = new_mtu;
2309
2310 if (netif_running(dev)) {
2311 skge_down(dev);
2312 skge_up(dev);
2313 }
2314
2315 return err;
2316 }
2317
2318 static void genesis_set_multicast(struct net_device *dev)
2319 {
2320 struct skge_port *skge = netdev_priv(dev);
2321 struct skge_hw *hw = skge->hw;
2322 int port = skge->port;
2323 int i, count = dev->mc_count;
2324 struct dev_mc_list *list = dev->mc_list;
2325 u32 mode;
2326 u8 filter[8];
2327
2328 mode = xm_read32(hw, port, XM_MODE);
2329 mode |= XM_MD_ENA_HASH;
2330 if (dev->flags & IFF_PROMISC)
2331 mode |= XM_MD_ENA_PROM;
2332 else
2333 mode &= ~XM_MD_ENA_PROM;
2334
2335 if (dev->flags & IFF_ALLMULTI)
2336 memset(filter, 0xff, sizeof(filter));
2337 else {
2338 memset(filter, 0, sizeof(filter));
2339 for (i = 0; list && i < count; i++, list = list->next) {
2340 u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
2341 u8 bit = 63 - (crc & 63);
2342
2343 filter[bit/8] |= 1 << (bit%8);
2344 }
2345 }
2346
2347 xm_outhash(hw, port, XM_HSM, filter);
2348
2349 xm_write32(hw, port, XM_MODE, mode);
2350 }
2351
2352 static void yukon_set_multicast(struct net_device *dev)
2353 {
2354 struct skge_port *skge = netdev_priv(dev);
2355 struct skge_hw *hw = skge->hw;
2356 int port = skge->port;
2357 struct dev_mc_list *list = dev->mc_list;
2358 u16 reg;
2359 u8 filter[8];
2360
2361 memset(filter, 0, sizeof(filter));
2362
2363 reg = gma_read16(hw, port, GM_RX_CTRL);
2364 reg |= GM_RXCR_UCF_ENA;
2365
2366 if (dev->flags & IFF_PROMISC) /* promiscious */
2367 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2368 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2369 memset(filter, 0xff, sizeof(filter));
2370 else if (dev->mc_count == 0) /* no multicast */
2371 reg &= ~GM_RXCR_MCF_ENA;
2372 else {
2373 int i;
2374 reg |= GM_RXCR_MCF_ENA;
2375
2376 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2377 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2378 filter[bit/8] |= 1 << (bit%8);
2379 }
2380 }
2381
2382
2383 gma_write16(hw, port, GM_MC_ADDR_H1,
2384 (u16)filter[0] | ((u16)filter[1] << 8));
2385 gma_write16(hw, port, GM_MC_ADDR_H2,
2386 (u16)filter[2] | ((u16)filter[3] << 8));
2387 gma_write16(hw, port, GM_MC_ADDR_H3,
2388 (u16)filter[4] | ((u16)filter[5] << 8));
2389 gma_write16(hw, port, GM_MC_ADDR_H4,
2390 (u16)filter[6] | ((u16)filter[7] << 8));
2391
2392 gma_write16(hw, port, GM_RX_CTRL, reg);
2393 }
2394
2395 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2396 {
2397 if (hw->chip_id == CHIP_ID_GENESIS)
2398 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2399 else
2400 return (status & GMR_FS_ANY_ERR) ||
2401 (status & GMR_FS_RX_OK) == 0;
2402 }
2403
2404 static void skge_rx_error(struct skge_port *skge, int slot,
2405 u32 control, u32 status)
2406 {
2407 if (netif_msg_rx_err(skge))
2408 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2409 skge->netdev->name, slot, control, status);
2410
2411 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2412 || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2413 skge->net_stats.rx_length_errors++;
2414 else {
2415 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2416 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2417 skge->net_stats.rx_length_errors++;
2418 if (status & XMR_FS_FRA_ERR)
2419 skge->net_stats.rx_frame_errors++;
2420 if (status & XMR_FS_FCS_ERR)
2421 skge->net_stats.rx_crc_errors++;
2422 } else {
2423 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2424 skge->net_stats.rx_length_errors++;
2425 if (status & GMR_FS_FRAGMENT)
2426 skge->net_stats.rx_frame_errors++;
2427 if (status & GMR_FS_CRC_ERR)
2428 skge->net_stats.rx_crc_errors++;
2429 }
2430 }
2431 }
2432
2433 static int skge_poll(struct net_device *dev, int *budget)
2434 {
2435 struct skge_port *skge = netdev_priv(dev);
2436 struct skge_hw *hw = skge->hw;
2437 struct skge_ring *ring = &skge->rx_ring;
2438 struct skge_element *e;
2439 unsigned int to_do = min(dev->quota, *budget);
2440 unsigned int work_done = 0;
2441 int done;
2442 static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
2443
2444 for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
2445 e = e->next) {
2446 struct skge_rx_desc *rd = e->desc;
2447 struct sk_buff *skb = e->skb;
2448 u32 control, len, status;
2449
2450 rmb();
2451 control = rd->control;
2452 if (control & BMU_OWN)
2453 break;
2454
2455 len = control & BMU_BBC;
2456 e->skb = NULL;
2457
2458 pci_unmap_single(hw->pdev,
2459 pci_unmap_addr(e, mapaddr),
2460 pci_unmap_len(e, maplen),
2461 PCI_DMA_FROMDEVICE);
2462
2463 status = rd->status;
2464 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2465 || len > dev->mtu + VLAN_ETH_HLEN
2466 || bad_phy_status(hw, status)) {
2467 skge_rx_error(skge, e - ring->start, control, status);
2468 dev_kfree_skb(skb);
2469 continue;
2470 }
2471
2472 if (netif_msg_rx_status(skge))
2473 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2474 dev->name, e - ring->start, rd->status, len);
2475
2476 skb_put(skb, len);
2477 skb->protocol = eth_type_trans(skb, dev);
2478
2479 if (skge->rx_csum) {
2480 skb->csum = le16_to_cpu(rd->csum2);
2481 skb->ip_summed = CHECKSUM_HW;
2482 }
2483
2484 dev->last_rx = jiffies;
2485 netif_receive_skb(skb);
2486
2487 ++work_done;
2488 }
2489 ring->to_clean = e;
2490
2491 *budget -= work_done;
2492 dev->quota -= work_done;
2493 done = work_done < to_do;
2494
2495 if (skge_rx_fill(skge))
2496 done = 0;
2497
2498 /* restart receiver */
2499 wmb();
2500 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2501 CSR_START | CSR_IRQ_CL_F);
2502
2503 if (done) {
2504 local_irq_disable();
2505 hw->intr_mask |= irqmask[skge->port];
2506 /* Order is important since data can get interrupted */
2507 skge_write32(hw, B0_IMSK, hw->intr_mask);
2508 __netif_rx_complete(dev);
2509 local_irq_enable();
2510 }
2511
2512 return !done;
2513 }
2514
2515 static inline void skge_tx_intr(struct net_device *dev)
2516 {
2517 struct skge_port *skge = netdev_priv(dev);
2518 struct skge_hw *hw = skge->hw;
2519 struct skge_ring *ring = &skge->tx_ring;
2520 struct skge_element *e;
2521
2522 spin_lock(&skge->tx_lock);
2523 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2524 struct skge_tx_desc *td = e->desc;
2525 u32 control;
2526
2527 rmb();
2528 control = td->control;
2529 if (control & BMU_OWN)
2530 break;
2531
2532 if (unlikely(netif_msg_tx_done(skge)))
2533 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2534 dev->name, e - ring->start, td->status);
2535
2536 skge_tx_free(hw, e);
2537 e->skb = NULL;
2538 ++skge->tx_avail;
2539 }
2540 ring->to_clean = e;
2541 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2542
2543 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2544 netif_wake_queue(dev);
2545
2546 spin_unlock(&skge->tx_lock);
2547 }
2548
2549 static void skge_mac_parity(struct skge_hw *hw, int port)
2550 {
2551 printk(KERN_ERR PFX "%s: mac data parity error\n",
2552 hw->dev[port] ? hw->dev[port]->name
2553 : (port == 0 ? "(port A)": "(port B"));
2554
2555 if (hw->chip_id == CHIP_ID_GENESIS)
2556 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2557 MFF_CLR_PERR);
2558 else
2559 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2560 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2561 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2562 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2563 }
2564
2565 static void skge_pci_clear(struct skge_hw *hw)
2566 {
2567 u16 status;
2568
2569 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2570 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2571 pci_write_config_word(hw->pdev, PCI_STATUS,
2572 status | PCI_STATUS_ERROR_BITS);
2573 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2574 }
2575
2576 static void skge_mac_intr(struct skge_hw *hw, int port)
2577 {
2578 if (hw->chip_id == CHIP_ID_GENESIS)
2579 genesis_mac_intr(hw, port);
2580 else
2581 yukon_mac_intr(hw, port);
2582 }
2583
2584 /* Handle device specific framing and timeout interrupts */
2585 static void skge_error_irq(struct skge_hw *hw)
2586 {
2587 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2588
2589 if (hw->chip_id == CHIP_ID_GENESIS) {
2590 /* clear xmac errors */
2591 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2592 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2593 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2594 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2595 } else {
2596 /* Timestamp (unused) overflow */
2597 if (hwstatus & IS_IRQ_TIST_OV)
2598 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2599
2600 if (hwstatus & IS_IRQ_SENSOR) {
2601 /* no sensors on 32-bit Yukon */
2602 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2603 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2604 skge_write32(hw, B0_HWE_IMSK,
2605 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2606 } else
2607 printk(KERN_WARNING PFX "sensor interrupt\n");
2608 }
2609
2610
2611 }
2612
2613 if (hwstatus & IS_RAM_RD_PAR) {
2614 printk(KERN_ERR PFX "Ram read data parity error\n");
2615 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2616 }
2617
2618 if (hwstatus & IS_RAM_WR_PAR) {
2619 printk(KERN_ERR PFX "Ram write data parity error\n");
2620 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2621 }
2622
2623 if (hwstatus & IS_M1_PAR_ERR)
2624 skge_mac_parity(hw, 0);
2625
2626 if (hwstatus & IS_M2_PAR_ERR)
2627 skge_mac_parity(hw, 1);
2628
2629 if (hwstatus & IS_R1_PAR_ERR)
2630 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2631
2632 if (hwstatus & IS_R2_PAR_ERR)
2633 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2634
2635 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2636 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2637 hwstatus);
2638
2639 skge_pci_clear(hw);
2640
2641 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2642 if (hwstatus & IS_IRQ_STAT) {
2643 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2644 hwstatus);
2645 hw->intr_mask &= ~IS_HW_ERR;
2646 }
2647 }
2648 }
2649
2650 /*
2651 * Interrrupt from PHY are handled in tasklet (soft irq)
2652 * because accessing phy registers requires spin wait which might
2653 * cause excess interrupt latency.
2654 */
2655 static void skge_extirq(unsigned long data)
2656 {
2657 struct skge_hw *hw = (struct skge_hw *) data;
2658 int port;
2659
2660 spin_lock(&hw->phy_lock);
2661 for (port = 0; port < 2; port++) {
2662 struct net_device *dev = hw->dev[port];
2663
2664 if (dev && netif_running(dev)) {
2665 struct skge_port *skge = netdev_priv(dev);
2666
2667 if (hw->chip_id != CHIP_ID_GENESIS)
2668 yukon_phy_intr(skge);
2669 else
2670 genesis_bcom_intr(skge);
2671 }
2672 }
2673 spin_unlock(&hw->phy_lock);
2674
2675 local_irq_disable();
2676 hw->intr_mask |= IS_EXT_REG;
2677 skge_write32(hw, B0_IMSK, hw->intr_mask);
2678 local_irq_enable();
2679 }
2680
2681 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2682 {
2683 struct skge_hw *hw = dev_id;
2684 u32 status = skge_read32(hw, B0_SP_ISRC);
2685
2686 if (status == 0 || status == ~0) /* hotplug or shared irq */
2687 return IRQ_NONE;
2688
2689 status &= hw->intr_mask;
2690
2691 if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
2692 status &= ~IS_R1_F;
2693 hw->intr_mask &= ~IS_R1_F;
2694 skge_write32(hw, B0_IMSK, hw->intr_mask);
2695 __netif_rx_schedule(hw->dev[0]);
2696 }
2697
2698 if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
2699 status &= ~IS_R2_F;
2700 hw->intr_mask &= ~IS_R2_F;
2701 skge_write32(hw, B0_IMSK, hw->intr_mask);
2702 __netif_rx_schedule(hw->dev[1]);
2703 }
2704
2705 if (status & IS_XA1_F)
2706 skge_tx_intr(hw->dev[0]);
2707
2708 if (status & IS_XA2_F)
2709 skge_tx_intr(hw->dev[1]);
2710
2711 if (status & IS_MAC1)
2712 skge_mac_intr(hw, 0);
2713
2714 if (status & IS_MAC2)
2715 skge_mac_intr(hw, 1);
2716
2717 if (status & IS_HW_ERR)
2718 skge_error_irq(hw);
2719
2720 if (status & IS_EXT_REG) {
2721 hw->intr_mask &= ~IS_EXT_REG;
2722 tasklet_schedule(&hw->ext_tasklet);
2723 }
2724
2725 if (status)
2726 skge_write32(hw, B0_IMSK, hw->intr_mask);
2727
2728 return IRQ_HANDLED;
2729 }
2730
2731 #ifdef CONFIG_NET_POLL_CONTROLLER
2732 static void skge_netpoll(struct net_device *dev)
2733 {
2734 struct skge_port *skge = netdev_priv(dev);
2735
2736 disable_irq(dev->irq);
2737 skge_intr(dev->irq, skge->hw, NULL);
2738 enable_irq(dev->irq);
2739 }
2740 #endif
2741
2742 static int skge_set_mac_address(struct net_device *dev, void *p)
2743 {
2744 struct skge_port *skge = netdev_priv(dev);
2745 struct sockaddr *addr = p;
2746 int err = 0;
2747
2748 if (!is_valid_ether_addr(addr->sa_data))
2749 return -EADDRNOTAVAIL;
2750
2751 skge_down(dev);
2752 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2753 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2754 dev->dev_addr, ETH_ALEN);
2755 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2756 dev->dev_addr, ETH_ALEN);
2757 if (dev->flags & IFF_UP)
2758 err = skge_up(dev);
2759 return err;
2760 }
2761
2762 static const struct {
2763 u8 id;
2764 const char *name;
2765 } skge_chips[] = {
2766 { CHIP_ID_GENESIS, "Genesis" },
2767 { CHIP_ID_YUKON, "Yukon" },
2768 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2769 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2770 };
2771
2772 static const char *skge_board_name(const struct skge_hw *hw)
2773 {
2774 int i;
2775 static char buf[16];
2776
2777 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2778 if (skge_chips[i].id == hw->chip_id)
2779 return skge_chips[i].name;
2780
2781 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2782 return buf;
2783 }
2784
2785
2786 /*
2787 * Setup the board data structure, but don't bring up
2788 * the port(s)
2789 */
2790 static int skge_reset(struct skge_hw *hw)
2791 {
2792 u16 ctst;
2793 u8 t8, mac_cfg;
2794 int i;
2795
2796 ctst = skge_read16(hw, B0_CTST);
2797
2798 /* do a SW reset */
2799 skge_write8(hw, B0_CTST, CS_RST_SET);
2800 skge_write8(hw, B0_CTST, CS_RST_CLR);
2801
2802 /* clear PCI errors, if any */
2803 skge_pci_clear(hw);
2804
2805 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2806
2807 /* restore CLK_RUN bits (for Yukon-Lite) */
2808 skge_write16(hw, B0_CTST,
2809 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2810
2811 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2812 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2813 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2814
2815 switch (hw->chip_id) {
2816 case CHIP_ID_GENESIS:
2817 switch (hw->phy_type) {
2818 case SK_PHY_BCOM:
2819 hw->phy_addr = PHY_ADDR_BCOM;
2820 break;
2821 default:
2822 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2823 pci_name(hw->pdev), hw->phy_type);
2824 return -EOPNOTSUPP;
2825 }
2826 break;
2827
2828 case CHIP_ID_YUKON:
2829 case CHIP_ID_YUKON_LITE:
2830 case CHIP_ID_YUKON_LP:
2831 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2832 hw->phy_type = SK_PHY_MARV_COPPER;
2833
2834 hw->phy_addr = PHY_ADDR_MARV;
2835 if (!iscopper(hw))
2836 hw->phy_type = SK_PHY_MARV_FIBER;
2837
2838 break;
2839
2840 default:
2841 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2842 pci_name(hw->pdev), hw->chip_id);
2843 return -EOPNOTSUPP;
2844 }
2845
2846 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2847 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2848 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2849
2850 /* read the adapters RAM size */
2851 t8 = skge_read8(hw, B2_E_0);
2852 if (hw->chip_id == CHIP_ID_GENESIS) {
2853 if (t8 == 3) {
2854 /* special case: 4 x 64k x 36, offset = 0x80000 */
2855 hw->ram_size = 0x100000;
2856 hw->ram_offset = 0x80000;
2857 } else
2858 hw->ram_size = t8 * 512;
2859 }
2860 else if (t8 == 0)
2861 hw->ram_size = 0x20000;
2862 else
2863 hw->ram_size = t8 * 4096;
2864
2865 if (hw->chip_id == CHIP_ID_GENESIS)
2866 genesis_init(hw);
2867 else {
2868 /* switch power to VCC (WA for VAUX problem) */
2869 skge_write8(hw, B0_POWER_CTRL,
2870 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2871 for (i = 0; i < hw->ports; i++) {
2872 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2873 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2874 }
2875 }
2876
2877 /* turn off hardware timer (unused) */
2878 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2879 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2880 skge_write8(hw, B0_LED, LED_STAT_ON);
2881
2882 /* enable the Tx Arbiters */
2883 for (i = 0; i < hw->ports; i++)
2884 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2885
2886 /* Initialize ram interface */
2887 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2888
2889 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2890 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2891 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2892 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2893 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2894 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2895 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2896 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2897 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2898 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2899 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2900 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2901
2902 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2903
2904 /* Set interrupt moderation for Transmit only
2905 * Receive interrupts avoided by NAPI
2906 */
2907 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2908 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2909 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2910
2911 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
2912 if (hw->ports > 1)
2913 hw->intr_mask |= IS_PORT_2;
2914 skge_write32(hw, B0_IMSK, hw->intr_mask);
2915
2916 if (hw->chip_id != CHIP_ID_GENESIS)
2917 skge_write8(hw, GMAC_IRQ_MSK, 0);
2918
2919 spin_lock_bh(&hw->phy_lock);
2920 for (i = 0; i < hw->ports; i++) {
2921 if (hw->chip_id == CHIP_ID_GENESIS)
2922 genesis_reset(hw, i);
2923 else
2924 yukon_reset(hw, i);
2925 }
2926 spin_unlock_bh(&hw->phy_lock);
2927
2928 return 0;
2929 }
2930
2931 /* Initialize network device */
2932 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
2933 int highmem)
2934 {
2935 struct skge_port *skge;
2936 struct net_device *dev = alloc_etherdev(sizeof(*skge));
2937
2938 if (!dev) {
2939 printk(KERN_ERR "skge etherdev alloc failed");
2940 return NULL;
2941 }
2942
2943 SET_MODULE_OWNER(dev);
2944 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2945 dev->open = skge_up;
2946 dev->stop = skge_down;
2947 dev->hard_start_xmit = skge_xmit_frame;
2948 dev->get_stats = skge_get_stats;
2949 if (hw->chip_id == CHIP_ID_GENESIS)
2950 dev->set_multicast_list = genesis_set_multicast;
2951 else
2952 dev->set_multicast_list = yukon_set_multicast;
2953
2954 dev->set_mac_address = skge_set_mac_address;
2955 dev->change_mtu = skge_change_mtu;
2956 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
2957 dev->tx_timeout = skge_tx_timeout;
2958 dev->watchdog_timeo = TX_WATCHDOG;
2959 dev->poll = skge_poll;
2960 dev->weight = NAPI_WEIGHT;
2961 #ifdef CONFIG_NET_POLL_CONTROLLER
2962 dev->poll_controller = skge_netpoll;
2963 #endif
2964 dev->irq = hw->pdev->irq;
2965 dev->features = NETIF_F_LLTX;
2966 if (highmem)
2967 dev->features |= NETIF_F_HIGHDMA;
2968
2969 skge = netdev_priv(dev);
2970 skge->netdev = dev;
2971 skge->hw = hw;
2972 skge->msg_enable = netif_msg_init(debug, default_msg);
2973 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
2974 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
2975
2976 /* Auto speed and flow control */
2977 skge->autoneg = AUTONEG_ENABLE;
2978 skge->flow_control = FLOW_MODE_SYMMETRIC;
2979 skge->duplex = -1;
2980 skge->speed = -1;
2981 skge->advertising = skge_supported_modes(hw);
2982
2983 hw->dev[port] = dev;
2984
2985 skge->port = port;
2986
2987 spin_lock_init(&skge->tx_lock);
2988
2989 init_timer(&skge->link_check);
2990 skge->link_check.function = skge_link_timer;
2991 skge->link_check.data = (unsigned long) skge;
2992
2993 init_timer(&skge->led_blink);
2994 skge->led_blink.function = skge_blink_timer;
2995 skge->led_blink.data = (unsigned long) skge;
2996
2997 if (hw->chip_id != CHIP_ID_GENESIS) {
2998 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2999 skge->rx_csum = 1;
3000 }
3001
3002 /* read the mac address */
3003 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3004
3005 /* device is off until link detection */
3006 netif_carrier_off(dev);
3007 netif_stop_queue(dev);
3008
3009 return dev;
3010 }
3011
3012 static void __devinit skge_show_addr(struct net_device *dev)
3013 {
3014 const struct skge_port *skge = netdev_priv(dev);
3015
3016 if (netif_msg_probe(skge))
3017 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3018 dev->name,
3019 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3020 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3021 }
3022
3023 static int __devinit skge_probe(struct pci_dev *pdev,
3024 const struct pci_device_id *ent)
3025 {
3026 struct net_device *dev, *dev1;
3027 struct skge_hw *hw;
3028 int err, using_dac = 0;
3029
3030 if ((err = pci_enable_device(pdev))) {
3031 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3032 pci_name(pdev));
3033 goto err_out;
3034 }
3035
3036 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3037 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3038 pci_name(pdev));
3039 goto err_out_disable_pdev;
3040 }
3041
3042 pci_set_master(pdev);
3043
3044 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3045 using_dac = 1;
3046 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3047 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3048 pci_name(pdev));
3049 goto err_out_free_regions;
3050 }
3051
3052 #ifdef __BIG_ENDIAN
3053 /* byte swap decriptors in hardware */
3054 {
3055 u32 reg;
3056
3057 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3058 reg |= PCI_REV_DESC;
3059 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3060 }
3061 #endif
3062
3063 err = -ENOMEM;
3064 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3065 if (!hw) {
3066 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3067 pci_name(pdev));
3068 goto err_out_free_regions;
3069 }
3070
3071 memset(hw, 0, sizeof(*hw));
3072 hw->pdev = pdev;
3073 spin_lock_init(&hw->phy_lock);
3074 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3075
3076 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3077 if (!hw->regs) {
3078 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3079 pci_name(pdev));
3080 goto err_out_free_hw;
3081 }
3082
3083 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3084 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3085 pci_name(pdev), pdev->irq);
3086 goto err_out_iounmap;
3087 }
3088 pci_set_drvdata(pdev, hw);
3089
3090 err = skge_reset(hw);
3091 if (err)
3092 goto err_out_free_irq;
3093
3094 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3095 pci_resource_start(pdev, 0), pdev->irq,
3096 skge_board_name(hw), hw->chip_rev);
3097
3098 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3099 goto err_out_led_off;
3100
3101 if ((err = register_netdev(dev))) {
3102 printk(KERN_ERR PFX "%s: cannot register net device\n",
3103 pci_name(pdev));
3104 goto err_out_free_netdev;
3105 }
3106
3107 skge_show_addr(dev);
3108
3109 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3110 if (register_netdev(dev1) == 0)
3111 skge_show_addr(dev1);
3112 else {
3113 /* Failure to register second port need not be fatal */
3114 printk(KERN_WARNING PFX "register of second port failed\n");
3115 hw->dev[1] = NULL;
3116 free_netdev(dev1);
3117 }
3118 }
3119
3120 return 0;
3121
3122 err_out_free_netdev:
3123 free_netdev(dev);
3124 err_out_led_off:
3125 skge_write16(hw, B0_LED, LED_STAT_OFF);
3126 err_out_free_irq:
3127 free_irq(pdev->irq, hw);
3128 err_out_iounmap:
3129 iounmap(hw->regs);
3130 err_out_free_hw:
3131 kfree(hw);
3132 err_out_free_regions:
3133 pci_release_regions(pdev);
3134 err_out_disable_pdev:
3135 pci_disable_device(pdev);
3136 pci_set_drvdata(pdev, NULL);
3137 err_out:
3138 return err;
3139 }
3140
3141 static void __devexit skge_remove(struct pci_dev *pdev)
3142 {
3143 struct skge_hw *hw = pci_get_drvdata(pdev);
3144 struct net_device *dev0, *dev1;
3145
3146 if (!hw)
3147 return;
3148
3149 if ((dev1 = hw->dev[1]))
3150 unregister_netdev(dev1);
3151 dev0 = hw->dev[0];
3152 unregister_netdev(dev0);
3153
3154 tasklet_kill(&hw->ext_tasklet);
3155
3156 free_irq(pdev->irq, hw);
3157 pci_release_regions(pdev);
3158 pci_disable_device(pdev);
3159 if (dev1)
3160 free_netdev(dev1);
3161 free_netdev(dev0);
3162 skge_write16(hw, B0_LED, LED_STAT_OFF);
3163 iounmap(hw->regs);
3164 kfree(hw);
3165 pci_set_drvdata(pdev, NULL);
3166 }
3167
3168 #ifdef CONFIG_PM
3169 static int skge_suspend(struct pci_dev *pdev, u32 state)
3170 {
3171 struct skge_hw *hw = pci_get_drvdata(pdev);
3172 int i, wol = 0;
3173
3174 for (i = 0; i < 2; i++) {
3175 struct net_device *dev = hw->dev[i];
3176
3177 if (dev) {
3178 struct skge_port *skge = netdev_priv(dev);
3179 if (netif_running(dev)) {
3180 netif_carrier_off(dev);
3181 skge_down(dev);
3182 }
3183 netif_device_detach(dev);
3184 wol |= skge->wol;
3185 }
3186 }
3187
3188 pci_save_state(pdev);
3189 pci_enable_wake(pdev, state, wol);
3190 pci_disable_device(pdev);
3191 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3192
3193 return 0;
3194 }
3195
3196 static int skge_resume(struct pci_dev *pdev)
3197 {
3198 struct skge_hw *hw = pci_get_drvdata(pdev);
3199 int i;
3200
3201 pci_set_power_state(pdev, PCI_D0);
3202 pci_restore_state(pdev);
3203 pci_enable_wake(pdev, PCI_D0, 0);
3204
3205 skge_reset(hw);
3206
3207 for (i = 0; i < 2; i++) {
3208 struct net_device *dev = hw->dev[i];
3209 if (dev) {
3210 netif_device_attach(dev);
3211 if (netif_running(dev))
3212 skge_up(dev);
3213 }
3214 }
3215 return 0;
3216 }
3217 #endif
3218
3219 static struct pci_driver skge_driver = {
3220 .name = DRV_NAME,
3221 .id_table = skge_id_table,
3222 .probe = skge_probe,
3223 .remove = __devexit_p(skge_remove),
3224 #ifdef CONFIG_PM
3225 .suspend = skge_suspend,
3226 .resume = skge_resume,
3227 #endif
3228 };
3229
3230 static int __init skge_init_module(void)
3231 {
3232 return pci_module_init(&skge_driver);
3233 }
3234
3235 static void __exit skge_cleanup_module(void)
3236 {
3237 pci_unregister_driver(&skge_driver);
3238 }
3239
3240 module_init(skge_init_module);
3241 module_exit(skge_cleanup_module);
Stable & featurefull patchset based on Linus's git branch