2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/config.h>
6 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/capability.h>
12 #include <linux/sched.h>
13 #include <linux/errno.h>
14 #include <linux/bootmem.h>
16 #include <asm/processor.h>
19 #include <asm/sections.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base
= 0;
35 unsigned long isa_mem_base
= 0;
36 unsigned long pci_dram_offset
= 0;
37 int pcibios_assign_bus_offset
= 1;
39 void pcibios_make_OF_bus_map(void);
41 static int pci_relocate_bridge_resource(struct pci_bus
*bus
, int i
);
42 static int probe_resource(struct pci_bus
*parent
, struct resource
*pr
,
43 struct resource
*res
, struct resource
**conflict
);
44 static void update_bridge_base(struct pci_bus
*bus
, int i
);
45 static void pcibios_fixup_resources(struct pci_dev
* dev
);
46 static void fixup_broken_pcnet32(struct pci_dev
* dev
);
47 static int reparent_resources(struct resource
*parent
, struct resource
*res
);
48 static void fixup_rev1_53c810(struct pci_dev
* dev
);
49 static void fixup_cpc710_pci64(struct pci_dev
* dev
);
51 static u8
* pci_to_OF_bus_map
;
54 /* By default, we don't re-assign bus numbers. We do this only on
57 int pci_assign_all_buses
;
59 struct pci_controller
* hose_head
;
60 struct pci_controller
** hose_tail
= &hose_head
;
62 static int pci_bus_count
;
65 fixup_rev1_53c810(struct pci_dev
* dev
)
67 /* rev 1 ncr53c810 chips don't set the class at all which means
68 * they don't get their resources remapped. Fix that here.
71 if ((dev
->class == PCI_CLASS_NOT_DEFINED
)) {
72 printk("NCR 53c810 rev 1 detected, setting PCI class.\n");
73 dev
->class = PCI_CLASS_STORAGE_SCSI
;
76 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
79 fixup_broken_pcnet32(struct pci_dev
* dev
)
81 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
82 dev
->vendor
= PCI_VENDOR_ID_AMD
;
83 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
89 fixup_cpc710_pci64(struct pci_dev
* dev
)
91 /* Hide the PCI64 BARs from the kernel as their content doesn't
92 * fit well in the resource management
94 dev
->resource
[0].start
= dev
->resource
[0].end
= 0;
95 dev
->resource
[0].flags
= 0;
96 dev
->resource
[1].start
= dev
->resource
[1].end
= 0;
97 dev
->resource
[1].flags
= 0;
99 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CPC710_PCI64
, fixup_cpc710_pci64
);
102 pcibios_fixup_resources(struct pci_dev
*dev
)
104 struct pci_controller
* hose
= (struct pci_controller
*)dev
->sysdata
;
106 unsigned long offset
;
109 printk(KERN_ERR
"No hose for PCI dev %s!\n", pci_name(dev
));
112 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
113 struct resource
*res
= dev
->resource
+ i
;
116 if (res
->end
== 0xffffffff) {
117 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
118 pci_name(dev
), i
, res
->start
, res
->end
);
119 res
->end
-= res
->start
;
121 res
->flags
|= IORESOURCE_UNSET
;
125 if (res
->flags
& IORESOURCE_MEM
) {
126 offset
= hose
->pci_mem_offset
;
127 } else if (res
->flags
& IORESOURCE_IO
) {
128 offset
= (unsigned long) hose
->io_base_virt
132 res
->start
+= offset
;
135 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
136 i
, res
->flags
, pci_name(dev
),
137 res
->start
- offset
, res
->start
);
142 /* Call machine specific resource fixup */
143 if (ppc_md
.pcibios_fixup_resources
)
144 ppc_md
.pcibios_fixup_resources(dev
);
146 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
148 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
149 struct resource
*res
)
151 unsigned long offset
= 0;
152 struct pci_controller
*hose
= dev
->sysdata
;
154 if (hose
&& res
->flags
& IORESOURCE_IO
)
155 offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
156 else if (hose
&& res
->flags
& IORESOURCE_MEM
)
157 offset
= hose
->pci_mem_offset
;
158 region
->start
= res
->start
- offset
;
159 region
->end
= res
->end
- offset
;
161 EXPORT_SYMBOL(pcibios_resource_to_bus
);
163 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
164 struct pci_bus_region
*region
)
166 unsigned long offset
= 0;
167 struct pci_controller
*hose
= dev
->sysdata
;
169 if (hose
&& res
->flags
& IORESOURCE_IO
)
170 offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
171 else if (hose
&& res
->flags
& IORESOURCE_MEM
)
172 offset
= hose
->pci_mem_offset
;
173 res
->start
= region
->start
+ offset
;
174 res
->end
= region
->end
+ offset
;
176 EXPORT_SYMBOL(pcibios_bus_to_resource
);
179 * We need to avoid collisions with `mirrored' VGA ports
180 * and other strange ISA hardware, so we always want the
181 * addresses to be allocated in the 0x000-0x0ff region
184 * Why? Because some silly external IO cards only decode
185 * the low 10 bits of the IO address. The 0x00-0xff region
186 * is reserved for motherboard devices that decode all 16
187 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
188 * but we want to try to avoid allocating at 0x2900-0x2bff
189 * which might have be mirrored at 0x0100-0x03ff..
191 void pcibios_align_resource(void *data
, struct resource
*res
, unsigned long size
,
194 struct pci_dev
*dev
= data
;
196 if (res
->flags
& IORESOURCE_IO
) {
197 unsigned long start
= res
->start
;
200 printk(KERN_ERR
"PCI: I/O Region %s/%d too large"
201 " (%ld bytes)\n", pci_name(dev
),
202 dev
->resource
- res
, size
);
206 start
= (start
+ 0x3ff) & ~0x3ff;
211 EXPORT_SYMBOL(pcibios_align_resource
);
214 * Handle resources of PCI devices. If the world were perfect, we could
215 * just allocate all the resource regions and do nothing more. It isn't.
216 * On the other hand, we cannot just re-allocate all devices, as it would
217 * require us to know lots of host bridge internals. So we attempt to
218 * keep as much of the original configuration as possible, but tweak it
219 * when it's found to be wrong.
221 * Known BIOS problems we have to work around:
222 * - I/O or memory regions not configured
223 * - regions configured, but not enabled in the command register
224 * - bogus I/O addresses above 64K used
225 * - expansion ROMs left enabled (this may sound harmless, but given
226 * the fact the PCI specs explicitly allow address decoders to be
227 * shared between expansion ROMs and other resource regions, it's
228 * at least dangerous)
231 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
232 * This gives us fixed barriers on where we can allocate.
233 * (2) Allocate resources for all enabled devices. If there is
234 * a collision, just mark the resource as unallocated. Also
235 * disable expansion ROMs during this step.
236 * (3) Try to allocate resources for disabled devices. If the
237 * resources were assigned correctly, everything goes well,
238 * if they weren't, they won't disturb allocation of other
240 * (4) Assign new addresses to resources which were either
241 * not configured at all or misconfigured. If explicitly
242 * requested by the user, configure expansion ROM address
247 pcibios_allocate_bus_resources(struct list_head
*bus_list
)
251 struct resource
*res
, *pr
;
253 /* Depth-First Search on bus tree */
254 list_for_each_entry(bus
, bus_list
, node
) {
255 for (i
= 0; i
< 4; ++i
) {
256 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
257 || res
->start
> res
->end
)
259 if (bus
->parent
== NULL
)
260 pr
= (res
->flags
& IORESOURCE_IO
)?
261 &ioport_resource
: &iomem_resource
;
263 pr
= pci_find_parent_resource(bus
->self
, res
);
265 /* this happens when the generic PCI
266 * code (wrongly) decides that this
267 * bridge is transparent -- paulus
273 DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n",
274 res
->start
, res
->end
, res
->flags
, pr
);
276 if (request_resource(pr
, res
) == 0)
279 * Must be a conflict with an existing entry.
280 * Move that entry (or entries) under the
281 * bridge resource and try again.
283 if (reparent_resources(pr
, res
) == 0)
286 printk(KERN_ERR
"PCI: Cannot allocate resource region "
287 "%d of PCI bridge %d\n", i
, bus
->number
);
288 if (pci_relocate_bridge_resource(bus
, i
))
289 bus
->resource
[i
] = NULL
;
291 pcibios_allocate_bus_resources(&bus
->children
);
296 * Reparent resource children of pr that conflict with res
297 * under res, and make res replace those children.
300 reparent_resources(struct resource
*parent
, struct resource
*res
)
302 struct resource
*p
, **pp
;
303 struct resource
**firstpp
= NULL
;
305 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
306 if (p
->end
< res
->start
)
308 if (res
->end
< p
->start
)
310 if (p
->start
< res
->start
|| p
->end
> res
->end
)
311 return -1; /* not completely contained */
316 return -1; /* didn't find any conflicting entries? */
317 res
->parent
= parent
;
318 res
->child
= *firstpp
;
322 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
324 DBG(KERN_INFO
"PCI: reparented %s [%lx..%lx] under %s\n",
325 p
->name
, p
->start
, p
->end
, res
->name
);
331 * A bridge has been allocated a range which is outside the range
332 * of its parent bridge, so it needs to be moved.
335 pci_relocate_bridge_resource(struct pci_bus
*bus
, int i
)
337 struct resource
*res
, *pr
, *conflict
;
338 unsigned long try, size
;
340 struct pci_bus
*parent
= bus
->parent
;
342 if (parent
== NULL
) {
343 /* shouldn't ever happen */
344 printk(KERN_ERR
"PCI: can't move host bridge resource\n");
347 res
= bus
->resource
[i
];
351 for (j
= 0; j
< 4; j
++) {
352 struct resource
*r
= parent
->resource
[j
];
355 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
357 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
)) {
361 if (res
->flags
& IORESOURCE_PREFETCH
)
366 size
= res
->end
- res
->start
;
367 if (pr
->start
> pr
->end
|| size
> pr
->end
- pr
->start
)
371 res
->start
= try - size
;
373 if (probe_resource(bus
->parent
, pr
, res
, &conflict
) == 0)
375 if (conflict
->start
<= pr
->start
+ size
)
377 try = conflict
->start
- 1;
379 if (request_resource(pr
, res
)) {
380 DBG(KERN_ERR
"PCI: huh? couldn't move to %lx..%lx\n",
381 res
->start
, res
->end
);
382 return -1; /* "can't happen" */
384 update_bridge_base(bus
, i
);
385 printk(KERN_INFO
"PCI: bridge %d resource %d moved to %lx..%lx\n",
386 bus
->number
, i
, res
->start
, res
->end
);
391 probe_resource(struct pci_bus
*parent
, struct resource
*pr
,
392 struct resource
*res
, struct resource
**conflict
)
399 for (r
= pr
->child
; r
!= NULL
; r
= r
->sibling
) {
400 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
405 list_for_each_entry(bus
, &parent
->children
, node
) {
406 for (i
= 0; i
< 4; ++i
) {
407 if ((r
= bus
->resource
[i
]) == NULL
)
409 if (!r
->flags
|| r
->start
> r
->end
|| r
== res
)
411 if (pci_find_parent_resource(bus
->self
, r
) != pr
)
413 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
419 list_for_each_entry(dev
, &parent
->devices
, bus_list
) {
420 for (i
= 0; i
< 6; ++i
) {
421 r
= &dev
->resource
[i
];
422 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
424 if (pci_find_parent_resource(dev
, r
) != pr
)
426 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
436 update_bridge_base(struct pci_bus
*bus
, int i
)
438 struct resource
*res
= bus
->resource
[i
];
439 u8 io_base_lo
, io_limit_lo
;
440 u16 mem_base
, mem_limit
;
442 unsigned long start
, end
, off
;
443 struct pci_dev
*dev
= bus
->self
;
444 struct pci_controller
*hose
= dev
->sysdata
;
447 printk("update_bridge_base: no hose?\n");
450 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
451 pci_write_config_word(dev
, PCI_COMMAND
,
452 cmd
& ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
));
453 if (res
->flags
& IORESOURCE_IO
) {
454 off
= (unsigned long) hose
->io_base_virt
- isa_io_base
;
455 start
= res
->start
- off
;
456 end
= res
->end
- off
;
457 io_base_lo
= (start
>> 8) & PCI_IO_RANGE_MASK
;
458 io_limit_lo
= (end
>> 8) & PCI_IO_RANGE_MASK
;
460 pci_write_config_word(dev
, PCI_IO_BASE_UPPER16
,
462 pci_write_config_word(dev
, PCI_IO_LIMIT_UPPER16
,
464 io_base_lo
|= PCI_IO_RANGE_TYPE_32
;
466 io_base_lo
|= PCI_IO_RANGE_TYPE_16
;
467 pci_write_config_byte(dev
, PCI_IO_BASE
, io_base_lo
);
468 pci_write_config_byte(dev
, PCI_IO_LIMIT
, io_limit_lo
);
470 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
472 off
= hose
->pci_mem_offset
;
473 mem_base
= ((res
->start
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
474 mem_limit
= ((res
->end
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
475 pci_write_config_word(dev
, PCI_MEMORY_BASE
, mem_base
);
476 pci_write_config_word(dev
, PCI_MEMORY_LIMIT
, mem_limit
);
478 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
479 == (IORESOURCE_MEM
| IORESOURCE_PREFETCH
)) {
480 off
= hose
->pci_mem_offset
;
481 mem_base
= ((res
->start
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
482 mem_limit
= ((res
->end
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
483 pci_write_config_word(dev
, PCI_PREF_MEMORY_BASE
, mem_base
);
484 pci_write_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, mem_limit
);
487 DBG(KERN_ERR
"PCI: ugh, bridge %s res %d has flags=%lx\n",
488 pci_name(dev
), i
, res
->flags
);
490 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
493 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
495 struct resource
*pr
, *r
= &dev
->resource
[idx
];
497 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
498 pci_name(dev
), idx
, r
->start
, r
->end
, r
->flags
);
499 pr
= pci_find_parent_resource(dev
, r
);
500 if (!pr
|| request_resource(pr
, r
) < 0) {
501 printk(KERN_ERR
"PCI: Cannot allocate resource region %d"
502 " of device %s\n", idx
, pci_name(dev
));
504 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n",
505 pr
, pr
->start
, pr
->end
, pr
->flags
);
506 /* We'll assign a new address later */
507 r
->flags
|= IORESOURCE_UNSET
;
514 pcibios_allocate_resources(int pass
)
516 struct pci_dev
*dev
= NULL
;
521 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
522 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
523 for (idx
= 0; idx
< 6; idx
++) {
524 r
= &dev
->resource
[idx
];
525 if (r
->parent
) /* Already allocated */
527 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
528 continue; /* Not assigned at all */
529 if (r
->flags
& IORESOURCE_IO
)
530 disabled
= !(command
& PCI_COMMAND_IO
);
532 disabled
= !(command
& PCI_COMMAND_MEMORY
);
533 if (pass
== disabled
)
534 alloc_resource(dev
, idx
);
538 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
539 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
540 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
542 DBG("PCI: Switching off ROM of %s\n", pci_name(dev
));
543 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
544 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
545 pci_write_config_dword(dev
, dev
->rom_base_reg
,
546 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
552 pcibios_assign_resources(void)
554 struct pci_dev
*dev
= NULL
;
558 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
559 int class = dev
->class >> 8;
561 /* Don't touch classless devices and host bridges */
562 if (!class || class == PCI_CLASS_BRIDGE_HOST
)
565 for (idx
= 0; idx
< 6; idx
++) {
566 r
= &dev
->resource
[idx
];
569 * We shall assign a new address to this resource,
570 * either because the BIOS (sic) forgot to do so
571 * or because we have decided the old address was
572 * unusable for some reason.
574 if ((r
->flags
& IORESOURCE_UNSET
) && r
->end
&&
575 (!ppc_md
.pcibios_enable_device_hook
||
576 !ppc_md
.pcibios_enable_device_hook(dev
, 1))) {
577 r
->flags
&= ~IORESOURCE_UNSET
;
578 pci_assign_resource(dev
, idx
);
582 #if 0 /* don't assign ROMs */
583 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
587 pci_assign_resource(dev
, PCI_ROM_RESOURCE
);
594 pcibios_enable_resources(struct pci_dev
*dev
, int mask
)
600 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
602 for (idx
=0; idx
<6; idx
++) {
603 /* Only set up the requested stuff */
604 if (!(mask
& (1<<idx
)))
607 r
= &dev
->resource
[idx
];
608 if (r
->flags
& IORESOURCE_UNSET
) {
609 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", pci_name(dev
));
612 if (r
->flags
& IORESOURCE_IO
)
613 cmd
|= PCI_COMMAND_IO
;
614 if (r
->flags
& IORESOURCE_MEM
)
615 cmd
|= PCI_COMMAND_MEMORY
;
617 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
618 cmd
|= PCI_COMMAND_MEMORY
;
619 if (cmd
!= old_cmd
) {
620 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev
), old_cmd
, cmd
);
621 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
626 static int next_controller_index
;
628 struct pci_controller
* __init
629 pcibios_alloc_controller(void)
631 struct pci_controller
*hose
;
633 hose
= (struct pci_controller
*)alloc_bootmem(sizeof(*hose
));
634 memset(hose
, 0, sizeof(struct pci_controller
));
637 hose_tail
= &hose
->next
;
639 hose
->index
= next_controller_index
++;
646 * Functions below are used on OpenFirmware machines.
649 make_one_node_map(struct device_node
* node
, u8 pci_bus
)
654 if (pci_bus
>= pci_bus_count
)
656 bus_range
= (int *) get_property(node
, "bus-range", &len
);
657 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
658 printk(KERN_WARNING
"Can't get bus-range for %s, "
659 "assuming it starts at 0\n", node
->full_name
);
660 pci_to_OF_bus_map
[pci_bus
] = 0;
662 pci_to_OF_bus_map
[pci_bus
] = bus_range
[0];
664 for (node
=node
->child
; node
!= 0;node
= node
->sibling
) {
666 unsigned int *class_code
, *reg
;
668 class_code
= (unsigned int *) get_property(node
, "class-code", NULL
);
669 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
670 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
672 reg
= (unsigned int *)get_property(node
, "reg", NULL
);
675 dev
= pci_find_slot(pci_bus
, ((reg
[0] >> 8) & 0xff));
676 if (!dev
|| !dev
->subordinate
)
678 make_one_node_map(node
, dev
->subordinate
->number
);
683 pcibios_make_OF_bus_map(void)
686 struct pci_controller
* hose
;
689 pci_to_OF_bus_map
= (u8
*)kmalloc(pci_bus_count
, GFP_KERNEL
);
690 if (!pci_to_OF_bus_map
) {
691 printk(KERN_ERR
"Can't allocate OF bus map !\n");
695 /* We fill the bus map with invalid values, that helps
698 for (i
=0; i
<pci_bus_count
; i
++)
699 pci_to_OF_bus_map
[i
] = 0xff;
701 /* For each hose, we begin searching bridges */
702 for(hose
=hose_head
; hose
; hose
=hose
->next
) {
703 struct device_node
* node
;
704 node
= (struct device_node
*)hose
->arch_data
;
707 make_one_node_map(node
, hose
->first_busno
);
709 of_prop_map
= get_property(find_path_device("/"), "pci-OF-bus-map", NULL
);
711 memcpy(of_prop_map
, pci_to_OF_bus_map
, pci_bus_count
);
713 printk("PCI->OF bus map:\n");
714 for (i
=0; i
<pci_bus_count
; i
++) {
715 if (pci_to_OF_bus_map
[i
] == 0xff)
717 printk("%d -> %d\n", i
, pci_to_OF_bus_map
[i
]);
722 typedef int (*pci_OF_scan_iterator
)(struct device_node
* node
, void* data
);
724 static struct device_node
*
725 scan_OF_pci_childs(struct device_node
* node
, pci_OF_scan_iterator filter
, void* data
)
727 struct device_node
* sub_node
;
729 for (; node
!= 0;node
= node
->sibling
) {
730 unsigned int *class_code
;
732 if (filter(node
, data
))
735 /* For PCI<->PCI bridges or CardBus bridges, we go down
736 * Note: some OFs create a parent node "multifunc-device" as
737 * a fake root for all functions of a multi-function device,
738 * we go down them as well.
740 class_code
= (unsigned int *) get_property(node
, "class-code", NULL
);
741 if ((!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
742 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
)) &&
743 strcmp(node
->name
, "multifunc-device"))
745 sub_node
= scan_OF_pci_childs(node
->child
, filter
, data
);
753 scan_OF_pci_childs_iterator(struct device_node
* node
, void* data
)
756 u8
* fdata
= (u8
*)data
;
758 reg
= (unsigned int *) get_property(node
, "reg", NULL
);
759 if (reg
&& ((reg
[0] >> 8) & 0xff) == fdata
[1]
760 && ((reg
[0] >> 16) & 0xff) == fdata
[0])
765 static struct device_node
*
766 scan_OF_childs_for_device(struct device_node
* node
, u8 bus
, u8 dev_fn
)
768 u8 filter_data
[2] = {bus
, dev_fn
};
770 return scan_OF_pci_childs(node
, scan_OF_pci_childs_iterator
, filter_data
);
774 * Scans the OF tree for a device node matching a PCI device
777 pci_busdev_to_OF_node(struct pci_bus
*bus
, int devfn
)
779 struct pci_controller
*hose
;
780 struct device_node
*node
;
786 /* Lookup the hose */
788 hose
= pci_bus_to_hose(busnr
);
792 /* Check it has an OF node associated */
793 node
= (struct device_node
*) hose
->arch_data
;
797 /* Fixup bus number according to what OF think it is. */
798 #ifdef CONFIG_PPC_PMAC
799 /* The G5 need a special case here. Basically, we don't remap all
800 * busses on it so we don't create the pci-OF-map. However, we do
801 * remap the AGP bus and so have to deal with it. A future better
802 * fix has to be done by making the remapping per-host and always
803 * filling the pci_to_OF map. --BenH
805 if (_machine
== _MACH_Pmac
&& busnr
>= 0xf0)
809 if (pci_to_OF_bus_map
)
810 busnr
= pci_to_OF_bus_map
[busnr
];
814 /* Now, lookup childs of the hose */
815 return scan_OF_childs_for_device(node
->child
, busnr
, devfn
);
817 EXPORT_SYMBOL(pci_busdev_to_OF_node
);
820 pci_device_to_OF_node(struct pci_dev
*dev
)
822 return pci_busdev_to_OF_node(dev
->bus
, dev
->devfn
);
824 EXPORT_SYMBOL(pci_device_to_OF_node
);
826 /* This routine is meant to be used early during boot, when the
827 * PCI bus numbers have not yet been assigned, and you need to
828 * issue PCI config cycles to an OF device.
829 * It could also be used to "fix" RTAS config cycles if you want
830 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
833 struct pci_controller
*
834 pci_find_hose_for_OF_device(struct device_node
* node
)
839 struct pci_controller
* hose
;
840 for (hose
=hose_head
;hose
;hose
=hose
->next
)
841 if (hose
->arch_data
== node
)
849 find_OF_pci_device_filter(struct device_node
* node
, void* data
)
851 return ((void *)node
== data
);
855 * Returns the PCI device matching a given OF node
858 pci_device_from_OF_node(struct device_node
* node
, u8
* bus
, u8
* devfn
)
861 struct pci_controller
* hose
;
862 struct pci_dev
* dev
= NULL
;
866 /* Make sure it's really a PCI device */
867 hose
= pci_find_hose_for_OF_device(node
);
868 if (!hose
|| !hose
->arch_data
)
870 if (!scan_OF_pci_childs(((struct device_node
*)hose
->arch_data
)->child
,
871 find_OF_pci_device_filter
, (void *)node
))
873 reg
= (unsigned int *) get_property(node
, "reg", NULL
);
876 *bus
= (reg
[0] >> 16) & 0xff;
877 *devfn
= ((reg
[0] >> 8) & 0xff);
879 /* Ok, here we need some tweak. If we have already renumbered
880 * all busses, we can't rely on the OF bus number any more.
881 * the pci_to_OF_bus_map is not enough as several PCI busses
882 * may match the same OF bus number.
884 if (!pci_to_OF_bus_map
)
886 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
887 if (pci_to_OF_bus_map
[dev
->bus
->number
] != *bus
)
889 if (dev
->devfn
!= *devfn
)
891 *bus
= dev
->bus
->number
;
896 EXPORT_SYMBOL(pci_device_from_OF_node
);
899 pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
900 struct device_node
*dev
, int primary
)
902 static unsigned int static_lc_ranges
[256] __initdata
;
903 unsigned int *dt_ranges
, *lc_ranges
, *ranges
, *prev
;
905 int rlen
= 0, orig_rlen
;
907 struct resource
*res
;
908 int np
, na
= prom_n_addr_cells(dev
);
911 /* First we try to merge ranges to fix a problem with some pmacs
912 * that can have more than 3 ranges, fortunately using contiguous
915 dt_ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
918 /* Sanity check, though hopefully that never happens */
919 if (rlen
> sizeof(static_lc_ranges
)) {
920 printk(KERN_WARNING
"OF ranges property too large !\n");
921 rlen
= sizeof(static_lc_ranges
);
923 lc_ranges
= static_lc_ranges
;
924 memcpy(lc_ranges
, dt_ranges
, rlen
);
927 /* Let's work on a copy of the "ranges" property instead of damaging
928 * the device-tree image in memory
932 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
934 if (prev
[0] == ranges
[0] && prev
[1] == ranges
[1] &&
935 (prev
[2] + prev
[na
+4]) == ranges
[2] &&
936 (prev
[na
+2] + prev
[na
+4]) == ranges
[na
+2]) {
937 prev
[na
+4] += ranges
[na
+4];
948 * The ranges property is laid out as an array of elements,
949 * each of which comprises:
950 * cells 0 - 2: a PCI address
951 * cells 3 or 3+4: a CPU physical address
952 * (size depending on dev->n_addr_cells)
953 * cells 4+5 or 5+6: the size of the range
957 while (ranges
&& (rlen
-= np
* sizeof(unsigned int)) >= 0) {
960 switch (ranges
[0] >> 24) {
961 case 1: /* I/O space */
964 hose
->io_base_phys
= ranges
[na
+2];
965 /* limit I/O space to 16MB */
966 if (size
> 0x01000000)
968 hose
->io_base_virt
= ioremap(ranges
[na
+2], size
);
970 isa_io_base
= (unsigned long) hose
->io_base_virt
;
971 res
= &hose
->io_resource
;
972 res
->flags
= IORESOURCE_IO
;
973 res
->start
= ranges
[2];
975 case 2: /* memory space */
977 if (ranges
[1] == 0 && ranges
[2] == 0
978 && ranges
[na
+4] <= (16 << 20)) {
979 /* 1st 16MB, i.e. ISA memory area */
981 isa_mem_base
= ranges
[na
+2];
984 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
987 hose
->pci_mem_offset
= ranges
[na
+2] - ranges
[2];
989 res
= &hose
->mem_resources
[memno
];
990 res
->flags
= IORESOURCE_MEM
;
991 res
->start
= ranges
[na
+2];
996 res
->name
= dev
->full_name
;
997 res
->end
= res
->start
+ size
- 1;
1006 /* We create the "pci-OF-bus-map" property now so it appears in the
1010 pci_create_OF_bus_map(void)
1012 struct property
* of_prop
;
1014 of_prop
= (struct property
*) alloc_bootmem(sizeof(struct property
) + 256);
1015 if (of_prop
&& find_path_device("/")) {
1016 memset(of_prop
, -1, sizeof(struct property
) + 256);
1017 of_prop
->name
= "pci-OF-bus-map";
1018 of_prop
->length
= 256;
1019 of_prop
->value
= (unsigned char *)&of_prop
[1];
1020 prom_add_property(find_path_device("/"), of_prop
);
1024 static ssize_t
pci_show_devspec(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1026 struct pci_dev
*pdev
;
1027 struct device_node
*np
;
1029 pdev
= to_pci_dev (dev
);
1030 np
= pci_device_to_OF_node(pdev
);
1031 if (np
== NULL
|| np
->full_name
== NULL
)
1033 return sprintf(buf
, "%s", np
->full_name
);
1035 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
1037 #else /* CONFIG_PPC_OF */
1038 void pcibios_make_OF_bus_map(void)
1041 #endif /* CONFIG_PPC_OF */
1043 /* Add sysfs properties */
1044 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
1046 #ifdef CONFIG_PPC_OF
1047 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
1048 #endif /* CONFIG_PPC_OF */
1052 #ifdef CONFIG_PPC_PMAC
1054 * This set of routines checks for PCI<->PCI bridges that have closed
1055 * IO resources and have child devices. It tries to re-open an IO
1058 * This is a _temporary_ fix to workaround a problem with Apple's OF
1059 * closing IO windows on P2P bridges when the OF drivers of cards
1060 * below this bridge don't claim any IO range (typically ATI or
1063 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1064 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1065 * ordering when creating the host bus resources, and maybe a few more
1069 /* Initialize bridges with base/limit values we have collected */
1071 do_update_p2p_io_resource(struct pci_bus
*bus
, int enable_vga
)
1073 struct pci_dev
*bridge
= bus
->self
;
1074 struct pci_controller
* hose
= (struct pci_controller
*)bridge
->sysdata
;
1077 struct resource res
;
1079 if (bus
->resource
[0] == NULL
)
1081 res
= *(bus
->resource
[0]);
1083 DBG("Remapping Bus %d, bridge: %s\n", bus
->number
, pci_name(bridge
));
1084 res
.start
-= ((unsigned long) hose
->io_base_virt
- isa_io_base
);
1085 res
.end
-= ((unsigned long) hose
->io_base_virt
- isa_io_base
);
1086 DBG(" IO window: %08lx-%08lx\n", res
.start
, res
.end
);
1088 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1089 pci_read_config_dword(bridge
, PCI_IO_BASE
, &l
);
1091 l
|= (res
.start
>> 8) & 0x00f0;
1092 l
|= res
.end
& 0xf000;
1093 pci_write_config_dword(bridge
, PCI_IO_BASE
, l
);
1095 if ((l
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
1096 l
= (res
.start
>> 16) | (res
.end
& 0xffff0000);
1097 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, l
);
1100 pci_read_config_word(bridge
, PCI_COMMAND
, &w
);
1101 w
|= PCI_COMMAND_IO
;
1102 pci_write_config_word(bridge
, PCI_COMMAND
, w
);
1104 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1106 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
, &w
);
1107 w
|= PCI_BRIDGE_CTL_VGA
;
1108 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
, w
);
1113 /* This function is pretty basic and actually quite broken for the
1114 * general case, it's enough for us right now though. It's supposed
1115 * to tell us if we need to open an IO range at all or not and what
1119 check_for_io_childs(struct pci_bus
*bus
, struct resource
* res
, int *found_vga
)
1121 struct pci_dev
*dev
;
1125 #define push_end(res, size) do { unsigned long __sz = (size) ; \
1126 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \
1129 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1130 u16
class = dev
->class >> 8;
1132 if (class == PCI_CLASS_DISPLAY_VGA
||
1133 class == PCI_CLASS_NOT_DEFINED_VGA
)
1135 if (class >> 8 == PCI_BASE_CLASS_BRIDGE
&& dev
->subordinate
)
1136 rc
|= check_for_io_childs(dev
->subordinate
, res
, found_vga
);
1137 if (class == PCI_CLASS_BRIDGE_CARDBUS
)
1138 push_end(res
, 0xfff);
1140 for (i
=0; i
<PCI_NUM_RESOURCES
; i
++) {
1142 unsigned long r_size
;
1144 if (dev
->class >> 8 == PCI_CLASS_BRIDGE_PCI
1145 && i
>= PCI_BRIDGE_RESOURCES
)
1147 r
= &dev
->resource
[i
];
1148 r_size
= r
->end
- r
->start
;
1151 if (r
->flags
& IORESOURCE_IO
&& (r_size
) != 0) {
1153 push_end(res
, r_size
);
1161 /* Here we scan all P2P bridges of a given level that have a closed
1162 * IO window. Note that the test for the presence of a VGA card should
1163 * be improved to take into account already configured P2P bridges,
1164 * currently, we don't see them and might end up configuring 2 bridges
1165 * with VGA pass through enabled
1168 do_fixup_p2p_level(struct pci_bus
*bus
)
1174 for (parent_io
=0; parent_io
<4; parent_io
++)
1175 if (bus
->resource
[parent_io
]
1176 && bus
->resource
[parent_io
]->flags
& IORESOURCE_IO
)
1181 list_for_each_entry(b
, &bus
->children
, node
) {
1182 struct pci_dev
*d
= b
->self
;
1183 struct pci_controller
* hose
= (struct pci_controller
*)d
->sysdata
;
1184 struct resource
*res
= b
->resource
[0];
1185 struct resource tmp_res
;
1189 memset(&tmp_res
, 0, sizeof(tmp_res
));
1190 tmp_res
.start
= bus
->resource
[parent_io
]->start
;
1192 /* We don't let low addresses go through that closed P2P bridge, well,
1193 * that may not be necessary but I feel safer that way
1195 if (tmp_res
.start
== 0)
1196 tmp_res
.start
= 0x1000;
1198 if (!list_empty(&b
->devices
) && res
&& res
->flags
== 0 &&
1199 res
!= bus
->resource
[parent_io
] &&
1200 (d
->class >> 8) == PCI_CLASS_BRIDGE_PCI
&&
1201 check_for_io_childs(b
, &tmp_res
, &found_vga
)) {
1204 printk(KERN_INFO
"Fixing up IO bus %s\n", b
->name
);
1208 printk(KERN_WARNING
"Skipping VGA, already active"
1209 " on bus segment\n");
1214 pci_read_config_byte(d
, PCI_IO_BASE
, &io_base_lo
);
1216 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
)
1217 max
= ((unsigned long) hose
->io_base_virt
1218 - isa_io_base
) + 0xffffffff;
1220 max
= ((unsigned long) hose
->io_base_virt
1221 - isa_io_base
) + 0xffff;
1224 res
->flags
= IORESOURCE_IO
;
1225 res
->name
= b
->name
;
1227 /* Find a resource in the parent where we can allocate */
1228 for (i
= 0 ; i
< 4; i
++) {
1229 struct resource
*r
= bus
->resource
[i
];
1232 if ((r
->flags
& IORESOURCE_IO
) == 0)
1234 DBG("Trying to allocate from %08lx, size %08lx from parent"
1235 " res %d: %08lx -> %08lx\n",
1236 res
->start
, res
->end
, i
, r
->start
, r
->end
);
1238 if (allocate_resource(r
, res
, res
->end
+ 1, res
->start
, max
,
1239 res
->end
+ 1, NULL
, NULL
) < 0) {
1243 do_update_p2p_io_resource(b
, found_vga
);
1247 do_fixup_p2p_level(b
);
1252 pcibios_fixup_p2p_bridges(void)
1256 list_for_each_entry(b
, &pci_root_buses
, node
)
1257 do_fixup_p2p_level(b
);
1260 #endif /* CONFIG_PPC_PMAC */
1265 struct pci_controller
*hose
;
1266 struct pci_bus
*bus
;
1269 printk(KERN_INFO
"PCI: Probing PCI hardware\n");
1271 /* Scan all of the recorded PCI controllers. */
1272 for (next_busno
= 0, hose
= hose_head
; hose
; hose
= hose
->next
) {
1273 if (pci_assign_all_buses
)
1274 hose
->first_busno
= next_busno
;
1275 hose
->last_busno
= 0xff;
1276 bus
= pci_scan_bus(hose
->first_busno
, hose
->ops
, hose
);
1277 hose
->last_busno
= bus
->subordinate
;
1278 if (pci_assign_all_buses
|| next_busno
<= hose
->last_busno
)
1279 next_busno
= hose
->last_busno
+ pcibios_assign_bus_offset
;
1281 pci_bus_count
= next_busno
;
1283 /* OpenFirmware based machines need a map of OF bus
1284 * numbers vs. kernel bus numbers since we may have to
1287 if (pci_assign_all_buses
&& have_of
)
1288 pcibios_make_OF_bus_map();
1290 /* Do machine dependent PCI interrupt routing */
1291 if (ppc_md
.pci_swizzle
&& ppc_md
.pci_map_irq
)
1292 pci_fixup_irqs(ppc_md
.pci_swizzle
, ppc_md
.pci_map_irq
);
1294 /* Call machine dependent fixup */
1295 if (ppc_md
.pcibios_fixup
)
1296 ppc_md
.pcibios_fixup();
1298 /* Allocate and assign resources */
1299 pcibios_allocate_bus_resources(&pci_root_buses
);
1300 pcibios_allocate_resources(0);
1301 pcibios_allocate_resources(1);
1302 #ifdef CONFIG_PPC_PMAC
1303 pcibios_fixup_p2p_bridges();
1304 #endif /* CONFIG_PPC_PMAC */
1305 pcibios_assign_resources();
1307 /* Call machine dependent post-init code */
1308 if (ppc_md
.pcibios_after_init
)
1309 ppc_md
.pcibios_after_init();
1314 subsys_initcall(pcibios_init
);
1316 unsigned char __init
1317 common_swizzle(struct pci_dev
*dev
, unsigned char *pinp
)
1319 struct pci_controller
*hose
= dev
->sysdata
;
1321 if (dev
->bus
->number
!= hose
->first_busno
) {
1324 pin
= bridge_swizzle(pin
, PCI_SLOT(dev
->devfn
));
1325 /* Move up the chain of bridges. */
1326 dev
= dev
->bus
->self
;
1327 } while (dev
->bus
->self
);
1330 /* The slot is the idsel of the last bridge. */
1332 return PCI_SLOT(dev
->devfn
);
1335 unsigned long resource_fixup(struct pci_dev
* dev
, struct resource
* res
,
1336 unsigned long start
, unsigned long size
)
1341 void __init
pcibios_fixup_bus(struct pci_bus
*bus
)
1343 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
1344 unsigned long io_offset
;
1345 struct resource
*res
;
1348 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1349 if (bus
->parent
== NULL
) {
1350 /* This is a host bridge - fill in its resources */
1353 bus
->resource
[0] = res
= &hose
->io_resource
;
1356 printk(KERN_ERR
"I/O resource not set for host"
1357 " bridge %d\n", hose
->index
);
1359 res
->end
= IO_SPACE_LIMIT
;
1360 res
->flags
= IORESOURCE_IO
;
1362 res
->start
+= io_offset
;
1363 res
->end
+= io_offset
;
1365 for (i
= 0; i
< 3; ++i
) {
1366 res
= &hose
->mem_resources
[i
];
1370 printk(KERN_ERR
"Memory resource not set for "
1371 "host bridge %d\n", hose
->index
);
1372 res
->start
= hose
->pci_mem_offset
;
1374 res
->flags
= IORESOURCE_MEM
;
1376 bus
->resource
[i
+1] = res
;
1379 /* This is a subordinate bridge */
1380 pci_read_bridge_bases(bus
);
1382 for (i
= 0; i
< 4; ++i
) {
1383 if ((res
= bus
->resource
[i
]) == NULL
)
1387 if (io_offset
&& (res
->flags
& IORESOURCE_IO
)) {
1388 res
->start
+= io_offset
;
1389 res
->end
+= io_offset
;
1390 } else if (hose
->pci_mem_offset
1391 && (res
->flags
& IORESOURCE_MEM
)) {
1392 res
->start
+= hose
->pci_mem_offset
;
1393 res
->end
+= hose
->pci_mem_offset
;
1398 if (ppc_md
.pcibios_fixup_bus
)
1399 ppc_md
.pcibios_fixup_bus(bus
);
1402 char __init
*pcibios_setup(char *str
)
1407 /* the next one is stolen from the alpha port... */
1409 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
1411 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
1412 /* XXX FIXME - update OF device tree node interrupt property */
1415 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1421 if (ppc_md
.pcibios_enable_device_hook
)
1422 if (ppc_md
.pcibios_enable_device_hook(dev
, 0))
1425 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1427 for (idx
=0; idx
<6; idx
++) {
1428 r
= &dev
->resource
[idx
];
1429 if (r
->flags
& IORESOURCE_UNSET
) {
1430 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", pci_name(dev
));
1433 if (r
->flags
& IORESOURCE_IO
)
1434 cmd
|= PCI_COMMAND_IO
;
1435 if (r
->flags
& IORESOURCE_MEM
)
1436 cmd
|= PCI_COMMAND_MEMORY
;
1438 if (cmd
!= old_cmd
) {
1439 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1440 pci_name(dev
), old_cmd
, cmd
);
1441 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1446 struct pci_controller
*
1447 pci_bus_to_hose(int bus
)
1449 struct pci_controller
* hose
= hose_head
;
1451 for (; hose
; hose
= hose
->next
)
1452 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
1458 pci_bus_io_base(unsigned int bus
)
1460 struct pci_controller
*hose
;
1462 hose
= pci_bus_to_hose(bus
);
1465 return hose
->io_base_virt
;
1469 pci_bus_io_base_phys(unsigned int bus
)
1471 struct pci_controller
*hose
;
1473 hose
= pci_bus_to_hose(bus
);
1476 return hose
->io_base_phys
;
1480 pci_bus_mem_base_phys(unsigned int bus
)
1482 struct pci_controller
*hose
;
1484 hose
= pci_bus_to_hose(bus
);
1487 return hose
->pci_mem_offset
;
1491 pci_resource_to_bus(struct pci_dev
*pdev
, struct resource
*res
)
1493 /* Hack alert again ! See comments in chrp_pci.c
1495 struct pci_controller
* hose
=
1496 (struct pci_controller
*)pdev
->sysdata
;
1497 if (hose
&& res
->flags
& IORESOURCE_MEM
)
1498 return res
->start
- hose
->pci_mem_offset
;
1499 /* We may want to do something with IOs here... */
1504 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
1505 unsigned long *offset
,
1506 enum pci_mmap_state mmap_state
)
1508 struct pci_controller
*hose
= pci_bus_to_hose(dev
->bus
->number
);
1509 unsigned long io_offset
= 0;
1513 return NULL
; /* should never happen */
1515 /* If memory, add on the PCI bridge address offset */
1516 if (mmap_state
== pci_mmap_mem
) {
1517 *offset
+= hose
->pci_mem_offset
;
1518 res_bit
= IORESOURCE_MEM
;
1520 io_offset
= hose
->io_base_virt
- ___IO_BASE
;
1521 *offset
+= io_offset
;
1522 res_bit
= IORESOURCE_IO
;
1526 * Check that the offset requested corresponds to one of the
1527 * resources of the device.
1529 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
1530 struct resource
*rp
= &dev
->resource
[i
];
1531 int flags
= rp
->flags
;
1533 /* treat ROM as memory (should be already) */
1534 if (i
== PCI_ROM_RESOURCE
)
1535 flags
|= IORESOURCE_MEM
;
1537 /* Active and same type? */
1538 if ((flags
& res_bit
) == 0)
1541 /* In the range of this resource? */
1542 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
1545 /* found it! construct the final physical address */
1546 if (mmap_state
== pci_mmap_io
)
1547 *offset
+= hose
->io_base_phys
- io_offset
;
1555 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1558 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
1559 pgprot_t protection
,
1560 enum pci_mmap_state mmap_state
,
1563 unsigned long prot
= pgprot_val(protection
);
1565 /* Write combine is always 0 on non-memory space mappings. On
1566 * memory space, if the user didn't pass 1, we check for a
1567 * "prefetchable" resource. This is a bit hackish, but we use
1568 * this to workaround the inability of /sysfs to provide a write
1571 if (mmap_state
!= pci_mmap_mem
)
1573 else if (write_combine
== 0) {
1574 if (rp
->flags
& IORESOURCE_PREFETCH
)
1578 /* XXX would be nice to have a way to ask for write-through */
1579 prot
|= _PAGE_NO_CACHE
;
1581 prot
&= ~_PAGE_GUARDED
;
1583 prot
|= _PAGE_GUARDED
;
1585 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
1588 return __pgprot(prot
);
1592 * This one is used by /dev/mem and fbdev who have no clue about the
1593 * PCI device, it tries to find the PCI device first and calls the
1596 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
1599 pgprot_t protection
)
1601 struct pci_dev
*pdev
= NULL
;
1602 struct resource
*found
= NULL
;
1603 unsigned long prot
= pgprot_val(protection
);
1604 unsigned long offset
= pfn
<< PAGE_SHIFT
;
1607 if (page_is_ram(pfn
))
1610 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
1612 for_each_pci_dev(pdev
) {
1613 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
1614 struct resource
*rp
= &pdev
->resource
[i
];
1615 int flags
= rp
->flags
;
1617 /* Active and same type? */
1618 if ((flags
& IORESOURCE_MEM
) == 0)
1620 /* In the range of this resource? */
1621 if (offset
< (rp
->start
& PAGE_MASK
) ||
1631 if (found
->flags
& IORESOURCE_PREFETCH
)
1632 prot
&= ~_PAGE_GUARDED
;
1636 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
1638 return __pgprot(prot
);
1643 * Perform the actual remap of the pages for a PCI device mapping, as
1644 * appropriate for this architecture. The region in the process to map
1645 * is described by vm_start and vm_end members of VMA, the base physical
1646 * address is found in vm_pgoff.
1647 * The pci device structure is provided so that architectures may make mapping
1648 * decisions on a per-device or per-bus basis.
1650 * Returns a negative error code on failure, zero on success.
1652 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1653 enum pci_mmap_state mmap_state
,
1656 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
1657 struct resource
*rp
;
1660 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
1664 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
1665 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
1666 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
1668 mmap_state
, write_combine
);
1670 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
1671 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
1676 /* Obsolete functions. Should be removed once the symbios driver
1680 phys_to_bus(unsigned long pa
)
1682 struct pci_controller
*hose
;
1685 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
1686 for (i
= 0; i
< 3; ++i
) {
1687 if (pa
>= hose
->mem_resources
[i
].start
1688 && pa
<= hose
->mem_resources
[i
].end
) {
1690 * XXX the hose->pci_mem_offset really
1691 * only applies to mem_resources[0].
1692 * We need a way to store an offset for
1693 * the others. -- paulus
1696 pa
-= hose
->pci_mem_offset
;
1701 /* hmmm, didn't find it */
1706 pci_phys_to_bus(unsigned long pa
, int busnr
)
1708 struct pci_controller
* hose
= pci_bus_to_hose(busnr
);
1711 return pa
- hose
->pci_mem_offset
;
1715 pci_bus_to_phys(unsigned int ba
, int busnr
)
1717 struct pci_controller
* hose
= pci_bus_to_hose(busnr
);
1720 return ba
+ hose
->pci_mem_offset
;
1723 /* Provide information on locations of various I/O regions in physical
1724 * memory. Do this on a per-card basis so that we choose the right
1726 * Note that the returned IO or memory base is a physical address
1729 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
1731 struct pci_controller
* hose
;
1732 long result
= -EOPNOTSUPP
;
1734 /* Argh ! Please forgive me for that hack, but that's the
1735 * simplest way to get existing XFree to not lockup on some
1736 * G5 machines... So when something asks for bus 0 io base
1737 * (bus 0 is HT root), we return the AGP one instead.
1739 #ifdef CONFIG_PPC_PMAC
1740 if (_machine
== _MACH_Pmac
&& machine_is_compatible("MacRISC4"))
1743 #endif /* CONFIG_PPC_PMAC */
1745 hose
= pci_bus_to_hose(bus
);
1750 case IOBASE_BRIDGE_NUMBER
:
1751 return (long)hose
->first_busno
;
1753 return (long)hose
->pci_mem_offset
;
1755 return (long)hose
->io_base_phys
;
1757 return (long)isa_io_base
;
1758 case IOBASE_ISA_MEM
:
1759 return (long)isa_mem_base
;
1765 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1766 const struct resource
*rsrc
,
1767 u64
*start
, u64
*end
)
1769 struct pci_controller
*hose
= pci_bus_to_hose(dev
->bus
->number
);
1770 unsigned long offset
= 0;
1775 if (rsrc
->flags
& IORESOURCE_IO
)
1776 offset
= ___IO_BASE
- hose
->io_base_virt
+ hose
->io_base_phys
;
1778 *start
= rsrc
->start
+ offset
;
1779 *end
= rsrc
->end
+ offset
;
1783 pci_init_resource(struct resource
*res
, unsigned long start
, unsigned long end
,
1784 int flags
, char *name
)
1791 res
->sibling
= NULL
;
1795 void __iomem
*pci_iomap(struct pci_dev
*dev
, int bar
, unsigned long max
)
1797 unsigned long start
= pci_resource_start(dev
, bar
);
1798 unsigned long len
= pci_resource_len(dev
, bar
);
1799 unsigned long flags
= pci_resource_flags(dev
, bar
);
1803 if (max
&& len
> max
)
1805 if (flags
& IORESOURCE_IO
)
1806 return ioport_map(start
, len
);
1807 if (flags
& IORESOURCE_MEM
)
1808 /* Not checking IORESOURCE_CACHEABLE because PPC does
1809 * not currently distinguish between ioremap and
1812 return ioremap(start
, len
);
1817 void pci_iounmap(struct pci_dev
*dev
, void __iomem
*addr
)
1821 EXPORT_SYMBOL(pci_iomap
);
1822 EXPORT_SYMBOL(pci_iounmap
);
1826 * Null PCI config access functions, for the case when we can't
1829 #define NULL_PCI_OP(rw, size, type) \
1831 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1833 return PCIBIOS_DEVICE_NOT_FOUND; \
1837 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1840 return PCIBIOS_DEVICE_NOT_FOUND
;
1844 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1847 return PCIBIOS_DEVICE_NOT_FOUND
;
1850 static struct pci_ops null_pci_ops
=
1857 * These functions are used early on before PCI scanning is done
1858 * and all of the pci_dev and pci_bus structures have been created.
1860 static struct pci_bus
*
1861 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1863 static struct pci_bus bus
;
1866 hose
= pci_bus_to_hose(busnr
);
1868 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1872 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1876 #define EARLY_PCI_OP(rw, size, type) \
1877 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1878 int devfn, int offset, type value) \
1880 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1881 devfn, offset, value); \
1884 EARLY_PCI_OP(read
, byte
, u8
*)
1885 EARLY_PCI_OP(read
, word
, u16
*)
1886 EARLY_PCI_OP(read
, dword
, u32
*)
1887 EARLY_PCI_OP(write
, byte
, u8
)
1888 EARLY_PCI_OP(write
, word
, u16
)
1889 EARLY_PCI_OP(write
, dword
, u32
)