drivers/net/irda/via-ircc.h

   1 /*********************************************************************
   2  *
   3  * Filename:      via-ircc.h
   4  * Version:       1.0
   5  * Description:   Driver for the VIA VT8231/VT8233 IrDA chipsets
   6  * Author:        VIA Technologies, inc
   7  * Date  :        08/06/2003
   8
   9 Copyright (c) 1998-2003 VIA Technologies, Inc.
  10
  11 This program is free software; you can redistribute it and/or modify it under
  12 the terms of the GNU General Public License as published by the Free Software
  13 Foundation; either version 2, or (at your option) any later version.
  14
  15 This program is distributed in the hope that it will be useful, but WITHOUT
  16 ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  18 See the GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License along with
  21 this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23
  24  * Comment:
  25  * jul/08/2002 : Rx buffer length should use Rx ring ptr.
  26  * Oct/28/2002 : Add SB id for 3147 and 3177.
  27  * jul/09/2002 : only implement two kind of dongle currently.
  28  * Oct/02/2002 : work on VT8231 and VT8233 .
  29  * Aug/06/2003 : change driver format to pci driver .
  30  ********************************************************************/
  31 #ifndef via_IRCC_H
  32 #define via_IRCC_H
  33 #include <linux/time.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/pm.h>
  36 #include <linux/types.h>
  37 #include <asm/io.h>
  38
  39 #define MAX_TX_WINDOW 7
  40 #define MAX_RX_WINDOW 7
  41
  42 struct st_fifo_entry {
  43         int status;
  44         int len;
  45 };
  46
  47 struct st_fifo {
  48         struct st_fifo_entry entries[MAX_RX_WINDOW + 2];
  49         int pending_bytes;
  50         int head;
  51         int tail;
  52         int len;
  53 };
  54
  55 struct frame_cb {
  56         void *start;            /* Start of frame in DMA mem */
  57         int len;                /* Length of frame in DMA mem */
  58 };
  59
  60 struct tx_fifo {
  61         struct frame_cb queue[MAX_TX_WINDOW + 2];       /* Info about frames in queue */
  62         int ptr;                /* Currently being sent */
  63         int len;                /* Length of queue */
  64         int free;               /* Next free slot */
  65         void *tail;             /* Next free start in DMA mem */
  66 };
  67
  68
  69 struct eventflag                // for keeping track of Interrupt Events
  70 {
  71         //--------tx part
  72         unsigned char TxFIFOUnderRun;
  73         unsigned char EOMessage;
  74         unsigned char TxFIFOReady;
  75         unsigned char EarlyEOM;
  76         //--------rx part
  77         unsigned char PHYErr;
  78         unsigned char CRCErr;
  79         unsigned char RxFIFOOverRun;
  80         unsigned char EOPacket;
  81         unsigned char RxAvail;
  82         unsigned char TooLargePacket;
  83         unsigned char SIRBad;
  84         //--------unknown
  85         unsigned char Unknown;
  86         //----------
  87         unsigned char TimeOut;
  88         unsigned char RxDMATC;
  89         unsigned char TxDMATC;
  90 };
  91
  92 /* Private data for each instance */
  93 struct via_ircc_cb {
  94         struct st_fifo st_fifo; /* Info about received frames */
  95         struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
  96
  97         struct net_device *netdev;      /* Yes! we are some kind of netdevice */
  98         struct net_device_stats stats;
  99
 100         struct irlap_cb *irlap; /* The link layer we are binded to */
 101         struct qos_info qos;    /* QoS capabilities for this device */
 102
 103         chipio_t io;            /* IrDA controller information */
 104         iobuff_t tx_buff;       /* Transmit buffer */
 105         iobuff_t rx_buff;       /* Receive buffer */
 106         dma_addr_t tx_buff_dma;
 107         dma_addr_t rx_buff_dma;
 108
 109         __u8 ier;               /* Interrupt enable register */
 110
 111         struct timeval stamp;
 112         struct timeval now;
 113
 114         spinlock_t lock;        /* For serializing operations */
 115
 116         __u32 flags;            /* Interface flags */
 117         __u32 new_speed;
 118         int index;              /* Instance index */
 119
 120         struct eventflag EventFlag;
 121         unsigned int chip_id;   /* to remember chip id */
 122         unsigned int RetryCount;
 123         unsigned int RxDataReady;
 124         unsigned int RxLastCount;
 125 };
 126
 127
 128 //---------I=Infrared,  H=Host, M=Misc, T=Tx, R=Rx, ST=Status,
 129 //         CF=Config, CT=Control, L=Low, H=High, C=Count
 130 #define  I_CF_L_0               0x10
 131 #define  I_CF_H_0               0x11
 132 #define  I_SIR_BOF              0x12
 133 #define  I_SIR_EOF              0x13
 134 #define  I_ST_CT_0              0x15
 135 #define  I_ST_L_1               0x16
 136 #define  I_ST_H_1               0x17
 137 #define  I_CF_L_1               0x18
 138 #define  I_CF_H_1               0x19
 139 #define  I_CF_L_2               0x1a
 140 #define  I_CF_H_2               0x1b
 141 #define  I_CF_3         0x1e
 142 #define  H_CT                   0x20
 143 #define  H_ST                   0x21
 144 #define  M_CT                   0x22
 145 #define  TX_CT_1                0x23
 146 #define  TX_CT_2                0x24
 147 #define  TX_ST                  0x25
 148 #define  RX_CT                  0x26
 149 #define  RX_ST                  0x27
 150 #define  RESET                  0x28
 151 #define  P_ADDR         0x29
 152 #define  RX_C_L         0x2a
 153 #define  RX_C_H         0x2b
 154 #define  RX_P_L         0x2c
 155 #define  RX_P_H         0x2d
 156 #define  TX_C_L         0x2e
 157 #define  TX_C_H         0x2f
 158 #define  TIMER          0x32
 159 #define  I_CF_4                 0x33
 160 #define  I_T_C_L                0x34
 161 #define  I_T_C_H                0x35
 162 #define  VERSION                0x3f
 163 //-------------------------------
 164 #define StartAddr       0x10    // the first register address
 165 #define EndAddr         0x3f    // the last register address
 166 #define GetBit(val,bit)  val = (unsigned char) ((val>>bit) & 0x1)
 167                         // Returns the bit
 168 #define SetBit(val,bit)  val= (unsigned char ) (val | (0x1 << bit))
 169                         // Sets bit to 1
 170 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
 171                         // Sets bit to 0
 172
 173 #define OFF   0
 174 #define ON   1
 175 #define DMA_TX_MODE   0x08
 176 #define DMA_RX_MODE   0x04
 177
 178 #define DMA1   0
 179 #define DMA2   0xc0
 180 #define MASK1   DMA1+0x0a
 181 #define MASK2   DMA2+0x14
 182
 183 #define Clk_bit 0x40
 184 #define Tx_bit 0x01
 185 #define Rd_Valid 0x08
 186 #define RxBit 0x08
 187
 188 static void DisableDmaChannel(unsigned int channel)
 189 {
 190         switch (channel) {      // 8 Bit DMA channels DMAC1
 191         case 0:
 192                 outb(4, MASK1); //mask channel 0
 193                 break;
 194         case 1:
 195                 outb(5, MASK1); //Mask channel 1
 196                 break;
 197         case 2:
 198                 outb(6, MASK1); //Mask channel 2
 199                 break;
 200         case 3:
 201                 outb(7, MASK1); //Mask channel 3
 202                 break;
 203         case 5:
 204                 outb(5, MASK2); //Mask channel 5
 205                 break;
 206         case 6:
 207                 outb(6, MASK2); //Mask channel 6
 208                 break;
 209         case 7:
 210                 outb(7, MASK2); //Mask channel 7
 211                 break;
 212         default:
 213                 break;
 214         };                      //Switch
 215 }
 216
 217 static unsigned char ReadLPCReg(int iRegNum)
 218 {
 219         unsigned char iVal;
 220
 221         outb(0x87, 0x2e);
 222         outb(0x87, 0x2e);
 223         outb(iRegNum, 0x2e);
 224         iVal = inb(0x2f);
 225         outb(0xaa, 0x2e);
 226
 227         return iVal;
 228 }
 229
 230 static void WriteLPCReg(int iRegNum, unsigned char iVal)
 231 {
 232
 233         outb(0x87, 0x2e);
 234         outb(0x87, 0x2e);
 235         outb(iRegNum, 0x2e);
 236         outb(iVal, 0x2f);
 237         outb(0xAA, 0x2e);
 238 }
 239
 240 static __u8 ReadReg(unsigned int BaseAddr, int iRegNum)
 241 {
 242         return ((__u8) inb(BaseAddr + iRegNum));
 243 }
 244
 245 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
 246 {
 247         outb(iVal, BaseAddr + iRegNum);
 248 }
 249
 250 static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,
 251                 unsigned char BitPos, unsigned char value)
 252 {
 253         __u8 Rtemp, Wtemp;
 254
 255         if (BitPos > 7) {
 256                 return -1;
 257         }
 258         if ((RegNum < StartAddr) || (RegNum > EndAddr))
 259                 return -1;
 260         Rtemp = ReadReg(BaseAddr, RegNum);
 261         if (value == 0)
 262                 Wtemp = ResetBit(Rtemp, BitPos);
 263         else {
 264                 if (value == 1)
 265                         Wtemp = SetBit(Rtemp, BitPos);
 266                 else
 267                         return -1;
 268         }
 269         WriteReg(BaseAddr, RegNum, Wtemp);
 270         return 0;
 271 }
 272
 273 static __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum,
 274                  unsigned char BitPos)
 275 {
 276         __u8 temp;
 277
 278         if (BitPos > 7)
 279                 return 0xff;
 280         if ((RegNum < StartAddr) || (RegNum > EndAddr)) {
 281 //     printf("what is the register %x!\n",RegNum);
 282         }
 283         temp = ReadReg(BaseAddr, RegNum);
 284         return GetBit(temp, BitPos);
 285 }
 286
 287 static void SetMaxRxPacketSize(__u16 iobase, __u16 size)
 288 {
 289         __u16 low, high;
 290         if ((size & 0xe000) == 0) {
 291                 low = size & 0x00ff;
 292                 high = (size & 0x1f00) >> 8;
 293                 WriteReg(iobase, I_CF_L_2, low);
 294                 WriteReg(iobase, I_CF_H_2, high);
 295
 296         }
 297
 298 }
 299
 300 //for both Rx and Tx
 301
 302 static void SetFIFO(__u16 iobase, __u16 value)
 303 {
 304         switch (value) {
 305         case 128:
 306                 WriteRegBit(iobase, 0x11, 0, 0);
 307                 WriteRegBit(iobase, 0x11, 7, 1);
 308                 break;
 309         case 64:
 310                 WriteRegBit(iobase, 0x11, 0, 0);
 311                 WriteRegBit(iobase, 0x11, 7, 0);
 312                 break;
 313         case 32:
 314                 WriteRegBit(iobase, 0x11, 0, 1);
 315                 WriteRegBit(iobase, 0x11, 7, 0);
 316                 break;
 317         default:
 318                 WriteRegBit(iobase, 0x11, 0, 0);
 319                 WriteRegBit(iobase, 0x11, 7, 0);
 320         }
 321
 322 }
 323
 324 #define CRC16(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_L_0,7,val)        //0 for 32 CRC
 325 /*
 326 #define SetVFIR(BaseAddr,val)       WriteRegBit(BaseAddr,I_CF_H_0,5,val)
 327 #define SetFIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,6,val)
 328 #define SetMIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,5,val)
 329 #define SetSIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,4,val)
 330 */
 331 #define SIRFilter(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_L_0,3,val)
 332 #define Filter(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,2,val)
 333 #define InvertTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,1,val)
 334 #define InvertRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,0,val)
 335 //****************************I_CF_H_0
 336 #define EnableTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,4,val)
 337 #define EnableRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,3,val)
 338 #define EnableDMA(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_H_0,2,val)
 339 #define SIRRecvAny(BaseAddr,val)    WriteRegBit(BaseAddr,I_CF_H_0,1,val)
 340 #define DiableTrans(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_H_0,0,val)
 341 //***************************I_SIR_BOF,I_SIR_EOF
 342 #define SetSIRBOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_BOF,val)
 343 #define SetSIREOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_EOF,val)
 344 #define GetSIRBOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_BOF)
 345 #define GetSIREOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_EOF)
 346 //*******************I_ST_CT_0
 347 #define EnPhys(BaseAddr,val)   WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
 348 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO
 349 #define IsVFIROn(BaseAddr)     CheckRegBit(BaseAddr,0x14,0)     //RO for VT1211 only
 350 #define IsFIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO
 351 #define IsMIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO
 352 #define IsSIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO
 353 #define IsEnableTX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO
 354 #define IsEnableRX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO
 355 #define Is16CRC(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO
 356 //***************************I_CF_3
 357 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val)      //1 disable
 358 #define DisablePulseWidthAdjust(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_3,4,val)      //1 disable
 359 #define UseOneRX(BaseAddr,val)                  WriteRegBit(BaseAddr,I_CF_3,1,val)      //0 use two RX
 360 #define SlowIRRXLowActive(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_3,0,val)      //0 show RX high=1 in SIR
 361 //***************************H_CT
 362 #define EnAllInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,7,val)
 363 #define TXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,6,val)
 364 #define RXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,5,val)
 365 #define ClearRXInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,4,val)     // 1 clear
 366 //*****************H_ST
 367 #define IsRXInt(BaseAddr)           CheckRegBit(BaseAddr,H_ST,4)
 368 #define GetIntIndentify(BaseAddr)   ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)
 369 #define IsHostBusy(BaseAddr)        CheckRegBit(BaseAddr,H_ST,0)
 370 #define GetHostStatus(BaseAddr)     ReadReg(BaseAddr,H_ST)      //RO
 371 //**************************M_CT
 372 #define EnTXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,7,val)
 373 #define EnRXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,6,val)
 374 #define SwapDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,5,val)
 375 #define EnInternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,4,val)
 376 #define EnExternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,3,val)
 377 //**************************TX_CT_1
 378 #define EnTXFIFOHalfLevelInt(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_1,4,val)        //half empty int (1 half)
 379 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
 380 #define EnTXFIFOReadyInt(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_1,6,val)        //int when reach it threshold (setting by bit 4)
 381 //**************************TX_CT_2
 382 #define ForceUnderrun(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_2,7,val)       // force an underrun int
 383 #define EnTXCRC(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,6,val)       //1 for FIR,MIR...0 (not SIR)
 384 #define ForceBADCRC(BaseAddr,val)     WriteRegBit(BaseAddr,TX_CT_2,5,val)       //force an bad CRC
 385 #define SendSIP(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,4,val)       //send indication pulse for prevent SIR disturb
 386 #define ClearEnTX(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_2,3,val)       // opposite to EnTX
 387 //*****************TX_ST
 388 #define GetTXStatus(BaseAddr)   ReadReg(BaseAddr,TX_ST) //RO
 389 //**************************RX_CT
 390 #define EnRXSpecInt(BaseAddr,val)           WriteRegBit(BaseAddr,RX_CT,0,val)
 391 #define EnRXFIFOReadyInt(BaseAddr,val)      WriteRegBit(BaseAddr,RX_CT,1,val)   //enable int when reach it threshold (setting by bit 7)
 392 #define EnRXFIFOHalfLevelInt(BaseAddr,val)  WriteRegBit(BaseAddr,RX_CT,7,val)   //enable int when (1) half full...or (0) just not full
 393 //*****************RX_ST
 394 #define GetRXStatus(BaseAddr)   ReadReg(BaseAddr,RX_ST) //RO
 395 //***********************P_ADDR
 396 #define SetPacketAddr(BaseAddr,addr)        WriteReg(BaseAddr,P_ADDR,addr)
 397 //***********************I_CF_4
 398 #define EnGPIOtoRX2(BaseAddr,val)       WriteRegBit(BaseAddr,I_CF_4,7,val)
 399 #define EnTimerInt(BaseAddr,val)                WriteRegBit(BaseAddr,I_CF_4,1,val)
 400 #define ClearTimerInt(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_4,0,val)
 401 //***********************I_T_C_L
 402 #define WriteGIO(BaseAddr,val)      WriteRegBit(BaseAddr,I_T_C_L,7,val)
 403 #define ReadGIO(BaseAddr)                   CheckRegBit(BaseAddr,I_T_C_L,7)
 404 #define ReadRX(BaseAddr)                    CheckRegBit(BaseAddr,I_T_C_L,3)     //RO
 405 #define WriteTX(BaseAddr,val)           WriteRegBit(BaseAddr,I_T_C_L,0,val)
 406 //***********************I_T_C_H
 407 #define EnRX2(BaseAddr,val)                 WriteRegBit(BaseAddr,I_T_C_H,7,val)
 408 #define ReadRX2(BaseAddr)           CheckRegBit(BaseAddr,I_T_C_H,7)
 409 //**********************Version
 410 #define GetFIRVersion(BaseAddr)         ReadReg(BaseAddr,VERSION)
 411
 412
 413 static void SetTimer(__u16 iobase, __u8 count)
 414 {
 415         EnTimerInt(iobase, OFF);
 416         WriteReg(iobase, TIMER, count);
 417         EnTimerInt(iobase, ON);
 418 }
 419
 420
 421 static void SetSendByte(__u16 iobase, __u32 count)
 422 {
 423         __u32 low, high;
 424
 425         if ((count & 0xf000) == 0) {
 426                 low = count & 0x00ff;
 427                 high = (count & 0x0f00) >> 8;
 428                 WriteReg(iobase, TX_C_L, low);
 429                 WriteReg(iobase, TX_C_H, high);
 430         }
 431 }
 432
 433 static void ResetChip(__u16 iobase, __u8 type)
 434 {
 435         __u8 value;
 436
 437         value = (type + 2) << 4;
 438         WriteReg(iobase, RESET, type);
 439 }
 440
 441 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self)
 442 {
 443         __u8 low, high;
 444         __u16 wTmp = 0, wTmp1 = 0, wTmp_new = 0;
 445
 446         low = ReadReg(iobase, RX_C_L);
 447         high = ReadReg(iobase, RX_C_H);
 448         wTmp1 = high;
 449         wTmp = (wTmp1 << 8) | low;
 450         udelay(10);
 451         low = ReadReg(iobase, RX_C_L);
 452         high = ReadReg(iobase, RX_C_H);
 453         wTmp1 = high;
 454         wTmp_new = (wTmp1 << 8) | low;
 455         if (wTmp_new != wTmp)
 456                 return 1;
 457         else
 458                 return 0;
 459
 460 }
 461
 462 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self)
 463 {
 464         __u8 low, high;
 465         __u16 wTmp = 0, wTmp1 = 0;
 466
 467         low = ReadReg(iobase, RX_P_L);
 468         high = ReadReg(iobase, RX_P_H);
 469         wTmp1 = high;
 470         wTmp = (wTmp1 << 8) | low;
 471         return wTmp;
 472 }
 473
 474 /* This Routine can only use in recevie_complete
 475  * for it will update last count.
 476  */
 477
 478 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self)
 479 {
 480         __u8 low, high;
 481         __u16 wTmp, wTmp1, ret;
 482
 483         low = ReadReg(iobase, RX_P_L);
 484         high = ReadReg(iobase, RX_P_H);
 485         wTmp1 = high;
 486         wTmp = (wTmp1 << 8) | low;
 487
 488
 489         if (wTmp >= self->RxLastCount)
 490                 ret = wTmp - self->RxLastCount;
 491         else
 492                 ret = (0x8000 - self->RxLastCount) + wTmp;
 493         self->RxLastCount = wTmp;
 494
 495 /* RX_P is more actually the RX_C
 496  low=ReadReg(iobase,RX_C_L);
 497  high=ReadReg(iobase,RX_C_H);
 498
 499  if(!(high&0xe000)) {
 500          temp=(high<<8)+low;
 501          return temp;
 502  }
 503  else return 0;
 504 */
 505         return ret;
 506 }
 507
 508 static void Sdelay(__u16 scale)
 509 {
 510         __u8 bTmp;
 511         int i, j;
 512
 513         for (j = 0; j < scale; j++) {
 514                 for (i = 0; i < 0x20; i++) {
 515                         bTmp = inb(0xeb);
 516                         outb(bTmp, 0xeb);
 517                 }
 518         }
 519 }
 520
 521 static void Tdelay(__u16 scale)
 522 {
 523         __u8 bTmp;
 524         int i, j;
 525
 526         for (j = 0; j < scale; j++) {
 527                 for (i = 0; i < 0x50; i++) {
 528                         bTmp = inb(0xeb);
 529                         outb(bTmp, 0xeb);
 530                 }
 531         }
 532 }
 533
 534
 535 static void ActClk(__u16 iobase, __u8 value)
 536 {
 537         __u8 bTmp;
 538         bTmp = ReadReg(iobase, 0x34);
 539         if (value)
 540                 WriteReg(iobase, 0x34, bTmp | Clk_bit);
 541         else
 542                 WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
 543 }
 544
 545 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx)
 546 {
 547         __u8 bTmp;
 548
 549         bTmp = ReadReg(iobase, 0x34);
 550         if (Clk == 0)
 551                 bTmp &= ~Clk_bit;
 552         else {
 553                 if (Clk == 1)
 554                         bTmp |= Clk_bit;
 555         }
 556         WriteReg(iobase, 0x34, bTmp);
 557         Sdelay(1);
 558         if (Tx == 0)
 559                 bTmp &= ~Tx_bit;
 560         else {
 561                 if (Tx == 1)
 562                         bTmp |= Tx_bit;
 563         }
 564         WriteReg(iobase, 0x34, bTmp);
 565 }
 566
 567 static void Wr_Byte(__u16 iobase, __u8 data)
 568 {
 569         __u8 bData = data;
 570 //      __u8 btmp;
 571         int i;
 572
 573         ClkTx(iobase, 0, 1);
 574
 575         Tdelay(2);
 576         ActClk(iobase, 1);
 577         Tdelay(1);
 578
 579         for (i = 0; i < 8; i++) {       //LDN
 580
 581                 if ((bData >> i) & 0x01) {
 582                         ClkTx(iobase, 0, 1);    //bit data = 1;
 583                 } else {
 584                         ClkTx(iobase, 0, 0);    //bit data = 1;
 585                 }
 586                 Tdelay(2);
 587                 Sdelay(1);
 588                 ActClk(iobase, 1);      //clk hi
 589                 Tdelay(1);
 590         }
 591 }
 592
 593 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index)
 594 {
 595         __u8 data = 0, bTmp, data_bit;
 596         int i;
 597
 598         bTmp = addr | (index << 1) | 0;
 599         ClkTx(iobase, 0, 0);
 600         Tdelay(2);
 601         ActClk(iobase, 1);
 602         udelay(1);
 603         Wr_Byte(iobase, bTmp);
 604         Sdelay(1);
 605         ClkTx(iobase, 0, 0);
 606         Tdelay(2);
 607         for (i = 0; i < 10; i++) {
 608                 ActClk(iobase, 1);
 609                 Tdelay(1);
 610                 ActClk(iobase, 0);
 611                 Tdelay(1);
 612                 ClkTx(iobase, 0, 1);
 613                 Tdelay(1);
 614                 bTmp = ReadReg(iobase, 0x34);
 615                 if (!(bTmp & Rd_Valid))
 616                         break;
 617         }
 618         if (!(bTmp & Rd_Valid)) {
 619                 for (i = 0; i < 8; i++) {
 620                         ActClk(iobase, 1);
 621                         Tdelay(1);
 622                         ActClk(iobase, 0);
 623                         bTmp = ReadReg(iobase, 0x34);
 624                         data_bit = 1 << i;
 625                         if (bTmp & RxBit)
 626                                 data |= data_bit;
 627                         else
 628                                 data &= ~data_bit;
 629                         Tdelay(2);
 630                 }
 631         } else {
 632                 for (i = 0; i < 2; i++) {
 633                         ActClk(iobase, 1);
 634                         Tdelay(1);
 635                         ActClk(iobase, 0);
 636                         Tdelay(2);
 637                 }
 638                 bTmp = ReadReg(iobase, 0x34);
 639         }
 640         for (i = 0; i < 1; i++) {
 641                 ActClk(iobase, 1);
 642                 Tdelay(1);
 643                 ActClk(iobase, 0);
 644                 Tdelay(2);
 645         }
 646         ClkTx(iobase, 0, 0);
 647         Tdelay(1);
 648         for (i = 0; i < 3; i++) {
 649                 ActClk(iobase, 1);
 650                 Tdelay(1);
 651                 ActClk(iobase, 0);
 652                 Tdelay(2);
 653         }
 654         return data;
 655 }
 656
 657 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data)
 658 {
 659         int i;
 660         __u8 bTmp;
 661
 662         ClkTx(iobase, 0, 0);
 663         udelay(2);
 664         ActClk(iobase, 1);
 665         udelay(1);
 666         bTmp = addr | (index << 1) | 1;
 667         Wr_Byte(iobase, bTmp);
 668         Wr_Byte(iobase, data);
 669         for (i = 0; i < 2; i++) {
 670                 ClkTx(iobase, 0, 0);
 671                 Tdelay(2);
 672                 ActClk(iobase, 1);
 673                 Tdelay(1);
 674         }
 675         ActClk(iobase, 0);
 676 }
 677
 678 static void ResetDongle(__u16 iobase)
 679 {
 680         int i;
 681         ClkTx(iobase, 0, 0);
 682         Tdelay(1);
 683         for (i = 0; i < 30; i++) {
 684                 ActClk(iobase, 1);
 685                 Tdelay(1);
 686                 ActClk(iobase, 0);
 687                 Tdelay(1);
 688         }
 689         ActClk(iobase, 0);
 690 }
 691
 692 static void SetSITmode(__u16 iobase)
 693 {
 694
 695         __u8 bTmp;
 696
 697         bTmp = ReadLPCReg(0x28);
 698         WriteLPCReg(0x28, bTmp | 0x10); //select ITMOFF
 699         bTmp = ReadReg(iobase, 0x35);
 700         WriteReg(iobase, 0x35, bTmp | 0x40);    // Driver ITMOFF
 701         WriteReg(iobase, 0x28, bTmp | 0x80);    // enable All interrupt
 702 }
 703
 704 static void SI_SetMode(__u16 iobase, int mode)
 705 {
 706         //__u32 dTmp;
 707         __u8 bTmp;
 708
 709         WriteLPCReg(0x28, 0x70);        // S/W Reset
 710         SetSITmode(iobase);
 711         ResetDongle(iobase);
 712         udelay(10);
 713         Wr_Indx(iobase, 0x40, 0x0, 0x17);       //RX ,APEN enable,Normal power
 714         Wr_Indx(iobase, 0x40, 0x1, mode);       //Set Mode
 715         Wr_Indx(iobase, 0x40, 0x2, 0xff);       //Set power to FIR VFIR > 1m
 716         bTmp = Rd_Indx(iobase, 0x40, 1);
 717 }
 718
 719 static void InitCard(__u16 iobase)
 720 {
 721         ResetChip(iobase, 5);
 722         WriteReg(iobase, I_ST_CT_0, 0x00);      // open CHIP on
 723         SetSIRBOF(iobase, 0xc0);        // hardware default value
 724         SetSIREOF(iobase, 0xc1);
 725 }
 726
 727 static void CommonInit(__u16 iobase)
 728 {
 729 //  EnTXCRC(iobase,0);
 730         SwapDMA(iobase, OFF);
 731         SetMaxRxPacketSize(iobase, 0x0fff);     //set to max:4095
 732         EnRXFIFOReadyInt(iobase, OFF);
 733         EnRXFIFOHalfLevelInt(iobase, OFF);
 734         EnTXFIFOHalfLevelInt(iobase, OFF);
 735         EnTXFIFOUnderrunEOMInt(iobase, ON);
 736 //  EnTXFIFOReadyInt(iobase,ON);
 737         InvertTX(iobase, OFF);
 738         InvertRX(iobase, OFF);
 739 //  WriteLPCReg(0xF0,0); //(if VT1211 then do this)
 740         if (IsSIROn(iobase)) {
 741                 SIRFilter(iobase, ON);
 742                 SIRRecvAny(iobase, ON);
 743         } else {
 744                 SIRFilter(iobase, OFF);
 745                 SIRRecvAny(iobase, OFF);
 746         }
 747         EnRXSpecInt(iobase, ON);
 748         WriteReg(iobase, I_ST_CT_0, 0x80);
 749         EnableDMA(iobase, ON);
 750 }
 751
 752 static void SetBaudRate(__u16 iobase, __u32 rate)
 753 {
 754         __u8 value = 11, temp;
 755
 756         if (IsSIROn(iobase)) {
 757                 switch (rate) {
 758                 case (__u32) (2400L):
 759                         value = 47;
 760                         break;
 761                 case (__u32) (9600L):
 762                         value = 11;
 763                         break;
 764                 case (__u32) (19200L):
 765                         value = 5;
 766                         break;
 767                 case (__u32) (38400L):
 768                         value = 2;
 769                         break;
 770                 case (__u32) (57600L):
 771                         value = 1;
 772                         break;
 773                 case (__u32) (115200L):
 774                         value = 0;
 775                         break;
 776                 default:
 777                         break;
 778                 };
 779         } else if (IsMIROn(iobase)) {
 780                 value = 0;      // will automatically be fixed in 1.152M
 781         } else if (IsFIROn(iobase)) {
 782                 value = 0;      // will automatically be fixed in 4M
 783         }
 784         temp = (ReadReg(iobase, I_CF_H_1) & 0x03);
 785         temp |= value << 2;
 786         WriteReg(iobase, I_CF_H_1, temp);
 787 }
 788
 789 static void SetPulseWidth(__u16 iobase, __u8 width)
 790 {
 791         __u8 temp, temp1, temp2;
 792
 793         temp = (ReadReg(iobase, I_CF_L_1) & 0x1f);
 794         temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc);
 795         temp2 = (width & 0x07) << 5;
 796         temp |= temp2;
 797         temp2 = (width & 0x18) >> 3;
 798         temp1 |= temp2;
 799         WriteReg(iobase, I_CF_L_1, temp);
 800         WriteReg(iobase, I_CF_H_1, temp1);
 801 }
 802
 803 static void SetSendPreambleCount(__u16 iobase, __u8 count)
 804 {
 805         __u8 temp;
 806
 807         temp = ReadReg(iobase, I_CF_L_1) & 0xe0;
 808         temp |= count;
 809         WriteReg(iobase, I_CF_L_1, temp);
 810
 811 }
 812
 813 static void SetVFIR(__u16 BaseAddr, __u8 val)
 814 {
 815         __u8 tmp;
 816
 817         tmp = ReadReg(BaseAddr, I_CF_L_0);
 818         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 819         WriteRegBit(BaseAddr, I_CF_H_0, 5, val);
 820 }
 821
 822 static void SetFIR(__u16 BaseAddr, __u8 val)
 823 {
 824         __u8 tmp;
 825
 826         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 827         tmp = ReadReg(BaseAddr, I_CF_L_0);
 828         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 829         WriteRegBit(BaseAddr, I_CF_L_0, 6, val);
 830 }
 831
 832 static void SetMIR(__u16 BaseAddr, __u8 val)
 833 {
 834         __u8 tmp;
 835
 836         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 837         tmp = ReadReg(BaseAddr, I_CF_L_0);
 838         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 839         WriteRegBit(BaseAddr, I_CF_L_0, 5, val);
 840 }
 841
 842 static void SetSIR(__u16 BaseAddr, __u8 val)
 843 {
 844         __u8 tmp;
 845
 846         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 847         tmp = ReadReg(BaseAddr, I_CF_L_0);
 848         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 849         WriteRegBit(BaseAddr, I_CF_L_0, 4, val);
 850 }
 851
 852 #endif                          /* via_IRCC_H */