2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
29 #include <asm/byteorder.h>
34 #undef SERIAL_DEBUG_PCI
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
42 struct pci_serial_quirk
{
47 int (*init
)(struct pci_dev
*dev
);
48 int (*setup
)(struct serial_private
*, struct pciserial_board
*,
49 struct uart_port
*port
, int idx
);
50 void (*exit
)(struct pci_dev
*dev
);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private
{
58 void __iomem
*remapped_bar
[PCI_NUM_BAR_RESOURCES
];
59 struct pci_serial_quirk
*quirk
;
63 static void moan_device(const char *str
, struct pci_dev
*dev
)
65 printk(KERN_WARNING
"%s: %s\n"
66 KERN_WARNING
"Please send the output of lspci -vv, this\n"
67 KERN_WARNING
"message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING
"manufacturer and name of serial board or\n"
69 KERN_WARNING
"modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev
), str
, dev
->vendor
, dev
->device
,
71 dev
->subsystem_vendor
, dev
->subsystem_device
);
75 setup_port(struct serial_private
*priv
, struct uart_port
*port
,
76 int bar
, int offset
, int regshift
)
78 struct pci_dev
*dev
= priv
->dev
;
79 unsigned long base
, len
;
81 if (bar
>= PCI_NUM_BAR_RESOURCES
)
84 base
= pci_resource_start(dev
, bar
);
86 if (pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) {
87 len
= pci_resource_len(dev
, bar
);
89 if (!priv
->remapped_bar
[bar
])
90 priv
->remapped_bar
[bar
] = ioremap(base
, len
);
91 if (!priv
->remapped_bar
[bar
])
94 port
->iotype
= UPIO_MEM
;
96 port
->mapbase
= base
+ offset
;
97 port
->membase
= priv
->remapped_bar
[bar
] + offset
;
98 port
->regshift
= regshift
;
100 port
->iotype
= UPIO_PORT
;
101 port
->iobase
= base
+ offset
;
103 port
->membase
= NULL
;
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
114 afavlab_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
115 struct uart_port
*port
, int idx
)
117 unsigned int bar
, offset
= board
->first_offset
;
119 bar
= FL_GET_BASE(board
->flags
);
124 offset
+= (idx
- 4) * board
->uart_offset
;
127 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
137 static int __devinit
pci_hp_diva_init(struct pci_dev
*dev
)
141 switch (dev
->subsystem_device
) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1
:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME
:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE
:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2
:
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR
:
163 * HP's Diva chip puts the 4th/5th serial port further out, and
164 * some serial ports are supposed to be hidden on certain models.
167 pci_hp_diva_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
168 struct uart_port
*port
, int idx
)
170 unsigned int offset
= board
->first_offset
;
171 unsigned int bar
= FL_GET_BASE(board
->flags
);
173 switch (priv
->dev
->subsystem_device
) {
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
188 offset
+= idx
* board
->uart_offset
;
190 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
194 * Added for EKF Intel i960 serial boards
196 static int __devinit
pci_inteli960ni_init(struct pci_dev
*dev
)
198 unsigned long oldval
;
200 if (!(dev
->subsystem_device
& 0x1000))
203 /* is firmware started? */
204 pci_read_config_dword(dev
, 0x44, (void*) &oldval
);
205 if (oldval
== 0x00001000L
) { /* RESET value */
206 printk(KERN_DEBUG
"Local i960 firmware missing");
213 * Some PCI serial cards using the PLX 9050 PCI interface chip require
214 * that the card interrupt be explicitly enabled or disabled. This
215 * seems to be mainly needed on card using the PLX which also use I/O
218 static int __devinit
pci_plx9050_init(struct pci_dev
*dev
)
223 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0) {
224 moan_device("no memory in bar 0", dev
);
229 if (dev
->vendor
== PCI_VENDOR_ID_PANACOM
)
231 if ((dev
->vendor
== PCI_VENDOR_ID_PLX
) &&
232 (dev
->device
== PCI_DEVICE_ID_PLX_ROMULUS
)) {
234 * As the megawolf cards have the int pins active
235 * high, and have 2 UART chips, both ints must be
236 * enabled on the 9050. Also, the UARTS are set in
237 * 16450 mode by default, so we have to enable the
238 * 16C950 'enhanced' mode so that we can use the
245 * enable/disable interrupts
247 p
= ioremap(pci_resource_start(dev
, 0), 0x80);
250 writel(irq_config
, p
+ 0x4c);
253 * Read the register back to ensure that it took effect.
261 static void __devexit
pci_plx9050_exit(struct pci_dev
*dev
)
265 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0)
271 p
= ioremap(pci_resource_start(dev
, 0), 0x80);
276 * Read the register back to ensure that it took effect.
283 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
285 sbs_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
286 struct uart_port
*port
, int idx
)
288 unsigned int bar
, offset
= board
->first_offset
;
293 /* first four channels map to 0, 0x100, 0x200, 0x300 */
294 offset
+= idx
* board
->uart_offset
;
295 } else if (idx
< 8) {
296 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
297 offset
+= idx
* board
->uart_offset
+ 0xC00;
298 } else /* we have only 8 ports on PMC-OCTALPRO */
301 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
305 * This does initialization for PMC OCTALPRO cards:
306 * maps the device memory, resets the UARTs (needed, bc
307 * if the module is removed and inserted again, the card
308 * is in the sleep mode) and enables global interrupt.
311 /* global control register offset for SBS PMC-OctalPro */
312 #define OCT_REG_CR_OFF 0x500
314 static int __devinit
sbs_init(struct pci_dev
*dev
)
318 p
= ioremap(pci_resource_start(dev
, 0),pci_resource_len(dev
,0));
322 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
323 writeb(0x10,p
+ OCT_REG_CR_OFF
);
325 writeb(0x0,p
+ OCT_REG_CR_OFF
);
327 /* Set bit-2 (INTENABLE) of Control Register */
328 writeb(0x4, p
+ OCT_REG_CR_OFF
);
335 * Disables the global interrupt of PMC-OctalPro
338 static void __devexit
sbs_exit(struct pci_dev
*dev
)
342 p
= ioremap(pci_resource_start(dev
, 0),pci_resource_len(dev
,0));
344 writeb(0, p
+ OCT_REG_CR_OFF
);
350 * SIIG serial cards have an PCI interface chip which also controls
351 * the UART clocking frequency. Each UART can be clocked independently
352 * (except cards equiped with 4 UARTs) and initial clocking settings
353 * are stored in the EEPROM chip. It can cause problems because this
354 * version of serial driver doesn't support differently clocked UART's
355 * on single PCI card. To prevent this, initialization functions set
356 * high frequency clocking for all UART's on given card. It is safe (I
357 * hope) because it doesn't touch EEPROM settings to prevent conflicts
358 * with other OSes (like M$ DOS).
360 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
362 * There is two family of SIIG serial cards with different PCI
363 * interface chip and different configuration methods:
364 * - 10x cards have control registers in IO and/or memory space;
365 * - 20x cards have control registers in standard PCI configuration space.
367 * Note: all 10x cards have PCI device ids 0x10..
368 * all 20x cards have PCI device ids 0x20..
370 * There are also Quartet Serial cards which use Oxford Semiconductor
371 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
373 * Note: some SIIG cards are probed by the parport_serial object.
376 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
377 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
379 static int pci_siig10x_init(struct pci_dev
*dev
)
384 switch (dev
->device
& 0xfff8) {
385 case PCI_DEVICE_ID_SIIG_1S_10x
: /* 1S */
388 case PCI_DEVICE_ID_SIIG_2S_10x
: /* 2S, 2S1P */
391 default: /* 1S1P, 4S */
396 p
= ioremap(pci_resource_start(dev
, 0), 0x80);
400 writew(readw(p
+ 0x28) & data
, p
+ 0x28);
406 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
407 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
409 static int pci_siig20x_init(struct pci_dev
*dev
)
413 /* Change clock frequency for the first UART. */
414 pci_read_config_byte(dev
, 0x6f, &data
);
415 pci_write_config_byte(dev
, 0x6f, data
& 0xef);
417 /* If this card has 2 UART, we have to do the same with second UART. */
418 if (((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x
) ||
419 ((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x
)) {
420 pci_read_config_byte(dev
, 0x73, &data
);
421 pci_write_config_byte(dev
, 0x73, data
& 0xef);
426 static int pci_siig_init(struct pci_dev
*dev
)
428 unsigned int type
= dev
->device
& 0xff00;
431 return pci_siig10x_init(dev
);
432 else if (type
== 0x2000)
433 return pci_siig20x_init(dev
);
435 moan_device("Unknown SIIG card", dev
);
439 int pci_siig10x_fn(struct pci_dev
*dev
, int enable
)
443 ret
= pci_siig10x_init(dev
);
447 int pci_siig20x_fn(struct pci_dev
*dev
, int enable
)
451 ret
= pci_siig20x_init(dev
);
455 EXPORT_SYMBOL(pci_siig10x_fn
);
456 EXPORT_SYMBOL(pci_siig20x_fn
);
459 * Timedia has an explosion of boards, and to avoid the PCI table from
460 * growing *huge*, we use this function to collapse some 70 entries
461 * in the PCI table into one, for sanity's and compactness's sake.
463 static unsigned short timedia_single_port
[] = {
464 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
467 static unsigned short timedia_dual_port
[] = {
468 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
469 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
470 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
471 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
475 static unsigned short timedia_quad_port
[] = {
476 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
477 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
478 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
482 static unsigned short timedia_eight_port
[] = {
483 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
484 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
487 static struct timedia_struct
{
491 { 1, timedia_single_port
},
492 { 2, timedia_dual_port
},
493 { 4, timedia_quad_port
},
494 { 8, timedia_eight_port
},
498 static int __devinit
pci_timedia_init(struct pci_dev
*dev
)
503 for (i
= 0; timedia_data
[i
].num
; i
++) {
504 ids
= timedia_data
[i
].ids
;
505 for (j
= 0; ids
[j
]; j
++)
506 if (dev
->subsystem_device
== ids
[j
])
507 return timedia_data
[i
].num
;
513 * Timedia/SUNIX uses a mixture of BARs and offsets
514 * Ugh, this is ugly as all hell --- TYT
517 pci_timedia_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
518 struct uart_port
*port
, int idx
)
520 unsigned int bar
= 0, offset
= board
->first_offset
;
527 offset
= board
->uart_offset
;
534 offset
= board
->uart_offset
;
543 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
547 * Some Titan cards are also a little weird
550 titan_400l_800l_setup(struct serial_private
*priv
,
551 struct pciserial_board
*board
,
552 struct uart_port
*port
, int idx
)
554 unsigned int bar
, offset
= board
->first_offset
;
565 offset
= (idx
- 2) * board
->uart_offset
;
568 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
571 static int __devinit
pci_xircom_init(struct pci_dev
*dev
)
577 static int __devinit
pci_netmos_init(struct pci_dev
*dev
)
579 /* subdevice 0x00PS means <P> parallel, <S> serial */
580 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
588 pci_default_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
589 struct uart_port
*port
, int idx
)
591 unsigned int bar
, offset
= board
->first_offset
, maxnr
;
593 bar
= FL_GET_BASE(board
->flags
);
594 if (board
->flags
& FL_BASE_BARS
)
597 offset
+= idx
* board
->uart_offset
;
599 maxnr
= (pci_resource_len(priv
->dev
, bar
) - board
->first_offset
) /
600 (8 << board
->reg_shift
);
602 if (board
->flags
& FL_REGION_SZ_CAP
&& idx
>= maxnr
)
605 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
608 /* This should be in linux/pci_ids.h */
609 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
610 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
611 #define PCI_DEVICE_ID_OCTPRO 0x0001
612 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
613 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
614 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
615 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
618 * Master list of serial port init/setup/exit quirks.
619 * This does not describe the general nature of the port.
620 * (ie, baud base, number and location of ports, etc)
622 * This list is ordered alphabetically by vendor then device.
623 * Specific entries must come before more generic entries.
625 static struct pci_serial_quirk pci_serial_quirks
[] = {
628 * It is not clear whether this applies to all products.
631 .vendor
= PCI_VENDOR_ID_AFAVLAB
,
632 .device
= PCI_ANY_ID
,
633 .subvendor
= PCI_ANY_ID
,
634 .subdevice
= PCI_ANY_ID
,
635 .setup
= afavlab_setup
,
641 .vendor
= PCI_VENDOR_ID_HP
,
642 .device
= PCI_DEVICE_ID_HP_DIVA
,
643 .subvendor
= PCI_ANY_ID
,
644 .subdevice
= PCI_ANY_ID
,
645 .init
= pci_hp_diva_init
,
646 .setup
= pci_hp_diva_setup
,
652 .vendor
= PCI_VENDOR_ID_INTEL
,
653 .device
= PCI_DEVICE_ID_INTEL_80960_RP
,
655 .subdevice
= PCI_ANY_ID
,
656 .init
= pci_inteli960ni_init
,
657 .setup
= pci_default_setup
,
663 .vendor
= PCI_VENDOR_ID_PANACOM
,
664 .device
= PCI_DEVICE_ID_PANACOM_QUADMODEM
,
665 .subvendor
= PCI_ANY_ID
,
666 .subdevice
= PCI_ANY_ID
,
667 .init
= pci_plx9050_init
,
668 .setup
= pci_default_setup
,
669 .exit
= __devexit_p(pci_plx9050_exit
),
672 .vendor
= PCI_VENDOR_ID_PANACOM
,
673 .device
= PCI_DEVICE_ID_PANACOM_DUALMODEM
,
674 .subvendor
= PCI_ANY_ID
,
675 .subdevice
= PCI_ANY_ID
,
676 .init
= pci_plx9050_init
,
677 .setup
= pci_default_setup
,
678 .exit
= __devexit_p(pci_plx9050_exit
),
684 .vendor
= PCI_VENDOR_ID_PLX
,
685 .device
= PCI_DEVICE_ID_PLX_9050
,
686 .subvendor
= PCI_SUBVENDOR_ID_KEYSPAN
,
687 .subdevice
= PCI_SUBDEVICE_ID_KEYSPAN_SX2
,
688 .init
= pci_plx9050_init
,
689 .setup
= pci_default_setup
,
690 .exit
= __devexit_p(pci_plx9050_exit
),
693 .vendor
= PCI_VENDOR_ID_PLX
,
694 .device
= PCI_DEVICE_ID_PLX_ROMULUS
,
695 .subvendor
= PCI_VENDOR_ID_PLX
,
696 .subdevice
= PCI_DEVICE_ID_PLX_ROMULUS
,
697 .init
= pci_plx9050_init
,
698 .setup
= pci_default_setup
,
699 .exit
= __devexit_p(pci_plx9050_exit
),
702 * SBS Technologies, Inc., PMC-OCTALPRO 232
705 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
706 .device
= PCI_DEVICE_ID_OCTPRO
,
707 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
708 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO232
,
711 .exit
= __devexit_p(sbs_exit
),
714 * SBS Technologies, Inc., PMC-OCTALPRO 422
717 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
718 .device
= PCI_DEVICE_ID_OCTPRO
,
719 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
720 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO422
,
723 .exit
= __devexit_p(sbs_exit
),
726 * SBS Technologies, Inc., P-Octal 232
729 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
730 .device
= PCI_DEVICE_ID_OCTPRO
,
731 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
732 .subdevice
= PCI_SUBDEVICE_ID_POCTAL232
,
735 .exit
= __devexit_p(sbs_exit
),
738 * SBS Technologies, Inc., P-Octal 422
741 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
742 .device
= PCI_DEVICE_ID_OCTPRO
,
743 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
744 .subdevice
= PCI_SUBDEVICE_ID_POCTAL422
,
747 .exit
= __devexit_p(sbs_exit
),
753 .vendor
= PCI_VENDOR_ID_SIIG
,
754 .device
= PCI_ANY_ID
,
755 .subvendor
= PCI_ANY_ID
,
756 .subdevice
= PCI_ANY_ID
,
757 .init
= pci_siig_init
,
758 .setup
= pci_default_setup
,
764 .vendor
= PCI_VENDOR_ID_TITAN
,
765 .device
= PCI_DEVICE_ID_TITAN_400L
,
766 .subvendor
= PCI_ANY_ID
,
767 .subdevice
= PCI_ANY_ID
,
768 .setup
= titan_400l_800l_setup
,
771 .vendor
= PCI_VENDOR_ID_TITAN
,
772 .device
= PCI_DEVICE_ID_TITAN_800L
,
773 .subvendor
= PCI_ANY_ID
,
774 .subdevice
= PCI_ANY_ID
,
775 .setup
= titan_400l_800l_setup
,
781 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
782 .device
= PCI_DEVICE_ID_TIMEDIA_1889
,
783 .subvendor
= PCI_VENDOR_ID_TIMEDIA
,
784 .subdevice
= PCI_ANY_ID
,
785 .init
= pci_timedia_init
,
786 .setup
= pci_timedia_setup
,
789 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
790 .device
= PCI_ANY_ID
,
791 .subvendor
= PCI_ANY_ID
,
792 .subdevice
= PCI_ANY_ID
,
793 .setup
= pci_timedia_setup
,
799 .vendor
= PCI_VENDOR_ID_XIRCOM
,
800 .device
= PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
801 .subvendor
= PCI_ANY_ID
,
802 .subdevice
= PCI_ANY_ID
,
803 .init
= pci_xircom_init
,
804 .setup
= pci_default_setup
,
810 .vendor
= PCI_VENDOR_ID_NETMOS
,
811 .device
= PCI_ANY_ID
,
812 .subvendor
= PCI_ANY_ID
,
813 .subdevice
= PCI_ANY_ID
,
814 .init
= pci_netmos_init
,
815 .setup
= pci_default_setup
,
818 * Default "match everything" terminator entry
821 .vendor
= PCI_ANY_ID
,
822 .device
= PCI_ANY_ID
,
823 .subvendor
= PCI_ANY_ID
,
824 .subdevice
= PCI_ANY_ID
,
825 .setup
= pci_default_setup
,
829 static inline int quirk_id_matches(u32 quirk_id
, u32 dev_id
)
831 return quirk_id
== PCI_ANY_ID
|| quirk_id
== dev_id
;
834 static struct pci_serial_quirk
*find_quirk(struct pci_dev
*dev
)
836 struct pci_serial_quirk
*quirk
;
838 for (quirk
= pci_serial_quirks
; ; quirk
++)
839 if (quirk_id_matches(quirk
->vendor
, dev
->vendor
) &&
840 quirk_id_matches(quirk
->device
, dev
->device
) &&
841 quirk_id_matches(quirk
->subvendor
, dev
->subsystem_vendor
) &&
842 quirk_id_matches(quirk
->subdevice
, dev
->subsystem_device
))
848 get_pci_irq(struct pci_dev
*dev
, struct pciserial_board
*board
)
850 if (board
->flags
& FL_NOIRQ
)
857 * This is the configuration table for all of the PCI serial boards
858 * which we support. It is directly indexed by the pci_board_num_t enum
859 * value, which is encoded in the pci_device_id PCI probe table's
860 * driver_data member.
862 * The makeup of these names are:
865 * bn = PCI BAR number
866 * bt = Index using PCI BARs
867 * n = number of serial ports
870 * This table is sorted by (in order): baud, bt, bn, n.
872 * Please note: in theory if n = 1, _bt infix should make no difference.
873 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
875 enum pci_board_num_t
{
942 * Board-specific versions.
962 * uart_offset - the space between channels
963 * reg_shift - describes how the UART registers are mapped
964 * to PCI memory by the card.
965 * For example IER register on SBS, Inc. PMC-OctPro is located at
966 * offset 0x10 from the UART base, while UART_IER is defined as 1
967 * in include/linux/serial_reg.h,
968 * see first lines of serial_in() and serial_out() in 8250.c
971 static struct pciserial_board pci_boards
[] __devinitdata
= {
978 [pbn_b0_1_115200
] = {
984 [pbn_b0_2_115200
] = {
990 [pbn_b0_4_115200
] = {
996 [pbn_b0_5_115200
] = {
1003 [pbn_b0_1_921600
] = {
1006 .base_baud
= 921600,
1009 [pbn_b0_2_921600
] = {
1012 .base_baud
= 921600,
1015 [pbn_b0_4_921600
] = {
1018 .base_baud
= 921600,
1021 [pbn_b0_4_1152000
] = {
1024 .base_baud
= 1152000,
1028 [pbn_b0_bt_1_115200
] = {
1029 .flags
= FL_BASE0
|FL_BASE_BARS
,
1031 .base_baud
= 115200,
1034 [pbn_b0_bt_2_115200
] = {
1035 .flags
= FL_BASE0
|FL_BASE_BARS
,
1037 .base_baud
= 115200,
1040 [pbn_b0_bt_8_115200
] = {
1041 .flags
= FL_BASE0
|FL_BASE_BARS
,
1043 .base_baud
= 115200,
1047 [pbn_b0_bt_1_460800
] = {
1048 .flags
= FL_BASE0
|FL_BASE_BARS
,
1050 .base_baud
= 460800,
1053 [pbn_b0_bt_2_460800
] = {
1054 .flags
= FL_BASE0
|FL_BASE_BARS
,
1056 .base_baud
= 460800,
1059 [pbn_b0_bt_4_460800
] = {
1060 .flags
= FL_BASE0
|FL_BASE_BARS
,
1062 .base_baud
= 460800,
1066 [pbn_b0_bt_1_921600
] = {
1067 .flags
= FL_BASE0
|FL_BASE_BARS
,
1069 .base_baud
= 921600,
1072 [pbn_b0_bt_2_921600
] = {
1073 .flags
= FL_BASE0
|FL_BASE_BARS
,
1075 .base_baud
= 921600,
1078 [pbn_b0_bt_4_921600
] = {
1079 .flags
= FL_BASE0
|FL_BASE_BARS
,
1081 .base_baud
= 921600,
1084 [pbn_b0_bt_8_921600
] = {
1085 .flags
= FL_BASE0
|FL_BASE_BARS
,
1087 .base_baud
= 921600,
1091 [pbn_b1_1_115200
] = {
1094 .base_baud
= 115200,
1097 [pbn_b1_2_115200
] = {
1100 .base_baud
= 115200,
1103 [pbn_b1_4_115200
] = {
1106 .base_baud
= 115200,
1109 [pbn_b1_8_115200
] = {
1112 .base_baud
= 115200,
1116 [pbn_b1_1_921600
] = {
1119 .base_baud
= 921600,
1122 [pbn_b1_2_921600
] = {
1125 .base_baud
= 921600,
1128 [pbn_b1_4_921600
] = {
1131 .base_baud
= 921600,
1134 [pbn_b1_8_921600
] = {
1137 .base_baud
= 921600,
1141 [pbn_b1_bt_2_921600
] = {
1142 .flags
= FL_BASE1
|FL_BASE_BARS
,
1144 .base_baud
= 921600,
1148 [pbn_b1_1_1382400
] = {
1151 .base_baud
= 1382400,
1154 [pbn_b1_2_1382400
] = {
1157 .base_baud
= 1382400,
1160 [pbn_b1_4_1382400
] = {
1163 .base_baud
= 1382400,
1166 [pbn_b1_8_1382400
] = {
1169 .base_baud
= 1382400,
1173 [pbn_b2_1_115200
] = {
1176 .base_baud
= 115200,
1179 [pbn_b2_8_115200
] = {
1182 .base_baud
= 115200,
1186 [pbn_b2_1_460800
] = {
1189 .base_baud
= 460800,
1192 [pbn_b2_4_460800
] = {
1195 .base_baud
= 460800,
1198 [pbn_b2_8_460800
] = {
1201 .base_baud
= 460800,
1204 [pbn_b2_16_460800
] = {
1207 .base_baud
= 460800,
1211 [pbn_b2_1_921600
] = {
1214 .base_baud
= 921600,
1217 [pbn_b2_4_921600
] = {
1220 .base_baud
= 921600,
1223 [pbn_b2_8_921600
] = {
1226 .base_baud
= 921600,
1230 [pbn_b2_bt_1_115200
] = {
1231 .flags
= FL_BASE2
|FL_BASE_BARS
,
1233 .base_baud
= 115200,
1236 [pbn_b2_bt_2_115200
] = {
1237 .flags
= FL_BASE2
|FL_BASE_BARS
,
1239 .base_baud
= 115200,
1242 [pbn_b2_bt_4_115200
] = {
1243 .flags
= FL_BASE2
|FL_BASE_BARS
,
1245 .base_baud
= 115200,
1249 [pbn_b2_bt_2_921600
] = {
1250 .flags
= FL_BASE2
|FL_BASE_BARS
,
1252 .base_baud
= 921600,
1255 [pbn_b2_bt_4_921600
] = {
1256 .flags
= FL_BASE2
|FL_BASE_BARS
,
1258 .base_baud
= 921600,
1262 [pbn_b3_4_115200
] = {
1265 .base_baud
= 115200,
1268 [pbn_b3_8_115200
] = {
1271 .base_baud
= 115200,
1276 * Entries following this are board-specific.
1285 .base_baud
= 921600,
1286 .uart_offset
= 0x400,
1290 .flags
= FL_BASE2
|FL_BASE_BARS
,
1292 .base_baud
= 921600,
1293 .uart_offset
= 0x400,
1297 .flags
= FL_BASE2
|FL_BASE_BARS
,
1299 .base_baud
= 921600,
1300 .uart_offset
= 0x400,
1304 /* I think this entry is broken - the first_offset looks wrong --rmk */
1305 [pbn_plx_romulus
] = {
1308 .base_baud
= 921600,
1309 .uart_offset
= 8 << 2,
1311 .first_offset
= 0x03,
1315 * This board uses the size of PCI Base region 0 to
1316 * signal now many ports are available
1319 .flags
= FL_BASE0
|FL_REGION_SZ_CAP
,
1321 .base_baud
= 115200,
1326 * EKF addition for i960 Boards form EKF with serial port.
1329 [pbn_intel_i960
] = {
1332 .base_baud
= 921600,
1333 .uart_offset
= 8 << 2,
1335 .first_offset
= 0x10000,
1338 .flags
= FL_BASE0
|FL_NOIRQ
,
1340 .base_baud
= 458333,
1343 .first_offset
= 0x20178,
1347 * NEC Vrc-5074 (Nile 4) builtin UART.
1352 .base_baud
= 520833,
1353 .uart_offset
= 8 << 3,
1355 .first_offset
= 0x300,
1359 * Computone - uses IOMEM.
1361 [pbn_computone_4
] = {
1364 .base_baud
= 921600,
1365 .uart_offset
= 0x40,
1367 .first_offset
= 0x200,
1369 [pbn_computone_6
] = {
1372 .base_baud
= 921600,
1373 .uart_offset
= 0x40,
1375 .first_offset
= 0x200,
1377 [pbn_computone_8
] = {
1380 .base_baud
= 921600,
1381 .uart_offset
= 0x40,
1383 .first_offset
= 0x200,
1388 .base_baud
= 460800,
1393 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1394 * Only basic 16550A support.
1395 * XR17C15[24] are not tested, but they should work.
1397 [pbn_exar_XR17C152
] = {
1400 .base_baud
= 921600,
1401 .uart_offset
= 0x200,
1403 [pbn_exar_XR17C154
] = {
1406 .base_baud
= 921600,
1407 .uart_offset
= 0x200,
1409 [pbn_exar_XR17C158
] = {
1412 .base_baud
= 921600,
1413 .uart_offset
= 0x200,
1418 * Given a complete unknown PCI device, try to use some heuristics to
1419 * guess what the configuration might be, based on the pitiful PCI
1420 * serial specs. Returns 0 on success, 1 on failure.
1422 static int __devinit
1423 serial_pci_guess_board(struct pci_dev
*dev
, struct pciserial_board
*board
)
1425 int num_iomem
, num_port
, first_port
= -1, i
;
1428 * If it is not a communications device or the programming
1429 * interface is greater than 6, give up.
1431 * (Should we try to make guesses for multiport serial devices
1434 if ((((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL
) &&
1435 ((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM
)) ||
1436 (dev
->class & 0xff) > 6)
1439 num_iomem
= num_port
= 0;
1440 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
1441 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
) {
1443 if (first_port
== -1)
1446 if (pci_resource_flags(dev
, i
) & IORESOURCE_MEM
)
1451 * If there is 1 or 0 iomem regions, and exactly one port,
1452 * use it. We guess the number of ports based on the IO
1455 if (num_iomem
<= 1 && num_port
== 1) {
1456 board
->flags
= first_port
;
1457 board
->num_ports
= pci_resource_len(dev
, first_port
) / 8;
1462 * Now guess if we've got a board which indexes by BARs.
1463 * Each IO BAR should be 8 bytes, and they should follow
1468 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
1469 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
&&
1470 pci_resource_len(dev
, i
) == 8 &&
1471 (first_port
== -1 || (first_port
+ num_port
) == i
)) {
1473 if (first_port
== -1)
1479 board
->flags
= first_port
| FL_BASE_BARS
;
1480 board
->num_ports
= num_port
;
1488 serial_pci_matches(struct pciserial_board
*board
,
1489 struct pciserial_board
*guessed
)
1492 board
->num_ports
== guessed
->num_ports
&&
1493 board
->base_baud
== guessed
->base_baud
&&
1494 board
->uart_offset
== guessed
->uart_offset
&&
1495 board
->reg_shift
== guessed
->reg_shift
&&
1496 board
->first_offset
== guessed
->first_offset
;
1499 struct serial_private
*
1500 pciserial_init_ports(struct pci_dev
*dev
, struct pciserial_board
*board
)
1502 struct uart_port serial_port
;
1503 struct serial_private
*priv
;
1504 struct pci_serial_quirk
*quirk
;
1505 int rc
, nr_ports
, i
;
1507 nr_ports
= board
->num_ports
;
1510 * Find an init and setup quirks.
1512 quirk
= find_quirk(dev
);
1515 * Run the new-style initialization function.
1516 * The initialization function returns:
1518 * 0 - use board->num_ports
1519 * >0 - number of ports
1522 rc
= quirk
->init(dev
);
1531 priv
= kmalloc(sizeof(struct serial_private
) +
1532 sizeof(unsigned int) * nr_ports
,
1535 priv
= ERR_PTR(-ENOMEM
);
1539 memset(priv
, 0, sizeof(struct serial_private
) +
1540 sizeof(unsigned int) * nr_ports
);
1543 priv
->quirk
= quirk
;
1545 memset(&serial_port
, 0, sizeof(struct uart_port
));
1546 serial_port
.flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
| UPF_SHARE_IRQ
;
1547 serial_port
.uartclk
= board
->base_baud
* 16;
1548 serial_port
.irq
= get_pci_irq(dev
, board
);
1549 serial_port
.dev
= &dev
->dev
;
1551 for (i
= 0; i
< nr_ports
; i
++) {
1552 if (quirk
->setup(priv
, board
, &serial_port
, i
))
1555 #ifdef SERIAL_DEBUG_PCI
1556 printk("Setup PCI port: port %x, irq %d, type %d\n",
1557 serial_port
.iobase
, serial_port
.irq
, serial_port
.iotype
);
1560 priv
->line
[i
] = serial8250_register_port(&serial_port
);
1561 if (priv
->line
[i
] < 0) {
1562 printk(KERN_WARNING
"Couldn't register serial port %s: %d\n", pci_name(dev
), priv
->line
[i
]);
1577 EXPORT_SYMBOL_GPL(pciserial_init_ports
);
1579 void pciserial_remove_ports(struct serial_private
*priv
)
1581 struct pci_serial_quirk
*quirk
;
1584 for (i
= 0; i
< priv
->nr
; i
++)
1585 serial8250_unregister_port(priv
->line
[i
]);
1587 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
1588 if (priv
->remapped_bar
[i
])
1589 iounmap(priv
->remapped_bar
[i
]);
1590 priv
->remapped_bar
[i
] = NULL
;
1594 * Find the exit quirks.
1596 quirk
= find_quirk(priv
->dev
);
1598 quirk
->exit(priv
->dev
);
1602 EXPORT_SYMBOL_GPL(pciserial_remove_ports
);
1604 void pciserial_suspend_ports(struct serial_private
*priv
)
1608 for (i
= 0; i
< priv
->nr
; i
++)
1609 if (priv
->line
[i
] >= 0)
1610 serial8250_suspend_port(priv
->line
[i
]);
1612 EXPORT_SYMBOL_GPL(pciserial_suspend_ports
);
1614 void pciserial_resume_ports(struct serial_private
*priv
)
1619 * Ensure that the board is correctly configured.
1621 if (priv
->quirk
->init
)
1622 priv
->quirk
->init(priv
->dev
);
1624 for (i
= 0; i
< priv
->nr
; i
++)
1625 if (priv
->line
[i
] >= 0)
1626 serial8250_resume_port(priv
->line
[i
]);
1628 EXPORT_SYMBOL_GPL(pciserial_resume_ports
);
1631 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1632 * to the arrangement of serial ports on a PCI card.
1634 static int __devinit
1635 pciserial_init_one(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
1637 struct serial_private
*priv
;
1638 struct pciserial_board
*board
, tmp
;
1641 if (ent
->driver_data
>= ARRAY_SIZE(pci_boards
)) {
1642 printk(KERN_ERR
"pci_init_one: invalid driver_data: %ld\n",
1647 board
= &pci_boards
[ent
->driver_data
];
1649 rc
= pci_enable_device(dev
);
1653 if (ent
->driver_data
== pbn_default
) {
1655 * Use a copy of the pci_board entry for this;
1656 * avoid changing entries in the table.
1658 memcpy(&tmp
, board
, sizeof(struct pciserial_board
));
1662 * We matched one of our class entries. Try to
1663 * determine the parameters of this board.
1665 rc
= serial_pci_guess_board(dev
, board
);
1670 * We matched an explicit entry. If we are able to
1671 * detect this boards settings with our heuristic,
1672 * then we no longer need this entry.
1674 memcpy(&tmp
, &pci_boards
[pbn_default
],
1675 sizeof(struct pciserial_board
));
1676 rc
= serial_pci_guess_board(dev
, &tmp
);
1677 if (rc
== 0 && serial_pci_matches(board
, &tmp
))
1678 moan_device("Redundant entry in serial pci_table.",
1682 priv
= pciserial_init_ports(dev
, board
);
1683 if (!IS_ERR(priv
)) {
1684 pci_set_drvdata(dev
, priv
);
1691 pci_disable_device(dev
);
1695 static void __devexit
pciserial_remove_one(struct pci_dev
*dev
)
1697 struct serial_private
*priv
= pci_get_drvdata(dev
);
1699 pci_set_drvdata(dev
, NULL
);
1701 pciserial_remove_ports(priv
);
1703 pci_disable_device(dev
);
1706 static int pciserial_suspend_one(struct pci_dev
*dev
, pm_message_t state
)
1708 struct serial_private
*priv
= pci_get_drvdata(dev
);
1711 pciserial_suspend_ports(priv
);
1713 pci_save_state(dev
);
1714 pci_set_power_state(dev
, pci_choose_state(dev
, state
));
1718 static int pciserial_resume_one(struct pci_dev
*dev
)
1720 struct serial_private
*priv
= pci_get_drvdata(dev
);
1722 pci_set_power_state(dev
, PCI_D0
);
1723 pci_restore_state(dev
);
1727 * The device may have been disabled. Re-enable it.
1729 pci_enable_device(dev
);
1731 pciserial_resume_ports(priv
);
1736 static struct pci_device_id serial_pci_tbl
[] = {
1737 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
1738 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1739 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
1741 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
1742 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1743 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
1745 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
1746 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1747 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
1749 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1750 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1751 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
1753 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1754 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1755 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
1757 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1758 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1759 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
1761 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1762 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1763 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485
, 0, 0,
1765 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1766 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1767 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4
, 0, 0,
1769 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1770 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1771 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485
, 0, 0,
1773 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1774 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1775 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2
, 0, 0,
1777 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1778 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1779 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485
, 0, 0,
1781 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1782 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1783 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6
, 0, 0,
1785 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1786 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1787 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1
, 0, 0,
1789 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
1790 PCI_SUBVENDOR_ID_CONNECT_TECH
,
1791 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1
, 0, 0,
1794 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_U530
,
1795 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1796 pbn_b2_bt_1_115200
},
1797 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM2
,
1798 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1799 pbn_b2_bt_2_115200
},
1800 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM422
,
1801 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1802 pbn_b2_bt_4_115200
},
1803 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM232
,
1804 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1805 pbn_b2_bt_2_115200
},
1806 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM4
,
1807 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1808 pbn_b2_bt_4_115200
},
1809 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM8
,
1810 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1812 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM8
,
1813 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1816 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_GTEK_SERIAL2
,
1817 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1818 pbn_b2_bt_2_115200
},
1819 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM200
,
1820 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1821 pbn_b2_bt_2_921600
},
1823 * VScom SPCOM800, from sl@s.pl
1825 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM800
,
1826 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1828 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_1077
,
1829 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1831 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1832 PCI_SUBVENDOR_ID_KEYSPAN
,
1833 PCI_SUBDEVICE_ID_KEYSPAN_SX2
, 0, 0,
1835 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_QUADMODEM
,
1836 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1838 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_DUALMODEM
,
1839 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1841 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1842 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
1843 PCI_SUBDEVICE_ID_CHASE_PCIFAST4
, 0, 0,
1845 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1846 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
1847 PCI_SUBDEVICE_ID_CHASE_PCIFAST8
, 0, 0,
1849 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1850 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
1851 PCI_SUBDEVICE_ID_CHASE_PCIFAST16
, 0, 0,
1853 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1854 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
1855 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC
, 0, 0,
1857 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1858 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
1859 PCI_SUBDEVICE_ID_CHASE_PCIRAS4
, 0, 0,
1861 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
1862 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
1863 PCI_SUBDEVICE_ID_CHASE_PCIRAS8
, 0, 0,
1866 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1869 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_ROMULUS
,
1870 0x10b5, 0x106a, 0, 0,
1872 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSC100
,
1873 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1875 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSC100
,
1876 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1878 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100D
,
1879 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1881 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100M
,
1882 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1884 { PCI_VENDOR_ID_SPECIALIX
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
1885 PCI_VENDOR_ID_SPECIALIX
, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4
, 0, 0,
1887 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
1888 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL
, 0, 0,
1890 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
1891 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1893 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI952
,
1894 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1895 pbn_b0_bt_2_921600
},
1898 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1899 * from skokodyn@yahoo.com
1901 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
1902 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO232
, 0, 0,
1904 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
1905 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO422
, 0, 0,
1907 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
1908 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL232
, 0, 0,
1910 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
1911 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL422
, 0, 0,
1915 * Digitan DS560-558, from jimd@esoft.com
1917 { PCI_VENDOR_ID_ATT
, PCI_DEVICE_ID_ATT_VENUS_MODEM
,
1918 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1922 * Titan Electronic cards
1923 * The 400L and 800L have a custom setup quirk.
1925 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100
,
1926 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1928 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200
,
1929 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1931 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400
,
1932 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1934 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800B
,
1935 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1937 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100L
,
1938 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1940 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200L
,
1941 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1942 pbn_b1_bt_2_921600
},
1943 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400L
,
1944 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1945 pbn_b0_bt_4_921600
},
1946 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800L
,
1947 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1948 pbn_b0_bt_8_921600
},
1950 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_550
,
1951 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1953 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_650
,
1954 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1956 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_850
,
1957 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1959 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_550
,
1960 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1961 pbn_b2_bt_2_921600
},
1962 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_650
,
1963 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1964 pbn_b2_bt_2_921600
},
1965 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_850
,
1966 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1967 pbn_b2_bt_2_921600
},
1968 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_550
,
1969 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1970 pbn_b2_bt_4_921600
},
1971 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_650
,
1972 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1973 pbn_b2_bt_4_921600
},
1974 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_850
,
1975 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1976 pbn_b2_bt_4_921600
},
1977 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_550
,
1978 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1980 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_650
,
1981 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1983 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_850
,
1984 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1986 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_550
,
1987 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1988 pbn_b0_bt_2_921600
},
1989 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_650
,
1990 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1991 pbn_b0_bt_2_921600
},
1992 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_850
,
1993 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1994 pbn_b0_bt_2_921600
},
1995 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_550
,
1996 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1997 pbn_b0_bt_4_921600
},
1998 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_650
,
1999 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2000 pbn_b0_bt_4_921600
},
2001 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_850
,
2002 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2003 pbn_b0_bt_4_921600
},
2006 * Computone devices submitted by Doug McNash dmcnash@computone.com
2008 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
2009 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG4
,
2010 0, 0, pbn_computone_4
},
2011 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
2012 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG8
,
2013 0, 0, pbn_computone_8
},
2014 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
2015 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG6
,
2016 0, 0, pbn_computone_6
},
2018 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI95N
,
2019 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2021 { PCI_VENDOR_ID_TIMEDIA
, PCI_DEVICE_ID_TIMEDIA_1889
,
2022 PCI_VENDOR_ID_TIMEDIA
, PCI_ANY_ID
, 0, 0,
2023 pbn_b0_bt_1_921600
},
2026 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2028 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P028
,
2029 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2030 pbn_b0_bt_8_115200
},
2031 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P030
,
2032 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2033 pbn_b0_bt_8_115200
},
2035 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_DSERIAL
,
2036 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2037 pbn_b0_bt_2_115200
},
2038 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_A
,
2039 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2040 pbn_b0_bt_2_115200
},
2041 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_B
,
2042 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2043 pbn_b0_bt_2_115200
},
2044 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_A
,
2045 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2046 pbn_b0_bt_4_460800
},
2047 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_B
,
2048 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2049 pbn_b0_bt_4_460800
},
2050 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_PLUS
,
2051 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2052 pbn_b0_bt_2_460800
},
2053 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_A
,
2054 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2055 pbn_b0_bt_2_460800
},
2056 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_B
,
2057 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2058 pbn_b0_bt_2_460800
},
2059 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_SSERIAL
,
2060 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2061 pbn_b0_bt_1_115200
},
2062 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_650
,
2063 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2064 pbn_b0_bt_1_460800
},
2067 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2069 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RAC4
,
2070 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2074 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2076 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RACIII
,
2077 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2081 * RAStel 2 port modem, gerg@moreton.com.au
2083 { PCI_VENDOR_ID_MORETON
, PCI_DEVICE_ID_RASTEL_2PORT
,
2084 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2085 pbn_b2_bt_2_115200
},
2088 * EKF addition for i960 Boards form EKF with serial port
2090 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80960_RP
,
2091 0xE4BF, PCI_ANY_ID
, 0, 0,
2095 * Xircom Cardbus/Ethernet combos
2097 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
2098 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2101 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2103 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_RBM56G
,
2104 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2108 * Untested PCI modems, sent in from various folks...
2112 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2114 { PCI_VENDOR_ID_ROCKWELL
, 0x1004,
2115 0x1048, 0x1500, 0, 0,
2118 { PCI_VENDOR_ID_SGI
, PCI_DEVICE_ID_SGI_IOC3
,
2125 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
2126 PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_RMP3
, 0, 0,
2128 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
2129 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2131 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_AUX
,
2132 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2136 * NEC Vrc-5074 (Nile 4) builtin UART.
2138 { PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_NILE4
,
2139 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2142 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM4
,
2143 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2145 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM8
,
2146 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2150 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2152 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2153 PCI_ANY_ID
, PCI_ANY_ID
,
2155 0, pbn_exar_XR17C152
},
2156 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2157 PCI_ANY_ID
, PCI_ANY_ID
,
2159 0, pbn_exar_XR17C154
},
2160 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2161 PCI_ANY_ID
, PCI_ANY_ID
,
2163 0, pbn_exar_XR17C158
},
2166 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2168 { PCI_VENDOR_ID_TOPIC
, PCI_DEVICE_ID_TOPIC_TP560
,
2169 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2173 * These entries match devices with class COMMUNICATION_SERIAL,
2174 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2176 { PCI_ANY_ID
, PCI_ANY_ID
,
2177 PCI_ANY_ID
, PCI_ANY_ID
,
2178 PCI_CLASS_COMMUNICATION_SERIAL
<< 8,
2179 0xffff00, pbn_default
},
2180 { PCI_ANY_ID
, PCI_ANY_ID
,
2181 PCI_ANY_ID
, PCI_ANY_ID
,
2182 PCI_CLASS_COMMUNICATION_MODEM
<< 8,
2183 0xffff00, pbn_default
},
2184 { PCI_ANY_ID
, PCI_ANY_ID
,
2185 PCI_ANY_ID
, PCI_ANY_ID
,
2186 PCI_CLASS_COMMUNICATION_MULTISERIAL
<< 8,
2187 0xffff00, pbn_default
},
2191 static struct pci_driver serial_pci_driver
= {
2193 .probe
= pciserial_init_one
,
2194 .remove
= __devexit_p(pciserial_remove_one
),
2195 .suspend
= pciserial_suspend_one
,
2196 .resume
= pciserial_resume_one
,
2197 .id_table
= serial_pci_tbl
,
2200 static int __init
serial8250_pci_init(void)
2202 return pci_register_driver(&serial_pci_driver
);
2205 static void __exit
serial8250_pci_exit(void)
2207 pci_unregister_driver(&serial_pci_driver
);
2210 module_init(serial8250_pci_init
);
2211 module_exit(serial8250_pci_exit
);
2213 MODULE_LICENSE("GPL");
2214 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2215 MODULE_DEVICE_TABLE(pci
, serial_pci_tbl
);