drivers/net/wireless/madwifi/hal/ah_desc.h

   1 /*-
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros
   3  * Communications, Inc.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms are permitted
   6  * provided that the following conditions are met:
   7  * 1. The materials contained herein are unmodified and are used
   8  *    unmodified.
   9  * 2. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following NO
  11  *    ''WARRANTY'' disclaimer below (''Disclaimer''), without
  12  *    modification.
  13  * 3. Redistributions in binary form must reproduce at minimum a
  14  *    disclaimer similar to the Disclaimer below and any redistribution
  15  *    must be conditioned upon including a substantially similar
  16  *    Disclaimer requirement for further binary redistribution.
  17  * 4. Neither the names of the above-listed copyright holders nor the
  18  *    names of any contributors may be used to endorse or promote
  19  *    product derived from this software without specific prior written
  20  *    permission.
  21  *
  22  * NO WARRANTY
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  24  * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
  26  * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
  28  * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  30  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  33  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGES.
  35  *
  36  * $Id: ah_desc.h 3851 2008-08-29 10:00:02Z nbd $
  37  */
  38
  39 #ifndef _DEV_ATH_DESC_H
  40 #define _DEV_ATH_DESC_H
  41
  42 #include "opt_ah.h"             /* NB: required for AH_SUPPORT_AR5416 */
  43
  44 /*
  45  * Transmit descriptor status.  This structure is filled
  46  * in only after the tx descriptor process method finds a
  47  * ``done'' descriptor; at which point it returns something
  48  * other than HAL_EINPROGRESS.
  49  *
  50  * Note that ts_antenna may not be valid for all h/w.  It
  51  * should be used only if non-zero.
  52  */
  53 struct ath_tx_status {
  54         u_int16_t       ts_seqnum;      /* h/w assigned sequence number */
  55         u_int16_t       ts_tstamp;      /* h/w assigned timestamp */
  56         u_int8_t        ts_status;      /* frame status, 0 => xmit ok */
  57         u_int8_t        ts_rate;        /* h/w transmit rate index */
  58 #define HAL_TXSTAT_ALTRATE      0x80    /* alternate xmit rate used */
  59         int8_t          ts_rssi;        /* tx ack RSSI */
  60         u_int8_t        ts_shortretry;  /* # short retries */
  61         u_int8_t        ts_longretry;   /* # long retries */
  62         u_int8_t        ts_virtcol;     /* virtual collision count */
  63         u_int8_t        ts_antenna;     /* antenna information */
  64         u_int8_t        ts_finaltsi;    /* final transmit series index */
  65 #ifdef AH_SUPPORT_AR5416
  66                                         /* 802.11n status */
  67         u_int8_t        ts_flags;       /* misc flags */
  68         int8_t          ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
  69         int8_t          ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
  70 /* #define ts_rssi ts_rssi_combined */
  71         u_int32_t       ts_ba_low;      /* blockack bitmap low */
  72         u_int32_t       ts_ba_high;     /* blockack bitmap high */
  73         u_int32_t       ts_evm0;        /* evm bytes */
  74         u_int32_t       ts_evm1;
  75         u_int32_t       ts_evm2;
  76 #endif /* AH_SUPPORT_AR5416 */
  77 };
  78
  79 /* bits found in ts_status */
  80 #define HAL_TXERR_XRETRY        0x01    /* excessive retries */
  81 #define HAL_TXERR_FILT          0x02    /* blocked by tx filtering */
  82 #define HAL_TXERR_FIFO          0x04    /* fifo underrun */
  83 #define HAL_TXERR_XTXOP         0x08    /* txop exceeded */
  84 #define HAL_TXERR_DESC_CFG_ERR  0x10    /* Error in 20/40 desc config */
  85 #define HAL_TXERR_DATA_UNDERRUN 0x20    /* Tx buffer underrun */
  86 #define HAL_TXERR_DELIM_UNDERRUN 0x40   /* Tx delimiter underrun */
  87
  88 /* bits found in ts_flags */
  89 #define HAL_TX_BA               0x01    /* Block Ack seen */
  90 #define HAL_TX_AGGR             0x02    /* Aggregate */
  91
  92 /*
  93  * Receive descriptor status.  This structure is filled
  94  * in only after the rx descriptor process method finds a
  95  * ``done'' descriptor; at which point it returns something
  96  * other than HAL_EINPROGRESS.
  97  *
  98  * If rx_status is zero, then the frame was received ok;
  99  * otherwise the error information is indicated and rs_phyerr
 100  * contains a phy error code if HAL_RXERR_PHY is set.  In general
 101  * the frame contents is undefined when an error occurred thought
 102  * for some errors (e.g. a decryption error), it may be meaningful.
 103  *
 104  * Note that the receive timestamp is expanded using the TSF to
 105  * at least 15 bits (regardless of what the h/w provides directly).
 106  * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
 107  * find out if the hardware is capable.
 108  *
 109  * rx_rssi is in units of dbm above the noise floor.  This value
 110  * is measured during the preamble and PLCP; i.e. with the initial
 111  * 4us of detection.  The noise floor is typically a consistent
 112  * -96dBm absolute power in a 20MHz channel.
 113  */
 114 struct ath_rx_status {
 115         u_int16_t       rs_datalen;     /* rx frame length */
 116         u_int8_t        rs_status;      /* rx status, 0 => recv ok */
 117         u_int8_t        rs_phyerr;      /* phy error code */
 118         int8_t          rs_rssi;        /* rx frame RSSI (combined for 11n) */
 119         u_int8_t        rs_keyix;       /* key cache index */
 120         u_int8_t        rs_rate;        /* h/w receive rate index */
 121         u_int8_t        rs_more;        /* more descriptors follow */
 122         u_int32_t       rs_tstamp;      /* h/w assigned timestamp */
 123         u_int32_t       rs_antenna;     /* antenna information */
 124 #ifdef AH_SUPPORT_AR5416
 125                                         /* 802.11n status */
 126         int8_t          rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
 127         int8_t          rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
 128         u_int8_t        rs_isaggr;      /* is part of the aggregate */
 129         u_int8_t        rs_moreaggr;    /* more frames in aggr to follow */
 130         u_int8_t        rs_num_delims;  /* number of delims in aggr */
 131         u_int8_t        rs_flags;       /* misc flags */
 132         u_int32_t       rs_evm0;        /* evm bytes */
 133         u_int32_t       rs_evm1;
 134         u_int32_t       rs_evm2;
 135 #endif /* AH_SUPPORT_AR5416 */
 136 };
 137
 138 /* bits found in rs_status */
 139 #define HAL_RXERR_CRC           0x01    /* CRC error on frame */
 140 #define HAL_RXERR_PHY           0x02    /* PHY error, rs_phyerr is valid */
 141 #define HAL_RXERR_FIFO          0x04    /* fifo overrun */
 142 #define HAL_RXERR_DECRYPT       0x08    /* non-Michael decrypt error */
 143 #define HAL_RXERR_MIC           0x10    /* Michael MIC decrypt error */
 144
 145 /* bits found in rs_flags */
 146 #define HAL_RX_MORE             0x01    /* more descriptors follow */
 147 #define HAL_RX_MORE_AGGR        0x02    /* more frames in aggr */
 148 #define HAL_RX_GI               0x04    /* full gi */
 149 #define HAL_RX_2040             0x08    /* 40 MHz */
 150 #define HAL_RX_DELIM_CRC_PRE    0x10    /* crc error in delimiter pre */
 151 #define HAL_RX_DELIM_CRC_POST   0x20    /* crc error in delim after */
 152 #define HAL_RX_DECRYPT_BUSY     0x40    /* decrypt was too slow */
 153 #define HAL_RX_DUP_FRAME        0x80    /* Dup frame rx'd on control channel */
 154
 155 enum {
 156         HAL_PHYERR_UNDERRUN             = 0,    /* Transmit underrun */
 157         HAL_PHYERR_TIMING               = 1,    /* Timing error */
 158         HAL_PHYERR_PARITY               = 2,    /* Illegal parity */
 159         HAL_PHYERR_RATE                 = 3,    /* Illegal rate */
 160         HAL_PHYERR_LENGTH               = 4,    /* Illegal length */
 161         HAL_PHYERR_RADAR                = 5,    /* Radar detect */
 162         HAL_PHYERR_SERVICE              = 6,    /* Illegal service */
 163         HAL_PHYERR_TOR                  = 7,    /* Transmit override receive */
 164         /* NB: these are specific to the 5212 */
 165         HAL_PHYERR_OFDM_TIMING          = 17,   /* */
 166         HAL_PHYERR_OFDM_SIGNAL_PARITY   = 18,   /* */
 167         HAL_PHYERR_OFDM_RATE_ILLEGAL    = 19,   /* */
 168         HAL_PHYERR_OFDM_LENGTH_ILLEGAL  = 20,   /* */
 169         HAL_PHYERR_OFDM_POWER_DROP      = 21,   /* */
 170         HAL_PHYERR_OFDM_SERVICE         = 22,   /* */
 171         HAL_PHYERR_OFDM_RESTART         = 23,   /* */
 172         HAL_PHYERR_CCK_TIMING           = 25,   /* */
 173         HAL_PHYERR_CCK_HEADER_CRC       = 26,   /* */
 174         HAL_PHYERR_CCK_RATE_ILLEGAL     = 27,   /* */
 175         HAL_PHYERR_CCK_SERVICE          = 30,   /* */
 176         HAL_PHYERR_CCK_RESTART          = 31,   /* */
 177 };
 178
 179 /* value found in rs_keyix to mark invalid entries */
 180 #define HAL_RXKEYIX_INVALID     ((u_int8_t) -1)
 181 /* value used to specify no encryption key for xmit */
 182 #define HAL_TXKEYIX_INVALID     ((u_int) -1)
 183
 184 /* XXX rs_antenna definitions */
 185
 186 /*
 187  * Definitions for the software frame/packet descriptors used by
 188  * the Atheros HAL.  This definition obscures hardware-specific
 189  * details from the driver.  Drivers are expected to fillin the
 190  * portions of a descriptor that are not opaque then use HAL calls
 191  * to complete the work.  Status for completed frames is returned
 192  * in a device-independent format.
 193  */
 194 #ifdef AH_SUPPORT_AR5416
 195 #define HAL_DESC_HW_SIZE        20
 196 #else
 197 #define HAL_DESC_HW_SIZE        4
 198 #endif /* AH_SUPPORT_AR5416 */
 199
 200 struct ath_desc {
 201         /*
 202          * The following definitions are passed directly
 203          * the hardware and managed by the HAL.  Drivers
 204          * should not touch those elements marked opaque.
 205          */
 206         u_int32_t       ds_link;        /* phys address of next descriptor */
 207         u_int32_t       ds_data;        /* phys address of data buffer */
 208         u_int32_t       ds_ctl0;        /* opaque DMA control 0 */
 209         u_int32_t       ds_ctl1;        /* opaque DMA control 1 */
 210         u_int32_t       ds_hw[HAL_DESC_HW_SIZE];        /* opaque h/w region */
 211 };
 212
 213 struct ath_desc_status {
 214         union {
 215                 struct ath_tx_status tx;/* xmit status */
 216                 struct ath_rx_status rx;/* recv status */
 217         } ds_us;
 218 };
 219
 220 #define ds_txstat       ds_us.tx
 221 #define ds_rxstat       ds_us.rx
 222
 223 /* flags passed to tx descriptor setup methods */
 224 #define HAL_TXDESC_CLRDMASK     0x0001  /* clear destination filter mask */
 225 #define HAL_TXDESC_NOACK        0x0002  /* don't wait for ACK */
 226 #define HAL_TXDESC_RTSENA       0x0004  /* enable RTS */
 227 #define HAL_TXDESC_CTSENA       0x0008  /* enable CTS */
 228 #define HAL_TXDESC_INTREQ       0x0010  /* enable per-descriptor interrupt */
 229 #define HAL_TXDESC_VEOL         0x0020  /* mark virtual EOL */
 230 /* NB: this only affects frame, not any RTS/CTS */
 231 #define HAL_TXDESC_DURENA       0x0040  /* enable h/w write of duration field */
 232 #define HAL_TXDESC_EXT_ONLY     0x0080  /* send on ext channel only (11n) */
 233 #define HAL_TXDESC_EXT_AND_CTL  0x0100  /* send on ext + ctl channels (11n) */
 234 #define HAL_TXDESC_VMF          0x0200  /* virtual more frag */
 235
 236 /* flags passed to rx descriptor setup methods */
 237 #define HAL_RXDESC_INTREQ       0x0020  /* enable per-descriptor interrupt */
 238 #endif /* _DEV_ATH_DESC_H */