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x86: IO-APIC - use NMI_NONE instead of numeric constant
[linux-2.6/zen-sources.git] / arch / x86 / kernel / io_apic_64.c
blob40a184d4dff89f1944c406f28182de93ce82485a
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 #define __apicdebuginit __init
86
87 int sis_apic_bug; /* not actually supported, dummy for compile */
88
89 static int no_timer_check;
90
91 static int disable_timer_pin_1 __initdata;
92
93 int timer_through_8259 __initdata;
94
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
97
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
100
101 /*
102 * # of IRQ routing registers
103 */
104 int nr_ioapic_registers[MAX_IO_APICS];
105
106 /* I/O APIC entries */
107 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
108 int nr_ioapics;
109
110 /* MP IRQ source entries */
111 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
112
113 /* # of MP IRQ source entries */
114 int mp_irq_entries;
115
116 /*
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
119 */
120 #define MAX_PLUS_SHARED_IRQS NR_IRQS
121 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
122
123 /*
124 * This is performance-critical, we want to do it O(1)
125 *
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
128 */
129
130 static struct irq_pin_list {
131 short apic, pin, next;
132 } irq_2_pin[PIN_MAP_SIZE];
133
134 struct io_apic {
135 unsigned int index;
136 unsigned int unused[3];
137 unsigned int data;
138 };
139
140 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
141 {
142 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
143 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
144 }
145
146 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
147 {
148 struct io_apic __iomem *io_apic = io_apic_base(apic);
149 writel(reg, &io_apic->index);
150 return readl(&io_apic->data);
151 }
152
153 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
154 {
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 writel(value, &io_apic->data);
158 }
159
160 /*
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
163 */
164 static inline void io_apic_modify(unsigned int apic, unsigned int value)
165 {
166 struct io_apic __iomem *io_apic = io_apic_base(apic);
167 writel(value, &io_apic->data);
168 }
169
170 static bool io_apic_level_ack_pending(unsigned int irq)
171 {
172 struct irq_pin_list *entry;
173 unsigned long flags;
174
175 spin_lock_irqsave(&ioapic_lock, flags);
176 entry = irq_2_pin + irq;
177 for (;;) {
178 unsigned int reg;
179 int pin;
180
181 pin = entry->pin;
182 if (pin == -1)
183 break;
184 reg = io_apic_read(entry->apic, 0x10 + pin*2);
185 /* Is the remote IRR bit set? */
186 if ((reg >> 14) & 1) {
187 spin_unlock_irqrestore(&ioapic_lock, flags);
188 return true;
189 }
190 if (!entry->next)
191 break;
192 entry = irq_2_pin + entry->next;
193 }
194 spin_unlock_irqrestore(&ioapic_lock, flags);
195
196 return false;
197 }
198
199 /*
200 * Synchronize the IO-APIC and the CPU by doing
201 * a dummy read from the IO-APIC
202 */
203 static inline void io_apic_sync(unsigned int apic)
204 {
205 struct io_apic __iomem *io_apic = io_apic_base(apic);
206 readl(&io_apic->data);
207 }
208
209 #define __DO_ACTION(R, ACTION, FINAL) \
210 \
211 { \
212 int pin; \
213 struct irq_pin_list *entry = irq_2_pin + irq; \
214 \
215 BUG_ON(irq >= NR_IRQS); \
216 for (;;) { \
217 unsigned int reg; \
218 pin = entry->pin; \
219 if (pin == -1) \
220 break; \
221 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
222 reg ACTION; \
223 io_apic_modify(entry->apic, reg); \
224 FINAL; \
225 if (!entry->next) \
226 break; \
227 entry = irq_2_pin + entry->next; \
228 } \
229 }
230
231 union entry_union {
232 struct { u32 w1, w2; };
233 struct IO_APIC_route_entry entry;
234 };
235
236 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
237 {
238 union entry_union eu;
239 unsigned long flags;
240 spin_lock_irqsave(&ioapic_lock, flags);
241 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
242 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
244 return eu.entry;
245 }
246
247 /*
248 * When we write a new IO APIC routing entry, we need to write the high
249 * word first! If the mask bit in the low word is clear, we will enable
250 * the interrupt, and we need to make sure the entry is fully populated
251 * before that happens.
252 */
253 static void
254 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
255 {
256 union entry_union eu;
257 eu.entry = e;
258 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
259 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
260 }
261
262 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
263 {
264 unsigned long flags;
265 spin_lock_irqsave(&ioapic_lock, flags);
266 __ioapic_write_entry(apic, pin, e);
267 spin_unlock_irqrestore(&ioapic_lock, flags);
268 }
269
270 /*
271 * When we mask an IO APIC routing entry, we need to write the low
272 * word first, in order to set the mask bit before we change the
273 * high bits!
274 */
275 static void ioapic_mask_entry(int apic, int pin)
276 {
277 unsigned long flags;
278 union entry_union eu = { .entry.mask = 1 };
279
280 spin_lock_irqsave(&ioapic_lock, flags);
281 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
282 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
284 }
285
286 #ifdef CONFIG_SMP
287 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
288 {
289 int apic, pin;
290 struct irq_pin_list *entry = irq_2_pin + irq;
291
292 BUG_ON(irq >= NR_IRQS);
293 for (;;) {
294 unsigned int reg;
295 apic = entry->apic;
296 pin = entry->pin;
297 if (pin == -1)
298 break;
299 io_apic_write(apic, 0x11 + pin*2, dest);
300 reg = io_apic_read(apic, 0x10 + pin*2);
301 reg &= ~0x000000ff;
302 reg |= vector;
303 io_apic_modify(apic, reg);
304 if (!entry->next)
305 break;
306 entry = irq_2_pin + entry->next;
307 }
308 }
309
310 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
311 {
312 struct irq_cfg *cfg = irq_cfg + irq;
313 unsigned long flags;
314 unsigned int dest;
315 cpumask_t tmp;
316
317 cpus_and(tmp, mask, cpu_online_map);
318 if (cpus_empty(tmp))
319 return;
320
321 if (assign_irq_vector(irq, mask))
322 return;
323
324 cpus_and(tmp, cfg->domain, mask);
325 dest = cpu_mask_to_apicid(tmp);
326
327 /*
328 * Only the high 8 bits are valid.
329 */
330 dest = SET_APIC_LOGICAL_ID(dest);
331
332 spin_lock_irqsave(&ioapic_lock, flags);
333 __target_IO_APIC_irq(irq, dest, cfg->vector);
334 irq_desc[irq].affinity = mask;
335 spin_unlock_irqrestore(&ioapic_lock, flags);
336 }
337 #endif
338
339 /*
340 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
341 * shared ISA-space IRQs, so we have to support them. We are super
342 * fast in the common case, and fast for shared ISA-space IRQs.
343 */
344 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
345 {
346 static int first_free_entry = NR_IRQS;
347 struct irq_pin_list *entry = irq_2_pin + irq;
348
349 BUG_ON(irq >= NR_IRQS);
350 while (entry->next)
351 entry = irq_2_pin + entry->next;
352
353 if (entry->pin != -1) {
354 entry->next = first_free_entry;
355 entry = irq_2_pin + entry->next;
356 if (++first_free_entry >= PIN_MAP_SIZE)
357 panic("io_apic.c: ran out of irq_2_pin entries!");
358 }
359 entry->apic = apic;
360 entry->pin = pin;
361 }
362
363
364 #define DO_ACTION(name,R,ACTION, FINAL) \
365 \
366 static void name##_IO_APIC_irq (unsigned int irq) \
367 __DO_ACTION(R, ACTION, FINAL)
368
369 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
370 /* mask = 1 */
371 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
372 /* mask = 0 */
373
374 static void mask_IO_APIC_irq (unsigned int irq)
375 {
376 unsigned long flags;
377
378 spin_lock_irqsave(&ioapic_lock, flags);
379 __mask_IO_APIC_irq(irq);
380 spin_unlock_irqrestore(&ioapic_lock, flags);
381 }
382
383 static void unmask_IO_APIC_irq (unsigned int irq)
384 {
385 unsigned long flags;
386
387 spin_lock_irqsave(&ioapic_lock, flags);
388 __unmask_IO_APIC_irq(irq);
389 spin_unlock_irqrestore(&ioapic_lock, flags);
390 }
391
392 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
393 {
394 struct IO_APIC_route_entry entry;
395
396 /* Check delivery_mode to be sure we're not clearing an SMI pin */
397 entry = ioapic_read_entry(apic, pin);
398 if (entry.delivery_mode == dest_SMI)
399 return;
400 /*
401 * Disable it in the IO-APIC irq-routing table:
402 */
403 ioapic_mask_entry(apic, pin);
404 }
405
406 static void clear_IO_APIC (void)
407 {
408 int apic, pin;
409
410 for (apic = 0; apic < nr_ioapics; apic++)
411 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
412 clear_IO_APIC_pin(apic, pin);
413 }
414
415 int skip_ioapic_setup;
416 int ioapic_force;
417
418 static int __init parse_noapic(char *str)
419 {
420 disable_ioapic_setup();
421 return 0;
422 }
423 early_param("noapic", parse_noapic);
424
425 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
426 static int __init disable_timer_pin_setup(char *arg)
427 {
428 disable_timer_pin_1 = 1;
429 return 1;
430 }
431 __setup("disable_timer_pin_1", disable_timer_pin_setup);
432
433
434 /*
435 * Find the IRQ entry number of a certain pin.
436 */
437 static int find_irq_entry(int apic, int pin, int type)
438 {
439 int i;
440
441 for (i = 0; i < mp_irq_entries; i++)
442 if (mp_irqs[i].mpc_irqtype == type &&
443 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
444 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
445 mp_irqs[i].mpc_dstirq == pin)
446 return i;
447
448 return -1;
449 }
450
451 /*
452 * Find the pin to which IRQ[irq] (ISA) is connected
453 */
454 static int __init find_isa_irq_pin(int irq, int type)
455 {
456 int i;
457
458 for (i = 0; i < mp_irq_entries; i++) {
459 int lbus = mp_irqs[i].mpc_srcbus;
460
461 if (test_bit(lbus, mp_bus_not_pci) &&
462 (mp_irqs[i].mpc_irqtype == type) &&
463 (mp_irqs[i].mpc_srcbusirq == irq))
464
465 return mp_irqs[i].mpc_dstirq;
466 }
467 return -1;
468 }
469
470 static int __init find_isa_irq_apic(int irq, int type)
471 {
472 int i;
473
474 for (i = 0; i < mp_irq_entries; i++) {
475 int lbus = mp_irqs[i].mpc_srcbus;
476
477 if (test_bit(lbus, mp_bus_not_pci) &&
478 (mp_irqs[i].mpc_irqtype == type) &&
479 (mp_irqs[i].mpc_srcbusirq == irq))
480 break;
481 }
482 if (i < mp_irq_entries) {
483 int apic;
484 for(apic = 0; apic < nr_ioapics; apic++) {
485 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
486 return apic;
487 }
488 }
489
490 return -1;
491 }
492
493 /*
494 * Find a specific PCI IRQ entry.
495 * Not an __init, possibly needed by modules
496 */
497 static int pin_2_irq(int idx, int apic, int pin);
498
499 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
500 {
501 int apic, i, best_guess = -1;
502
503 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
504 bus, slot, pin);
505 if (mp_bus_id_to_pci_bus[bus] == -1) {
506 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
507 return -1;
508 }
509 for (i = 0; i < mp_irq_entries; i++) {
510 int lbus = mp_irqs[i].mpc_srcbus;
511
512 for (apic = 0; apic < nr_ioapics; apic++)
513 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
514 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
515 break;
516
517 if (!test_bit(lbus, mp_bus_not_pci) &&
518 !mp_irqs[i].mpc_irqtype &&
519 (bus == lbus) &&
520 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
521 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
522
523 if (!(apic || IO_APIC_IRQ(irq)))
524 continue;
525
526 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
527 return irq;
528 /*
529 * Use the first all-but-pin matching entry as a
530 * best-guess fuzzy result for broken mptables.
531 */
532 if (best_guess < 0)
533 best_guess = irq;
534 }
535 }
536 BUG_ON(best_guess >= NR_IRQS);
537 return best_guess;
538 }
539
540 /* ISA interrupts are always polarity zero edge triggered,
541 * when listed as conforming in the MP table. */
542
543 #define default_ISA_trigger(idx) (0)
544 #define default_ISA_polarity(idx) (0)
545
546 /* PCI interrupts are always polarity one level triggered,
547 * when listed as conforming in the MP table. */
548
549 #define default_PCI_trigger(idx) (1)
550 #define default_PCI_polarity(idx) (1)
551
552 static int MPBIOS_polarity(int idx)
553 {
554 int bus = mp_irqs[idx].mpc_srcbus;
555 int polarity;
556
557 /*
558 * Determine IRQ line polarity (high active or low active):
559 */
560 switch (mp_irqs[idx].mpc_irqflag & 3)
561 {
562 case 0: /* conforms, ie. bus-type dependent polarity */
563 if (test_bit(bus, mp_bus_not_pci))
564 polarity = default_ISA_polarity(idx);
565 else
566 polarity = default_PCI_polarity(idx);
567 break;
568 case 1: /* high active */
569 {
570 polarity = 0;
571 break;
572 }
573 case 2: /* reserved */
574 {
575 printk(KERN_WARNING "broken BIOS!!\n");
576 polarity = 1;
577 break;
578 }
579 case 3: /* low active */
580 {
581 polarity = 1;
582 break;
583 }
584 default: /* invalid */
585 {
586 printk(KERN_WARNING "broken BIOS!!\n");
587 polarity = 1;
588 break;
589 }
590 }
591 return polarity;
592 }
593
594 static int MPBIOS_trigger(int idx)
595 {
596 int bus = mp_irqs[idx].mpc_srcbus;
597 int trigger;
598
599 /*
600 * Determine IRQ trigger mode (edge or level sensitive):
601 */
602 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
603 {
604 case 0: /* conforms, ie. bus-type dependent */
605 if (test_bit(bus, mp_bus_not_pci))
606 trigger = default_ISA_trigger(idx);
607 else
608 trigger = default_PCI_trigger(idx);
609 break;
610 case 1: /* edge */
611 {
612 trigger = 0;
613 break;
614 }
615 case 2: /* reserved */
616 {
617 printk(KERN_WARNING "broken BIOS!!\n");
618 trigger = 1;
619 break;
620 }
621 case 3: /* level */
622 {
623 trigger = 1;
624 break;
625 }
626 default: /* invalid */
627 {
628 printk(KERN_WARNING "broken BIOS!!\n");
629 trigger = 0;
630 break;
631 }
632 }
633 return trigger;
634 }
635
636 static inline int irq_polarity(int idx)
637 {
638 return MPBIOS_polarity(idx);
639 }
640
641 static inline int irq_trigger(int idx)
642 {
643 return MPBIOS_trigger(idx);
644 }
645
646 static int pin_2_irq(int idx, int apic, int pin)
647 {
648 int irq, i;
649 int bus = mp_irqs[idx].mpc_srcbus;
650
651 /*
652 * Debugging check, we are in big trouble if this message pops up!
653 */
654 if (mp_irqs[idx].mpc_dstirq != pin)
655 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
656
657 if (test_bit(bus, mp_bus_not_pci)) {
658 irq = mp_irqs[idx].mpc_srcbusirq;
659 } else {
660 /*
661 * PCI IRQs are mapped in order
662 */
663 i = irq = 0;
664 while (i < apic)
665 irq += nr_ioapic_registers[i++];
666 irq += pin;
667 }
668 BUG_ON(irq >= NR_IRQS);
669 return irq;
670 }
671
672 static int __assign_irq_vector(int irq, cpumask_t mask)
673 {
674 /*
675 * NOTE! The local APIC isn't very good at handling
676 * multiple interrupts at the same interrupt level.
677 * As the interrupt level is determined by taking the
678 * vector number and shifting that right by 4, we
679 * want to spread these out a bit so that they don't
680 * all fall in the same interrupt level.
681 *
682 * Also, we've got to be careful not to trash gate
683 * 0x80, because int 0x80 is hm, kind of importantish. ;)
684 */
685 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
686 unsigned int old_vector;
687 int cpu;
688 struct irq_cfg *cfg;
689
690 BUG_ON((unsigned)irq >= NR_IRQS);
691 cfg = &irq_cfg[irq];
692
693 /* Only try and allocate irqs on cpus that are present */
694 cpus_and(mask, mask, cpu_online_map);
695
696 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
697 return -EBUSY;
698
699 old_vector = cfg->vector;
700 if (old_vector) {
701 cpumask_t tmp;
702 cpus_and(tmp, cfg->domain, mask);
703 if (!cpus_empty(tmp))
704 return 0;
705 }
706
707 for_each_cpu_mask(cpu, mask) {
708 cpumask_t domain, new_mask;
709 int new_cpu;
710 int vector, offset;
711
712 domain = vector_allocation_domain(cpu);
713 cpus_and(new_mask, domain, cpu_online_map);
714
715 vector = current_vector;
716 offset = current_offset;
717 next:
718 vector += 8;
719 if (vector >= FIRST_SYSTEM_VECTOR) {
720 /* If we run out of vectors on large boxen, must share them. */
721 offset = (offset + 1) % 8;
722 vector = FIRST_DEVICE_VECTOR + offset;
723 }
724 if (unlikely(current_vector == vector))
725 continue;
726 if (vector == IA32_SYSCALL_VECTOR)
727 goto next;
728 for_each_cpu_mask(new_cpu, new_mask)
729 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
730 goto next;
731 /* Found one! */
732 current_vector = vector;
733 current_offset = offset;
734 if (old_vector) {
735 cfg->move_in_progress = 1;
736 cfg->old_domain = cfg->domain;
737 }
738 for_each_cpu_mask(new_cpu, new_mask)
739 per_cpu(vector_irq, new_cpu)[vector] = irq;
740 cfg->vector = vector;
741 cfg->domain = domain;
742 return 0;
743 }
744 return -ENOSPC;
745 }
746
747 static int assign_irq_vector(int irq, cpumask_t mask)
748 {
749 int err;
750 unsigned long flags;
751
752 spin_lock_irqsave(&vector_lock, flags);
753 err = __assign_irq_vector(irq, mask);
754 spin_unlock_irqrestore(&vector_lock, flags);
755 return err;
756 }
757
758 static void __clear_irq_vector(int irq)
759 {
760 struct irq_cfg *cfg;
761 cpumask_t mask;
762 int cpu, vector;
763
764 BUG_ON((unsigned)irq >= NR_IRQS);
765 cfg = &irq_cfg[irq];
766 BUG_ON(!cfg->vector);
767
768 vector = cfg->vector;
769 cpus_and(mask, cfg->domain, cpu_online_map);
770 for_each_cpu_mask(cpu, mask)
771 per_cpu(vector_irq, cpu)[vector] = -1;
772
773 cfg->vector = 0;
774 cpus_clear(cfg->domain);
775 }
776
777 void __setup_vector_irq(int cpu)
778 {
779 /* Initialize vector_irq on a new cpu */
780 /* This function must be called with vector_lock held */
781 int irq, vector;
782
783 /* Mark the inuse vectors */
784 for (irq = 0; irq < NR_IRQS; ++irq) {
785 if (!cpu_isset(cpu, irq_cfg[irq].domain))
786 continue;
787 vector = irq_cfg[irq].vector;
788 per_cpu(vector_irq, cpu)[vector] = irq;
789 }
790 /* Mark the free vectors */
791 for (vector = 0; vector < NR_VECTORS; ++vector) {
792 irq = per_cpu(vector_irq, cpu)[vector];
793 if (irq < 0)
794 continue;
795 if (!cpu_isset(cpu, irq_cfg[irq].domain))
796 per_cpu(vector_irq, cpu)[vector] = -1;
797 }
798 }
799
800
801 static struct irq_chip ioapic_chip;
802
803 static void ioapic_register_intr(int irq, unsigned long trigger)
804 {
805 if (trigger) {
806 irq_desc[irq].status |= IRQ_LEVEL;
807 set_irq_chip_and_handler_name(irq, &ioapic_chip,
808 handle_fasteoi_irq, "fasteoi");
809 } else {
810 irq_desc[irq].status &= ~IRQ_LEVEL;
811 set_irq_chip_and_handler_name(irq, &ioapic_chip,
812 handle_edge_irq, "edge");
813 }
814 }
815
816 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
817 int trigger, int polarity)
818 {
819 struct irq_cfg *cfg = irq_cfg + irq;
820 struct IO_APIC_route_entry entry;
821 cpumask_t mask;
822
823 if (!IO_APIC_IRQ(irq))
824 return;
825
826 mask = TARGET_CPUS;
827 if (assign_irq_vector(irq, mask))
828 return;
829
830 cpus_and(mask, cfg->domain, mask);
831
832 apic_printk(APIC_VERBOSE,KERN_DEBUG
833 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
834 "IRQ %d Mode:%i Active:%i)\n",
835 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
836 irq, trigger, polarity);
837
838 /*
839 * add it to the IO-APIC irq-routing table:
840 */
841 memset(&entry,0,sizeof(entry));
842
843 entry.delivery_mode = INT_DELIVERY_MODE;
844 entry.dest_mode = INT_DEST_MODE;
845 entry.dest = cpu_mask_to_apicid(mask);
846 entry.mask = 0; /* enable IRQ */
847 entry.trigger = trigger;
848 entry.polarity = polarity;
849 entry.vector = cfg->vector;
850
851 /* Mask level triggered irqs.
852 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
853 */
854 if (trigger)
855 entry.mask = 1;
856
857 ioapic_register_intr(irq, trigger);
858 if (irq < 16)
859 disable_8259A_irq(irq);
860
861 ioapic_write_entry(apic, pin, entry);
862 }
863
864 static void __init setup_IO_APIC_irqs(void)
865 {
866 int apic, pin, idx, irq, first_notcon = 1;
867
868 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
869
870 for (apic = 0; apic < nr_ioapics; apic++) {
871 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
872
873 idx = find_irq_entry(apic,pin,mp_INT);
874 if (idx == -1) {
875 if (first_notcon) {
876 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
877 first_notcon = 0;
878 } else
879 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
880 continue;
881 }
882 if (!first_notcon) {
883 apic_printk(APIC_VERBOSE, " not connected.\n");
884 first_notcon = 1;
885 }
886
887 irq = pin_2_irq(idx, apic, pin);
888 add_pin_to_irq(irq, apic, pin);
889
890 setup_IO_APIC_irq(apic, pin, irq,
891 irq_trigger(idx), irq_polarity(idx));
892 }
893 }
894
895 if (!first_notcon)
896 apic_printk(APIC_VERBOSE, " not connected.\n");
897 }
898
899 /*
900 * Set up the timer pin, possibly with the 8259A-master behind.
901 */
902 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
903 int vector)
904 {
905 struct IO_APIC_route_entry entry;
906
907 memset(&entry, 0, sizeof(entry));
908
909 /*
910 * We use logical delivery to get the timer IRQ
911 * to the first CPU.
912 */
913 entry.dest_mode = INT_DEST_MODE;
914 entry.mask = 1; /* mask IRQ now */
915 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
916 entry.delivery_mode = INT_DELIVERY_MODE;
917 entry.polarity = 0;
918 entry.trigger = 0;
919 entry.vector = vector;
920
921 /*
922 * The timer IRQ doesn't have to know that behind the
923 * scene we may have a 8259A-master in AEOI mode ...
924 */
925 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
926
927 /*
928 * Add it to the IO-APIC irq-routing table:
929 */
930 ioapic_write_entry(apic, pin, entry);
931 }
932
933 void __apicdebuginit print_IO_APIC(void)
934 {
935 int apic, i;
936 union IO_APIC_reg_00 reg_00;
937 union IO_APIC_reg_01 reg_01;
938 union IO_APIC_reg_02 reg_02;
939 unsigned long flags;
940
941 if (apic_verbosity == APIC_QUIET)
942 return;
943
944 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
945 for (i = 0; i < nr_ioapics; i++)
946 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
947 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
948
949 /*
950 * We are a bit conservative about what we expect. We have to
951 * know about every hardware change ASAP.
952 */
953 printk(KERN_INFO "testing the IO APIC.......................\n");
954
955 for (apic = 0; apic < nr_ioapics; apic++) {
956
957 spin_lock_irqsave(&ioapic_lock, flags);
958 reg_00.raw = io_apic_read(apic, 0);
959 reg_01.raw = io_apic_read(apic, 1);
960 if (reg_01.bits.version >= 0x10)
961 reg_02.raw = io_apic_read(apic, 2);
962 spin_unlock_irqrestore(&ioapic_lock, flags);
963
964 printk("\n");
965 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
966 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
967 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
968
969 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
970 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
971
972 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
973 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
974
975 if (reg_01.bits.version >= 0x10) {
976 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
977 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
978 }
979
980 printk(KERN_DEBUG ".... IRQ redirection table:\n");
981
982 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
983 " Stat Dmod Deli Vect: \n");
984
985 for (i = 0; i <= reg_01.bits.entries; i++) {
986 struct IO_APIC_route_entry entry;
987
988 entry = ioapic_read_entry(apic, i);
989
990 printk(KERN_DEBUG " %02x %03X ",
991 i,
992 entry.dest
993 );
994
995 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
996 entry.mask,
997 entry.trigger,
998 entry.irr,
999 entry.polarity,
1000 entry.delivery_status,
1001 entry.dest_mode,
1002 entry.delivery_mode,
1003 entry.vector
1004 );
1005 }
1006 }
1007 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1008 for (i = 0; i < NR_IRQS; i++) {
1009 struct irq_pin_list *entry = irq_2_pin + i;
1010 if (entry->pin < 0)
1011 continue;
1012 printk(KERN_DEBUG "IRQ%d ", i);
1013 for (;;) {
1014 printk("-> %d:%d", entry->apic, entry->pin);
1015 if (!entry->next)
1016 break;
1017 entry = irq_2_pin + entry->next;
1018 }
1019 printk("\n");
1020 }
1021
1022 printk(KERN_INFO ".................................... done.\n");
1023
1024 return;
1025 }
1026
1027 #if 0
1028
1029 static __apicdebuginit void print_APIC_bitfield (int base)
1030 {
1031 unsigned int v;
1032 int i, j;
1033
1034 if (apic_verbosity == APIC_QUIET)
1035 return;
1036
1037 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1038 for (i = 0; i < 8; i++) {
1039 v = apic_read(base + i*0x10);
1040 for (j = 0; j < 32; j++) {
1041 if (v & (1<<j))
1042 printk("1");
1043 else
1044 printk("0");
1045 }
1046 printk("\n");
1047 }
1048 }
1049
1050 void __apicdebuginit print_local_APIC(void * dummy)
1051 {
1052 unsigned int v, ver, maxlvt;
1053
1054 if (apic_verbosity == APIC_QUIET)
1055 return;
1056
1057 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1058 smp_processor_id(), hard_smp_processor_id());
1059 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1060 v = apic_read(APIC_LVR);
1061 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1062 ver = GET_APIC_VERSION(v);
1063 maxlvt = lapic_get_maxlvt();
1064
1065 v = apic_read(APIC_TASKPRI);
1066 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1067
1068 v = apic_read(APIC_ARBPRI);
1069 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1070 v & APIC_ARBPRI_MASK);
1071 v = apic_read(APIC_PROCPRI);
1072 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1073
1074 v = apic_read(APIC_EOI);
1075 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1076 v = apic_read(APIC_RRR);
1077 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1078 v = apic_read(APIC_LDR);
1079 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1080 v = apic_read(APIC_DFR);
1081 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1082 v = apic_read(APIC_SPIV);
1083 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1084
1085 printk(KERN_DEBUG "... APIC ISR field:\n");
1086 print_APIC_bitfield(APIC_ISR);
1087 printk(KERN_DEBUG "... APIC TMR field:\n");
1088 print_APIC_bitfield(APIC_TMR);
1089 printk(KERN_DEBUG "... APIC IRR field:\n");
1090 print_APIC_bitfield(APIC_IRR);
1091
1092 v = apic_read(APIC_ESR);
1093 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1094
1095 v = apic_read(APIC_ICR);
1096 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1097 v = apic_read(APIC_ICR2);
1098 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1099
1100 v = apic_read(APIC_LVTT);
1101 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1102
1103 if (maxlvt > 3) { /* PC is LVT#4. */
1104 v = apic_read(APIC_LVTPC);
1105 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1106 }
1107 v = apic_read(APIC_LVT0);
1108 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1109 v = apic_read(APIC_LVT1);
1110 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1111
1112 if (maxlvt > 2) { /* ERR is LVT#3. */
1113 v = apic_read(APIC_LVTERR);
1114 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1115 }
1116
1117 v = apic_read(APIC_TMICT);
1118 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1119 v = apic_read(APIC_TMCCT);
1120 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1121 v = apic_read(APIC_TDCR);
1122 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1123 printk("\n");
1124 }
1125
1126 void print_all_local_APICs (void)
1127 {
1128 on_each_cpu(print_local_APIC, NULL, 1, 1);
1129 }
1130
1131 void __apicdebuginit print_PIC(void)
1132 {
1133 unsigned int v;
1134 unsigned long flags;
1135
1136 if (apic_verbosity == APIC_QUIET)
1137 return;
1138
1139 printk(KERN_DEBUG "\nprinting PIC contents\n");
1140
1141 spin_lock_irqsave(&i8259A_lock, flags);
1142
1143 v = inb(0xa1) << 8 | inb(0x21);
1144 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1145
1146 v = inb(0xa0) << 8 | inb(0x20);
1147 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1148
1149 outb(0x0b,0xa0);
1150 outb(0x0b,0x20);
1151 v = inb(0xa0) << 8 | inb(0x20);
1152 outb(0x0a,0xa0);
1153 outb(0x0a,0x20);
1154
1155 spin_unlock_irqrestore(&i8259A_lock, flags);
1156
1157 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1158
1159 v = inb(0x4d1) << 8 | inb(0x4d0);
1160 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1161 }
1162
1163 #endif /* 0 */
1164
1165 void __init enable_IO_APIC(void)
1166 {
1167 union IO_APIC_reg_01 reg_01;
1168 int i8259_apic, i8259_pin;
1169 int i, apic;
1170 unsigned long flags;
1171
1172 for (i = 0; i < PIN_MAP_SIZE; i++) {
1173 irq_2_pin[i].pin = -1;
1174 irq_2_pin[i].next = 0;
1175 }
1176
1177 /*
1178 * The number of IO-APIC IRQ registers (== #pins):
1179 */
1180 for (apic = 0; apic < nr_ioapics; apic++) {
1181 spin_lock_irqsave(&ioapic_lock, flags);
1182 reg_01.raw = io_apic_read(apic, 1);
1183 spin_unlock_irqrestore(&ioapic_lock, flags);
1184 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1185 }
1186 for(apic = 0; apic < nr_ioapics; apic++) {
1187 int pin;
1188 /* See if any of the pins is in ExtINT mode */
1189 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1190 struct IO_APIC_route_entry entry;
1191 entry = ioapic_read_entry(apic, pin);
1192
1193 /* If the interrupt line is enabled and in ExtInt mode
1194 * I have found the pin where the i8259 is connected.
1195 */
1196 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1197 ioapic_i8259.apic = apic;
1198 ioapic_i8259.pin = pin;
1199 goto found_i8259;
1200 }
1201 }
1202 }
1203 found_i8259:
1204 /* Look to see what if the MP table has reported the ExtINT */
1205 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1206 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1207 /* Trust the MP table if nothing is setup in the hardware */
1208 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1209 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1210 ioapic_i8259.pin = i8259_pin;
1211 ioapic_i8259.apic = i8259_apic;
1212 }
1213 /* Complain if the MP table and the hardware disagree */
1214 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1215 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1216 {
1217 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1218 }
1219
1220 /*
1221 * Do not trust the IO-APIC being empty at bootup
1222 */
1223 clear_IO_APIC();
1224 }
1225
1226 /*
1227 * Not an __init, needed by the reboot code
1228 */
1229 void disable_IO_APIC(void)
1230 {
1231 /*
1232 * Clear the IO-APIC before rebooting:
1233 */
1234 clear_IO_APIC();
1235
1236 /*
1237 * If the i8259 is routed through an IOAPIC
1238 * Put that IOAPIC in virtual wire mode
1239 * so legacy interrupts can be delivered.
1240 */
1241 if (ioapic_i8259.pin != -1) {
1242 struct IO_APIC_route_entry entry;
1243
1244 memset(&entry, 0, sizeof(entry));
1245 entry.mask = 0; /* Enabled */
1246 entry.trigger = 0; /* Edge */
1247 entry.irr = 0;
1248 entry.polarity = 0; /* High */
1249 entry.delivery_status = 0;
1250 entry.dest_mode = 0; /* Physical */
1251 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1252 entry.vector = 0;
1253 entry.dest = GET_APIC_ID(read_apic_id());
1254
1255 /*
1256 * Add it to the IO-APIC irq-routing table:
1257 */
1258 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1259 }
1260
1261 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1262 }
1263
1264 /*
1265 * There is a nasty bug in some older SMP boards, their mptable lies
1266 * about the timer IRQ. We do the following to work around the situation:
1267 *
1268 * - timer IRQ defaults to IO-APIC IRQ
1269 * - if this function detects that timer IRQs are defunct, then we fall
1270 * back to ISA timer IRQs
1271 */
1272 static int __init timer_irq_works(void)
1273 {
1274 unsigned long t1 = jiffies;
1275 unsigned long flags;
1276
1277 local_save_flags(flags);
1278 local_irq_enable();
1279 /* Let ten ticks pass... */
1280 mdelay((10 * 1000) / HZ);
1281 local_irq_restore(flags);
1282
1283 /*
1284 * Expect a few ticks at least, to be sure some possible
1285 * glue logic does not lock up after one or two first
1286 * ticks in a non-ExtINT mode. Also the local APIC
1287 * might have cached one ExtINT interrupt. Finally, at
1288 * least one tick may be lost due to delays.
1289 */
1290
1291 /* jiffies wrap? */
1292 if (time_after(jiffies, t1 + 4))
1293 return 1;
1294 return 0;
1295 }
1296
1297 /*
1298 * In the SMP+IOAPIC case it might happen that there are an unspecified
1299 * number of pending IRQ events unhandled. These cases are very rare,
1300 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1301 * better to do it this way as thus we do not have to be aware of
1302 * 'pending' interrupts in the IRQ path, except at this point.
1303 */
1304 /*
1305 * Edge triggered needs to resend any interrupt
1306 * that was delayed but this is now handled in the device
1307 * independent code.
1308 */
1309
1310 /*
1311 * Starting up a edge-triggered IO-APIC interrupt is
1312 * nasty - we need to make sure that we get the edge.
1313 * If it is already asserted for some reason, we need
1314 * return 1 to indicate that is was pending.
1315 *
1316 * This is not complete - we should be able to fake
1317 * an edge even if it isn't on the 8259A...
1318 */
1319
1320 static unsigned int startup_ioapic_irq(unsigned int irq)
1321 {
1322 int was_pending = 0;
1323 unsigned long flags;
1324
1325 spin_lock_irqsave(&ioapic_lock, flags);
1326 if (irq < 16) {
1327 disable_8259A_irq(irq);
1328 if (i8259A_irq_pending(irq))
1329 was_pending = 1;
1330 }
1331 __unmask_IO_APIC_irq(irq);
1332 spin_unlock_irqrestore(&ioapic_lock, flags);
1333
1334 return was_pending;
1335 }
1336
1337 static int ioapic_retrigger_irq(unsigned int irq)
1338 {
1339 struct irq_cfg *cfg = &irq_cfg[irq];
1340 cpumask_t mask;
1341 unsigned long flags;
1342
1343 spin_lock_irqsave(&vector_lock, flags);
1344 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1345 send_IPI_mask(mask, cfg->vector);
1346 spin_unlock_irqrestore(&vector_lock, flags);
1347
1348 return 1;
1349 }
1350
1351 /*
1352 * Level and edge triggered IO-APIC interrupts need different handling,
1353 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1354 * handled with the level-triggered descriptor, but that one has slightly
1355 * more overhead. Level-triggered interrupts cannot be handled with the
1356 * edge-triggered handler, without risking IRQ storms and other ugly
1357 * races.
1358 */
1359
1360 #ifdef CONFIG_SMP
1361 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1362 {
1363 unsigned vector, me;
1364 ack_APIC_irq();
1365 exit_idle();
1366 irq_enter();
1367
1368 me = smp_processor_id();
1369 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1370 unsigned int irq;
1371 struct irq_desc *desc;
1372 struct irq_cfg *cfg;
1373 irq = __get_cpu_var(vector_irq)[vector];
1374 if (irq >= NR_IRQS)
1375 continue;
1376
1377 desc = irq_desc + irq;
1378 cfg = irq_cfg + irq;
1379 spin_lock(&desc->lock);
1380 if (!cfg->move_cleanup_count)
1381 goto unlock;
1382
1383 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1384 goto unlock;
1385
1386 __get_cpu_var(vector_irq)[vector] = -1;
1387 cfg->move_cleanup_count--;
1388 unlock:
1389 spin_unlock(&desc->lock);
1390 }
1391
1392 irq_exit();
1393 }
1394
1395 static void irq_complete_move(unsigned int irq)
1396 {
1397 struct irq_cfg *cfg = irq_cfg + irq;
1398 unsigned vector, me;
1399
1400 if (likely(!cfg->move_in_progress))
1401 return;
1402
1403 vector = ~get_irq_regs()->orig_ax;
1404 me = smp_processor_id();
1405 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1406 cpumask_t cleanup_mask;
1407
1408 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1409 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1410 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1411 cfg->move_in_progress = 0;
1412 }
1413 }
1414 #else
1415 static inline void irq_complete_move(unsigned int irq) {}
1416 #endif
1417
1418 static void ack_apic_edge(unsigned int irq)
1419 {
1420 irq_complete_move(irq);
1421 move_native_irq(irq);
1422 ack_APIC_irq();
1423 }
1424
1425 static void ack_apic_level(unsigned int irq)
1426 {
1427 int do_unmask_irq = 0;
1428
1429 irq_complete_move(irq);
1430 #ifdef CONFIG_GENERIC_PENDING_IRQ
1431 /* If we are moving the irq we need to mask it */
1432 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1433 do_unmask_irq = 1;
1434 mask_IO_APIC_irq(irq);
1435 }
1436 #endif
1437
1438 /*
1439 * We must acknowledge the irq before we move it or the acknowledge will
1440 * not propagate properly.
1441 */
1442 ack_APIC_irq();
1443
1444 /* Now we can move and renable the irq */
1445 if (unlikely(do_unmask_irq)) {
1446 /* Only migrate the irq if the ack has been received.
1447 *
1448 * On rare occasions the broadcast level triggered ack gets
1449 * delayed going to ioapics, and if we reprogram the
1450 * vector while Remote IRR is still set the irq will never
1451 * fire again.
1452 *
1453 * To prevent this scenario we read the Remote IRR bit
1454 * of the ioapic. This has two effects.
1455 * - On any sane system the read of the ioapic will
1456 * flush writes (and acks) going to the ioapic from
1457 * this cpu.
1458 * - We get to see if the ACK has actually been delivered.
1459 *
1460 * Based on failed experiments of reprogramming the
1461 * ioapic entry from outside of irq context starting
1462 * with masking the ioapic entry and then polling until
1463 * Remote IRR was clear before reprogramming the
1464 * ioapic I don't trust the Remote IRR bit to be
1465 * completey accurate.
1466 *
1467 * However there appears to be no other way to plug
1468 * this race, so if the Remote IRR bit is not
1469 * accurate and is causing problems then it is a hardware bug
1470 * and you can go talk to the chipset vendor about it.
1471 */
1472 if (!io_apic_level_ack_pending(irq))
1473 move_masked_irq(irq);
1474 unmask_IO_APIC_irq(irq);
1475 }
1476 }
1477
1478 static struct irq_chip ioapic_chip __read_mostly = {
1479 .name = "IO-APIC",
1480 .startup = startup_ioapic_irq,
1481 .mask = mask_IO_APIC_irq,
1482 .unmask = unmask_IO_APIC_irq,
1483 .ack = ack_apic_edge,
1484 .eoi = ack_apic_level,
1485 #ifdef CONFIG_SMP
1486 .set_affinity = set_ioapic_affinity_irq,
1487 #endif
1488 .retrigger = ioapic_retrigger_irq,
1489 };
1490
1491 static inline void init_IO_APIC_traps(void)
1492 {
1493 int irq;
1494
1495 /*
1496 * NOTE! The local APIC isn't very good at handling
1497 * multiple interrupts at the same interrupt level.
1498 * As the interrupt level is determined by taking the
1499 * vector number and shifting that right by 4, we
1500 * want to spread these out a bit so that they don't
1501 * all fall in the same interrupt level.
1502 *
1503 * Also, we've got to be careful not to trash gate
1504 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1505 */
1506 for (irq = 0; irq < NR_IRQS ; irq++) {
1507 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1508 /*
1509 * Hmm.. We don't have an entry for this,
1510 * so default to an old-fashioned 8259
1511 * interrupt if we can..
1512 */
1513 if (irq < 16)
1514 make_8259A_irq(irq);
1515 else
1516 /* Strange. Oh, well.. */
1517 irq_desc[irq].chip = &no_irq_chip;
1518 }
1519 }
1520 }
1521
1522 static void enable_lapic_irq (unsigned int irq)
1523 {
1524 unsigned long v;
1525
1526 v = apic_read(APIC_LVT0);
1527 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1528 }
1529
1530 static void disable_lapic_irq (unsigned int irq)
1531 {
1532 unsigned long v;
1533
1534 v = apic_read(APIC_LVT0);
1535 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1536 }
1537
1538 static void ack_lapic_irq (unsigned int irq)
1539 {
1540 ack_APIC_irq();
1541 }
1542
1543 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1544
1545 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1546 .name = "local-APIC",
1547 .typename = "local-APIC-edge",
1548 .startup = NULL, /* startup_irq() not used for IRQ0 */
1549 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1550 .enable = enable_lapic_irq,
1551 .disable = disable_lapic_irq,
1552 .ack = ack_lapic_irq,
1553 .end = end_lapic_irq,
1554 };
1555
1556 static void __init setup_nmi(void)
1557 {
1558 /*
1559 * Dirty trick to enable the NMI watchdog ...
1560 * We put the 8259A master into AEOI mode and
1561 * unmask on all local APICs LVT0 as NMI.
1562 *
1563 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1564 * is from Maciej W. Rozycki - so we do not have to EOI from
1565 * the NMI handler or the timer interrupt.
1566 */
1567 printk(KERN_INFO "activating NMI Watchdog ...");
1568
1569 enable_NMI_through_LVT0();
1570
1571 printk(" done.\n");
1572 }
1573
1574 /*
1575 * This looks a bit hackish but it's about the only one way of sending
1576 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1577 * not support the ExtINT mode, unfortunately. We need to send these
1578 * cycles as some i82489DX-based boards have glue logic that keeps the
1579 * 8259A interrupt line asserted until INTA. --macro
1580 */
1581 static inline void __init unlock_ExtINT_logic(void)
1582 {
1583 int apic, pin, i;
1584 struct IO_APIC_route_entry entry0, entry1;
1585 unsigned char save_control, save_freq_select;
1586
1587 pin = find_isa_irq_pin(8, mp_INT);
1588 apic = find_isa_irq_apic(8, mp_INT);
1589 if (pin == -1)
1590 return;
1591
1592 entry0 = ioapic_read_entry(apic, pin);
1593
1594 clear_IO_APIC_pin(apic, pin);
1595
1596 memset(&entry1, 0, sizeof(entry1));
1597
1598 entry1.dest_mode = 0; /* physical delivery */
1599 entry1.mask = 0; /* unmask IRQ now */
1600 entry1.dest = hard_smp_processor_id();
1601 entry1.delivery_mode = dest_ExtINT;
1602 entry1.polarity = entry0.polarity;
1603 entry1.trigger = 0;
1604 entry1.vector = 0;
1605
1606 ioapic_write_entry(apic, pin, entry1);
1607
1608 save_control = CMOS_READ(RTC_CONTROL);
1609 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1610 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1611 RTC_FREQ_SELECT);
1612 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1613
1614 i = 100;
1615 while (i-- > 0) {
1616 mdelay(10);
1617 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1618 i -= 10;
1619 }
1620
1621 CMOS_WRITE(save_control, RTC_CONTROL);
1622 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1623 clear_IO_APIC_pin(apic, pin);
1624
1625 ioapic_write_entry(apic, pin, entry0);
1626 }
1627
1628 /*
1629 * This code may look a bit paranoid, but it's supposed to cooperate with
1630 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1631 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1632 * fanatically on his truly buggy board.
1633 *
1634 * FIXME: really need to revamp this for modern platforms only.
1635 */
1636 static inline void __init check_timer(void)
1637 {
1638 struct irq_cfg *cfg = irq_cfg + 0;
1639 int apic1, pin1, apic2, pin2;
1640 unsigned long flags;
1641 int no_pin1 = 0;
1642
1643 local_irq_save(flags);
1644
1645 /*
1646 * get/set the timer IRQ vector:
1647 */
1648 disable_8259A_irq(0);
1649 assign_irq_vector(0, TARGET_CPUS);
1650
1651 /*
1652 * As IRQ0 is to be enabled in the 8259A, the virtual
1653 * wire has to be disabled in the local APIC.
1654 */
1655 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1656 init_8259A(1);
1657
1658 pin1 = find_isa_irq_pin(0, mp_INT);
1659 apic1 = find_isa_irq_apic(0, mp_INT);
1660 pin2 = ioapic_i8259.pin;
1661 apic2 = ioapic_i8259.apic;
1662
1663 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1664 cfg->vector, apic1, pin1, apic2, pin2);
1665
1666 /*
1667 * Some BIOS writers are clueless and report the ExtINTA
1668 * I/O APIC input from the cascaded 8259A as the timer
1669 * interrupt input. So just in case, if only one pin
1670 * was found above, try it both directly and through the
1671 * 8259A.
1672 */
1673 if (pin1 == -1) {
1674 pin1 = pin2;
1675 apic1 = apic2;
1676 no_pin1 = 1;
1677 } else if (pin2 == -1) {
1678 pin2 = pin1;
1679 apic2 = apic1;
1680 }
1681
1682 if (pin1 != -1) {
1683 /*
1684 * Ok, does IRQ0 through the IOAPIC work?
1685 */
1686 if (no_pin1) {
1687 add_pin_to_irq(0, apic1, pin1);
1688 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1689 }
1690 unmask_IO_APIC_irq(0);
1691 if (!no_timer_check && timer_irq_works()) {
1692 nmi_watchdog_default();
1693 if (nmi_watchdog == NMI_IO_APIC) {
1694 setup_nmi();
1695 enable_8259A_irq(0);
1696 }
1697 if (disable_timer_pin_1 > 0)
1698 clear_IO_APIC_pin(0, pin1);
1699 goto out;
1700 }
1701 clear_IO_APIC_pin(apic1, pin1);
1702 if (!no_pin1)
1703 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1704 "8254 timer not connected to IO-APIC\n");
1705
1706 apic_printk(APIC_VERBOSE,KERN_INFO
1707 "...trying to set up timer (IRQ0) "
1708 "through the 8259A ... ");
1709 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1710 apic2, pin2);
1711 /*
1712 * legacy devices should be connected to IO APIC #0
1713 */
1714 /* replace_pin_at_irq(0, apic1, pin1, apic2, pin2); */
1715 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1716 unmask_IO_APIC_irq(0);
1717 enable_8259A_irq(0);
1718 if (timer_irq_works()) {
1719 apic_printk(APIC_VERBOSE," works.\n");
1720 timer_through_8259 = 1;
1721 nmi_watchdog_default();
1722 if (nmi_watchdog == NMI_IO_APIC) {
1723 disable_8259A_irq(0);
1724 setup_nmi();
1725 enable_8259A_irq(0);
1726 }
1727 goto out;
1728 }
1729 /*
1730 * Cleanup, just in case ...
1731 */
1732 disable_8259A_irq(0);
1733 clear_IO_APIC_pin(apic2, pin2);
1734 apic_printk(APIC_VERBOSE," failed.\n");
1735 }
1736
1737 if (nmi_watchdog == NMI_IO_APIC) {
1738 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1739 nmi_watchdog = NMI_NONE;
1740 }
1741
1742 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1743
1744 irq_desc[0].chip = &lapic_irq_type;
1745 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1746 enable_8259A_irq(0);
1747
1748 if (timer_irq_works()) {
1749 apic_printk(APIC_VERBOSE," works.\n");
1750 goto out;
1751 }
1752 disable_8259A_irq(0);
1753 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1754 apic_printk(APIC_VERBOSE," failed.\n");
1755
1756 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1757
1758 init_8259A(0);
1759 make_8259A_irq(0);
1760 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1761
1762 unlock_ExtINT_logic();
1763
1764 if (timer_irq_works()) {
1765 apic_printk(APIC_VERBOSE," works.\n");
1766 goto out;
1767 }
1768 apic_printk(APIC_VERBOSE," failed :(.\n");
1769 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1770 out:
1771 local_irq_restore(flags);
1772 }
1773
1774 static int __init notimercheck(char *s)
1775 {
1776 no_timer_check = 1;
1777 return 1;
1778 }
1779 __setup("no_timer_check", notimercheck);
1780
1781 /*
1782 *
1783 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1784 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1785 * Linux doesn't really care, as it's not actually used
1786 * for any interrupt handling anyway.
1787 */
1788 #define PIC_IRQS (1<<2)
1789
1790 void __init setup_IO_APIC(void)
1791 {
1792
1793 /*
1794 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1795 */
1796
1797 if (acpi_ioapic)
1798 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1799 else
1800 io_apic_irqs = ~PIC_IRQS;
1801
1802 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1803
1804 sync_Arb_IDs();
1805 setup_IO_APIC_irqs();
1806 init_IO_APIC_traps();
1807 check_timer();
1808 if (!acpi_ioapic)
1809 print_IO_APIC();
1810 }
1811
1812 struct sysfs_ioapic_data {
1813 struct sys_device dev;
1814 struct IO_APIC_route_entry entry[0];
1815 };
1816 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1817
1818 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1819 {
1820 struct IO_APIC_route_entry *entry;
1821 struct sysfs_ioapic_data *data;
1822 int i;
1823
1824 data = container_of(dev, struct sysfs_ioapic_data, dev);
1825 entry = data->entry;
1826 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1827 *entry = ioapic_read_entry(dev->id, i);
1828
1829 return 0;
1830 }
1831
1832 static int ioapic_resume(struct sys_device *dev)
1833 {
1834 struct IO_APIC_route_entry *entry;
1835 struct sysfs_ioapic_data *data;
1836 unsigned long flags;
1837 union IO_APIC_reg_00 reg_00;
1838 int i;
1839
1840 data = container_of(dev, struct sysfs_ioapic_data, dev);
1841 entry = data->entry;
1842
1843 spin_lock_irqsave(&ioapic_lock, flags);
1844 reg_00.raw = io_apic_read(dev->id, 0);
1845 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1846 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1847 io_apic_write(dev->id, 0, reg_00.raw);
1848 }
1849 spin_unlock_irqrestore(&ioapic_lock, flags);
1850 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1851 ioapic_write_entry(dev->id, i, entry[i]);
1852
1853 return 0;
1854 }
1855
1856 static struct sysdev_class ioapic_sysdev_class = {
1857 .name = "ioapic",
1858 .suspend = ioapic_suspend,
1859 .resume = ioapic_resume,
1860 };
1861
1862 static int __init ioapic_init_sysfs(void)
1863 {
1864 struct sys_device * dev;
1865 int i, size, error;
1866
1867 error = sysdev_class_register(&ioapic_sysdev_class);
1868 if (error)
1869 return error;
1870
1871 for (i = 0; i < nr_ioapics; i++ ) {
1872 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1873 * sizeof(struct IO_APIC_route_entry);
1874 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1875 if (!mp_ioapic_data[i]) {
1876 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1877 continue;
1878 }
1879 dev = &mp_ioapic_data[i]->dev;
1880 dev->id = i;
1881 dev->cls = &ioapic_sysdev_class;
1882 error = sysdev_register(dev);
1883 if (error) {
1884 kfree(mp_ioapic_data[i]);
1885 mp_ioapic_data[i] = NULL;
1886 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1887 continue;
1888 }
1889 }
1890
1891 return 0;
1892 }
1893
1894 device_initcall(ioapic_init_sysfs);
1895
1896 /*
1897 * Dynamic irq allocate and deallocation
1898 */
1899 int create_irq(void)
1900 {
1901 /* Allocate an unused irq */
1902 int irq;
1903 int new;
1904 unsigned long flags;
1905
1906 irq = -ENOSPC;
1907 spin_lock_irqsave(&vector_lock, flags);
1908 for (new = (NR_IRQS - 1); new >= 0; new--) {
1909 if (platform_legacy_irq(new))
1910 continue;
1911 if (irq_cfg[new].vector != 0)
1912 continue;
1913 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1914 irq = new;
1915 break;
1916 }
1917 spin_unlock_irqrestore(&vector_lock, flags);
1918
1919 if (irq >= 0) {
1920 dynamic_irq_init(irq);
1921 }
1922 return irq;
1923 }
1924
1925 void destroy_irq(unsigned int irq)
1926 {
1927 unsigned long flags;
1928
1929 dynamic_irq_cleanup(irq);
1930
1931 spin_lock_irqsave(&vector_lock, flags);
1932 __clear_irq_vector(irq);
1933 spin_unlock_irqrestore(&vector_lock, flags);
1934 }
1935
1936 /*
1937 * MSI message composition
1938 */
1939 #ifdef CONFIG_PCI_MSI
1940 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1941 {
1942 struct irq_cfg *cfg = irq_cfg + irq;
1943 int err;
1944 unsigned dest;
1945 cpumask_t tmp;
1946
1947 tmp = TARGET_CPUS;
1948 err = assign_irq_vector(irq, tmp);
1949 if (!err) {
1950 cpus_and(tmp, cfg->domain, tmp);
1951 dest = cpu_mask_to_apicid(tmp);
1952
1953 msg->address_hi = MSI_ADDR_BASE_HI;
1954 msg->address_lo =
1955 MSI_ADDR_BASE_LO |
1956 ((INT_DEST_MODE == 0) ?
1957 MSI_ADDR_DEST_MODE_PHYSICAL:
1958 MSI_ADDR_DEST_MODE_LOGICAL) |
1959 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1960 MSI_ADDR_REDIRECTION_CPU:
1961 MSI_ADDR_REDIRECTION_LOWPRI) |
1962 MSI_ADDR_DEST_ID(dest);
1963
1964 msg->data =
1965 MSI_DATA_TRIGGER_EDGE |
1966 MSI_DATA_LEVEL_ASSERT |
1967 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1968 MSI_DATA_DELIVERY_FIXED:
1969 MSI_DATA_DELIVERY_LOWPRI) |
1970 MSI_DATA_VECTOR(cfg->vector);
1971 }
1972 return err;
1973 }
1974
1975 #ifdef CONFIG_SMP
1976 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1977 {
1978 struct irq_cfg *cfg = irq_cfg + irq;
1979 struct msi_msg msg;
1980 unsigned int dest;
1981 cpumask_t tmp;
1982
1983 cpus_and(tmp, mask, cpu_online_map);
1984 if (cpus_empty(tmp))
1985 return;
1986
1987 if (assign_irq_vector(irq, mask))
1988 return;
1989
1990 cpus_and(tmp, cfg->domain, mask);
1991 dest = cpu_mask_to_apicid(tmp);
1992
1993 read_msi_msg(irq, &msg);
1994
1995 msg.data &= ~MSI_DATA_VECTOR_MASK;
1996 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1997 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1998 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1999
2000 write_msi_msg(irq, &msg);
2001 irq_desc[irq].affinity = mask;
2002 }
2003 #endif /* CONFIG_SMP */
2004
2005 /*
2006 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2007 * which implement the MSI or MSI-X Capability Structure.
2008 */
2009 static struct irq_chip msi_chip = {
2010 .name = "PCI-MSI",
2011 .unmask = unmask_msi_irq,
2012 .mask = mask_msi_irq,
2013 .ack = ack_apic_edge,
2014 #ifdef CONFIG_SMP
2015 .set_affinity = set_msi_irq_affinity,
2016 #endif
2017 .retrigger = ioapic_retrigger_irq,
2018 };
2019
2020 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2021 {
2022 struct msi_msg msg;
2023 int irq, ret;
2024 irq = create_irq();
2025 if (irq < 0)
2026 return irq;
2027
2028 ret = msi_compose_msg(dev, irq, &msg);
2029 if (ret < 0) {
2030 destroy_irq(irq);
2031 return ret;
2032 }
2033
2034 set_irq_msi(irq, desc);
2035 write_msi_msg(irq, &msg);
2036
2037 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2038
2039 return 0;
2040 }
2041
2042 void arch_teardown_msi_irq(unsigned int irq)
2043 {
2044 destroy_irq(irq);
2045 }
2046
2047 #ifdef CONFIG_DMAR
2048 #ifdef CONFIG_SMP
2049 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2050 {
2051 struct irq_cfg *cfg = irq_cfg + irq;
2052 struct msi_msg msg;
2053 unsigned int dest;
2054 cpumask_t tmp;
2055
2056 cpus_and(tmp, mask, cpu_online_map);
2057 if (cpus_empty(tmp))
2058 return;
2059
2060 if (assign_irq_vector(irq, mask))
2061 return;
2062
2063 cpus_and(tmp, cfg->domain, mask);
2064 dest = cpu_mask_to_apicid(tmp);
2065
2066 dmar_msi_read(irq, &msg);
2067
2068 msg.data &= ~MSI_DATA_VECTOR_MASK;
2069 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2070 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2071 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2072
2073 dmar_msi_write(irq, &msg);
2074 irq_desc[irq].affinity = mask;
2075 }
2076 #endif /* CONFIG_SMP */
2077
2078 struct irq_chip dmar_msi_type = {
2079 .name = "DMAR_MSI",
2080 .unmask = dmar_msi_unmask,
2081 .mask = dmar_msi_mask,
2082 .ack = ack_apic_edge,
2083 #ifdef CONFIG_SMP
2084 .set_affinity = dmar_msi_set_affinity,
2085 #endif
2086 .retrigger = ioapic_retrigger_irq,
2087 };
2088
2089 int arch_setup_dmar_msi(unsigned int irq)
2090 {
2091 int ret;
2092 struct msi_msg msg;
2093
2094 ret = msi_compose_msg(NULL, irq, &msg);
2095 if (ret < 0)
2096 return ret;
2097 dmar_msi_write(irq, &msg);
2098 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2099 "edge");
2100 return 0;
2101 }
2102 #endif
2103
2104 #endif /* CONFIG_PCI_MSI */
2105 /*
2106 * Hypertransport interrupt support
2107 */
2108 #ifdef CONFIG_HT_IRQ
2109
2110 #ifdef CONFIG_SMP
2111
2112 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2113 {
2114 struct ht_irq_msg msg;
2115 fetch_ht_irq_msg(irq, &msg);
2116
2117 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2118 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2119
2120 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2121 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2122
2123 write_ht_irq_msg(irq, &msg);
2124 }
2125
2126 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2127 {
2128 struct irq_cfg *cfg = irq_cfg + irq;
2129 unsigned int dest;
2130 cpumask_t tmp;
2131
2132 cpus_and(tmp, mask, cpu_online_map);
2133 if (cpus_empty(tmp))
2134 return;
2135
2136 if (assign_irq_vector(irq, mask))
2137 return;
2138
2139 cpus_and(tmp, cfg->domain, mask);
2140 dest = cpu_mask_to_apicid(tmp);
2141
2142 target_ht_irq(irq, dest, cfg->vector);
2143 irq_desc[irq].affinity = mask;
2144 }
2145 #endif
2146
2147 static struct irq_chip ht_irq_chip = {
2148 .name = "PCI-HT",
2149 .mask = mask_ht_irq,
2150 .unmask = unmask_ht_irq,
2151 .ack = ack_apic_edge,
2152 #ifdef CONFIG_SMP
2153 .set_affinity = set_ht_irq_affinity,
2154 #endif
2155 .retrigger = ioapic_retrigger_irq,
2156 };
2157
2158 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2159 {
2160 struct irq_cfg *cfg = irq_cfg + irq;
2161 int err;
2162 cpumask_t tmp;
2163
2164 tmp = TARGET_CPUS;
2165 err = assign_irq_vector(irq, tmp);
2166 if (!err) {
2167 struct ht_irq_msg msg;
2168 unsigned dest;
2169
2170 cpus_and(tmp, cfg->domain, tmp);
2171 dest = cpu_mask_to_apicid(tmp);
2172
2173 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2174
2175 msg.address_lo =
2176 HT_IRQ_LOW_BASE |
2177 HT_IRQ_LOW_DEST_ID(dest) |
2178 HT_IRQ_LOW_VECTOR(cfg->vector) |
2179 ((INT_DEST_MODE == 0) ?
2180 HT_IRQ_LOW_DM_PHYSICAL :
2181 HT_IRQ_LOW_DM_LOGICAL) |
2182 HT_IRQ_LOW_RQEOI_EDGE |
2183 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2184 HT_IRQ_LOW_MT_FIXED :
2185 HT_IRQ_LOW_MT_ARBITRATED) |
2186 HT_IRQ_LOW_IRQ_MASKED;
2187
2188 write_ht_irq_msg(irq, &msg);
2189
2190 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2191 handle_edge_irq, "edge");
2192 }
2193 return err;
2194 }
2195 #endif /* CONFIG_HT_IRQ */
2196
2197 /* --------------------------------------------------------------------------
2198 ACPI-based IOAPIC Configuration
2199 -------------------------------------------------------------------------- */
2200
2201 #ifdef CONFIG_ACPI
2202
2203 #define IO_APIC_MAX_ID 0xFE
2204
2205 int __init io_apic_get_redir_entries (int ioapic)
2206 {
2207 union IO_APIC_reg_01 reg_01;
2208 unsigned long flags;
2209
2210 spin_lock_irqsave(&ioapic_lock, flags);
2211 reg_01.raw = io_apic_read(ioapic, 1);
2212 spin_unlock_irqrestore(&ioapic_lock, flags);
2213
2214 return reg_01.bits.entries;
2215 }
2216
2217
2218 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2219 {
2220 if (!IO_APIC_IRQ(irq)) {
2221 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2222 ioapic);
2223 return -EINVAL;
2224 }
2225
2226 /*
2227 * IRQs < 16 are already in the irq_2_pin[] map
2228 */
2229 if (irq >= 16)
2230 add_pin_to_irq(irq, ioapic, pin);
2231
2232 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2233
2234 return 0;
2235 }
2236
2237
2238 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2239 {
2240 int i;
2241
2242 if (skip_ioapic_setup)
2243 return -1;
2244
2245 for (i = 0; i < mp_irq_entries; i++)
2246 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2247 mp_irqs[i].mpc_srcbusirq == bus_irq)
2248 break;
2249 if (i >= mp_irq_entries)
2250 return -1;
2251
2252 *trigger = irq_trigger(i);
2253 *polarity = irq_polarity(i);
2254 return 0;
2255 }
2256
2257 #endif /* CONFIG_ACPI */
2258
2259 /*
2260 * This function currently is only a helper for the i386 smp boot process where
2261 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2262 * so mask in all cases should simply be TARGET_CPUS
2263 */
2264 #ifdef CONFIG_SMP
2265 void __init setup_ioapic_dest(void)
2266 {
2267 int pin, ioapic, irq, irq_entry;
2268
2269 if (skip_ioapic_setup == 1)
2270 return;
2271
2272 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2273 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2274 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2275 if (irq_entry == -1)
2276 continue;
2277 irq = pin_2_irq(irq_entry, ioapic, pin);
2278
2279 /* setup_IO_APIC_irqs could fail to get vector for some device
2280 * when you have too many devices, because at that time only boot
2281 * cpu is online.
2282 */
2283 if (!irq_cfg[irq].vector)
2284 setup_IO_APIC_irq(ioapic, pin, irq,
2285 irq_trigger(irq_entry),
2286 irq_polarity(irq_entry));
2287 else
2288 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2289 }
2290
2291 }
2292 }
2293 #endif
2294
2295 #define IOAPIC_RESOURCE_NAME_SIZE 11
2296
2297 static struct resource *ioapic_resources;
2298
2299 static struct resource * __init ioapic_setup_resources(void)
2300 {
2301 unsigned long n;
2302 struct resource *res;
2303 char *mem;
2304 int i;
2305
2306 if (nr_ioapics <= 0)
2307 return NULL;
2308
2309 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2310 n *= nr_ioapics;
2311
2312 mem = alloc_bootmem(n);
2313 res = (void *)mem;
2314
2315 if (mem != NULL) {
2316 mem += sizeof(struct resource) * nr_ioapics;
2317
2318 for (i = 0; i < nr_ioapics; i++) {
2319 res[i].name = mem;
2320 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2321 sprintf(mem, "IOAPIC %u", i);
2322 mem += IOAPIC_RESOURCE_NAME_SIZE;
2323 }
2324 }
2325
2326 ioapic_resources = res;
2327
2328 return res;
2329 }
2330
2331 void __init ioapic_init_mappings(void)
2332 {
2333 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2334 struct resource *ioapic_res;
2335 int i;
2336
2337 ioapic_res = ioapic_setup_resources();
2338 for (i = 0; i < nr_ioapics; i++) {
2339 if (smp_found_config) {
2340 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2341 } else {
2342 ioapic_phys = (unsigned long)
2343 alloc_bootmem_pages(PAGE_SIZE);
2344 ioapic_phys = __pa(ioapic_phys);
2345 }
2346 set_fixmap_nocache(idx, ioapic_phys);
2347 apic_printk(APIC_VERBOSE,
2348 "mapped IOAPIC to %016lx (%016lx)\n",
2349 __fix_to_virt(idx), ioapic_phys);
2350 idx++;
2351
2352 if (ioapic_res != NULL) {
2353 ioapic_res->start = ioapic_phys;
2354 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2355 ioapic_res++;
2356 }
2357 }
2358 }
2359
2360 static int __init ioapic_insert_resources(void)
2361 {
2362 int i;
2363 struct resource *r = ioapic_resources;
2364
2365 if (!r) {
2366 printk(KERN_ERR
2367 "IO APIC resources could be not be allocated.\n");
2368 return -1;
2369 }
2370
2371 for (i = 0; i < nr_ioapics; i++) {
2372 insert_resource(&iomem_resource, r);
2373 r++;
2374 }
2375
2376 return 0;
2377 }
2378
2379 /* Insert the IO APIC resources after PCI initialization has occured to handle
2380 * IO APICS that are mapped in on a BAR in PCI space. */
2381 late_initcall(ioapic_insert_resources);
2382
Stable & featurefull patchset based on Linus's git branch