2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
24 unsigned int pci_pm_d3_delay
= 10;
26 #ifdef CONFIG_PCI_DOMAINS
27 int pci_domains_supported
= 1;
30 #define DEFAULT_CARDBUS_IO_SIZE (256)
31 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
33 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
34 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
43 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
45 struct list_head
*tmp
;
48 max
= bus
->subordinate
;
49 list_for_each(tmp
, &bus
->children
) {
50 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
56 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
60 * pci_max_busnr - returns maximum PCI bus number
62 * Returns the highest PCI bus number present in the system global list of
65 unsigned char __devinit
68 struct pci_bus
*bus
= NULL
;
72 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
73 n
= pci_bus_max_busnr(bus
);
82 #define PCI_FIND_CAP_TTL 48
84 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
85 u8 pos
, int cap
, int *ttl
)
90 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
94 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
100 pos
+= PCI_CAP_LIST_NEXT
;
105 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
108 int ttl
= PCI_FIND_CAP_TTL
;
110 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
113 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
115 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
116 pos
+ PCI_CAP_LIST_NEXT
, cap
);
118 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
120 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
121 unsigned int devfn
, u8 hdr_type
)
125 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
126 if (!(status
& PCI_STATUS_CAP_LIST
))
130 case PCI_HEADER_TYPE_NORMAL
:
131 case PCI_HEADER_TYPE_BRIDGE
:
132 return PCI_CAPABILITY_LIST
;
133 case PCI_HEADER_TYPE_CARDBUS
:
134 return PCI_CB_CAPABILITY_LIST
;
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
161 int pci_find_capability(struct pci_dev
*dev
, int cap
)
165 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
167 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
173 * pci_bus_find_capability - query for devices' capabilities
174 * @bus: the PCI bus to query
175 * @devfn: PCI device to query
176 * @cap: capability code
178 * Like pci_find_capability() but works for pci devices that do not have a
179 * pci_dev structure set up yet.
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
185 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
190 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
192 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
194 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
200 * pci_find_ext_capability - Find an extended capability
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Returns the address of the requested extended capability structure
205 * within the device's PCI configuration space or 0 if the device does
206 * not support it. Possible values for @cap:
208 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
209 * %PCI_EXT_CAP_ID_VC Virtual Channel
210 * %PCI_EXT_CAP_ID_DSN Device Serial Number
211 * %PCI_EXT_CAP_ID_PWR Power Budgeting
213 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
216 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
219 if (dev
->cfg_size
<= 256)
222 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
226 * If we have no capabilities, this is indicated by cap ID,
227 * cap version and next pointer all being 0.
233 if (PCI_EXT_CAP_ID(header
) == cap
)
236 pos
= PCI_EXT_CAP_NEXT(header
);
240 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
246 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
248 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
250 int rc
, ttl
= PCI_FIND_CAP_TTL
;
253 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
254 mask
= HT_3BIT_CAP_MASK
;
256 mask
= HT_5BIT_CAP_MASK
;
258 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
259 PCI_CAP_ID_HT
, &ttl
);
261 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
262 if (rc
!= PCIBIOS_SUCCESSFUL
)
265 if ((cap
& mask
) == ht_cap
)
268 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
269 pos
+ PCI_CAP_LIST_NEXT
,
270 PCI_CAP_ID_HT
, &ttl
);
276 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
277 * @dev: PCI device to query
278 * @pos: Position from which to continue searching
279 * @ht_cap: Hypertransport capability code
281 * To be used in conjunction with pci_find_ht_capability() to search for
282 * all capabilities matching @ht_cap. @pos should always be a value returned
283 * from pci_find_ht_capability().
285 * NB. To be 100% safe against broken PCI devices, the caller should take
286 * steps to avoid an infinite loop.
288 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
290 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
292 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
295 * pci_find_ht_capability - query a device's Hypertransport capabilities
296 * @dev: PCI device to query
297 * @ht_cap: Hypertransport capability code
299 * Tell if a device supports a given Hypertransport capability.
300 * Returns an address within the device's PCI configuration space
301 * or 0 in case the device does not support the request capability.
302 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
303 * which has a Hypertransport capability matching @ht_cap.
305 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
309 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
311 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
315 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
318 * pci_find_parent_resource - return resource region of parent bus of given region
319 * @dev: PCI device structure contains resources to be searched
320 * @res: child resource record for which parent is sought
322 * For given resource region of given device, return the resource
323 * region of parent bus the given region is contained in or where
324 * it should be allocated from.
327 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
329 const struct pci_bus
*bus
= dev
->bus
;
331 struct resource
*best
= NULL
;
333 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
334 struct resource
*r
= bus
->resource
[i
];
337 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
338 continue; /* Not contained */
339 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
340 continue; /* Wrong type */
341 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
342 return r
; /* Exact match */
343 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
344 best
= r
; /* Approximating prefetchable by non-prefetchable */
350 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
351 * @dev: PCI device to have its BARs restored
353 * Restore the BAR values for a given device, so as to make it
354 * accessible by its driver.
357 pci_restore_bars(struct pci_dev
*dev
)
361 switch (dev
->hdr_type
) {
362 case PCI_HEADER_TYPE_NORMAL
:
365 case PCI_HEADER_TYPE_BRIDGE
:
368 case PCI_HEADER_TYPE_CARDBUS
:
372 /* Should never get here, but just in case... */
376 for (i
= 0; i
< numres
; i
++)
377 pci_update_resource(dev
, &dev
->resource
[i
], i
);
380 static struct pci_platform_pm_ops
*pci_platform_pm
;
382 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
384 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
385 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
387 pci_platform_pm
= ops
;
391 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
393 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
396 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
399 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
402 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
404 return pci_platform_pm
?
405 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
408 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
410 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
413 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
415 return pci_platform_pm
?
416 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
420 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
422 * @dev: PCI device to handle.
423 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
426 * -EINVAL if the requested state is invalid.
427 * -EIO if device does not support PCI PM or its PM capabilities register has a
428 * wrong version, or device doesn't support the requested state.
429 * 0 if device already is in the requested state.
430 * 0 if device's power state has been successfully changed.
433 pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
436 bool need_restore
= false;
441 if (state
< PCI_D0
|| state
> PCI_D3hot
)
444 /* Validate current state:
445 * Can enter D0 from any state, but if we can only go deeper
446 * to sleep if we're already in a low power state
448 if (dev
->current_state
== state
) {
449 /* we're already there */
451 } else if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
452 && dev
->current_state
> state
) {
453 dev_err(&dev
->dev
, "invalid power transition "
454 "(from state %d to %d)\n", dev
->current_state
, state
);
458 /* check if this device supports the desired state */
459 if ((state
== PCI_D1
&& !dev
->d1_support
)
460 || (state
== PCI_D2
&& !dev
->d2_support
))
463 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
465 /* If we're (effectively) in D3, force entire word to 0.
466 * This doesn't affect PME_Status, disables PME_En, and
467 * sets PowerState to 0.
469 switch (dev
->current_state
) {
473 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
476 case PCI_UNKNOWN
: /* Boot-up */
477 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
478 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
480 /* Fall-through: force to D0 */
486 /* enter specified state */
487 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
489 /* Mandatory power management transition delays */
490 /* see PCI PM 1.1 5.6.1 table 18 */
491 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
492 msleep(pci_pm_d3_delay
);
493 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
496 dev
->current_state
= state
;
498 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
499 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
500 * from D3hot to D0 _may_ perform an internal reset, thereby
501 * going to "D0 Uninitialized" rather than "D0 Initialized".
502 * For example, at least some versions of the 3c905B and the
503 * 3c556B exhibit this behaviour.
505 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
506 * devices in a D3hot state at boot. Consequently, we need to
507 * restore at least the BARs so that the device will be
508 * accessible to its driver.
511 pci_restore_bars(dev
);
514 pcie_aspm_pm_state_change(dev
->bus
->self
);
520 * pci_update_current_state - Read PCI power state of given device from its
521 * PCI PM registers and cache it
522 * @dev: PCI device to handle.
524 static void pci_update_current_state(struct pci_dev
*dev
)
529 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
530 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
535 * pci_set_power_state - Set the power state of a PCI device
536 * @dev: PCI device to handle.
537 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
539 * Transition a device to a new power state, using the platform formware and/or
540 * the device's PCI PM registers.
543 * -EINVAL if the requested state is invalid.
544 * -EIO if device does not support PCI PM or its PM capabilities register has a
545 * wrong version, or device doesn't support the requested state.
546 * 0 if device already is in the requested state.
547 * 0 if device's power state has been successfully changed.
549 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
553 /* bound the state we're entering */
554 if (state
> PCI_D3hot
)
556 else if (state
< PCI_D0
)
558 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
560 * If the device or the parent bridge do not support PCI PM,
561 * ignore the request if we're doing anything other than putting
562 * it into D0 (which would only happen on boot).
566 if (state
== PCI_D0
&& platform_pci_power_manageable(dev
)) {
568 * Allow the platform to change the state, for example via ACPI
569 * _PR0, _PS0 and some such, but do not trust it.
571 int ret
= platform_pci_set_power_state(dev
, PCI_D0
);
573 pci_update_current_state(dev
);
576 error
= pci_raw_set_power_state(dev
, state
);
578 if (state
> PCI_D0
&& platform_pci_power_manageable(dev
)) {
579 /* Allow the platform to finalize the transition */
580 int ret
= platform_pci_set_power_state(dev
, state
);
582 pci_update_current_state(dev
);
591 * pci_choose_state - Choose the power state of a PCI device
592 * @dev: PCI device to be suspended
593 * @state: target sleep state for the whole system. This is the value
594 * that is passed to suspend() function.
596 * Returns PCI power state suitable for given device and given system
600 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
604 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
607 ret
= platform_pci_choose_state(dev
);
608 if (ret
!= PCI_POWER_ERROR
)
611 switch (state
.event
) {
614 case PM_EVENT_FREEZE
:
615 case PM_EVENT_PRETHAW
:
616 /* REVISIT both freeze and pre-thaw "should" use D0 */
617 case PM_EVENT_SUSPEND
:
618 case PM_EVENT_HIBERNATE
:
621 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
628 EXPORT_SYMBOL(pci_choose_state
);
630 static int pci_save_pcie_state(struct pci_dev
*dev
)
633 struct pci_cap_saved_state
*save_state
;
637 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
641 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
643 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
) * 4, GFP_KERNEL
);
647 dev_err(&dev
->dev
, "out of memory in pci_save_pcie_state\n");
650 cap
= (u16
*)&save_state
->data
[0];
652 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
653 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
654 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
655 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
656 save_state
->cap_nr
= PCI_CAP_ID_EXP
;
658 pci_add_saved_cap(dev
, save_state
);
662 static void pci_restore_pcie_state(struct pci_dev
*dev
)
665 struct pci_cap_saved_state
*save_state
;
668 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
669 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
670 if (!save_state
|| pos
<= 0)
672 cap
= (u16
*)&save_state
->data
[0];
674 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
675 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
676 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
677 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
681 static int pci_save_pcix_state(struct pci_dev
*dev
)
684 struct pci_cap_saved_state
*save_state
;
688 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
692 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
694 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
), GFP_KERNEL
);
698 dev_err(&dev
->dev
, "out of memory in pci_save_pcie_state\n");
701 cap
= (u16
*)&save_state
->data
[0];
703 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, &cap
[i
++]);
704 save_state
->cap_nr
= PCI_CAP_ID_PCIX
;
706 pci_add_saved_cap(dev
, save_state
);
710 static void pci_restore_pcix_state(struct pci_dev
*dev
)
713 struct pci_cap_saved_state
*save_state
;
716 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
717 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
718 if (!save_state
|| pos
<= 0)
720 cap
= (u16
*)&save_state
->data
[0];
722 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
727 * pci_save_state - save the PCI configuration space of a device before suspending
728 * @dev: - PCI device that we're dealing with
731 pci_save_state(struct pci_dev
*dev
)
734 /* XXX: 100% dword access ok here? */
735 for (i
= 0; i
< 16; i
++)
736 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
737 if ((i
= pci_save_pcie_state(dev
)) != 0)
739 if ((i
= pci_save_pcix_state(dev
)) != 0)
745 * pci_restore_state - Restore the saved state of a PCI device
746 * @dev: - PCI device that we're dealing with
749 pci_restore_state(struct pci_dev
*dev
)
754 /* PCI Express register must be restored first */
755 pci_restore_pcie_state(dev
);
758 * The Base Address register should be programmed before the command
761 for (i
= 15; i
>= 0; i
--) {
762 pci_read_config_dword(dev
, i
* 4, &val
);
763 if (val
!= dev
->saved_config_space
[i
]) {
764 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
765 "space at offset %#x (was %#x, writing %#x)\n",
766 i
, val
, (int)dev
->saved_config_space
[i
]);
767 pci_write_config_dword(dev
,i
* 4,
768 dev
->saved_config_space
[i
]);
771 pci_restore_pcix_state(dev
);
772 pci_restore_msi_state(dev
);
777 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
781 err
= pci_set_power_state(dev
, PCI_D0
);
782 if (err
< 0 && err
!= -EIO
)
784 err
= pcibios_enable_device(dev
, bars
);
787 pci_fixup_device(pci_fixup_enable
, dev
);
793 * pci_reenable_device - Resume abandoned device
794 * @dev: PCI device to be resumed
796 * Note this function is a backend of pci_default_resume and is not supposed
797 * to be called by normal code, write proper resume handler and use it instead.
799 int pci_reenable_device(struct pci_dev
*dev
)
801 if (atomic_read(&dev
->enable_cnt
))
802 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
806 static int __pci_enable_device_flags(struct pci_dev
*dev
,
807 resource_size_t flags
)
812 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
813 return 0; /* already enabled */
815 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
816 if (dev
->resource
[i
].flags
& flags
)
819 err
= do_pci_enable_device(dev
, bars
);
821 atomic_dec(&dev
->enable_cnt
);
826 * pci_enable_device_io - Initialize a device for use with IO space
827 * @dev: PCI device to be initialized
829 * Initialize device before it's used by a driver. Ask low-level code
830 * to enable I/O resources. Wake up the device if it was suspended.
831 * Beware, this function can fail.
833 int pci_enable_device_io(struct pci_dev
*dev
)
835 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
839 * pci_enable_device_mem - Initialize a device for use with Memory space
840 * @dev: PCI device to be initialized
842 * Initialize device before it's used by a driver. Ask low-level code
843 * to enable Memory resources. Wake up the device if it was suspended.
844 * Beware, this function can fail.
846 int pci_enable_device_mem(struct pci_dev
*dev
)
848 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
852 * pci_enable_device - Initialize device before it's used by a driver.
853 * @dev: PCI device to be initialized
855 * Initialize device before it's used by a driver. Ask low-level code
856 * to enable I/O and memory. Wake up the device if it was suspended.
857 * Beware, this function can fail.
859 * Note we don't actually enable the device many times if we call
860 * this function repeatedly (we just increment the count).
862 int pci_enable_device(struct pci_dev
*dev
)
864 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
868 * Managed PCI resources. This manages device on/off, intx/msi/msix
869 * on/off and BAR regions. pci_dev itself records msi/msix status, so
870 * there's no need to track it separately. pci_devres is initialized
871 * when a device is enabled using managed PCI device enable interface.
874 unsigned int enabled
:1;
875 unsigned int pinned
:1;
876 unsigned int orig_intx
:1;
877 unsigned int restore_intx
:1;
881 static void pcim_release(struct device
*gendev
, void *res
)
883 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
884 struct pci_devres
*this = res
;
887 if (dev
->msi_enabled
)
888 pci_disable_msi(dev
);
889 if (dev
->msix_enabled
)
890 pci_disable_msix(dev
);
892 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
893 if (this->region_mask
& (1 << i
))
894 pci_release_region(dev
, i
);
896 if (this->restore_intx
)
897 pci_intx(dev
, this->orig_intx
);
899 if (this->enabled
&& !this->pinned
)
900 pci_disable_device(dev
);
903 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
905 struct pci_devres
*dr
, *new_dr
;
907 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
911 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
914 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
917 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
919 if (pci_is_managed(pdev
))
920 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
925 * pcim_enable_device - Managed pci_enable_device()
926 * @pdev: PCI device to be initialized
928 * Managed pci_enable_device().
930 int pcim_enable_device(struct pci_dev
*pdev
)
932 struct pci_devres
*dr
;
935 dr
= get_pci_dr(pdev
);
941 rc
= pci_enable_device(pdev
);
943 pdev
->is_managed
= 1;
950 * pcim_pin_device - Pin managed PCI device
951 * @pdev: PCI device to pin
953 * Pin managed PCI device @pdev. Pinned device won't be disabled on
954 * driver detach. @pdev must have been enabled with
955 * pcim_enable_device().
957 void pcim_pin_device(struct pci_dev
*pdev
)
959 struct pci_devres
*dr
;
961 dr
= find_pci_dr(pdev
);
962 WARN_ON(!dr
|| !dr
->enabled
);
968 * pcibios_disable_device - disable arch specific PCI resources for device dev
969 * @dev: the PCI device to disable
971 * Disables architecture specific PCI resources for the device. This
972 * is the default implementation. Architecture implementations can
975 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
978 * pci_disable_device - Disable PCI device after use
979 * @dev: PCI device to be disabled
981 * Signal to the system that the PCI device is not in use by the system
982 * anymore. This only involves disabling PCI bus-mastering, if active.
984 * Note we don't actually disable the device until all callers of
985 * pci_device_enable() have called pci_device_disable().
988 pci_disable_device(struct pci_dev
*dev
)
990 struct pci_devres
*dr
;
993 dr
= find_pci_dr(dev
);
997 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1000 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1001 if (pci_command
& PCI_COMMAND_MASTER
) {
1002 pci_command
&= ~PCI_COMMAND_MASTER
;
1003 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1005 dev
->is_busmaster
= 0;
1007 pcibios_disable_device(dev
);
1011 * pcibios_set_pcie_reset_state - set reset state for device dev
1012 * @dev: the PCI-E device reset
1013 * @state: Reset state to enter into
1016 * Sets the PCI-E reset state for the device. This is the default
1017 * implementation. Architecture implementations can override this.
1019 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1020 enum pcie_reset_state state
)
1026 * pci_set_pcie_reset_state - set reset state for device dev
1027 * @dev: the PCI-E device reset
1028 * @state: Reset state to enter into
1031 * Sets the PCI reset state for the device.
1033 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1035 return pcibios_set_pcie_reset_state(dev
, state
);
1039 * pci_pme_capable - check the capability of PCI device to generate PME#
1040 * @dev: PCI device to handle.
1041 * @state: PCI state from which device will issue PME#.
1043 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1048 return !!(dev
->pme_support
& (1 << state
));
1052 * pci_pme_active - enable or disable PCI device's PME# function
1053 * @dev: PCI device to handle.
1054 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1056 * The caller must verify that the device is capable of generating PME# before
1057 * calling this function with @enable equal to 'true'.
1059 static void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1066 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1067 /* Clear PME_Status by writing 1 to it and enable PME# */
1068 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1070 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1072 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1074 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1075 enable
? "enabled" : "disabled");
1079 * pci_enable_wake - enable PCI device as wakeup event source
1080 * @dev: PCI device affected
1081 * @state: PCI state from which device will issue wakeup events
1082 * @enable: True to enable event generation; false to disable
1084 * This enables the device as a wakeup event source, or disables it.
1085 * When such events involves platform-specific hooks, those hooks are
1086 * called automatically by this routine.
1088 * Devices with legacy power management (no standard PCI PM capabilities)
1089 * always require such platform hooks.
1092 * 0 is returned on success
1093 * -EINVAL is returned if device is not supposed to wake up the system
1094 * Error code depending on the platform is returned if both the platform and
1095 * the native mechanism fail to enable the generation of wake-up events
1097 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1100 bool pme_done
= false;
1102 if (!device_may_wakeup(&dev
->dev
))
1106 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1107 * Anderson we should be doing PME# wake enable followed by ACPI wake
1108 * enable. To disable wake-up we call the platform first, for symmetry.
1111 if (!enable
&& platform_pci_can_wakeup(dev
))
1112 error
= platform_pci_sleep_wake(dev
, false);
1114 if (!enable
|| pci_pme_capable(dev
, state
)) {
1115 pci_pme_active(dev
, enable
);
1119 if (enable
&& platform_pci_can_wakeup(dev
))
1120 error
= platform_pci_sleep_wake(dev
, true);
1122 return pme_done
? 0 : error
;
1127 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1129 pci_power_t target_state
= PCI_D3hot
;
1131 if (platform_pci_power_manageable(dev
)) {
1133 * Call the platform to choose the target state of the device
1134 * and enable wake-up from this state if supported.
1136 pci_power_t state
= platform_pci_choose_state(dev
);
1139 case PCI_POWER_ERROR
:
1144 if (pci_no_d1d2(dev
))
1147 target_state
= state
;
1149 } else if (device_may_wakeup(&dev
->dev
)) {
1151 * Find the deepest state from which the device can generate
1152 * wake-up events, make it the target state and enable device
1156 return PCI_POWER_ERROR
;
1158 if (dev
->pme_support
) {
1160 && !(dev
->pme_support
& (1 << target_state
)))
1165 return target_state
;
1169 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1170 * @dev: Device to handle.
1172 * Choose the power state appropriate for the device depending on whether
1173 * it can wake up the system and/or is power manageable by the platform
1174 * (PCI_D3hot is the default) and put the device into that state.
1176 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1178 pci_power_t target_state
= pci_target_state(dev
);
1181 if (target_state
== PCI_POWER_ERROR
)
1184 pci_enable_wake(dev
, target_state
, true);
1186 error
= pci_set_power_state(dev
, target_state
);
1189 pci_enable_wake(dev
, target_state
, false);
1195 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1196 * @dev: Device to handle.
1198 * Disable device's sytem wake-up capability and put it into D0.
1200 int pci_back_from_sleep(struct pci_dev
*dev
)
1202 pci_enable_wake(dev
, PCI_D0
, false);
1203 return pci_set_power_state(dev
, PCI_D0
);
1207 * pci_pm_init - Initialize PM functions of given PCI device
1208 * @dev: PCI device to handle.
1210 void pci_pm_init(struct pci_dev
*dev
)
1217 /* find PCI PM capability in list */
1218 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1221 /* Check device's ability to generate PME# */
1222 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1224 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1225 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1226 pmc
& PCI_PM_CAP_VER_MASK
);
1232 dev
->d1_support
= false;
1233 dev
->d2_support
= false;
1234 if (!pci_no_d1d2(dev
)) {
1235 if (pmc
& PCI_PM_CAP_D1
) {
1236 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports D1\n");
1237 dev
->d1_support
= true;
1239 if (pmc
& PCI_PM_CAP_D2
) {
1240 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports D2\n");
1241 dev
->d2_support
= true;
1245 pmc
&= PCI_PM_CAP_PME_MASK
;
1247 dev_printk(KERN_INFO
, &dev
->dev
,
1248 "PME# supported from%s%s%s%s%s\n",
1249 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1250 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1251 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1252 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1253 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1254 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1256 * Make device's PM flags reflect the wake-up capability, but
1257 * let the user space enable it to wake up the system as needed.
1259 device_set_wakeup_capable(&dev
->dev
, true);
1260 device_set_wakeup_enable(&dev
->dev
, false);
1261 /* Disable the PME# generation functionality */
1262 pci_pme_active(dev
, false);
1264 dev
->pme_support
= 0;
1269 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1277 while (dev
->bus
->self
) {
1278 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
1279 dev
= dev
->bus
->self
;
1286 * pci_release_region - Release a PCI bar
1287 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1288 * @bar: BAR to release
1290 * Releases the PCI I/O and memory resources previously reserved by a
1291 * successful call to pci_request_region. Call this function only
1292 * after all use of the PCI regions has ceased.
1294 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1296 struct pci_devres
*dr
;
1298 if (pci_resource_len(pdev
, bar
) == 0)
1300 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1301 release_region(pci_resource_start(pdev
, bar
),
1302 pci_resource_len(pdev
, bar
));
1303 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1304 release_mem_region(pci_resource_start(pdev
, bar
),
1305 pci_resource_len(pdev
, bar
));
1307 dr
= find_pci_dr(pdev
);
1309 dr
->region_mask
&= ~(1 << bar
);
1313 * pci_request_region - Reserved PCI I/O and memory resource
1314 * @pdev: PCI device whose resources are to be reserved
1315 * @bar: BAR to be reserved
1316 * @res_name: Name to be associated with resource.
1318 * Mark the PCI region associated with PCI device @pdev BR @bar as
1319 * being reserved by owner @res_name. Do not access any
1320 * address inside the PCI regions unless this call returns
1323 * Returns 0 on success, or %EBUSY on error. A warning
1324 * message is also printed on failure.
1326 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1328 struct pci_devres
*dr
;
1330 if (pci_resource_len(pdev
, bar
) == 0)
1333 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1334 if (!request_region(pci_resource_start(pdev
, bar
),
1335 pci_resource_len(pdev
, bar
), res_name
))
1338 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1339 if (!request_mem_region(pci_resource_start(pdev
, bar
),
1340 pci_resource_len(pdev
, bar
), res_name
))
1344 dr
= find_pci_dr(pdev
);
1346 dr
->region_mask
|= 1 << bar
;
1351 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region [%#llx-%#llx]\n",
1353 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1354 (unsigned long long)pci_resource_start(pdev
, bar
),
1355 (unsigned long long)pci_resource_end(pdev
, bar
));
1360 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1361 * @pdev: PCI device whose resources were previously reserved
1362 * @bars: Bitmask of BARs to be released
1364 * Release selected PCI I/O and memory resources previously reserved.
1365 * Call this function only after all use of the PCI regions has ceased.
1367 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1371 for (i
= 0; i
< 6; i
++)
1372 if (bars
& (1 << i
))
1373 pci_release_region(pdev
, i
);
1377 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1378 * @pdev: PCI device whose resources are to be reserved
1379 * @bars: Bitmask of BARs to be requested
1380 * @res_name: Name to be associated with resource
1382 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1383 const char *res_name
)
1387 for (i
= 0; i
< 6; i
++)
1388 if (bars
& (1 << i
))
1389 if(pci_request_region(pdev
, i
, res_name
))
1395 if (bars
& (1 << i
))
1396 pci_release_region(pdev
, i
);
1402 * pci_release_regions - Release reserved PCI I/O and memory resources
1403 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1405 * Releases all PCI I/O and memory resources previously reserved by a
1406 * successful call to pci_request_regions. Call this function only
1407 * after all use of the PCI regions has ceased.
1410 void pci_release_regions(struct pci_dev
*pdev
)
1412 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1416 * pci_request_regions - Reserved PCI I/O and memory resources
1417 * @pdev: PCI device whose resources are to be reserved
1418 * @res_name: Name to be associated with resource.
1420 * Mark all PCI regions associated with PCI device @pdev as
1421 * being reserved by owner @res_name. Do not access any
1422 * address inside the PCI regions unless this call returns
1425 * Returns 0 on success, or %EBUSY on error. A warning
1426 * message is also printed on failure.
1428 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1430 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1434 * pci_set_master - enables bus-mastering for device dev
1435 * @dev: the PCI device to enable
1437 * Enables bus-mastering on the device and calls pcibios_set_master()
1438 * to do the needed arch specific settings.
1441 pci_set_master(struct pci_dev
*dev
)
1445 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1446 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1447 dev_dbg(&dev
->dev
, "enabling bus mastering\n");
1448 cmd
|= PCI_COMMAND_MASTER
;
1449 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1451 dev
->is_busmaster
= 1;
1452 pcibios_set_master(dev
);
1455 #ifdef PCI_DISABLE_MWI
1456 int pci_set_mwi(struct pci_dev
*dev
)
1461 int pci_try_set_mwi(struct pci_dev
*dev
)
1466 void pci_clear_mwi(struct pci_dev
*dev
)
1472 #ifndef PCI_CACHE_LINE_BYTES
1473 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1476 /* This can be overridden by arch code. */
1477 /* Don't forget this is measured in 32-bit words, not bytes */
1478 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1481 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1482 * @dev: the PCI device for which MWI is to be enabled
1484 * Helper function for pci_set_mwi.
1485 * Originally copied from drivers/net/acenic.c.
1486 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1488 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1491 pci_set_cacheline_size(struct pci_dev
*dev
)
1495 if (!pci_cache_line_size
)
1496 return -EINVAL
; /* The system doesn't support MWI. */
1498 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1499 equal to or multiple of the right value. */
1500 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1501 if (cacheline_size
>= pci_cache_line_size
&&
1502 (cacheline_size
% pci_cache_line_size
) == 0)
1505 /* Write the correct value. */
1506 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1508 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1509 if (cacheline_size
== pci_cache_line_size
)
1512 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1513 "supported\n", pci_cache_line_size
<< 2);
1519 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1520 * @dev: the PCI device for which MWI is enabled
1522 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1524 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1527 pci_set_mwi(struct pci_dev
*dev
)
1532 rc
= pci_set_cacheline_size(dev
);
1536 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1537 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1538 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1539 cmd
|= PCI_COMMAND_INVALIDATE
;
1540 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1547 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1548 * @dev: the PCI device for which MWI is enabled
1550 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1551 * Callers are not required to check the return value.
1553 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1555 int pci_try_set_mwi(struct pci_dev
*dev
)
1557 int rc
= pci_set_mwi(dev
);
1562 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1563 * @dev: the PCI device to disable
1565 * Disables PCI Memory-Write-Invalidate transaction on the device
1568 pci_clear_mwi(struct pci_dev
*dev
)
1572 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1573 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1574 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1575 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1578 #endif /* ! PCI_DISABLE_MWI */
1581 * pci_intx - enables/disables PCI INTx for device dev
1582 * @pdev: the PCI device to operate on
1583 * @enable: boolean: whether to enable or disable PCI INTx
1585 * Enables/disables PCI INTx for device dev
1588 pci_intx(struct pci_dev
*pdev
, int enable
)
1590 u16 pci_command
, new;
1592 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1595 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1597 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1600 if (new != pci_command
) {
1601 struct pci_devres
*dr
;
1603 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1605 dr
= find_pci_dr(pdev
);
1606 if (dr
&& !dr
->restore_intx
) {
1607 dr
->restore_intx
= 1;
1608 dr
->orig_intx
= !enable
;
1614 * pci_msi_off - disables any msi or msix capabilities
1615 * @dev: the PCI device to operate on
1617 * If you want to use msi see pci_enable_msi and friends.
1618 * This is a lower level primitive that allows us to disable
1619 * msi operation at the device level.
1621 void pci_msi_off(struct pci_dev
*dev
)
1626 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1628 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1629 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1630 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1632 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1634 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1635 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1636 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1640 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1642 * These can be overridden by arch-specific implementations
1645 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1647 if (!pci_dma_supported(dev
, mask
))
1650 dev
->dma_mask
= mask
;
1656 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1658 if (!pci_dma_supported(dev
, mask
))
1661 dev
->dev
.coherent_dma_mask
= mask
;
1667 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1668 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
1670 return dma_set_max_seg_size(&dev
->dev
, size
);
1672 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
1675 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1676 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
1678 return dma_set_seg_boundary(&dev
->dev
, mask
);
1680 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
1684 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1685 * @dev: PCI device to query
1687 * Returns mmrbc: maximum designed memory read count in bytes
1688 * or appropriate error value.
1690 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
1695 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1699 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1703 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
1705 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
1708 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1709 * @dev: PCI device to query
1711 * Returns mmrbc: maximum memory read count in bytes
1712 * or appropriate error value.
1714 int pcix_get_mmrbc(struct pci_dev
*dev
)
1719 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1723 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1725 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
1729 EXPORT_SYMBOL(pcix_get_mmrbc
);
1732 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1733 * @dev: PCI device to query
1734 * @mmrbc: maximum memory read count in bytes
1735 * valid values are 512, 1024, 2048, 4096
1737 * If possible sets maximum memory read byte count, some bridges have erratas
1738 * that prevent this.
1740 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
1742 int cap
, err
= -EINVAL
;
1743 u32 stat
, cmd
, v
, o
;
1745 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
1748 v
= ffs(mmrbc
) - 10;
1750 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1754 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1758 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
1761 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1765 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
1767 if (v
> o
&& dev
->bus
&&
1768 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
1771 cmd
&= ~PCI_X_CMD_MAX_READ
;
1773 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
1778 EXPORT_SYMBOL(pcix_set_mmrbc
);
1781 * pcie_get_readrq - get PCI Express read request size
1782 * @dev: PCI device to query
1784 * Returns maximum memory read request in bytes
1785 * or appropriate error value.
1787 int pcie_get_readrq(struct pci_dev
*dev
)
1792 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1796 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1798 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
1802 EXPORT_SYMBOL(pcie_get_readrq
);
1805 * pcie_set_readrq - set PCI Express maximum memory read request
1806 * @dev: PCI device to query
1807 * @rq: maximum memory read count in bytes
1808 * valid values are 128, 256, 512, 1024, 2048, 4096
1810 * If possible sets maximum read byte count
1812 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
1814 int cap
, err
= -EINVAL
;
1817 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
1820 v
= (ffs(rq
) - 8) << 12;
1822 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1826 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1830 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
1831 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
1833 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
1839 EXPORT_SYMBOL(pcie_set_readrq
);
1842 * pci_select_bars - Make BAR mask from the type of resource
1843 * @dev: the PCI device for which BAR mask is made
1844 * @flags: resource type mask to be selected
1846 * This helper routine makes bar mask from the type of resource.
1848 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
1851 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1852 if (pci_resource_flags(dev
, i
) & flags
)
1857 static void __devinit
pci_no_domains(void)
1859 #ifdef CONFIG_PCI_DOMAINS
1860 pci_domains_supported
= 0;
1864 static int __devinit
pci_init(void)
1866 struct pci_dev
*dev
= NULL
;
1868 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1869 pci_fixup_device(pci_fixup_final
, dev
);
1874 static int __devinit
pci_setup(char *str
)
1877 char *k
= strchr(str
, ',');
1880 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
1881 if (!strcmp(str
, "nomsi")) {
1883 } else if (!strcmp(str
, "noaer")) {
1885 } else if (!strcmp(str
, "nodomains")) {
1887 } else if (!strncmp(str
, "cbiosize=", 9)) {
1888 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
1889 } else if (!strncmp(str
, "cbmemsize=", 10)) {
1890 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
1892 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
1900 early_param("pci", pci_setup
);
1902 device_initcall(pci_init
);
1904 EXPORT_SYMBOL(pci_reenable_device
);
1905 EXPORT_SYMBOL(pci_enable_device_io
);
1906 EXPORT_SYMBOL(pci_enable_device_mem
);
1907 EXPORT_SYMBOL(pci_enable_device
);
1908 EXPORT_SYMBOL(pcim_enable_device
);
1909 EXPORT_SYMBOL(pcim_pin_device
);
1910 EXPORT_SYMBOL(pci_disable_device
);
1911 EXPORT_SYMBOL(pci_find_capability
);
1912 EXPORT_SYMBOL(pci_bus_find_capability
);
1913 EXPORT_SYMBOL(pci_release_regions
);
1914 EXPORT_SYMBOL(pci_request_regions
);
1915 EXPORT_SYMBOL(pci_release_region
);
1916 EXPORT_SYMBOL(pci_request_region
);
1917 EXPORT_SYMBOL(pci_release_selected_regions
);
1918 EXPORT_SYMBOL(pci_request_selected_regions
);
1919 EXPORT_SYMBOL(pci_set_master
);
1920 EXPORT_SYMBOL(pci_set_mwi
);
1921 EXPORT_SYMBOL(pci_try_set_mwi
);
1922 EXPORT_SYMBOL(pci_clear_mwi
);
1923 EXPORT_SYMBOL_GPL(pci_intx
);
1924 EXPORT_SYMBOL(pci_set_dma_mask
);
1925 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
1926 EXPORT_SYMBOL(pci_assign_resource
);
1927 EXPORT_SYMBOL(pci_find_parent_resource
);
1928 EXPORT_SYMBOL(pci_select_bars
);
1930 EXPORT_SYMBOL(pci_set_power_state
);
1931 EXPORT_SYMBOL(pci_save_state
);
1932 EXPORT_SYMBOL(pci_restore_state
);
1933 EXPORT_SYMBOL(pci_pme_capable
);
1934 EXPORT_SYMBOL(pci_enable_wake
);
1935 EXPORT_SYMBOL(pci_target_state
);
1936 EXPORT_SYMBOL(pci_prepare_to_sleep
);
1937 EXPORT_SYMBOL(pci_back_from_sleep
);
1938 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);