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net: use pci_dev->revision, again
[linux-2.6/x86.git] / drivers / net / cnic.c
blob5274de3e1bb9cd88ed29080fecb27a31b6d0ac36
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define BCM_VLAN 1
32 #endif
33 #include <net/ip.h>
34 #include <net/tcp.h>
35 #include <net/route.h>
36 #include <net/ipv6.h>
37 #include <net/ip6_route.h>
38 #include <net/ip6_checksum.h>
39 #include <scsi/iscsi_if.h>
40
41 #include "cnic_if.h"
42 #include "bnx2.h"
43 #include "bnx2x/bnx2x_reg.h"
44 #include "bnx2x/bnx2x_fw_defs.h"
45 #include "bnx2x/bnx2x_hsi.h"
46 #include "../scsi/bnx2i/57xx_iscsi_constants.h"
47 #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
48 #include "cnic.h"
49 #include "cnic_defs.h"
50
51 #define DRV_MODULE_NAME "cnic"
52
53 static char version[] __devinitdata =
54 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
55
56 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
57 "Chen (zongxi@broadcom.com");
58 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
59 MODULE_LICENSE("GPL");
60 MODULE_VERSION(CNIC_MODULE_VERSION);
61
62 /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
63 static LIST_HEAD(cnic_dev_list);
64 static LIST_HEAD(cnic_udev_list);
65 static DEFINE_RWLOCK(cnic_dev_lock);
66 static DEFINE_MUTEX(cnic_lock);
67
68 static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
69
70 /* helper function, assuming cnic_lock is held */
71 static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
72 {
73 return rcu_dereference_protected(cnic_ulp_tbl[type],
74 lockdep_is_held(&cnic_lock));
75 }
76
77 static int cnic_service_bnx2(void *, void *);
78 static int cnic_service_bnx2x(void *, void *);
79 static int cnic_ctl(void *, struct cnic_ctl_info *);
80
81 static struct cnic_ops cnic_bnx2_ops = {
82 .cnic_owner = THIS_MODULE,
83 .cnic_handler = cnic_service_bnx2,
84 .cnic_ctl = cnic_ctl,
85 };
86
87 static struct cnic_ops cnic_bnx2x_ops = {
88 .cnic_owner = THIS_MODULE,
89 .cnic_handler = cnic_service_bnx2x,
90 .cnic_ctl = cnic_ctl,
91 };
92
93 static struct workqueue_struct *cnic_wq;
94
95 static void cnic_shutdown_rings(struct cnic_dev *);
96 static void cnic_init_rings(struct cnic_dev *);
97 static int cnic_cm_set_pg(struct cnic_sock *);
98
99 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
100 {
101 struct cnic_uio_dev *udev = uinfo->priv;
102 struct cnic_dev *dev;
103
104 if (!capable(CAP_NET_ADMIN))
105 return -EPERM;
106
107 if (udev->uio_dev != -1)
108 return -EBUSY;
109
110 rtnl_lock();
111 dev = udev->dev;
112
113 if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
114 rtnl_unlock();
115 return -ENODEV;
116 }
117
118 udev->uio_dev = iminor(inode);
119
120 cnic_shutdown_rings(dev);
121 cnic_init_rings(dev);
122 rtnl_unlock();
123
124 return 0;
125 }
126
127 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
128 {
129 struct cnic_uio_dev *udev = uinfo->priv;
130
131 udev->uio_dev = -1;
132 return 0;
133 }
134
135 static inline void cnic_hold(struct cnic_dev *dev)
136 {
137 atomic_inc(&dev->ref_count);
138 }
139
140 static inline void cnic_put(struct cnic_dev *dev)
141 {
142 atomic_dec(&dev->ref_count);
143 }
144
145 static inline void csk_hold(struct cnic_sock *csk)
146 {
147 atomic_inc(&csk->ref_count);
148 }
149
150 static inline void csk_put(struct cnic_sock *csk)
151 {
152 atomic_dec(&csk->ref_count);
153 }
154
155 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
156 {
157 struct cnic_dev *cdev;
158
159 read_lock(&cnic_dev_lock);
160 list_for_each_entry(cdev, &cnic_dev_list, list) {
161 if (netdev == cdev->netdev) {
162 cnic_hold(cdev);
163 read_unlock(&cnic_dev_lock);
164 return cdev;
165 }
166 }
167 read_unlock(&cnic_dev_lock);
168 return NULL;
169 }
170
171 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
172 {
173 atomic_inc(&ulp_ops->ref_count);
174 }
175
176 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
177 {
178 atomic_dec(&ulp_ops->ref_count);
179 }
180
181 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
182 {
183 struct cnic_local *cp = dev->cnic_priv;
184 struct cnic_eth_dev *ethdev = cp->ethdev;
185 struct drv_ctl_info info;
186 struct drv_ctl_io *io = &info.data.io;
187
188 info.cmd = DRV_CTL_CTX_WR_CMD;
189 io->cid_addr = cid_addr;
190 io->offset = off;
191 io->data = val;
192 ethdev->drv_ctl(dev->netdev, &info);
193 }
194
195 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
196 {
197 struct cnic_local *cp = dev->cnic_priv;
198 struct cnic_eth_dev *ethdev = cp->ethdev;
199 struct drv_ctl_info info;
200 struct drv_ctl_io *io = &info.data.io;
201
202 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
203 io->offset = off;
204 io->dma_addr = addr;
205 ethdev->drv_ctl(dev->netdev, &info);
206 }
207
208 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
209 {
210 struct cnic_local *cp = dev->cnic_priv;
211 struct cnic_eth_dev *ethdev = cp->ethdev;
212 struct drv_ctl_info info;
213 struct drv_ctl_l2_ring *ring = &info.data.ring;
214
215 if (start)
216 info.cmd = DRV_CTL_START_L2_CMD;
217 else
218 info.cmd = DRV_CTL_STOP_L2_CMD;
219
220 ring->cid = cid;
221 ring->client_id = cl_id;
222 ethdev->drv_ctl(dev->netdev, &info);
223 }
224
225 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
226 {
227 struct cnic_local *cp = dev->cnic_priv;
228 struct cnic_eth_dev *ethdev = cp->ethdev;
229 struct drv_ctl_info info;
230 struct drv_ctl_io *io = &info.data.io;
231
232 info.cmd = DRV_CTL_IO_WR_CMD;
233 io->offset = off;
234 io->data = val;
235 ethdev->drv_ctl(dev->netdev, &info);
236 }
237
238 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
239 {
240 struct cnic_local *cp = dev->cnic_priv;
241 struct cnic_eth_dev *ethdev = cp->ethdev;
242 struct drv_ctl_info info;
243 struct drv_ctl_io *io = &info.data.io;
244
245 info.cmd = DRV_CTL_IO_RD_CMD;
246 io->offset = off;
247 ethdev->drv_ctl(dev->netdev, &info);
248 return io->data;
249 }
250
251 static int cnic_in_use(struct cnic_sock *csk)
252 {
253 return test_bit(SK_F_INUSE, &csk->flags);
254 }
255
256 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
257 {
258 struct cnic_local *cp = dev->cnic_priv;
259 struct cnic_eth_dev *ethdev = cp->ethdev;
260 struct drv_ctl_info info;
261
262 info.cmd = cmd;
263 info.data.credit.credit_count = count;
264 ethdev->drv_ctl(dev->netdev, &info);
265 }
266
267 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
268 {
269 u32 i;
270
271 for (i = 0; i < cp->max_cid_space; i++) {
272 if (cp->ctx_tbl[i].cid == cid) {
273 *l5_cid = i;
274 return 0;
275 }
276 }
277 return -EINVAL;
278 }
279
280 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
281 struct cnic_sock *csk)
282 {
283 struct iscsi_path path_req;
284 char *buf = NULL;
285 u16 len = 0;
286 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
287 struct cnic_ulp_ops *ulp_ops;
288 struct cnic_uio_dev *udev = cp->udev;
289 int rc = 0, retry = 0;
290
291 if (!udev || udev->uio_dev == -1)
292 return -ENODEV;
293
294 if (csk) {
295 len = sizeof(path_req);
296 buf = (char *) &path_req;
297 memset(&path_req, 0, len);
298
299 msg_type = ISCSI_KEVENT_PATH_REQ;
300 path_req.handle = (u64) csk->l5_cid;
301 if (test_bit(SK_F_IPV6, &csk->flags)) {
302 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
303 sizeof(struct in6_addr));
304 path_req.ip_addr_len = 16;
305 } else {
306 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
307 sizeof(struct in_addr));
308 path_req.ip_addr_len = 4;
309 }
310 path_req.vlan_id = csk->vlan_id;
311 path_req.pmtu = csk->mtu;
312 }
313
314 while (retry < 3) {
315 rc = 0;
316 rcu_read_lock();
317 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
318 if (ulp_ops)
319 rc = ulp_ops->iscsi_nl_send_msg(
320 cp->ulp_handle[CNIC_ULP_ISCSI],
321 msg_type, buf, len);
322 rcu_read_unlock();
323 if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
324 break;
325
326 msleep(100);
327 retry++;
328 }
329 return 0;
330 }
331
332 static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
333
334 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
335 char *buf, u16 len)
336 {
337 int rc = -EINVAL;
338
339 switch (msg_type) {
340 case ISCSI_UEVENT_PATH_UPDATE: {
341 struct cnic_local *cp;
342 u32 l5_cid;
343 struct cnic_sock *csk;
344 struct iscsi_path *path_resp;
345
346 if (len < sizeof(*path_resp))
347 break;
348
349 path_resp = (struct iscsi_path *) buf;
350 cp = dev->cnic_priv;
351 l5_cid = (u32) path_resp->handle;
352 if (l5_cid >= MAX_CM_SK_TBL_SZ)
353 break;
354
355 rcu_read_lock();
356 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
357 rc = -ENODEV;
358 rcu_read_unlock();
359 break;
360 }
361 csk = &cp->csk_tbl[l5_cid];
362 csk_hold(csk);
363 if (cnic_in_use(csk) &&
364 test_bit(SK_F_CONNECT_START, &csk->flags)) {
365
366 memcpy(csk->ha, path_resp->mac_addr, 6);
367 if (test_bit(SK_F_IPV6, &csk->flags))
368 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
369 sizeof(struct in6_addr));
370 else
371 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
372 sizeof(struct in_addr));
373
374 if (is_valid_ether_addr(csk->ha)) {
375 cnic_cm_set_pg(csk);
376 } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
377 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
378
379 cnic_cm_upcall(cp, csk,
380 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
381 clear_bit(SK_F_CONNECT_START, &csk->flags);
382 }
383 }
384 csk_put(csk);
385 rcu_read_unlock();
386 rc = 0;
387 }
388 }
389
390 return rc;
391 }
392
393 static int cnic_offld_prep(struct cnic_sock *csk)
394 {
395 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
396 return 0;
397
398 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
399 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
400 return 0;
401 }
402
403 return 1;
404 }
405
406 static int cnic_close_prep(struct cnic_sock *csk)
407 {
408 clear_bit(SK_F_CONNECT_START, &csk->flags);
409 smp_mb__after_clear_bit();
410
411 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
412 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
413 msleep(1);
414
415 return 1;
416 }
417 return 0;
418 }
419
420 static int cnic_abort_prep(struct cnic_sock *csk)
421 {
422 clear_bit(SK_F_CONNECT_START, &csk->flags);
423 smp_mb__after_clear_bit();
424
425 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
426 msleep(1);
427
428 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
429 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
430 return 1;
431 }
432
433 return 0;
434 }
435
436 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
437 {
438 struct cnic_dev *dev;
439
440 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
441 pr_err("%s: Bad type %d\n", __func__, ulp_type);
442 return -EINVAL;
443 }
444 mutex_lock(&cnic_lock);
445 if (cnic_ulp_tbl_prot(ulp_type)) {
446 pr_err("%s: Type %d has already been registered\n",
447 __func__, ulp_type);
448 mutex_unlock(&cnic_lock);
449 return -EBUSY;
450 }
451
452 read_lock(&cnic_dev_lock);
453 list_for_each_entry(dev, &cnic_dev_list, list) {
454 struct cnic_local *cp = dev->cnic_priv;
455
456 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
457 }
458 read_unlock(&cnic_dev_lock);
459
460 atomic_set(&ulp_ops->ref_count, 0);
461 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
462 mutex_unlock(&cnic_lock);
463
464 /* Prevent race conditions with netdev_event */
465 rtnl_lock();
466 list_for_each_entry(dev, &cnic_dev_list, list) {
467 struct cnic_local *cp = dev->cnic_priv;
468
469 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
470 ulp_ops->cnic_init(dev);
471 }
472 rtnl_unlock();
473
474 return 0;
475 }
476
477 int cnic_unregister_driver(int ulp_type)
478 {
479 struct cnic_dev *dev;
480 struct cnic_ulp_ops *ulp_ops;
481 int i = 0;
482
483 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
484 pr_err("%s: Bad type %d\n", __func__, ulp_type);
485 return -EINVAL;
486 }
487 mutex_lock(&cnic_lock);
488 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
489 if (!ulp_ops) {
490 pr_err("%s: Type %d has not been registered\n",
491 __func__, ulp_type);
492 goto out_unlock;
493 }
494 read_lock(&cnic_dev_lock);
495 list_for_each_entry(dev, &cnic_dev_list, list) {
496 struct cnic_local *cp = dev->cnic_priv;
497
498 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
499 pr_err("%s: Type %d still has devices registered\n",
500 __func__, ulp_type);
501 read_unlock(&cnic_dev_lock);
502 goto out_unlock;
503 }
504 }
505 read_unlock(&cnic_dev_lock);
506
507 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
508
509 mutex_unlock(&cnic_lock);
510 synchronize_rcu();
511 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
512 msleep(100);
513 i++;
514 }
515
516 if (atomic_read(&ulp_ops->ref_count) != 0)
517 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
518 return 0;
519
520 out_unlock:
521 mutex_unlock(&cnic_lock);
522 return -EINVAL;
523 }
524
525 static int cnic_start_hw(struct cnic_dev *);
526 static void cnic_stop_hw(struct cnic_dev *);
527
528 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
529 void *ulp_ctx)
530 {
531 struct cnic_local *cp = dev->cnic_priv;
532 struct cnic_ulp_ops *ulp_ops;
533
534 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
535 pr_err("%s: Bad type %d\n", __func__, ulp_type);
536 return -EINVAL;
537 }
538 mutex_lock(&cnic_lock);
539 if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
540 pr_err("%s: Driver with type %d has not been registered\n",
541 __func__, ulp_type);
542 mutex_unlock(&cnic_lock);
543 return -EAGAIN;
544 }
545 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
546 pr_err("%s: Type %d has already been registered to this device\n",
547 __func__, ulp_type);
548 mutex_unlock(&cnic_lock);
549 return -EBUSY;
550 }
551
552 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
553 cp->ulp_handle[ulp_type] = ulp_ctx;
554 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
555 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
556 cnic_hold(dev);
557
558 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
559 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
560 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
561
562 mutex_unlock(&cnic_lock);
563
564 return 0;
565
566 }
567 EXPORT_SYMBOL(cnic_register_driver);
568
569 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
570 {
571 struct cnic_local *cp = dev->cnic_priv;
572 int i = 0;
573
574 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
575 pr_err("%s: Bad type %d\n", __func__, ulp_type);
576 return -EINVAL;
577 }
578 mutex_lock(&cnic_lock);
579 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
580 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
581 cnic_put(dev);
582 } else {
583 pr_err("%s: device not registered to this ulp type %d\n",
584 __func__, ulp_type);
585 mutex_unlock(&cnic_lock);
586 return -EINVAL;
587 }
588 mutex_unlock(&cnic_lock);
589
590 if (ulp_type == CNIC_ULP_ISCSI)
591 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
592
593 synchronize_rcu();
594
595 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
596 i < 20) {
597 msleep(100);
598 i++;
599 }
600 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
601 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
602
603 return 0;
604 }
605 EXPORT_SYMBOL(cnic_unregister_driver);
606
607 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
608 {
609 id_tbl->start = start_id;
610 id_tbl->max = size;
611 id_tbl->next = 0;
612 spin_lock_init(&id_tbl->lock);
613 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
614 if (!id_tbl->table)
615 return -ENOMEM;
616
617 return 0;
618 }
619
620 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
621 {
622 kfree(id_tbl->table);
623 id_tbl->table = NULL;
624 }
625
626 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
627 {
628 int ret = -1;
629
630 id -= id_tbl->start;
631 if (id >= id_tbl->max)
632 return ret;
633
634 spin_lock(&id_tbl->lock);
635 if (!test_bit(id, id_tbl->table)) {
636 set_bit(id, id_tbl->table);
637 ret = 0;
638 }
639 spin_unlock(&id_tbl->lock);
640 return ret;
641 }
642
643 /* Returns -1 if not successful */
644 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
645 {
646 u32 id;
647
648 spin_lock(&id_tbl->lock);
649 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
650 if (id >= id_tbl->max) {
651 id = -1;
652 if (id_tbl->next != 0) {
653 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
654 if (id >= id_tbl->next)
655 id = -1;
656 }
657 }
658
659 if (id < id_tbl->max) {
660 set_bit(id, id_tbl->table);
661 id_tbl->next = (id + 1) & (id_tbl->max - 1);
662 id += id_tbl->start;
663 }
664
665 spin_unlock(&id_tbl->lock);
666
667 return id;
668 }
669
670 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
671 {
672 if (id == -1)
673 return;
674
675 id -= id_tbl->start;
676 if (id >= id_tbl->max)
677 return;
678
679 clear_bit(id, id_tbl->table);
680 }
681
682 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
683 {
684 int i;
685
686 if (!dma->pg_arr)
687 return;
688
689 for (i = 0; i < dma->num_pages; i++) {
690 if (dma->pg_arr[i]) {
691 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
692 dma->pg_arr[i], dma->pg_map_arr[i]);
693 dma->pg_arr[i] = NULL;
694 }
695 }
696 if (dma->pgtbl) {
697 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
698 dma->pgtbl, dma->pgtbl_map);
699 dma->pgtbl = NULL;
700 }
701 kfree(dma->pg_arr);
702 dma->pg_arr = NULL;
703 dma->num_pages = 0;
704 }
705
706 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
707 {
708 int i;
709 __le32 *page_table = (__le32 *) dma->pgtbl;
710
711 for (i = 0; i < dma->num_pages; i++) {
712 /* Each entry needs to be in big endian format. */
713 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
714 page_table++;
715 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
716 page_table++;
717 }
718 }
719
720 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
721 {
722 int i;
723 __le32 *page_table = (__le32 *) dma->pgtbl;
724
725 for (i = 0; i < dma->num_pages; i++) {
726 /* Each entry needs to be in little endian format. */
727 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
728 page_table++;
729 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
730 page_table++;
731 }
732 }
733
734 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
735 int pages, int use_pg_tbl)
736 {
737 int i, size;
738 struct cnic_local *cp = dev->cnic_priv;
739
740 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
741 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
742 if (dma->pg_arr == NULL)
743 return -ENOMEM;
744
745 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
746 dma->num_pages = pages;
747
748 for (i = 0; i < pages; i++) {
749 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
750 BCM_PAGE_SIZE,
751 &dma->pg_map_arr[i],
752 GFP_ATOMIC);
753 if (dma->pg_arr[i] == NULL)
754 goto error;
755 }
756 if (!use_pg_tbl)
757 return 0;
758
759 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
760 ~(BCM_PAGE_SIZE - 1);
761 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
762 &dma->pgtbl_map, GFP_ATOMIC);
763 if (dma->pgtbl == NULL)
764 goto error;
765
766 cp->setup_pgtbl(dev, dma);
767
768 return 0;
769
770 error:
771 cnic_free_dma(dev, dma);
772 return -ENOMEM;
773 }
774
775 static void cnic_free_context(struct cnic_dev *dev)
776 {
777 struct cnic_local *cp = dev->cnic_priv;
778 int i;
779
780 for (i = 0; i < cp->ctx_blks; i++) {
781 if (cp->ctx_arr[i].ctx) {
782 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
783 cp->ctx_arr[i].ctx,
784 cp->ctx_arr[i].mapping);
785 cp->ctx_arr[i].ctx = NULL;
786 }
787 }
788 }
789
790 static void __cnic_free_uio(struct cnic_uio_dev *udev)
791 {
792 uio_unregister_device(&udev->cnic_uinfo);
793
794 if (udev->l2_buf) {
795 dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
796 udev->l2_buf, udev->l2_buf_map);
797 udev->l2_buf = NULL;
798 }
799
800 if (udev->l2_ring) {
801 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
802 udev->l2_ring, udev->l2_ring_map);
803 udev->l2_ring = NULL;
804 }
805
806 pci_dev_put(udev->pdev);
807 kfree(udev);
808 }
809
810 static void cnic_free_uio(struct cnic_uio_dev *udev)
811 {
812 if (!udev)
813 return;
814
815 write_lock(&cnic_dev_lock);
816 list_del_init(&udev->list);
817 write_unlock(&cnic_dev_lock);
818 __cnic_free_uio(udev);
819 }
820
821 static void cnic_free_resc(struct cnic_dev *dev)
822 {
823 struct cnic_local *cp = dev->cnic_priv;
824 struct cnic_uio_dev *udev = cp->udev;
825
826 if (udev) {
827 udev->dev = NULL;
828 cp->udev = NULL;
829 }
830
831 cnic_free_context(dev);
832 kfree(cp->ctx_arr);
833 cp->ctx_arr = NULL;
834 cp->ctx_blks = 0;
835
836 cnic_free_dma(dev, &cp->gbl_buf_info);
837 cnic_free_dma(dev, &cp->conn_buf_info);
838 cnic_free_dma(dev, &cp->kwq_info);
839 cnic_free_dma(dev, &cp->kwq_16_data_info);
840 cnic_free_dma(dev, &cp->kcq2.dma);
841 cnic_free_dma(dev, &cp->kcq1.dma);
842 kfree(cp->iscsi_tbl);
843 cp->iscsi_tbl = NULL;
844 kfree(cp->ctx_tbl);
845 cp->ctx_tbl = NULL;
846
847 cnic_free_id_tbl(&cp->fcoe_cid_tbl);
848 cnic_free_id_tbl(&cp->cid_tbl);
849 }
850
851 static int cnic_alloc_context(struct cnic_dev *dev)
852 {
853 struct cnic_local *cp = dev->cnic_priv;
854
855 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
856 int i, k, arr_size;
857
858 cp->ctx_blk_size = BCM_PAGE_SIZE;
859 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
860 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
861 sizeof(struct cnic_ctx);
862 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
863 if (cp->ctx_arr == NULL)
864 return -ENOMEM;
865
866 k = 0;
867 for (i = 0; i < 2; i++) {
868 u32 j, reg, off, lo, hi;
869
870 if (i == 0)
871 off = BNX2_PG_CTX_MAP;
872 else
873 off = BNX2_ISCSI_CTX_MAP;
874
875 reg = cnic_reg_rd_ind(dev, off);
876 lo = reg >> 16;
877 hi = reg & 0xffff;
878 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
879 cp->ctx_arr[k].cid = j;
880 }
881
882 cp->ctx_blks = k;
883 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
884 cp->ctx_blks = 0;
885 return -ENOMEM;
886 }
887
888 for (i = 0; i < cp->ctx_blks; i++) {
889 cp->ctx_arr[i].ctx =
890 dma_alloc_coherent(&dev->pcidev->dev,
891 BCM_PAGE_SIZE,
892 &cp->ctx_arr[i].mapping,
893 GFP_KERNEL);
894 if (cp->ctx_arr[i].ctx == NULL)
895 return -ENOMEM;
896 }
897 }
898 return 0;
899 }
900
901 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
902 {
903 int err, i, is_bnx2 = 0;
904 struct kcqe **kcq;
905
906 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
907 is_bnx2 = 1;
908
909 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
910 if (err)
911 return err;
912
913 kcq = (struct kcqe **) info->dma.pg_arr;
914 info->kcq = kcq;
915
916 if (is_bnx2)
917 return 0;
918
919 for (i = 0; i < KCQ_PAGE_CNT; i++) {
920 struct bnx2x_bd_chain_next *next =
921 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
922 int j = i + 1;
923
924 if (j >= KCQ_PAGE_CNT)
925 j = 0;
926 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
927 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
928 }
929 return 0;
930 }
931
932 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
933 {
934 struct cnic_local *cp = dev->cnic_priv;
935 struct cnic_uio_dev *udev;
936
937 read_lock(&cnic_dev_lock);
938 list_for_each_entry(udev, &cnic_udev_list, list) {
939 if (udev->pdev == dev->pcidev) {
940 udev->dev = dev;
941 cp->udev = udev;
942 read_unlock(&cnic_dev_lock);
943 return 0;
944 }
945 }
946 read_unlock(&cnic_dev_lock);
947
948 udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
949 if (!udev)
950 return -ENOMEM;
951
952 udev->uio_dev = -1;
953
954 udev->dev = dev;
955 udev->pdev = dev->pcidev;
956 udev->l2_ring_size = pages * BCM_PAGE_SIZE;
957 udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
958 &udev->l2_ring_map,
959 GFP_KERNEL | __GFP_COMP);
960 if (!udev->l2_ring)
961 goto err_udev;
962
963 udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
964 udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
965 udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
966 &udev->l2_buf_map,
967 GFP_KERNEL | __GFP_COMP);
968 if (!udev->l2_buf)
969 goto err_dma;
970
971 write_lock(&cnic_dev_lock);
972 list_add(&udev->list, &cnic_udev_list);
973 write_unlock(&cnic_dev_lock);
974
975 pci_dev_get(udev->pdev);
976
977 cp->udev = udev;
978
979 return 0;
980 err_dma:
981 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
982 udev->l2_ring, udev->l2_ring_map);
983 err_udev:
984 kfree(udev);
985 return -ENOMEM;
986 }
987
988 static int cnic_init_uio(struct cnic_dev *dev)
989 {
990 struct cnic_local *cp = dev->cnic_priv;
991 struct cnic_uio_dev *udev = cp->udev;
992 struct uio_info *uinfo;
993 int ret = 0;
994
995 if (!udev)
996 return -ENOMEM;
997
998 uinfo = &udev->cnic_uinfo;
999
1000 uinfo->mem[0].addr = dev->netdev->base_addr;
1001 uinfo->mem[0].internal_addr = dev->regview;
1002 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
1003 uinfo->mem[0].memtype = UIO_MEM_PHYS;
1004
1005 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
1006 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
1007 PAGE_MASK;
1008 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
1009 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
1010 else
1011 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
1012
1013 uinfo->name = "bnx2_cnic";
1014 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
1015 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
1016 PAGE_MASK;
1017 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
1018
1019 uinfo->name = "bnx2x_cnic";
1020 }
1021
1022 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
1023
1024 uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
1025 uinfo->mem[2].size = udev->l2_ring_size;
1026 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
1027
1028 uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
1029 uinfo->mem[3].size = udev->l2_buf_size;
1030 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
1031
1032 uinfo->version = CNIC_MODULE_VERSION;
1033 uinfo->irq = UIO_IRQ_CUSTOM;
1034
1035 uinfo->open = cnic_uio_open;
1036 uinfo->release = cnic_uio_close;
1037
1038 if (udev->uio_dev == -1) {
1039 if (!uinfo->priv) {
1040 uinfo->priv = udev;
1041
1042 ret = uio_register_device(&udev->pdev->dev, uinfo);
1043 }
1044 } else {
1045 cnic_init_rings(dev);
1046 }
1047
1048 return ret;
1049 }
1050
1051 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1052 {
1053 struct cnic_local *cp = dev->cnic_priv;
1054 int ret;
1055
1056 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1057 if (ret)
1058 goto error;
1059 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1060
1061 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1062 if (ret)
1063 goto error;
1064
1065 ret = cnic_alloc_context(dev);
1066 if (ret)
1067 goto error;
1068
1069 ret = cnic_alloc_uio_rings(dev, 2);
1070 if (ret)
1071 goto error;
1072
1073 ret = cnic_init_uio(dev);
1074 if (ret)
1075 goto error;
1076
1077 return 0;
1078
1079 error:
1080 cnic_free_resc(dev);
1081 return ret;
1082 }
1083
1084 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1085 {
1086 struct cnic_local *cp = dev->cnic_priv;
1087 int ctx_blk_size = cp->ethdev->ctx_blk_size;
1088 int total_mem, blks, i;
1089
1090 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1091 blks = total_mem / ctx_blk_size;
1092 if (total_mem % ctx_blk_size)
1093 blks++;
1094
1095 if (blks > cp->ethdev->ctx_tbl_len)
1096 return -ENOMEM;
1097
1098 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1099 if (cp->ctx_arr == NULL)
1100 return -ENOMEM;
1101
1102 cp->ctx_blks = blks;
1103 cp->ctx_blk_size = ctx_blk_size;
1104 if (!BNX2X_CHIP_IS_57710(cp->chip_id))
1105 cp->ctx_align = 0;
1106 else
1107 cp->ctx_align = ctx_blk_size;
1108
1109 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1110
1111 for (i = 0; i < blks; i++) {
1112 cp->ctx_arr[i].ctx =
1113 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1114 &cp->ctx_arr[i].mapping,
1115 GFP_KERNEL);
1116 if (cp->ctx_arr[i].ctx == NULL)
1117 return -ENOMEM;
1118
1119 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1120 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1121 cnic_free_context(dev);
1122 cp->ctx_blk_size += cp->ctx_align;
1123 i = -1;
1124 continue;
1125 }
1126 }
1127 }
1128 return 0;
1129 }
1130
1131 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1132 {
1133 struct cnic_local *cp = dev->cnic_priv;
1134 struct cnic_eth_dev *ethdev = cp->ethdev;
1135 u32 start_cid = ethdev->starting_cid;
1136 int i, j, n, ret, pages;
1137 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1138
1139 cp->iro_arr = ethdev->iro_arr;
1140
1141 cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
1142 cp->iscsi_start_cid = start_cid;
1143 cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
1144
1145 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
1146 cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
1147 cp->fcoe_init_cid = ethdev->fcoe_init_cid;
1148 if (!cp->fcoe_init_cid)
1149 cp->fcoe_init_cid = 0x10;
1150 }
1151
1152 if (start_cid < BNX2X_ISCSI_START_CID) {
1153 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1154
1155 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1156 cp->fcoe_start_cid += delta;
1157 cp->max_cid_space += delta;
1158 }
1159
1160 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1161 GFP_KERNEL);
1162 if (!cp->iscsi_tbl)
1163 goto error;
1164
1165 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1166 cp->max_cid_space, GFP_KERNEL);
1167 if (!cp->ctx_tbl)
1168 goto error;
1169
1170 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1171 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1172 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1173 }
1174
1175 for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
1176 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
1177
1178 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1179 PAGE_SIZE;
1180
1181 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1182 if (ret)
1183 return -ENOMEM;
1184
1185 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1186 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1187 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1188
1189 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1190 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1191 off;
1192
1193 if ((i % n) == (n - 1))
1194 j++;
1195 }
1196
1197 ret = cnic_alloc_kcq(dev, &cp->kcq1);
1198 if (ret)
1199 goto error;
1200
1201 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
1202 ret = cnic_alloc_kcq(dev, &cp->kcq2);
1203 if (ret)
1204 goto error;
1205 }
1206
1207 pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
1208 BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
1209 ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
1210 if (ret)
1211 goto error;
1212
1213 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1214 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1215 if (ret)
1216 goto error;
1217
1218 ret = cnic_alloc_bnx2x_context(dev);
1219 if (ret)
1220 goto error;
1221
1222 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1223
1224 cp->l2_rx_ring_size = 15;
1225
1226 ret = cnic_alloc_uio_rings(dev, 4);
1227 if (ret)
1228 goto error;
1229
1230 ret = cnic_init_uio(dev);
1231 if (ret)
1232 goto error;
1233
1234 return 0;
1235
1236 error:
1237 cnic_free_resc(dev);
1238 return -ENOMEM;
1239 }
1240
1241 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1242 {
1243 return cp->max_kwq_idx -
1244 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1245 }
1246
1247 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1248 u32 num_wqes)
1249 {
1250 struct cnic_local *cp = dev->cnic_priv;
1251 struct kwqe *prod_qe;
1252 u16 prod, sw_prod, i;
1253
1254 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1255 return -EAGAIN; /* bnx2 is down */
1256
1257 spin_lock_bh(&cp->cnic_ulp_lock);
1258 if (num_wqes > cnic_kwq_avail(cp) &&
1259 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1260 spin_unlock_bh(&cp->cnic_ulp_lock);
1261 return -EAGAIN;
1262 }
1263
1264 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1265
1266 prod = cp->kwq_prod_idx;
1267 sw_prod = prod & MAX_KWQ_IDX;
1268 for (i = 0; i < num_wqes; i++) {
1269 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1270 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1271 prod++;
1272 sw_prod = prod & MAX_KWQ_IDX;
1273 }
1274 cp->kwq_prod_idx = prod;
1275
1276 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1277
1278 spin_unlock_bh(&cp->cnic_ulp_lock);
1279 return 0;
1280 }
1281
1282 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1283 union l5cm_specific_data *l5_data)
1284 {
1285 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1286 dma_addr_t map;
1287
1288 map = ctx->kwqe_data_mapping;
1289 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1290 l5_data->phy_address.hi = (u64) map >> 32;
1291 return ctx->kwqe_data;
1292 }
1293
1294 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1295 u32 type, union l5cm_specific_data *l5_data)
1296 {
1297 struct cnic_local *cp = dev->cnic_priv;
1298 struct l5cm_spe kwqe;
1299 struct kwqe_16 *kwq[1];
1300 u16 type_16;
1301 int ret;
1302
1303 kwqe.hdr.conn_and_cmd_data =
1304 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1305 BNX2X_HW_CID(cp, cid)));
1306
1307 type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1308 type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1309 SPE_HDR_FUNCTION_ID;
1310
1311 kwqe.hdr.type = cpu_to_le16(type_16);
1312 kwqe.hdr.reserved1 = 0;
1313 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1314 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1315
1316 kwq[0] = (struct kwqe_16 *) &kwqe;
1317
1318 spin_lock_bh(&cp->cnic_ulp_lock);
1319 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1320 spin_unlock_bh(&cp->cnic_ulp_lock);
1321
1322 if (ret == 1)
1323 return 0;
1324
1325 return -EBUSY;
1326 }
1327
1328 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1329 struct kcqe *cqes[], u32 num_cqes)
1330 {
1331 struct cnic_local *cp = dev->cnic_priv;
1332 struct cnic_ulp_ops *ulp_ops;
1333
1334 rcu_read_lock();
1335 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1336 if (likely(ulp_ops)) {
1337 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1338 cqes, num_cqes);
1339 }
1340 rcu_read_unlock();
1341 }
1342
1343 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1344 {
1345 struct cnic_local *cp = dev->cnic_priv;
1346 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1347 int hq_bds, pages;
1348 u32 pfid = cp->pfid;
1349
1350 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1351 cp->num_ccells = req1->num_ccells_per_conn;
1352 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1353 cp->num_iscsi_tasks;
1354 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1355 BNX2X_ISCSI_R2TQE_SIZE;
1356 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1357 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1358 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1359 cp->num_cqs = req1->num_cqs;
1360
1361 if (!dev->max_iscsi_conn)
1362 return 0;
1363
1364 /* init Tstorm RAM */
1365 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1366 req1->rq_num_wqes);
1367 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1368 PAGE_SIZE);
1369 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1370 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1371 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1372 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1373 req1->num_tasks_per_conn);
1374
1375 /* init Ustorm RAM */
1376 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1377 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1378 req1->rq_buffer_size);
1379 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1380 PAGE_SIZE);
1381 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1382 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1383 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1384 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1385 req1->num_tasks_per_conn);
1386 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1387 req1->rq_num_wqes);
1388 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1389 req1->cq_num_wqes);
1390 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1391 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1392
1393 /* init Xstorm RAM */
1394 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1395 PAGE_SIZE);
1396 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1397 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1398 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1399 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1400 req1->num_tasks_per_conn);
1401 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1402 hq_bds);
1403 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1404 req1->num_tasks_per_conn);
1405 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1406 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1407
1408 /* init Cstorm RAM */
1409 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1410 PAGE_SIZE);
1411 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1412 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1413 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1414 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1415 req1->num_tasks_per_conn);
1416 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1417 req1->cq_num_wqes);
1418 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1419 hq_bds);
1420
1421 return 0;
1422 }
1423
1424 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1425 {
1426 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1427 struct cnic_local *cp = dev->cnic_priv;
1428 u32 pfid = cp->pfid;
1429 struct iscsi_kcqe kcqe;
1430 struct kcqe *cqes[1];
1431
1432 memset(&kcqe, 0, sizeof(kcqe));
1433 if (!dev->max_iscsi_conn) {
1434 kcqe.completion_status =
1435 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1436 goto done;
1437 }
1438
1439 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1440 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1441 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1442 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1443 req2->error_bit_map[1]);
1444
1445 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1446 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1447 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1448 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1449 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1450 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1451 req2->error_bit_map[1]);
1452
1453 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1454 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1455
1456 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1457
1458 done:
1459 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1460 cqes[0] = (struct kcqe *) &kcqe;
1461 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1462
1463 return 0;
1464 }
1465
1466 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1467 {
1468 struct cnic_local *cp = dev->cnic_priv;
1469 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1470
1471 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1472 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1473
1474 cnic_free_dma(dev, &iscsi->hq_info);
1475 cnic_free_dma(dev, &iscsi->r2tq_info);
1476 cnic_free_dma(dev, &iscsi->task_array_info);
1477 cnic_free_id(&cp->cid_tbl, ctx->cid);
1478 } else {
1479 cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
1480 }
1481
1482 ctx->cid = 0;
1483 }
1484
1485 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1486 {
1487 u32 cid;
1488 int ret, pages;
1489 struct cnic_local *cp = dev->cnic_priv;
1490 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1491 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1492
1493 if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
1494 cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
1495 if (cid == -1) {
1496 ret = -ENOMEM;
1497 goto error;
1498 }
1499 ctx->cid = cid;
1500 return 0;
1501 }
1502
1503 cid = cnic_alloc_new_id(&cp->cid_tbl);
1504 if (cid == -1) {
1505 ret = -ENOMEM;
1506 goto error;
1507 }
1508
1509 ctx->cid = cid;
1510 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1511
1512 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1513 if (ret)
1514 goto error;
1515
1516 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1517 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1518 if (ret)
1519 goto error;
1520
1521 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1522 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1523 if (ret)
1524 goto error;
1525
1526 return 0;
1527
1528 error:
1529 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1530 return ret;
1531 }
1532
1533 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1534 struct regpair *ctx_addr)
1535 {
1536 struct cnic_local *cp = dev->cnic_priv;
1537 struct cnic_eth_dev *ethdev = cp->ethdev;
1538 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1539 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1540 unsigned long align_off = 0;
1541 dma_addr_t ctx_map;
1542 void *ctx;
1543
1544 if (cp->ctx_align) {
1545 unsigned long mask = cp->ctx_align - 1;
1546
1547 if (cp->ctx_arr[blk].mapping & mask)
1548 align_off = cp->ctx_align -
1549 (cp->ctx_arr[blk].mapping & mask);
1550 }
1551 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1552 (off * BNX2X_CONTEXT_MEM_SIZE);
1553 ctx = cp->ctx_arr[blk].ctx + align_off +
1554 (off * BNX2X_CONTEXT_MEM_SIZE);
1555 if (init)
1556 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1557
1558 ctx_addr->lo = ctx_map & 0xffffffff;
1559 ctx_addr->hi = (u64) ctx_map >> 32;
1560 return ctx;
1561 }
1562
1563 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1564 u32 num)
1565 {
1566 struct cnic_local *cp = dev->cnic_priv;
1567 struct iscsi_kwqe_conn_offload1 *req1 =
1568 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1569 struct iscsi_kwqe_conn_offload2 *req2 =
1570 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1571 struct iscsi_kwqe_conn_offload3 *req3;
1572 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1573 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1574 u32 cid = ctx->cid;
1575 u32 hw_cid = BNX2X_HW_CID(cp, cid);
1576 struct iscsi_context *ictx;
1577 struct regpair context_addr;
1578 int i, j, n = 2, n_max;
1579
1580 ctx->ctx_flags = 0;
1581 if (!req2->num_additional_wqes)
1582 return -EINVAL;
1583
1584 n_max = req2->num_additional_wqes + 2;
1585
1586 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1587 if (ictx == NULL)
1588 return -ENOMEM;
1589
1590 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1591
1592 ictx->xstorm_ag_context.hq_prod = 1;
1593
1594 ictx->xstorm_st_context.iscsi.first_burst_length =
1595 ISCSI_DEF_FIRST_BURST_LEN;
1596 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1597 ISCSI_DEF_MAX_RECV_SEG_LEN;
1598 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1599 req1->sq_page_table_addr_lo;
1600 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1601 req1->sq_page_table_addr_hi;
1602 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1603 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1604 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1605 iscsi->hq_info.pgtbl_map & 0xffffffff;
1606 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1607 (u64) iscsi->hq_info.pgtbl_map >> 32;
1608 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1609 iscsi->hq_info.pgtbl[0];
1610 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1611 iscsi->hq_info.pgtbl[1];
1612 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1613 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1614 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1615 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1616 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1617 iscsi->r2tq_info.pgtbl[0];
1618 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1619 iscsi->r2tq_info.pgtbl[1];
1620 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1621 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1622 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1623 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1624 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1625 BNX2X_ISCSI_PBL_NOT_CACHED;
1626 ictx->xstorm_st_context.iscsi.flags.flags |=
1627 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1628 ictx->xstorm_st_context.iscsi.flags.flags |=
1629 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1630
1631 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1632 /* TSTORM requires the base address of RQ DB & not PTE */
1633 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1634 req2->rq_page_table_addr_lo & PAGE_MASK;
1635 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1636 req2->rq_page_table_addr_hi;
1637 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1638 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1639 ictx->tstorm_st_context.tcp.flags2 |=
1640 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1641 ictx->tstorm_st_context.tcp.ooo_support_mode =
1642 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1643
1644 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1645
1646 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1647 req2->rq_page_table_addr_lo;
1648 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1649 req2->rq_page_table_addr_hi;
1650 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1651 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1652 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1653 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1654 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1655 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1656 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1657 iscsi->r2tq_info.pgtbl[0];
1658 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1659 iscsi->r2tq_info.pgtbl[1];
1660 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1661 req1->cq_page_table_addr_lo;
1662 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1663 req1->cq_page_table_addr_hi;
1664 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1665 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1666 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1667 ictx->ustorm_st_context.task_pbe_cache_index =
1668 BNX2X_ISCSI_PBL_NOT_CACHED;
1669 ictx->ustorm_st_context.task_pdu_cache_index =
1670 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1671
1672 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1673 if (j == 3) {
1674 if (n >= n_max)
1675 break;
1676 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1677 j = 0;
1678 }
1679 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1680 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1681 req3->qp_first_pte[j].hi;
1682 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1683 req3->qp_first_pte[j].lo;
1684 }
1685
1686 ictx->ustorm_st_context.task_pbl_base.lo =
1687 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1688 ictx->ustorm_st_context.task_pbl_base.hi =
1689 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1690 ictx->ustorm_st_context.tce_phy_addr.lo =
1691 iscsi->task_array_info.pgtbl[0];
1692 ictx->ustorm_st_context.tce_phy_addr.hi =
1693 iscsi->task_array_info.pgtbl[1];
1694 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1695 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1696 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1697 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1698 ISCSI_DEF_MAX_BURST_LEN;
1699 ictx->ustorm_st_context.negotiated_rx |=
1700 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1701 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1702
1703 ictx->cstorm_st_context.hq_pbl_base.lo =
1704 iscsi->hq_info.pgtbl_map & 0xffffffff;
1705 ictx->cstorm_st_context.hq_pbl_base.hi =
1706 (u64) iscsi->hq_info.pgtbl_map >> 32;
1707 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1708 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1709 ictx->cstorm_st_context.task_pbl_base.lo =
1710 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1711 ictx->cstorm_st_context.task_pbl_base.hi =
1712 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1713 /* CSTORM and USTORM initialization is different, CSTORM requires
1714 * CQ DB base & not PTE addr */
1715 ictx->cstorm_st_context.cq_db_base.lo =
1716 req1->cq_page_table_addr_lo & PAGE_MASK;
1717 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1718 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1719 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1720 for (i = 0; i < cp->num_cqs; i++) {
1721 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1722 ISCSI_INITIAL_SN;
1723 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1724 ISCSI_INITIAL_SN;
1725 }
1726
1727 ictx->xstorm_ag_context.cdu_reserved =
1728 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1729 ISCSI_CONNECTION_TYPE);
1730 ictx->ustorm_ag_context.cdu_usage =
1731 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1732 ISCSI_CONNECTION_TYPE);
1733 return 0;
1734
1735 }
1736
1737 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1738 u32 num, int *work)
1739 {
1740 struct iscsi_kwqe_conn_offload1 *req1;
1741 struct iscsi_kwqe_conn_offload2 *req2;
1742 struct cnic_local *cp = dev->cnic_priv;
1743 struct cnic_context *ctx;
1744 struct iscsi_kcqe kcqe;
1745 struct kcqe *cqes[1];
1746 u32 l5_cid;
1747 int ret = 0;
1748
1749 if (num < 2) {
1750 *work = num;
1751 return -EINVAL;
1752 }
1753
1754 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1755 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1756 if ((num - 2) < req2->num_additional_wqes) {
1757 *work = num;
1758 return -EINVAL;
1759 }
1760 *work = 2 + req2->num_additional_wqes;
1761
1762 l5_cid = req1->iscsi_conn_id;
1763 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1764 return -EINVAL;
1765
1766 memset(&kcqe, 0, sizeof(kcqe));
1767 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1768 kcqe.iscsi_conn_id = l5_cid;
1769 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1770
1771 ctx = &cp->ctx_tbl[l5_cid];
1772 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1773 kcqe.completion_status =
1774 ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1775 goto done;
1776 }
1777
1778 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1779 atomic_dec(&cp->iscsi_conn);
1780 goto done;
1781 }
1782 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1783 if (ret) {
1784 atomic_dec(&cp->iscsi_conn);
1785 ret = 0;
1786 goto done;
1787 }
1788 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1789 if (ret < 0) {
1790 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1791 atomic_dec(&cp->iscsi_conn);
1792 goto done;
1793 }
1794
1795 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1796 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
1797
1798 done:
1799 cqes[0] = (struct kcqe *) &kcqe;
1800 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1801 return ret;
1802 }
1803
1804
1805 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1806 {
1807 struct cnic_local *cp = dev->cnic_priv;
1808 struct iscsi_kwqe_conn_update *req =
1809 (struct iscsi_kwqe_conn_update *) kwqe;
1810 void *data;
1811 union l5cm_specific_data l5_data;
1812 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1813 int ret;
1814
1815 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1816 return -EINVAL;
1817
1818 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1819 if (!data)
1820 return -ENOMEM;
1821
1822 memcpy(data, kwqe, sizeof(struct kwqe));
1823
1824 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1825 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1826 return ret;
1827 }
1828
1829 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1830 {
1831 struct cnic_local *cp = dev->cnic_priv;
1832 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1833 union l5cm_specific_data l5_data;
1834 int ret;
1835 u32 hw_cid;
1836
1837 init_waitqueue_head(&ctx->waitq);
1838 ctx->wait_cond = 0;
1839 memset(&l5_data, 0, sizeof(l5_data));
1840 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1841
1842 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1843 hw_cid, NONE_CONNECTION_TYPE, &l5_data);
1844
1845 if (ret == 0)
1846 wait_event(ctx->waitq, ctx->wait_cond);
1847
1848 return ret;
1849 }
1850
1851 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1852 {
1853 struct cnic_local *cp = dev->cnic_priv;
1854 struct iscsi_kwqe_conn_destroy *req =
1855 (struct iscsi_kwqe_conn_destroy *) kwqe;
1856 u32 l5_cid = req->reserved0;
1857 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1858 int ret = 0;
1859 struct iscsi_kcqe kcqe;
1860 struct kcqe *cqes[1];
1861
1862 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
1863 goto skip_cfc_delete;
1864
1865 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
1866 unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
1867
1868 if (delta > (2 * HZ))
1869 delta = 0;
1870
1871 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
1872 queue_delayed_work(cnic_wq, &cp->delete_task, delta);
1873 goto destroy_reply;
1874 }
1875
1876 ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
1877
1878 skip_cfc_delete:
1879 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1880
1881 atomic_dec(&cp->iscsi_conn);
1882 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
1883
1884 destroy_reply:
1885 memset(&kcqe, 0, sizeof(kcqe));
1886 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1887 kcqe.iscsi_conn_id = l5_cid;
1888 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1889 kcqe.iscsi_conn_context_id = req->context_id;
1890
1891 cqes[0] = (struct kcqe *) &kcqe;
1892 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1893
1894 return ret;
1895 }
1896
1897 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1898 struct l4_kwq_connect_req1 *kwqe1,
1899 struct l4_kwq_connect_req3 *kwqe3,
1900 struct l5cm_active_conn_buffer *conn_buf)
1901 {
1902 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1903 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1904 &conn_buf->xstorm_conn_buffer;
1905 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1906 &conn_buf->tstorm_conn_buffer;
1907 struct regpair context_addr;
1908 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1909 struct in6_addr src_ip, dst_ip;
1910 int i;
1911 u32 *addrp;
1912
1913 addrp = (u32 *) &conn_addr->local_ip_addr;
1914 for (i = 0; i < 4; i++, addrp++)
1915 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1916
1917 addrp = (u32 *) &conn_addr->remote_ip_addr;
1918 for (i = 0; i < 4; i++, addrp++)
1919 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1920
1921 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1922
1923 xstorm_buf->context_addr.hi = context_addr.hi;
1924 xstorm_buf->context_addr.lo = context_addr.lo;
1925 xstorm_buf->mss = 0xffff;
1926 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1927 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1928 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1929 xstorm_buf->pseudo_header_checksum =
1930 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1931
1932 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1933 tstorm_buf->params |=
1934 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1935 if (kwqe3->ka_timeout) {
1936 tstorm_buf->ka_enable = 1;
1937 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1938 tstorm_buf->ka_interval = kwqe3->ka_interval;
1939 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1940 }
1941 tstorm_buf->rcv_buf = kwqe3->rcv_buf;
1942 tstorm_buf->snd_buf = kwqe3->snd_buf;
1943 tstorm_buf->max_rt_time = 0xffffffff;
1944 }
1945
1946 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1947 {
1948 struct cnic_local *cp = dev->cnic_priv;
1949 u32 pfid = cp->pfid;
1950 u8 *mac = dev->mac_addr;
1951
1952 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1953 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
1954 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1955 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
1956 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1957 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
1958 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1959 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
1960 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1961 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
1962 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1963 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
1964
1965 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1966 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
1967 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1968 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1969 mac[4]);
1970 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1971 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
1972 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1973 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
1974 mac[2]);
1975 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1976 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
1977 mac[1]);
1978 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1979 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
1980 mac[0]);
1981 }
1982
1983 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
1984 {
1985 struct cnic_local *cp = dev->cnic_priv;
1986 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1987 u16 tstorm_flags = 0;
1988
1989 if (tcp_ts) {
1990 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1991 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1992 }
1993
1994 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1995 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
1996
1997 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1998 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
1999 }
2000
2001 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
2002 u32 num, int *work)
2003 {
2004 struct cnic_local *cp = dev->cnic_priv;
2005 struct l4_kwq_connect_req1 *kwqe1 =
2006 (struct l4_kwq_connect_req1 *) wqes[0];
2007 struct l4_kwq_connect_req3 *kwqe3;
2008 struct l5cm_active_conn_buffer *conn_buf;
2009 struct l5cm_conn_addr_params *conn_addr;
2010 union l5cm_specific_data l5_data;
2011 u32 l5_cid = kwqe1->pg_cid;
2012 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
2013 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2014 int ret;
2015
2016 if (num < 2) {
2017 *work = num;
2018 return -EINVAL;
2019 }
2020
2021 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
2022 *work = 3;
2023 else
2024 *work = 2;
2025
2026 if (num < *work) {
2027 *work = num;
2028 return -EINVAL;
2029 }
2030
2031 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
2032 netdev_err(dev->netdev, "conn_buf size too big\n");
2033 return -ENOMEM;
2034 }
2035 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2036 if (!conn_buf)
2037 return -ENOMEM;
2038
2039 memset(conn_buf, 0, sizeof(*conn_buf));
2040
2041 conn_addr = &conn_buf->conn_addr_buf;
2042 conn_addr->remote_addr_0 = csk->ha[0];
2043 conn_addr->remote_addr_1 = csk->ha[1];
2044 conn_addr->remote_addr_2 = csk->ha[2];
2045 conn_addr->remote_addr_3 = csk->ha[3];
2046 conn_addr->remote_addr_4 = csk->ha[4];
2047 conn_addr->remote_addr_5 = csk->ha[5];
2048
2049 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
2050 struct l4_kwq_connect_req2 *kwqe2 =
2051 (struct l4_kwq_connect_req2 *) wqes[1];
2052
2053 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
2054 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
2055 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
2056
2057 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
2058 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
2059 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
2060 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
2061 }
2062 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
2063
2064 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
2065 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
2066 conn_addr->local_tcp_port = kwqe1->src_port;
2067 conn_addr->remote_tcp_port = kwqe1->dst_port;
2068
2069 conn_addr->pmtu = kwqe3->pmtu;
2070 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
2071
2072 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
2073 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
2074
2075 cnic_bnx2x_set_tcp_timestamp(dev,
2076 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
2077
2078 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2079 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2080 if (!ret)
2081 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2082
2083 return ret;
2084 }
2085
2086 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2087 {
2088 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2089 union l5cm_specific_data l5_data;
2090 int ret;
2091
2092 memset(&l5_data, 0, sizeof(l5_data));
2093 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2094 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2095 return ret;
2096 }
2097
2098 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2099 {
2100 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2101 union l5cm_specific_data l5_data;
2102 int ret;
2103
2104 memset(&l5_data, 0, sizeof(l5_data));
2105 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2106 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2107 return ret;
2108 }
2109 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2110 {
2111 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2112 struct l4_kcq kcqe;
2113 struct kcqe *cqes[1];
2114
2115 memset(&kcqe, 0, sizeof(kcqe));
2116 kcqe.pg_host_opaque = req->host_opaque;
2117 kcqe.pg_cid = req->host_opaque;
2118 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2119 cqes[0] = (struct kcqe *) &kcqe;
2120 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2121 return 0;
2122 }
2123
2124 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2125 {
2126 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2127 struct l4_kcq kcqe;
2128 struct kcqe *cqes[1];
2129
2130 memset(&kcqe, 0, sizeof(kcqe));
2131 kcqe.pg_host_opaque = req->pg_host_opaque;
2132 kcqe.pg_cid = req->pg_cid;
2133 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2134 cqes[0] = (struct kcqe *) &kcqe;
2135 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2136 return 0;
2137 }
2138
2139 static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
2140 {
2141 struct fcoe_kwqe_stat *req;
2142 struct fcoe_stat_ramrod_params *fcoe_stat;
2143 union l5cm_specific_data l5_data;
2144 struct cnic_local *cp = dev->cnic_priv;
2145 int ret;
2146 u32 cid;
2147
2148 req = (struct fcoe_kwqe_stat *) kwqe;
2149 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2150
2151 fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2152 if (!fcoe_stat)
2153 return -ENOMEM;
2154
2155 memset(fcoe_stat, 0, sizeof(*fcoe_stat));
2156 memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
2157
2158 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
2159 FCOE_CONNECTION_TYPE, &l5_data);
2160 return ret;
2161 }
2162
2163 static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
2164 u32 num, int *work)
2165 {
2166 int ret;
2167 struct cnic_local *cp = dev->cnic_priv;
2168 u32 cid;
2169 struct fcoe_init_ramrod_params *fcoe_init;
2170 struct fcoe_kwqe_init1 *req1;
2171 struct fcoe_kwqe_init2 *req2;
2172 struct fcoe_kwqe_init3 *req3;
2173 union l5cm_specific_data l5_data;
2174
2175 if (num < 3) {
2176 *work = num;
2177 return -EINVAL;
2178 }
2179 req1 = (struct fcoe_kwqe_init1 *) wqes[0];
2180 req2 = (struct fcoe_kwqe_init2 *) wqes[1];
2181 req3 = (struct fcoe_kwqe_init3 *) wqes[2];
2182 if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
2183 *work = 1;
2184 return -EINVAL;
2185 }
2186 if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
2187 *work = 2;
2188 return -EINVAL;
2189 }
2190
2191 if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
2192 netdev_err(dev->netdev, "fcoe_init size too big\n");
2193 return -ENOMEM;
2194 }
2195 fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2196 if (!fcoe_init)
2197 return -ENOMEM;
2198
2199 memset(fcoe_init, 0, sizeof(*fcoe_init));
2200 memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
2201 memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
2202 memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
2203 fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
2204 fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
2205 fcoe_init->eq_next_page_addr.lo =
2206 cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
2207 fcoe_init->eq_next_page_addr.hi =
2208 (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
2209
2210 fcoe_init->sb_num = cp->status_blk_num;
2211 fcoe_init->eq_prod = MAX_KCQ_IDX;
2212 fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
2213 cp->kcq2.sw_prod_idx = 0;
2214
2215 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2216 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
2217 FCOE_CONNECTION_TYPE, &l5_data);
2218 *work = 3;
2219 return ret;
2220 }
2221
2222 static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
2223 u32 num, int *work)
2224 {
2225 int ret = 0;
2226 u32 cid = -1, l5_cid;
2227 struct cnic_local *cp = dev->cnic_priv;
2228 struct fcoe_kwqe_conn_offload1 *req1;
2229 struct fcoe_kwqe_conn_offload2 *req2;
2230 struct fcoe_kwqe_conn_offload3 *req3;
2231 struct fcoe_kwqe_conn_offload4 *req4;
2232 struct fcoe_conn_offload_ramrod_params *fcoe_offload;
2233 struct cnic_context *ctx;
2234 struct fcoe_context *fctx;
2235 struct regpair ctx_addr;
2236 union l5cm_specific_data l5_data;
2237 struct fcoe_kcqe kcqe;
2238 struct kcqe *cqes[1];
2239
2240 if (num < 4) {
2241 *work = num;
2242 return -EINVAL;
2243 }
2244 req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
2245 req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
2246 req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
2247 req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
2248
2249 *work = 4;
2250
2251 l5_cid = req1->fcoe_conn_id;
2252 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2253 goto err_reply;
2254
2255 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2256
2257 ctx = &cp->ctx_tbl[l5_cid];
2258 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2259 goto err_reply;
2260
2261 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
2262 if (ret) {
2263 ret = 0;
2264 goto err_reply;
2265 }
2266 cid = ctx->cid;
2267
2268 fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
2269 if (fctx) {
2270 u32 hw_cid = BNX2X_HW_CID(cp, cid);
2271 u32 val;
2272
2273 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
2274 FCOE_CONNECTION_TYPE);
2275 fctx->xstorm_ag_context.cdu_reserved = val;
2276 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
2277 FCOE_CONNECTION_TYPE);
2278 fctx->ustorm_ag_context.cdu_usage = val;
2279 }
2280 if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
2281 netdev_err(dev->netdev, "fcoe_offload size too big\n");
2282 goto err_reply;
2283 }
2284 fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2285 if (!fcoe_offload)
2286 goto err_reply;
2287
2288 memset(fcoe_offload, 0, sizeof(*fcoe_offload));
2289 memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
2290 memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
2291 memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
2292 memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
2293
2294 cid = BNX2X_HW_CID(cp, cid);
2295 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
2296 FCOE_CONNECTION_TYPE, &l5_data);
2297 if (!ret)
2298 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2299
2300 return ret;
2301
2302 err_reply:
2303 if (cid != -1)
2304 cnic_free_bnx2x_conn_resc(dev, l5_cid);
2305
2306 memset(&kcqe, 0, sizeof(kcqe));
2307 kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
2308 kcqe.fcoe_conn_id = req1->fcoe_conn_id;
2309 kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
2310
2311 cqes[0] = (struct kcqe *) &kcqe;
2312 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2313 return ret;
2314 }
2315
2316 static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
2317 {
2318 struct fcoe_kwqe_conn_enable_disable *req;
2319 struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
2320 union l5cm_specific_data l5_data;
2321 int ret;
2322 u32 cid, l5_cid;
2323 struct cnic_local *cp = dev->cnic_priv;
2324
2325 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2326 cid = req->context_id;
2327 l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
2328
2329 if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
2330 netdev_err(dev->netdev, "fcoe_enable size too big\n");
2331 return -ENOMEM;
2332 }
2333 fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2334 if (!fcoe_enable)
2335 return -ENOMEM;
2336
2337 memset(fcoe_enable, 0, sizeof(*fcoe_enable));
2338 memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
2339 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
2340 FCOE_CONNECTION_TYPE, &l5_data);
2341 return ret;
2342 }
2343
2344 static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
2345 {
2346 struct fcoe_kwqe_conn_enable_disable *req;
2347 struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
2348 union l5cm_specific_data l5_data;
2349 int ret;
2350 u32 cid, l5_cid;
2351 struct cnic_local *cp = dev->cnic_priv;
2352
2353 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2354 cid = req->context_id;
2355 l5_cid = req->conn_id;
2356 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2357 return -EINVAL;
2358
2359 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2360
2361 if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
2362 netdev_err(dev->netdev, "fcoe_disable size too big\n");
2363 return -ENOMEM;
2364 }
2365 fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2366 if (!fcoe_disable)
2367 return -ENOMEM;
2368
2369 memset(fcoe_disable, 0, sizeof(*fcoe_disable));
2370 memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
2371 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
2372 FCOE_CONNECTION_TYPE, &l5_data);
2373 return ret;
2374 }
2375
2376 static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2377 {
2378 struct fcoe_kwqe_conn_destroy *req;
2379 union l5cm_specific_data l5_data;
2380 int ret;
2381 u32 cid, l5_cid;
2382 struct cnic_local *cp = dev->cnic_priv;
2383 struct cnic_context *ctx;
2384 struct fcoe_kcqe kcqe;
2385 struct kcqe *cqes[1];
2386
2387 req = (struct fcoe_kwqe_conn_destroy *) kwqe;
2388 cid = req->context_id;
2389 l5_cid = req->conn_id;
2390 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2391 return -EINVAL;
2392
2393 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2394
2395 ctx = &cp->ctx_tbl[l5_cid];
2396
2397 init_waitqueue_head(&ctx->waitq);
2398 ctx->wait_cond = 0;
2399
2400 memset(&l5_data, 0, sizeof(l5_data));
2401 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
2402 FCOE_CONNECTION_TYPE, &l5_data);
2403 if (ret == 0) {
2404 wait_event(ctx->waitq, ctx->wait_cond);
2405 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2406 queue_delayed_work(cnic_wq, &cp->delete_task,
2407 msecs_to_jiffies(2000));
2408 }
2409
2410 memset(&kcqe, 0, sizeof(kcqe));
2411 kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
2412 kcqe.fcoe_conn_id = req->conn_id;
2413 kcqe.fcoe_conn_context_id = cid;
2414
2415 cqes[0] = (struct kcqe *) &kcqe;
2416 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2417 return ret;
2418 }
2419
2420 static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2421 {
2422 struct fcoe_kwqe_destroy *req;
2423 union l5cm_specific_data l5_data;
2424 struct cnic_local *cp = dev->cnic_priv;
2425 int ret;
2426 u32 cid;
2427
2428 req = (struct fcoe_kwqe_destroy *) kwqe;
2429 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2430
2431 memset(&l5_data, 0, sizeof(l5_data));
2432 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
2433 FCOE_CONNECTION_TYPE, &l5_data);
2434 return ret;
2435 }
2436
2437 static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
2438 struct kwqe *wqes[], u32 num_wqes)
2439 {
2440 int i, work, ret;
2441 u32 opcode;
2442 struct kwqe *kwqe;
2443
2444 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2445 return -EAGAIN; /* bnx2 is down */
2446
2447 for (i = 0; i < num_wqes; ) {
2448 kwqe = wqes[i];
2449 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2450 work = 1;
2451
2452 switch (opcode) {
2453 case ISCSI_KWQE_OPCODE_INIT1:
2454 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2455 break;
2456 case ISCSI_KWQE_OPCODE_INIT2:
2457 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2458 break;
2459 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2460 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2461 num_wqes - i, &work);
2462 break;
2463 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2464 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2465 break;
2466 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2467 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2468 break;
2469 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2470 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2471 &work);
2472 break;
2473 case L4_KWQE_OPCODE_VALUE_CLOSE:
2474 ret = cnic_bnx2x_close(dev, kwqe);
2475 break;
2476 case L4_KWQE_OPCODE_VALUE_RESET:
2477 ret = cnic_bnx2x_reset(dev, kwqe);
2478 break;
2479 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2480 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2481 break;
2482 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2483 ret = cnic_bnx2x_update_pg(dev, kwqe);
2484 break;
2485 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2486 ret = 0;
2487 break;
2488 default:
2489 ret = 0;
2490 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2491 opcode);
2492 break;
2493 }
2494 if (ret < 0)
2495 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2496 opcode);
2497 i += work;
2498 }
2499 return 0;
2500 }
2501
2502 static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
2503 struct kwqe *wqes[], u32 num_wqes)
2504 {
2505 struct cnic_local *cp = dev->cnic_priv;
2506 int i, work, ret;
2507 u32 opcode;
2508 struct kwqe *kwqe;
2509
2510 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2511 return -EAGAIN; /* bnx2 is down */
2512
2513 if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
2514 return -EINVAL;
2515
2516 for (i = 0; i < num_wqes; ) {
2517 kwqe = wqes[i];
2518 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2519 work = 1;
2520
2521 switch (opcode) {
2522 case FCOE_KWQE_OPCODE_INIT1:
2523 ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
2524 num_wqes - i, &work);
2525 break;
2526 case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
2527 ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
2528 num_wqes - i, &work);
2529 break;
2530 case FCOE_KWQE_OPCODE_ENABLE_CONN:
2531 ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
2532 break;
2533 case FCOE_KWQE_OPCODE_DISABLE_CONN:
2534 ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
2535 break;
2536 case FCOE_KWQE_OPCODE_DESTROY_CONN:
2537 ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
2538 break;
2539 case FCOE_KWQE_OPCODE_DESTROY:
2540 ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
2541 break;
2542 case FCOE_KWQE_OPCODE_STAT:
2543 ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
2544 break;
2545 default:
2546 ret = 0;
2547 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2548 opcode);
2549 break;
2550 }
2551 if (ret < 0)
2552 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2553 opcode);
2554 i += work;
2555 }
2556 return 0;
2557 }
2558
2559 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2560 u32 num_wqes)
2561 {
2562 int ret = -EINVAL;
2563 u32 layer_code;
2564
2565 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2566 return -EAGAIN; /* bnx2x is down */
2567
2568 if (!num_wqes)
2569 return 0;
2570
2571 layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
2572 switch (layer_code) {
2573 case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
2574 case KWQE_FLAGS_LAYER_MASK_L4:
2575 case KWQE_FLAGS_LAYER_MASK_L2:
2576 ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
2577 break;
2578
2579 case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
2580 ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
2581 break;
2582 }
2583 return ret;
2584 }
2585
2586 static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
2587 {
2588 if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
2589 return KCQE_FLAGS_LAYER_MASK_L4;
2590
2591 return opflag & KCQE_FLAGS_LAYER_MASK;
2592 }
2593
2594 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2595 {
2596 struct cnic_local *cp = dev->cnic_priv;
2597 int i, j, comp = 0;
2598
2599 i = 0;
2600 j = 1;
2601 while (num_cqes) {
2602 struct cnic_ulp_ops *ulp_ops;
2603 int ulp_type;
2604 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2605 u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
2606
2607 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2608 comp++;
2609
2610 while (j < num_cqes) {
2611 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2612
2613 if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
2614 break;
2615
2616 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2617 comp++;
2618 j++;
2619 }
2620
2621 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2622 ulp_type = CNIC_ULP_RDMA;
2623 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2624 ulp_type = CNIC_ULP_ISCSI;
2625 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
2626 ulp_type = CNIC_ULP_FCOE;
2627 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2628 ulp_type = CNIC_ULP_L4;
2629 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2630 goto end;
2631 else {
2632 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2633 kcqe_op_flag);
2634 goto end;
2635 }
2636
2637 rcu_read_lock();
2638 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2639 if (likely(ulp_ops)) {
2640 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2641 cp->completed_kcq + i, j);
2642 }
2643 rcu_read_unlock();
2644 end:
2645 num_cqes -= j;
2646 i += j;
2647 j = 1;
2648 }
2649 if (unlikely(comp))
2650 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2651 }
2652
2653 static u16 cnic_bnx2_next_idx(u16 idx)
2654 {
2655 return idx + 1;
2656 }
2657
2658 static u16 cnic_bnx2_hw_idx(u16 idx)
2659 {
2660 return idx;
2661 }
2662
2663 static u16 cnic_bnx2x_next_idx(u16 idx)
2664 {
2665 idx++;
2666 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2667 idx++;
2668
2669 return idx;
2670 }
2671
2672 static u16 cnic_bnx2x_hw_idx(u16 idx)
2673 {
2674 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
2675 idx++;
2676 return idx;
2677 }
2678
2679 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2680 {
2681 struct cnic_local *cp = dev->cnic_priv;
2682 u16 i, ri, hw_prod, last;
2683 struct kcqe *kcqe;
2684 int kcqe_cnt = 0, last_cnt = 0;
2685
2686 i = ri = last = info->sw_prod_idx;
2687 ri &= MAX_KCQ_IDX;
2688 hw_prod = *info->hw_prod_idx_ptr;
2689 hw_prod = cp->hw_idx(hw_prod);
2690
2691 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2692 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2693 cp->completed_kcq[kcqe_cnt++] = kcqe;
2694 i = cp->next_idx(i);
2695 ri = i & MAX_KCQ_IDX;
2696 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2697 last_cnt = kcqe_cnt;
2698 last = i;
2699 }
2700 }
2701
2702 info->sw_prod_idx = last;
2703 return last_cnt;
2704 }
2705
2706 static int cnic_l2_completion(struct cnic_local *cp)
2707 {
2708 u16 hw_cons, sw_cons;
2709 struct cnic_uio_dev *udev = cp->udev;
2710 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2711 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
2712 u32 cmd;
2713 int comp = 0;
2714
2715 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2716 return 0;
2717
2718 hw_cons = *cp->rx_cons_ptr;
2719 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2720 hw_cons++;
2721
2722 sw_cons = cp->rx_cons;
2723 while (sw_cons != hw_cons) {
2724 u8 cqe_fp_flags;
2725
2726 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2727 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2728 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2729 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2730 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2731 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2732 cmd == RAMROD_CMD_ID_ETH_HALT)
2733 comp++;
2734 }
2735 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2736 }
2737 return comp;
2738 }
2739
2740 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2741 {
2742 u16 rx_cons, tx_cons;
2743 int comp = 0;
2744
2745 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2746 return;
2747
2748 rx_cons = *cp->rx_cons_ptr;
2749 tx_cons = *cp->tx_cons_ptr;
2750 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2751 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2752 comp = cnic_l2_completion(cp);
2753
2754 cp->tx_cons = tx_cons;
2755 cp->rx_cons = rx_cons;
2756
2757 if (cp->udev)
2758 uio_event_notify(&cp->udev->cnic_uinfo);
2759 }
2760 if (comp)
2761 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2762 }
2763
2764 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2765 {
2766 struct cnic_local *cp = dev->cnic_priv;
2767 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2768 int kcqe_cnt;
2769
2770 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2771
2772 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2773
2774 service_kcqes(dev, kcqe_cnt);
2775
2776 /* Tell compiler that status_blk fields can change. */
2777 barrier();
2778 if (status_idx != *cp->kcq1.status_idx_ptr) {
2779 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2780 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2781 } else
2782 break;
2783 }
2784
2785 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2786
2787 cnic_chk_pkt_rings(cp);
2788
2789 return status_idx;
2790 }
2791
2792 static int cnic_service_bnx2(void *data, void *status_blk)
2793 {
2794 struct cnic_dev *dev = data;
2795
2796 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2797 struct status_block *sblk = status_blk;
2798
2799 return sblk->status_idx;
2800 }
2801
2802 return cnic_service_bnx2_queues(dev);
2803 }
2804
2805 static void cnic_service_bnx2_msix(unsigned long data)
2806 {
2807 struct cnic_dev *dev = (struct cnic_dev *) data;
2808 struct cnic_local *cp = dev->cnic_priv;
2809
2810 cp->last_status_idx = cnic_service_bnx2_queues(dev);
2811
2812 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2813 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2814 }
2815
2816 static void cnic_doirq(struct cnic_dev *dev)
2817 {
2818 struct cnic_local *cp = dev->cnic_priv;
2819
2820 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2821 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
2822
2823 prefetch(cp->status_blk.gen);
2824 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2825
2826 tasklet_schedule(&cp->cnic_irq_task);
2827 }
2828 }
2829
2830 static irqreturn_t cnic_irq(int irq, void *dev_instance)
2831 {
2832 struct cnic_dev *dev = dev_instance;
2833 struct cnic_local *cp = dev->cnic_priv;
2834
2835 if (cp->ack_int)
2836 cp->ack_int(dev);
2837
2838 cnic_doirq(dev);
2839
2840 return IRQ_HANDLED;
2841 }
2842
2843 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2844 u16 index, u8 op, u8 update)
2845 {
2846 struct cnic_local *cp = dev->cnic_priv;
2847 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2848 COMMAND_REG_INT_ACK);
2849 struct igu_ack_register igu_ack;
2850
2851 igu_ack.status_block_index = index;
2852 igu_ack.sb_id_and_flags =
2853 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2854 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2855 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2856 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2857
2858 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2859 }
2860
2861 static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
2862 u16 index, u8 op, u8 update)
2863 {
2864 struct igu_regular cmd_data;
2865 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
2866
2867 cmd_data.sb_id_and_flags =
2868 (index << IGU_REGULAR_SB_INDEX_SHIFT) |
2869 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2870 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2871 (op << IGU_REGULAR_ENABLE_INT_SHIFT);
2872
2873
2874 CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
2875 }
2876
2877 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2878 {
2879 struct cnic_local *cp = dev->cnic_priv;
2880
2881 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
2882 IGU_INT_DISABLE, 0);
2883 }
2884
2885 static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
2886 {
2887 struct cnic_local *cp = dev->cnic_priv;
2888
2889 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
2890 IGU_INT_DISABLE, 0);
2891 }
2892
2893 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
2894 {
2895 u32 last_status = *info->status_idx_ptr;
2896 int kcqe_cnt;
2897
2898 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
2899
2900 service_kcqes(dev, kcqe_cnt);
2901
2902 /* Tell compiler that sblk fields can change. */
2903 barrier();
2904 if (last_status == *info->status_idx_ptr)
2905 break;
2906
2907 last_status = *info->status_idx_ptr;
2908 }
2909 return last_status;
2910 }
2911
2912 static void cnic_service_bnx2x_bh(unsigned long data)
2913 {
2914 struct cnic_dev *dev = (struct cnic_dev *) data;
2915 struct cnic_local *cp = dev->cnic_priv;
2916 u32 status_idx;
2917
2918 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2919 return;
2920
2921 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
2922
2923 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
2924
2925 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
2926 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
2927
2928 CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
2929 MAX_KCQ_IDX);
2930
2931 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
2932 status_idx, IGU_INT_ENABLE, 1);
2933 } else {
2934 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
2935 status_idx, IGU_INT_ENABLE, 1);
2936 }
2937 }
2938
2939 static int cnic_service_bnx2x(void *data, void *status_blk)
2940 {
2941 struct cnic_dev *dev = data;
2942 struct cnic_local *cp = dev->cnic_priv;
2943
2944 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
2945 cnic_doirq(dev);
2946
2947 cnic_chk_pkt_rings(cp);
2948
2949 return 0;
2950 }
2951
2952 static void cnic_ulp_stop(struct cnic_dev *dev)
2953 {
2954 struct cnic_local *cp = dev->cnic_priv;
2955 int if_type;
2956
2957 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2958
2959 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2960 struct cnic_ulp_ops *ulp_ops;
2961
2962 mutex_lock(&cnic_lock);
2963 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
2964 lockdep_is_held(&cnic_lock));
2965 if (!ulp_ops) {
2966 mutex_unlock(&cnic_lock);
2967 continue;
2968 }
2969 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2970 mutex_unlock(&cnic_lock);
2971
2972 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2973 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
2974
2975 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2976 }
2977 }
2978
2979 static void cnic_ulp_start(struct cnic_dev *dev)
2980 {
2981 struct cnic_local *cp = dev->cnic_priv;
2982 int if_type;
2983
2984 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
2985 struct cnic_ulp_ops *ulp_ops;
2986
2987 mutex_lock(&cnic_lock);
2988 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
2989 lockdep_is_held(&cnic_lock));
2990 if (!ulp_ops || !ulp_ops->cnic_start) {
2991 mutex_unlock(&cnic_lock);
2992 continue;
2993 }
2994 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2995 mutex_unlock(&cnic_lock);
2996
2997 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2998 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
2999
3000 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3001 }
3002 }
3003
3004 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
3005 {
3006 struct cnic_dev *dev = data;
3007
3008 switch (info->cmd) {
3009 case CNIC_CTL_STOP_CMD:
3010 cnic_hold(dev);
3011
3012 cnic_ulp_stop(dev);
3013 cnic_stop_hw(dev);
3014
3015 cnic_put(dev);
3016 break;
3017 case CNIC_CTL_START_CMD:
3018 cnic_hold(dev);
3019
3020 if (!cnic_start_hw(dev))
3021 cnic_ulp_start(dev);
3022
3023 cnic_put(dev);
3024 break;
3025 case CNIC_CTL_COMPLETION_CMD: {
3026 u32 cid = BNX2X_SW_CID(info->data.comp.cid);
3027 u32 l5_cid;
3028 struct cnic_local *cp = dev->cnic_priv;
3029
3030 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
3031 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3032
3033 ctx->wait_cond = 1;
3034 wake_up(&ctx->waitq);
3035 }
3036 break;
3037 }
3038 default:
3039 return -EINVAL;
3040 }
3041 return 0;
3042 }
3043
3044 static void cnic_ulp_init(struct cnic_dev *dev)
3045 {
3046 int i;
3047 struct cnic_local *cp = dev->cnic_priv;
3048
3049 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3050 struct cnic_ulp_ops *ulp_ops;
3051
3052 mutex_lock(&cnic_lock);
3053 ulp_ops = cnic_ulp_tbl_prot(i);
3054 if (!ulp_ops || !ulp_ops->cnic_init) {
3055 mutex_unlock(&cnic_lock);
3056 continue;
3057 }
3058 ulp_get(ulp_ops);
3059 mutex_unlock(&cnic_lock);
3060
3061 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3062 ulp_ops->cnic_init(dev);
3063
3064 ulp_put(ulp_ops);
3065 }
3066 }
3067
3068 static void cnic_ulp_exit(struct cnic_dev *dev)
3069 {
3070 int i;
3071 struct cnic_local *cp = dev->cnic_priv;
3072
3073 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3074 struct cnic_ulp_ops *ulp_ops;
3075
3076 mutex_lock(&cnic_lock);
3077 ulp_ops = cnic_ulp_tbl_prot(i);
3078 if (!ulp_ops || !ulp_ops->cnic_exit) {
3079 mutex_unlock(&cnic_lock);
3080 continue;
3081 }
3082 ulp_get(ulp_ops);
3083 mutex_unlock(&cnic_lock);
3084
3085 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3086 ulp_ops->cnic_exit(dev);
3087
3088 ulp_put(ulp_ops);
3089 }
3090 }
3091
3092 static int cnic_cm_offload_pg(struct cnic_sock *csk)
3093 {
3094 struct cnic_dev *dev = csk->dev;
3095 struct l4_kwq_offload_pg *l4kwqe;
3096 struct kwqe *wqes[1];
3097
3098 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
3099 memset(l4kwqe, 0, sizeof(*l4kwqe));
3100 wqes[0] = (struct kwqe *) l4kwqe;
3101
3102 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
3103 l4kwqe->flags =
3104 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
3105 l4kwqe->l2hdr_nbytes = ETH_HLEN;
3106
3107 l4kwqe->da0 = csk->ha[0];
3108 l4kwqe->da1 = csk->ha[1];
3109 l4kwqe->da2 = csk->ha[2];
3110 l4kwqe->da3 = csk->ha[3];
3111 l4kwqe->da4 = csk->ha[4];
3112 l4kwqe->da5 = csk->ha[5];
3113
3114 l4kwqe->sa0 = dev->mac_addr[0];
3115 l4kwqe->sa1 = dev->mac_addr[1];
3116 l4kwqe->sa2 = dev->mac_addr[2];
3117 l4kwqe->sa3 = dev->mac_addr[3];
3118 l4kwqe->sa4 = dev->mac_addr[4];
3119 l4kwqe->sa5 = dev->mac_addr[5];
3120
3121 l4kwqe->etype = ETH_P_IP;
3122 l4kwqe->ipid_start = DEF_IPID_START;
3123 l4kwqe->host_opaque = csk->l5_cid;
3124
3125 if (csk->vlan_id) {
3126 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
3127 l4kwqe->vlan_tag = csk->vlan_id;
3128 l4kwqe->l2hdr_nbytes += 4;
3129 }
3130
3131 return dev->submit_kwqes(dev, wqes, 1);
3132 }
3133
3134 static int cnic_cm_update_pg(struct cnic_sock *csk)
3135 {
3136 struct cnic_dev *dev = csk->dev;
3137 struct l4_kwq_update_pg *l4kwqe;
3138 struct kwqe *wqes[1];
3139
3140 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
3141 memset(l4kwqe, 0, sizeof(*l4kwqe));
3142 wqes[0] = (struct kwqe *) l4kwqe;
3143
3144 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
3145 l4kwqe->flags =
3146 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
3147 l4kwqe->pg_cid = csk->pg_cid;
3148
3149 l4kwqe->da0 = csk->ha[0];
3150 l4kwqe->da1 = csk->ha[1];
3151 l4kwqe->da2 = csk->ha[2];
3152 l4kwqe->da3 = csk->ha[3];
3153 l4kwqe->da4 = csk->ha[4];
3154 l4kwqe->da5 = csk->ha[5];
3155
3156 l4kwqe->pg_host_opaque = csk->l5_cid;
3157 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
3158
3159 return dev->submit_kwqes(dev, wqes, 1);
3160 }
3161
3162 static int cnic_cm_upload_pg(struct cnic_sock *csk)
3163 {
3164 struct cnic_dev *dev = csk->dev;
3165 struct l4_kwq_upload *l4kwqe;
3166 struct kwqe *wqes[1];
3167
3168 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
3169 memset(l4kwqe, 0, sizeof(*l4kwqe));
3170 wqes[0] = (struct kwqe *) l4kwqe;
3171
3172 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
3173 l4kwqe->flags =
3174 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
3175 l4kwqe->cid = csk->pg_cid;
3176
3177 return dev->submit_kwqes(dev, wqes, 1);
3178 }
3179
3180 static int cnic_cm_conn_req(struct cnic_sock *csk)
3181 {
3182 struct cnic_dev *dev = csk->dev;
3183 struct l4_kwq_connect_req1 *l4kwqe1;
3184 struct l4_kwq_connect_req2 *l4kwqe2;
3185 struct l4_kwq_connect_req3 *l4kwqe3;
3186 struct kwqe *wqes[3];
3187 u8 tcp_flags = 0;
3188 int num_wqes = 2;
3189
3190 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
3191 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
3192 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
3193 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
3194 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
3195 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
3196
3197 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
3198 l4kwqe3->flags =
3199 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
3200 l4kwqe3->ka_timeout = csk->ka_timeout;
3201 l4kwqe3->ka_interval = csk->ka_interval;
3202 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
3203 l4kwqe3->tos = csk->tos;
3204 l4kwqe3->ttl = csk->ttl;
3205 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
3206 l4kwqe3->pmtu = csk->mtu;
3207 l4kwqe3->rcv_buf = csk->rcv_buf;
3208 l4kwqe3->snd_buf = csk->snd_buf;
3209 l4kwqe3->seed = csk->seed;
3210
3211 wqes[0] = (struct kwqe *) l4kwqe1;
3212 if (test_bit(SK_F_IPV6, &csk->flags)) {
3213 wqes[1] = (struct kwqe *) l4kwqe2;
3214 wqes[2] = (struct kwqe *) l4kwqe3;
3215 num_wqes = 3;
3216
3217 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
3218 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
3219 l4kwqe2->flags =
3220 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
3221 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
3222 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
3223 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
3224 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
3225 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
3226 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
3227 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
3228 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
3229 sizeof(struct tcphdr);
3230 } else {
3231 wqes[1] = (struct kwqe *) l4kwqe3;
3232 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
3233 sizeof(struct tcphdr);
3234 }
3235
3236 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
3237 l4kwqe1->flags =
3238 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
3239 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
3240 l4kwqe1->cid = csk->cid;
3241 l4kwqe1->pg_cid = csk->pg_cid;
3242 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
3243 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
3244 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
3245 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
3246 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
3247 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
3248 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
3249 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
3250 if (csk->tcp_flags & SK_TCP_NAGLE)
3251 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
3252 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
3253 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
3254 if (csk->tcp_flags & SK_TCP_SACK)
3255 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
3256 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
3257 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
3258
3259 l4kwqe1->tcp_flags = tcp_flags;
3260
3261 return dev->submit_kwqes(dev, wqes, num_wqes);
3262 }
3263
3264 static int cnic_cm_close_req(struct cnic_sock *csk)
3265 {
3266 struct cnic_dev *dev = csk->dev;
3267 struct l4_kwq_close_req *l4kwqe;
3268 struct kwqe *wqes[1];
3269
3270 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
3271 memset(l4kwqe, 0, sizeof(*l4kwqe));
3272 wqes[0] = (struct kwqe *) l4kwqe;
3273
3274 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
3275 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
3276 l4kwqe->cid = csk->cid;
3277
3278 return dev->submit_kwqes(dev, wqes, 1);
3279 }
3280
3281 static int cnic_cm_abort_req(struct cnic_sock *csk)
3282 {
3283 struct cnic_dev *dev = csk->dev;
3284 struct l4_kwq_reset_req *l4kwqe;
3285 struct kwqe *wqes[1];
3286
3287 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
3288 memset(l4kwqe, 0, sizeof(*l4kwqe));
3289 wqes[0] = (struct kwqe *) l4kwqe;
3290
3291 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
3292 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
3293 l4kwqe->cid = csk->cid;
3294
3295 return dev->submit_kwqes(dev, wqes, 1);
3296 }
3297
3298 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
3299 u32 l5_cid, struct cnic_sock **csk, void *context)
3300 {
3301 struct cnic_local *cp = dev->cnic_priv;
3302 struct cnic_sock *csk1;
3303
3304 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3305 return -EINVAL;
3306
3307 if (cp->ctx_tbl) {
3308 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3309
3310 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3311 return -EAGAIN;
3312 }
3313
3314 csk1 = &cp->csk_tbl[l5_cid];
3315 if (atomic_read(&csk1->ref_count))
3316 return -EAGAIN;
3317
3318 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
3319 return -EBUSY;
3320
3321 csk1->dev = dev;
3322 csk1->cid = cid;
3323 csk1->l5_cid = l5_cid;
3324 csk1->ulp_type = ulp_type;
3325 csk1->context = context;
3326
3327 csk1->ka_timeout = DEF_KA_TIMEOUT;
3328 csk1->ka_interval = DEF_KA_INTERVAL;
3329 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
3330 csk1->tos = DEF_TOS;
3331 csk1->ttl = DEF_TTL;
3332 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
3333 csk1->rcv_buf = DEF_RCV_BUF;
3334 csk1->snd_buf = DEF_SND_BUF;
3335 csk1->seed = DEF_SEED;
3336
3337 *csk = csk1;
3338 return 0;
3339 }
3340
3341 static void cnic_cm_cleanup(struct cnic_sock *csk)
3342 {
3343 if (csk->src_port) {
3344 struct cnic_dev *dev = csk->dev;
3345 struct cnic_local *cp = dev->cnic_priv;
3346
3347 cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
3348 csk->src_port = 0;
3349 }
3350 }
3351
3352 static void cnic_close_conn(struct cnic_sock *csk)
3353 {
3354 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
3355 cnic_cm_upload_pg(csk);
3356 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3357 }
3358 cnic_cm_cleanup(csk);
3359 }
3360
3361 static int cnic_cm_destroy(struct cnic_sock *csk)
3362 {
3363 if (!cnic_in_use(csk))
3364 return -EINVAL;
3365
3366 csk_hold(csk);
3367 clear_bit(SK_F_INUSE, &csk->flags);
3368 smp_mb__after_clear_bit();
3369 while (atomic_read(&csk->ref_count) != 1)
3370 msleep(1);
3371 cnic_cm_cleanup(csk);
3372
3373 csk->flags = 0;
3374 csk_put(csk);
3375 return 0;
3376 }
3377
3378 static inline u16 cnic_get_vlan(struct net_device *dev,
3379 struct net_device **vlan_dev)
3380 {
3381 if (dev->priv_flags & IFF_802_1Q_VLAN) {
3382 *vlan_dev = vlan_dev_real_dev(dev);
3383 return vlan_dev_vlan_id(dev);
3384 }
3385 *vlan_dev = dev;
3386 return 0;
3387 }
3388
3389 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
3390 struct dst_entry **dst)
3391 {
3392 #if defined(CONFIG_INET)
3393 struct flowi fl;
3394 int err;
3395 struct rtable *rt;
3396
3397 memset(&fl, 0, sizeof(fl));
3398 fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
3399
3400 err = ip_route_output_key(&init_net, &rt, &fl);
3401 if (!err)
3402 *dst = &rt->dst;
3403 return err;
3404 #else
3405 return -ENETUNREACH;
3406 #endif
3407 }
3408
3409 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
3410 struct dst_entry **dst)
3411 {
3412 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
3413 struct flowi fl;
3414
3415 memset(&fl, 0, sizeof(fl));
3416 ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
3417 if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
3418 fl.oif = dst_addr->sin6_scope_id;
3419
3420 *dst = ip6_route_output(&init_net, NULL, &fl);
3421 if (*dst)
3422 return 0;
3423 #endif
3424
3425 return -ENETUNREACH;
3426 }
3427
3428 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
3429 int ulp_type)
3430 {
3431 struct cnic_dev *dev = NULL;
3432 struct dst_entry *dst;
3433 struct net_device *netdev = NULL;
3434 int err = -ENETUNREACH;
3435
3436 if (dst_addr->sin_family == AF_INET)
3437 err = cnic_get_v4_route(dst_addr, &dst);
3438 else if (dst_addr->sin_family == AF_INET6) {
3439 struct sockaddr_in6 *dst_addr6 =
3440 (struct sockaddr_in6 *) dst_addr;
3441
3442 err = cnic_get_v6_route(dst_addr6, &dst);
3443 } else
3444 return NULL;
3445
3446 if (err)
3447 return NULL;
3448
3449 if (!dst->dev)
3450 goto done;
3451
3452 cnic_get_vlan(dst->dev, &netdev);
3453
3454 dev = cnic_from_netdev(netdev);
3455
3456 done:
3457 dst_release(dst);
3458 if (dev)
3459 cnic_put(dev);
3460 return dev;
3461 }
3462
3463 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3464 {
3465 struct cnic_dev *dev = csk->dev;
3466 struct cnic_local *cp = dev->cnic_priv;
3467
3468 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
3469 }
3470
3471 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3472 {
3473 struct cnic_dev *dev = csk->dev;
3474 struct cnic_local *cp = dev->cnic_priv;
3475 int is_v6, rc = 0;
3476 struct dst_entry *dst = NULL;
3477 struct net_device *realdev;
3478 __be16 local_port;
3479 u32 port_id;
3480
3481 if (saddr->local.v6.sin6_family == AF_INET6 &&
3482 saddr->remote.v6.sin6_family == AF_INET6)
3483 is_v6 = 1;
3484 else if (saddr->local.v4.sin_family == AF_INET &&
3485 saddr->remote.v4.sin_family == AF_INET)
3486 is_v6 = 0;
3487 else
3488 return -EINVAL;
3489
3490 clear_bit(SK_F_IPV6, &csk->flags);
3491
3492 if (is_v6) {
3493 set_bit(SK_F_IPV6, &csk->flags);
3494 cnic_get_v6_route(&saddr->remote.v6, &dst);
3495
3496 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
3497 sizeof(struct in6_addr));
3498 csk->dst_port = saddr->remote.v6.sin6_port;
3499 local_port = saddr->local.v6.sin6_port;
3500
3501 } else {
3502 cnic_get_v4_route(&saddr->remote.v4, &dst);
3503
3504 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
3505 csk->dst_port = saddr->remote.v4.sin_port;
3506 local_port = saddr->local.v4.sin_port;
3507 }
3508
3509 csk->vlan_id = 0;
3510 csk->mtu = dev->netdev->mtu;
3511 if (dst && dst->dev) {
3512 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3513 if (realdev == dev->netdev) {
3514 csk->vlan_id = vlan;
3515 csk->mtu = dst_mtu(dst);
3516 }
3517 }
3518
3519 port_id = be16_to_cpu(local_port);
3520 if (port_id >= CNIC_LOCAL_PORT_MIN &&
3521 port_id < CNIC_LOCAL_PORT_MAX) {
3522 if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
3523 port_id = 0;
3524 } else
3525 port_id = 0;
3526
3527 if (!port_id) {
3528 port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
3529 if (port_id == -1) {
3530 rc = -ENOMEM;
3531 goto err_out;
3532 }
3533 local_port = cpu_to_be16(port_id);
3534 }
3535 csk->src_port = local_port;
3536
3537 err_out:
3538 dst_release(dst);
3539 return rc;
3540 }
3541
3542 static void cnic_init_csk_state(struct cnic_sock *csk)
3543 {
3544 csk->state = 0;
3545 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3546 clear_bit(SK_F_CLOSING, &csk->flags);
3547 }
3548
3549 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3550 {
3551 int err = 0;
3552
3553 if (!cnic_in_use(csk))
3554 return -EINVAL;
3555
3556 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3557 return -EINVAL;
3558
3559 cnic_init_csk_state(csk);
3560
3561 err = cnic_get_route(csk, saddr);
3562 if (err)
3563 goto err_out;
3564
3565 err = cnic_resolve_addr(csk, saddr);
3566 if (!err)
3567 return 0;
3568
3569 err_out:
3570 clear_bit(SK_F_CONNECT_START, &csk->flags);
3571 return err;
3572 }
3573
3574 static int cnic_cm_abort(struct cnic_sock *csk)
3575 {
3576 struct cnic_local *cp = csk->dev->cnic_priv;
3577 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3578
3579 if (!cnic_in_use(csk))
3580 return -EINVAL;
3581
3582 if (cnic_abort_prep(csk))
3583 return cnic_cm_abort_req(csk);
3584
3585 /* Getting here means that we haven't started connect, or
3586 * connect was not successful.
3587 */
3588
3589 cp->close_conn(csk, opcode);
3590 if (csk->state != opcode)
3591 return -EALREADY;
3592
3593 return 0;
3594 }
3595
3596 static int cnic_cm_close(struct cnic_sock *csk)
3597 {
3598 if (!cnic_in_use(csk))
3599 return -EINVAL;
3600
3601 if (cnic_close_prep(csk)) {
3602 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3603 return cnic_cm_close_req(csk);
3604 } else {
3605 return -EALREADY;
3606 }
3607 return 0;
3608 }
3609
3610 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3611 u8 opcode)
3612 {
3613 struct cnic_ulp_ops *ulp_ops;
3614 int ulp_type = csk->ulp_type;
3615
3616 rcu_read_lock();
3617 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3618 if (ulp_ops) {
3619 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3620 ulp_ops->cm_connect_complete(csk);
3621 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3622 ulp_ops->cm_close_complete(csk);
3623 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3624 ulp_ops->cm_remote_abort(csk);
3625 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3626 ulp_ops->cm_abort_complete(csk);
3627 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3628 ulp_ops->cm_remote_close(csk);
3629 }
3630 rcu_read_unlock();
3631 }
3632
3633 static int cnic_cm_set_pg(struct cnic_sock *csk)
3634 {
3635 if (cnic_offld_prep(csk)) {
3636 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3637 cnic_cm_update_pg(csk);
3638 else
3639 cnic_cm_offload_pg(csk);
3640 }
3641 return 0;
3642 }
3643
3644 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3645 {
3646 struct cnic_local *cp = dev->cnic_priv;
3647 u32 l5_cid = kcqe->pg_host_opaque;
3648 u8 opcode = kcqe->op_code;
3649 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3650
3651 csk_hold(csk);
3652 if (!cnic_in_use(csk))
3653 goto done;
3654
3655 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3656 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3657 goto done;
3658 }
3659 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3660 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3661 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3662 cnic_cm_upcall(cp, csk,
3663 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3664 goto done;
3665 }
3666
3667 csk->pg_cid = kcqe->pg_cid;
3668 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3669 cnic_cm_conn_req(csk);
3670
3671 done:
3672 csk_put(csk);
3673 }
3674
3675 static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
3676 {
3677 struct cnic_local *cp = dev->cnic_priv;
3678 struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
3679 u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
3680 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3681
3682 ctx->timestamp = jiffies;
3683 ctx->wait_cond = 1;
3684 wake_up(&ctx->waitq);
3685 }
3686
3687 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3688 {
3689 struct cnic_local *cp = dev->cnic_priv;
3690 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3691 u8 opcode = l4kcqe->op_code;
3692 u32 l5_cid;
3693 struct cnic_sock *csk;
3694
3695 if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
3696 cnic_process_fcoe_term_conn(dev, kcqe);
3697 return;
3698 }
3699 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3700 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3701 cnic_cm_process_offld_pg(dev, l4kcqe);
3702 return;
3703 }
3704
3705 l5_cid = l4kcqe->conn_id;
3706 if (opcode & 0x80)
3707 l5_cid = l4kcqe->cid;
3708 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3709 return;
3710
3711 csk = &cp->csk_tbl[l5_cid];
3712 csk_hold(csk);
3713
3714 if (!cnic_in_use(csk)) {
3715 csk_put(csk);
3716 return;
3717 }
3718
3719 switch (opcode) {
3720 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3721 if (l4kcqe->status != 0) {
3722 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3723 cnic_cm_upcall(cp, csk,
3724 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3725 }
3726 break;
3727 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3728 if (l4kcqe->status == 0)
3729 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3730
3731 smp_mb__before_clear_bit();
3732 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3733 cnic_cm_upcall(cp, csk, opcode);
3734 break;
3735
3736 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3737 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3738 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3739 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3740 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3741 cp->close_conn(csk, opcode);
3742 break;
3743
3744 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3745 cnic_cm_upcall(cp, csk, opcode);
3746 break;
3747 }
3748 csk_put(csk);
3749 }
3750
3751 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3752 {
3753 struct cnic_dev *dev = data;
3754 int i;
3755
3756 for (i = 0; i < num; i++)
3757 cnic_cm_process_kcqe(dev, kcqe[i]);
3758 }
3759
3760 static struct cnic_ulp_ops cm_ulp_ops = {
3761 .indicate_kcqes = cnic_cm_indicate_kcqe,
3762 };
3763
3764 static void cnic_cm_free_mem(struct cnic_dev *dev)
3765 {
3766 struct cnic_local *cp = dev->cnic_priv;
3767
3768 kfree(cp->csk_tbl);
3769 cp->csk_tbl = NULL;
3770 cnic_free_id_tbl(&cp->csk_port_tbl);
3771 }
3772
3773 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3774 {
3775 struct cnic_local *cp = dev->cnic_priv;
3776
3777 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3778 GFP_KERNEL);
3779 if (!cp->csk_tbl)
3780 return -ENOMEM;
3781
3782 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3783 CNIC_LOCAL_PORT_MIN)) {
3784 cnic_cm_free_mem(dev);
3785 return -ENOMEM;
3786 }
3787 return 0;
3788 }
3789
3790 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3791 {
3792 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
3793 /* Unsolicited RESET_COMP or RESET_RECEIVED */
3794 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3795 csk->state = opcode;
3796 }
3797
3798 /* 1. If event opcode matches the expected event in csk->state
3799 * 2. If the expected event is CLOSE_COMP, we accept any event
3800 * 3. If the expected event is 0, meaning the connection was never
3801 * never established, we accept the opcode from cm_abort.
3802 */
3803 if (opcode == csk->state || csk->state == 0 ||
3804 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
3805 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3806 if (csk->state == 0)
3807 csk->state = opcode;
3808 return 1;
3809 }
3810 }
3811 return 0;
3812 }
3813
3814 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3815 {
3816 struct cnic_dev *dev = csk->dev;
3817 struct cnic_local *cp = dev->cnic_priv;
3818
3819 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
3820 cnic_cm_upcall(cp, csk, opcode);
3821 return;
3822 }
3823
3824 clear_bit(SK_F_CONNECT_START, &csk->flags);
3825 cnic_close_conn(csk);
3826 csk->state = opcode;
3827 cnic_cm_upcall(cp, csk, opcode);
3828 }
3829
3830 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3831 {
3832 }
3833
3834 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3835 {
3836 u32 seed;
3837
3838 get_random_bytes(&seed, 4);
3839 cnic_ctx_wr(dev, 45, 0, seed);
3840 return 0;
3841 }
3842
3843 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3844 {
3845 struct cnic_dev *dev = csk->dev;
3846 struct cnic_local *cp = dev->cnic_priv;
3847 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3848 union l5cm_specific_data l5_data;
3849 u32 cmd = 0;
3850 int close_complete = 0;
3851
3852 switch (opcode) {
3853 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3854 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3855 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3856 if (cnic_ready_to_close(csk, opcode)) {
3857 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3858 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3859 else
3860 close_complete = 1;
3861 }
3862 break;
3863 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3864 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3865 break;
3866 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3867 close_complete = 1;
3868 break;
3869 }
3870 if (cmd) {
3871 memset(&l5_data, 0, sizeof(l5_data));
3872
3873 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3874 &l5_data);
3875 } else if (close_complete) {
3876 ctx->timestamp = jiffies;
3877 cnic_close_conn(csk);
3878 cnic_cm_upcall(cp, csk, csk->state);
3879 }
3880 }
3881
3882 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3883 {
3884 struct cnic_local *cp = dev->cnic_priv;
3885 int i;
3886
3887 if (!cp->ctx_tbl)
3888 return;
3889
3890 if (!netif_running(dev->netdev))
3891 return;
3892
3893 for (i = 0; i < cp->max_cid_space; i++) {
3894 struct cnic_context *ctx = &cp->ctx_tbl[i];
3895
3896 while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3897 msleep(10);
3898
3899 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3900 netdev_warn(dev->netdev, "CID %x not deleted\n",
3901 ctx->cid);
3902 }
3903
3904 cancel_delayed_work(&cp->delete_task);
3905 flush_workqueue(cnic_wq);
3906
3907 if (atomic_read(&cp->iscsi_conn) != 0)
3908 netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
3909 atomic_read(&cp->iscsi_conn));
3910 }
3911
3912 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3913 {
3914 struct cnic_local *cp = dev->cnic_priv;
3915 u32 pfid = cp->pfid;
3916 u32 port = CNIC_PORT(cp);
3917
3918 cnic_init_bnx2x_mac(dev);
3919 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3920
3921 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3922 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
3923
3924 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3925 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
3926 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3927 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
3928 DEF_MAX_DA_COUNT);
3929
3930 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3931 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
3932 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3933 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
3934 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3935 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
3936 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3937 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
3938
3939 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
3940 DEF_MAX_CWND);
3941 return 0;
3942 }
3943
3944 static void cnic_delete_task(struct work_struct *work)
3945 {
3946 struct cnic_local *cp;
3947 struct cnic_dev *dev;
3948 u32 i;
3949 int need_resched = 0;
3950
3951 cp = container_of(work, struct cnic_local, delete_task.work);
3952 dev = cp->dev;
3953
3954 for (i = 0; i < cp->max_cid_space; i++) {
3955 struct cnic_context *ctx = &cp->ctx_tbl[i];
3956
3957 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
3958 !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3959 continue;
3960
3961 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
3962 need_resched = 1;
3963 continue;
3964 }
3965
3966 if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3967 continue;
3968
3969 cnic_bnx2x_destroy_ramrod(dev, i);
3970
3971 cnic_free_bnx2x_conn_resc(dev, i);
3972 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
3973 atomic_dec(&cp->iscsi_conn);
3974
3975 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
3976 }
3977
3978 if (need_resched)
3979 queue_delayed_work(cnic_wq, &cp->delete_task,
3980 msecs_to_jiffies(10));
3981
3982 }
3983
3984 static int cnic_cm_open(struct cnic_dev *dev)
3985 {
3986 struct cnic_local *cp = dev->cnic_priv;
3987 int err;
3988
3989 err = cnic_cm_alloc_mem(dev);
3990 if (err)
3991 return err;
3992
3993 err = cp->start_cm(dev);
3994
3995 if (err)
3996 goto err_out;
3997
3998 INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
3999
4000 dev->cm_create = cnic_cm_create;
4001 dev->cm_destroy = cnic_cm_destroy;
4002 dev->cm_connect = cnic_cm_connect;
4003 dev->cm_abort = cnic_cm_abort;
4004 dev->cm_close = cnic_cm_close;
4005 dev->cm_select_dev = cnic_cm_select_dev;
4006
4007 cp->ulp_handle[CNIC_ULP_L4] = dev;
4008 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
4009 return 0;
4010
4011 err_out:
4012 cnic_cm_free_mem(dev);
4013 return err;
4014 }
4015
4016 static int cnic_cm_shutdown(struct cnic_dev *dev)
4017 {
4018 struct cnic_local *cp = dev->cnic_priv;
4019 int i;
4020
4021 cp->stop_cm(dev);
4022
4023 if (!cp->csk_tbl)
4024 return 0;
4025
4026 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
4027 struct cnic_sock *csk = &cp->csk_tbl[i];
4028
4029 clear_bit(SK_F_INUSE, &csk->flags);
4030 cnic_cm_cleanup(csk);
4031 }
4032 cnic_cm_free_mem(dev);
4033
4034 return 0;
4035 }
4036
4037 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
4038 {
4039 u32 cid_addr;
4040 int i;
4041
4042 cid_addr = GET_CID_ADDR(cid);
4043
4044 for (i = 0; i < CTX_SIZE; i += 4)
4045 cnic_ctx_wr(dev, cid_addr, i, 0);
4046 }
4047
4048 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
4049 {
4050 struct cnic_local *cp = dev->cnic_priv;
4051 int ret = 0, i;
4052 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
4053
4054 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4055 return 0;
4056
4057 for (i = 0; i < cp->ctx_blks; i++) {
4058 int j;
4059 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
4060 u32 val;
4061
4062 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
4063
4064 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
4065 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
4066 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
4067 (u64) cp->ctx_arr[i].mapping >> 32);
4068 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
4069 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4070 for (j = 0; j < 10; j++) {
4071
4072 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
4073 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
4074 break;
4075 udelay(5);
4076 }
4077 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
4078 ret = -EBUSY;
4079 break;
4080 }
4081 }
4082 return ret;
4083 }
4084
4085 static void cnic_free_irq(struct cnic_dev *dev)
4086 {
4087 struct cnic_local *cp = dev->cnic_priv;
4088 struct cnic_eth_dev *ethdev = cp->ethdev;
4089
4090 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4091 cp->disable_int_sync(dev);
4092 tasklet_kill(&cp->cnic_irq_task);
4093 free_irq(ethdev->irq_arr[0].vector, dev);
4094 }
4095 }
4096
4097 static int cnic_request_irq(struct cnic_dev *dev)
4098 {
4099 struct cnic_local *cp = dev->cnic_priv;
4100 struct cnic_eth_dev *ethdev = cp->ethdev;
4101 int err;
4102
4103 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
4104 if (err)
4105 tasklet_disable(&cp->cnic_irq_task);
4106
4107 return err;
4108 }
4109
4110 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
4111 {
4112 struct cnic_local *cp = dev->cnic_priv;
4113 struct cnic_eth_dev *ethdev = cp->ethdev;
4114
4115 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4116 int err, i = 0;
4117 int sblk_num = cp->status_blk_num;
4118 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4119 BNX2_HC_SB_CONFIG_1;
4120
4121 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4122
4123 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
4124 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
4125 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
4126
4127 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
4128 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
4129 (unsigned long) dev);
4130 err = cnic_request_irq(dev);
4131 if (err)
4132 return err;
4133
4134 while (cp->status_blk.bnx2->status_completion_producer_index &&
4135 i < 10) {
4136 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
4137 1 << (11 + sblk_num));
4138 udelay(10);
4139 i++;
4140 barrier();
4141 }
4142 if (cp->status_blk.bnx2->status_completion_producer_index) {
4143 cnic_free_irq(dev);
4144 goto failed;
4145 }
4146
4147 } else {
4148 struct status_block *sblk = cp->status_blk.gen;
4149 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
4150 int i = 0;
4151
4152 while (sblk->status_completion_producer_index && i < 10) {
4153 CNIC_WR(dev, BNX2_HC_COMMAND,
4154 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4155 udelay(10);
4156 i++;
4157 barrier();
4158 }
4159 if (sblk->status_completion_producer_index)
4160 goto failed;
4161
4162 }
4163 return 0;
4164
4165 failed:
4166 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
4167 return -EBUSY;
4168 }
4169
4170 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
4171 {
4172 struct cnic_local *cp = dev->cnic_priv;
4173 struct cnic_eth_dev *ethdev = cp->ethdev;
4174
4175 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4176 return;
4177
4178 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4179 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
4180 }
4181
4182 static void cnic_get_bnx2_iscsi_info(struct cnic_dev *dev)
4183 {
4184 u32 max_conn;
4185
4186 max_conn = cnic_reg_rd_ind(dev, BNX2_FW_MAX_ISCSI_CONN);
4187 dev->max_iscsi_conn = max_conn;
4188 }
4189
4190 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
4191 {
4192 struct cnic_local *cp = dev->cnic_priv;
4193 struct cnic_eth_dev *ethdev = cp->ethdev;
4194
4195 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4196 return;
4197
4198 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4199 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4200 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
4201 synchronize_irq(ethdev->irq_arr[0].vector);
4202 }
4203
4204 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
4205 {
4206 struct cnic_local *cp = dev->cnic_priv;
4207 struct cnic_eth_dev *ethdev = cp->ethdev;
4208 struct cnic_uio_dev *udev = cp->udev;
4209 u32 cid_addr, tx_cid, sb_id;
4210 u32 val, offset0, offset1, offset2, offset3;
4211 int i;
4212 struct tx_bd *txbd;
4213 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4214 struct status_block *s_blk = cp->status_blk.gen;
4215
4216 sb_id = cp->status_blk_num;
4217 tx_cid = 20;
4218 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
4219 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4220 struct status_block_msix *sblk = cp->status_blk.bnx2;
4221
4222 tx_cid = TX_TSS_CID + sb_id - 1;
4223 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
4224 (TX_TSS_CID << 7));
4225 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
4226 }
4227 cp->tx_cons = *cp->tx_cons_ptr;
4228
4229 cid_addr = GET_CID_ADDR(tx_cid);
4230 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
4231 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
4232
4233 for (i = 0; i < PHY_CTX_SIZE; i += 4)
4234 cnic_ctx_wr(dev, cid_addr2, i, 0);
4235
4236 offset0 = BNX2_L2CTX_TYPE_XI;
4237 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4238 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4239 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4240 } else {
4241 cnic_init_context(dev, tx_cid);
4242 cnic_init_context(dev, tx_cid + 1);
4243
4244 offset0 = BNX2_L2CTX_TYPE;
4245 offset1 = BNX2_L2CTX_CMD_TYPE;
4246 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4247 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4248 }
4249 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4250 cnic_ctx_wr(dev, cid_addr, offset0, val);
4251
4252 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4253 cnic_ctx_wr(dev, cid_addr, offset1, val);
4254
4255 txbd = (struct tx_bd *) udev->l2_ring;
4256
4257 buf_map = udev->l2_buf_map;
4258 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
4259 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
4260 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4261 }
4262 val = (u64) ring_map >> 32;
4263 cnic_ctx_wr(dev, cid_addr, offset2, val);
4264 txbd->tx_bd_haddr_hi = val;
4265
4266 val = (u64) ring_map & 0xffffffff;
4267 cnic_ctx_wr(dev, cid_addr, offset3, val);
4268 txbd->tx_bd_haddr_lo = val;
4269 }
4270
4271 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
4272 {
4273 struct cnic_local *cp = dev->cnic_priv;
4274 struct cnic_eth_dev *ethdev = cp->ethdev;
4275 struct cnic_uio_dev *udev = cp->udev;
4276 u32 cid_addr, sb_id, val, coal_reg, coal_val;
4277 int i;
4278 struct rx_bd *rxbd;
4279 struct status_block *s_blk = cp->status_blk.gen;
4280 dma_addr_t ring_map = udev->l2_ring_map;
4281
4282 sb_id = cp->status_blk_num;
4283 cnic_init_context(dev, 2);
4284 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
4285 coal_reg = BNX2_HC_COMMAND;
4286 coal_val = CNIC_RD(dev, coal_reg);
4287 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4288 struct status_block_msix *sblk = cp->status_blk.bnx2;
4289
4290 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
4291 coal_reg = BNX2_HC_COALESCE_NOW;
4292 coal_val = 1 << (11 + sb_id);
4293 }
4294 i = 0;
4295 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
4296 CNIC_WR(dev, coal_reg, coal_val);
4297 udelay(10);
4298 i++;
4299 barrier();
4300 }
4301 cp->rx_cons = *cp->rx_cons_ptr;
4302
4303 cid_addr = GET_CID_ADDR(2);
4304 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4305 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4306 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4307
4308 if (sb_id == 0)
4309 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
4310 else
4311 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
4312 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
4313
4314 rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
4315 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
4316 dma_addr_t buf_map;
4317 int n = (i % cp->l2_rx_ring_size) + 1;
4318
4319 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4320 rxbd->rx_bd_len = cp->l2_single_buf_size;
4321 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4322 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
4323 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4324 }
4325 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4326 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4327 rxbd->rx_bd_haddr_hi = val;
4328
4329 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4330 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4331 rxbd->rx_bd_haddr_lo = val;
4332
4333 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
4334 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
4335 }
4336
4337 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
4338 {
4339 struct kwqe *wqes[1], l2kwqe;
4340
4341 memset(&l2kwqe, 0, sizeof(l2kwqe));
4342 wqes[0] = &l2kwqe;
4343 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
4344 (L2_KWQE_OPCODE_VALUE_FLUSH <<
4345 KWQE_OPCODE_SHIFT) | 2;
4346 dev->submit_kwqes(dev, wqes, 1);
4347 }
4348
4349 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
4350 {
4351 struct cnic_local *cp = dev->cnic_priv;
4352 u32 val;
4353
4354 val = cp->func << 2;
4355
4356 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
4357
4358 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4359 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
4360 dev->mac_addr[0] = (u8) (val >> 8);
4361 dev->mac_addr[1] = (u8) val;
4362
4363 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
4364
4365 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4366 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
4367 dev->mac_addr[2] = (u8) (val >> 24);
4368 dev->mac_addr[3] = (u8) (val >> 16);
4369 dev->mac_addr[4] = (u8) (val >> 8);
4370 dev->mac_addr[5] = (u8) val;
4371
4372 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
4373
4374 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
4375 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4376 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
4377
4378 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
4379 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
4380 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
4381 }
4382
4383 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
4384 {
4385 struct cnic_local *cp = dev->cnic_priv;
4386 struct cnic_eth_dev *ethdev = cp->ethdev;
4387 struct status_block *sblk = cp->status_blk.gen;
4388 u32 val, kcq_cid_addr, kwq_cid_addr;
4389 int err;
4390
4391 cnic_set_bnx2_mac(dev);
4392
4393 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
4394 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4395 if (BCM_PAGE_BITS > 12)
4396 val |= (12 - 8) << 4;
4397 else
4398 val |= (BCM_PAGE_BITS - 8) << 4;
4399
4400 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
4401
4402 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
4403 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
4404 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
4405
4406 err = cnic_setup_5709_context(dev, 1);
4407 if (err)
4408 return err;
4409
4410 cnic_init_context(dev, KWQ_CID);
4411 cnic_init_context(dev, KCQ_CID);
4412
4413 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
4414 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
4415
4416 cp->max_kwq_idx = MAX_KWQ_IDX;
4417 cp->kwq_prod_idx = 0;
4418 cp->kwq_con_idx = 0;
4419 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
4420
4421 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
4422 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
4423 else
4424 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
4425
4426 /* Initialize the kernel work queue context. */
4427 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4428 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4429 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
4430
4431 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
4432 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4433
4434 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
4435 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4436
4437 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
4438 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4439
4440 val = (u32) cp->kwq_info.pgtbl_map;
4441 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4442
4443 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
4444 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
4445
4446 cp->kcq1.sw_prod_idx = 0;
4447 cp->kcq1.hw_prod_idx_ptr =
4448 (u16 *) &sblk->status_completion_producer_index;
4449
4450 cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
4451
4452 /* Initialize the kernel complete queue context. */
4453 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4454 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4455 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
4456
4457 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
4458 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4459
4460 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
4461 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4462
4463 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
4464 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4465
4466 val = (u32) cp->kcq1.dma.pgtbl_map;
4467 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4468
4469 cp->int_num = 0;
4470 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4471 struct status_block_msix *msblk = cp->status_blk.bnx2;
4472 u32 sb_id = cp->status_blk_num;
4473 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
4474
4475 cp->kcq1.hw_prod_idx_ptr =
4476 (u16 *) &msblk->status_completion_producer_index;
4477 cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
4478 cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
4479 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
4480 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4481 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4482 }
4483
4484 /* Enable Commnad Scheduler notification when we write to the
4485 * host producer index of the kernel contexts. */
4486 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
4487
4488 /* Enable Command Scheduler notification when we write to either
4489 * the Send Queue or Receive Queue producer indexes of the kernel
4490 * bypass contexts. */
4491 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
4492 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
4493
4494 /* Notify COM when the driver post an application buffer. */
4495 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
4496
4497 /* Set the CP and COM doorbells. These two processors polls the
4498 * doorbell for a non zero value before running. This must be done
4499 * after setting up the kernel queue contexts. */
4500 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
4501 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
4502
4503 cnic_init_bnx2_tx_ring(dev);
4504 cnic_init_bnx2_rx_ring(dev);
4505
4506 err = cnic_init_bnx2_irq(dev);
4507 if (err) {
4508 netdev_err(dev->netdev, "cnic_init_irq failed\n");
4509 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4510 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4511 return err;
4512 }
4513
4514 cnic_get_bnx2_iscsi_info(dev);
4515
4516 return 0;
4517 }
4518
4519 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
4520 {
4521 struct cnic_local *cp = dev->cnic_priv;
4522 struct cnic_eth_dev *ethdev = cp->ethdev;
4523 u32 start_offset = ethdev->ctx_tbl_offset;
4524 int i;
4525
4526 for (i = 0; i < cp->ctx_blks; i++) {
4527 struct cnic_ctx *ctx = &cp->ctx_arr[i];
4528 dma_addr_t map = ctx->mapping;
4529
4530 if (cp->ctx_align) {
4531 unsigned long mask = cp->ctx_align - 1;
4532
4533 map = (map + mask) & ~mask;
4534 }
4535
4536 cnic_ctx_tbl_wr(dev, start_offset + i, map);
4537 }
4538 }
4539
4540 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4541 {
4542 struct cnic_local *cp = dev->cnic_priv;
4543 struct cnic_eth_dev *ethdev = cp->ethdev;
4544 int err = 0;
4545
4546 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
4547 (unsigned long) dev);
4548 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4549 err = cnic_request_irq(dev);
4550
4551 return err;
4552 }
4553
4554 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4555 u16 sb_id, u8 sb_index,
4556 u8 disable)
4557 {
4558
4559 u32 addr = BAR_CSTRORM_INTMEM +
4560 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4561 offsetof(struct hc_status_block_data_e1x, index_data) +
4562 sizeof(struct hc_index_data)*sb_index +
4563 offsetof(struct hc_index_data, flags);
4564 u16 flags = CNIC_RD16(dev, addr);
4565 /* clear and set */
4566 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4567 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4568 HC_INDEX_DATA_HC_ENABLED);
4569 CNIC_WR16(dev, addr, flags);
4570 }
4571
4572 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4573 {
4574 struct cnic_local *cp = dev->cnic_priv;
4575 u8 sb_id = cp->status_blk_num;
4576
4577 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4578 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4579 offsetof(struct hc_status_block_data_e1x, index_data) +
4580 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4581 offsetof(struct hc_index_data, timeout), 64 / 12);
4582 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4583 }
4584
4585 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4586 {
4587 }
4588
4589 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4590 struct client_init_ramrod_data *data)
4591 {
4592 struct cnic_local *cp = dev->cnic_priv;
4593 struct cnic_uio_dev *udev = cp->udev;
4594 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4595 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4596 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4597 int port = CNIC_PORT(cp);
4598 int i;
4599 u32 cli = cp->ethdev->iscsi_l2_client_id;
4600 u32 val;
4601
4602 memset(txbd, 0, BCM_PAGE_SIZE);
4603
4604 buf_map = udev->l2_buf_map;
4605 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4606 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4607 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4608
4609 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4610 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4611 reg_bd->addr_hi = start_bd->addr_hi;
4612 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4613 start_bd->nbytes = cpu_to_le16(0x10);
4614 start_bd->nbd = cpu_to_le16(3);
4615 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4616 start_bd->general_data = (UNICAST_ADDRESS <<
4617 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
4618 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4619
4620 }
4621
4622 val = (u64) ring_map >> 32;
4623 txbd->next_bd.addr_hi = cpu_to_le32(val);
4624
4625 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4626
4627 val = (u64) ring_map & 0xffffffff;
4628 txbd->next_bd.addr_lo = cpu_to_le32(val);
4629
4630 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4631
4632 /* Other ramrod params */
4633 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4634 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4635
4636 /* reset xstorm per client statistics */
4637 if (cli < MAX_STAT_COUNTER_ID) {
4638 val = BAR_XSTRORM_INTMEM +
4639 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4640 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
4641 CNIC_WR(dev, val + i * 4, 0);
4642 }
4643
4644 cp->tx_cons_ptr =
4645 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4646 }
4647
4648 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4649 struct client_init_ramrod_data *data)
4650 {
4651 struct cnic_local *cp = dev->cnic_priv;
4652 struct cnic_uio_dev *udev = cp->udev;
4653 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4654 BCM_PAGE_SIZE);
4655 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4656 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
4657 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4658 int i;
4659 int port = CNIC_PORT(cp);
4660 u32 cli = cp->ethdev->iscsi_l2_client_id;
4661 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4662 u32 val;
4663 dma_addr_t ring_map = udev->l2_ring_map;
4664
4665 /* General data */
4666 data->general.client_id = cli;
4667 data->general.statistics_en_flg = 1;
4668 data->general.statistics_counter_id = cli;
4669 data->general.activate_flg = 1;
4670 data->general.sp_client_id = cli;
4671
4672 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
4673 dma_addr_t buf_map;
4674 int n = (i % cp->l2_rx_ring_size) + 1;
4675
4676 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4677 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4678 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4679 }
4680
4681 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4682 rxbd->addr_hi = cpu_to_le32(val);
4683 data->rx.bd_page_base.hi = cpu_to_le32(val);
4684
4685 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4686 rxbd->addr_lo = cpu_to_le32(val);
4687 data->rx.bd_page_base.lo = cpu_to_le32(val);
4688
4689 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
4690 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
4691 rxcqe->addr_hi = cpu_to_le32(val);
4692 data->rx.cqe_page_base.hi = cpu_to_le32(val);
4693
4694 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
4695 rxcqe->addr_lo = cpu_to_le32(val);
4696 data->rx.cqe_page_base.lo = cpu_to_le32(val);
4697
4698 /* Other ramrod params */
4699 data->rx.client_qzone_id = cl_qzone_id;
4700 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
4701 data->rx.status_block_id = BNX2X_DEF_SB_ID;
4702
4703 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
4704 data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
4705
4706 data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4707 data->rx.outer_vlan_removal_enable_flg = 1;
4708
4709 /* reset tstorm and ustorm per client statistics */
4710 if (cli < MAX_STAT_COUNTER_ID) {
4711 val = BAR_TSTRORM_INTMEM +
4712 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4713 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
4714 CNIC_WR(dev, val + i * 4, 0);
4715
4716 val = BAR_USTRORM_INTMEM +
4717 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
4718 for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
4719 CNIC_WR(dev, val + i * 4, 0);
4720 }
4721
4722 cp->rx_cons_ptr =
4723 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
4724 cp->rx_cons = *cp->rx_cons_ptr;
4725 }
4726
4727 static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
4728 {
4729 struct cnic_local *cp = dev->cnic_priv;
4730 u32 pfid = cp->pfid;
4731
4732 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
4733 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
4734 cp->kcq1.sw_prod_idx = 0;
4735
4736 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4737 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4738
4739 cp->kcq1.hw_prod_idx_ptr =
4740 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4741 cp->kcq1.status_idx_ptr =
4742 &sb->sb.running_index[SM_RX_ID];
4743 } else {
4744 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
4745
4746 cp->kcq1.hw_prod_idx_ptr =
4747 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4748 cp->kcq1.status_idx_ptr =
4749 &sb->sb.running_index[SM_RX_ID];
4750 }
4751
4752 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4753 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4754
4755 cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
4756 USTORM_FCOE_EQ_PROD_OFFSET(pfid);
4757 cp->kcq2.sw_prod_idx = 0;
4758 cp->kcq2.hw_prod_idx_ptr =
4759 &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
4760 cp->kcq2.status_idx_ptr =
4761 &sb->sb.running_index[SM_RX_ID];
4762 }
4763 }
4764
4765 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4766 {
4767 struct cnic_local *cp = dev->cnic_priv;
4768 struct cnic_eth_dev *ethdev = cp->ethdev;
4769 int func = CNIC_FUNC(cp), ret, i;
4770 u32 pfid;
4771
4772 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4773 u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
4774
4775 if (!(val & 1))
4776 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
4777 else
4778 val = (val >> 1) & 1;
4779
4780 if (val)
4781 cp->pfid = func >> 1;
4782 else
4783 cp->pfid = func & 0x6;
4784 } else {
4785 cp->pfid = func;
4786 }
4787 pfid = cp->pfid;
4788
4789 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4790 cp->iscsi_start_cid);
4791
4792 if (ret)
4793 return -ENOMEM;
4794
4795 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4796 ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
4797 BNX2X_FCOE_NUM_CONNECTIONS,
4798 cp->fcoe_start_cid);
4799
4800 if (ret)
4801 return -ENOMEM;
4802 }
4803
4804 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4805
4806 cnic_init_bnx2x_kcq(dev);
4807
4808 /* Only 1 EQ */
4809 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
4810 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4811 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
4812 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4813 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
4814 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
4815 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4816 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
4817 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
4818 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4819 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
4820 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
4821 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4822 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
4823 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
4824 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4825 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
4826 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4827 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
4828 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4829 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
4830 HC_INDEX_ISCSI_EQ_CONS);
4831
4832 for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
4833 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4834 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
4835 cp->conn_buf_info.pgtbl[2 * i]);
4836 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4837 TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
4838 cp->conn_buf_info.pgtbl[(2 * i) + 1]);
4839 }
4840
4841 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4842 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
4843 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4844 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4845 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
4846 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4847
4848 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4849 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
4850
4851 cnic_setup_bnx2x_context(dev);
4852
4853 ret = cnic_init_bnx2x_irq(dev);
4854 if (ret)
4855 return ret;
4856
4857 return 0;
4858 }
4859
4860 static void cnic_init_rings(struct cnic_dev *dev)
4861 {
4862 struct cnic_local *cp = dev->cnic_priv;
4863 struct cnic_uio_dev *udev = cp->udev;
4864
4865 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4866 return;
4867
4868 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4869 cnic_init_bnx2_tx_ring(dev);
4870 cnic_init_bnx2_rx_ring(dev);
4871 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4872 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4873 u32 cli = cp->ethdev->iscsi_l2_client_id;
4874 u32 cid = cp->ethdev->iscsi_l2_cid;
4875 u32 cl_qzone_id;
4876 struct client_init_ramrod_data *data;
4877 union l5cm_specific_data l5_data;
4878 struct ustorm_eth_rx_producers rx_prods = {0};
4879 u32 off, i;
4880
4881 rx_prods.bd_prod = 0;
4882 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4883 barrier();
4884
4885 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4886
4887 off = BAR_USTRORM_INTMEM +
4888 (BNX2X_CHIP_IS_E2(cp->chip_id) ?
4889 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
4890 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
4891
4892 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4893 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
4894
4895 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4896
4897 data = udev->l2_buf;
4898
4899 memset(data, 0, sizeof(*data));
4900
4901 cnic_init_bnx2x_tx_ring(dev, data);
4902 cnic_init_bnx2x_rx_ring(dev, data);
4903
4904 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
4905 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
4906
4907 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4908
4909 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4910 cid, ETH_CONNECTION_TYPE, &l5_data);
4911
4912 i = 0;
4913 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4914 ++i < 10)
4915 msleep(1);
4916
4917 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4918 netdev_err(dev->netdev,
4919 "iSCSI CLIENT_SETUP did not complete\n");
4920 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4921 cnic_ring_ctl(dev, cid, cli, 1);
4922 }
4923 }
4924
4925 static void cnic_shutdown_rings(struct cnic_dev *dev)
4926 {
4927 struct cnic_local *cp = dev->cnic_priv;
4928
4929 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4930 return;
4931
4932 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4933 cnic_shutdown_bnx2_rx_ring(dev);
4934 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4935 struct cnic_local *cp = dev->cnic_priv;
4936 u32 cli = cp->ethdev->iscsi_l2_client_id;
4937 u32 cid = cp->ethdev->iscsi_l2_cid;
4938 union l5cm_specific_data l5_data;
4939 int i;
4940
4941 cnic_ring_ctl(dev, cid, cli, 0);
4942
4943 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4944
4945 l5_data.phy_address.lo = cli;
4946 l5_data.phy_address.hi = 0;
4947 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4948 cid, ETH_CONNECTION_TYPE, &l5_data);
4949 i = 0;
4950 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4951 ++i < 10)
4952 msleep(1);
4953
4954 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4955 netdev_err(dev->netdev,
4956 "iSCSI CLIENT_HALT did not complete\n");
4957 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4958
4959 memset(&l5_data, 0, sizeof(l5_data));
4960 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
4961 cid, NONE_CONNECTION_TYPE, &l5_data);
4962 msleep(10);
4963 }
4964 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4965 }
4966
4967 static int cnic_register_netdev(struct cnic_dev *dev)
4968 {
4969 struct cnic_local *cp = dev->cnic_priv;
4970 struct cnic_eth_dev *ethdev = cp->ethdev;
4971 int err;
4972
4973 if (!ethdev)
4974 return -ENODEV;
4975
4976 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
4977 return 0;
4978
4979 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
4980 if (err)
4981 netdev_err(dev->netdev, "register_cnic failed\n");
4982
4983 return err;
4984 }
4985
4986 static void cnic_unregister_netdev(struct cnic_dev *dev)
4987 {
4988 struct cnic_local *cp = dev->cnic_priv;
4989 struct cnic_eth_dev *ethdev = cp->ethdev;
4990
4991 if (!ethdev)
4992 return;
4993
4994 ethdev->drv_unregister_cnic(dev->netdev);
4995 }
4996
4997 static int cnic_start_hw(struct cnic_dev *dev)
4998 {
4999 struct cnic_local *cp = dev->cnic_priv;
5000 struct cnic_eth_dev *ethdev = cp->ethdev;
5001 int err;
5002
5003 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
5004 return -EALREADY;
5005
5006 dev->regview = ethdev->io_base;
5007 pci_dev_get(dev->pcidev);
5008 cp->func = PCI_FUNC(dev->pcidev->devfn);
5009 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
5010 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
5011
5012 err = cp->alloc_resc(dev);
5013 if (err) {
5014 netdev_err(dev->netdev, "allocate resource failure\n");
5015 goto err1;
5016 }
5017
5018 err = cp->start_hw(dev);
5019 if (err)
5020 goto err1;
5021
5022 err = cnic_cm_open(dev);
5023 if (err)
5024 goto err1;
5025
5026 set_bit(CNIC_F_CNIC_UP, &dev->flags);
5027
5028 cp->enable_int(dev);
5029
5030 return 0;
5031
5032 err1:
5033 cp->free_resc(dev);
5034 pci_dev_put(dev->pcidev);
5035 return err;
5036 }
5037
5038 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
5039 {
5040 cnic_disable_bnx2_int_sync(dev);
5041
5042 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
5043 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
5044
5045 cnic_init_context(dev, KWQ_CID);
5046 cnic_init_context(dev, KCQ_CID);
5047
5048 cnic_setup_5709_context(dev, 0);
5049 cnic_free_irq(dev);
5050
5051 cnic_free_resc(dev);
5052 }
5053
5054
5055 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
5056 {
5057 struct cnic_local *cp = dev->cnic_priv;
5058
5059 cnic_free_irq(dev);
5060 *cp->kcq1.hw_prod_idx_ptr = 0;
5061 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5062 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
5063 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
5064 cnic_free_resc(dev);
5065 }
5066
5067 static void cnic_stop_hw(struct cnic_dev *dev)
5068 {
5069 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5070 struct cnic_local *cp = dev->cnic_priv;
5071 int i = 0;
5072
5073 /* Need to wait for the ring shutdown event to complete
5074 * before clearing the CNIC_UP flag.
5075 */
5076 while (cp->udev->uio_dev != -1 && i < 15) {
5077 msleep(100);
5078 i++;
5079 }
5080 cnic_shutdown_rings(dev);
5081 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
5082 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
5083 synchronize_rcu();
5084 cnic_cm_shutdown(dev);
5085 cp->stop_hw(dev);
5086 pci_dev_put(dev->pcidev);
5087 }
5088 }
5089
5090 static void cnic_free_dev(struct cnic_dev *dev)
5091 {
5092 int i = 0;
5093
5094 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
5095 msleep(100);
5096 i++;
5097 }
5098 if (atomic_read(&dev->ref_count) != 0)
5099 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
5100
5101 netdev_info(dev->netdev, "Removed CNIC device\n");
5102 dev_put(dev->netdev);
5103 kfree(dev);
5104 }
5105
5106 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
5107 struct pci_dev *pdev)
5108 {
5109 struct cnic_dev *cdev;
5110 struct cnic_local *cp;
5111 int alloc_size;
5112
5113 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
5114
5115 cdev = kzalloc(alloc_size , GFP_KERNEL);
5116 if (cdev == NULL) {
5117 netdev_err(dev, "allocate dev struct failure\n");
5118 return NULL;
5119 }
5120
5121 cdev->netdev = dev;
5122 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
5123 cdev->register_device = cnic_register_device;
5124 cdev->unregister_device = cnic_unregister_device;
5125 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
5126
5127 cp = cdev->cnic_priv;
5128 cp->dev = cdev;
5129 cp->l2_single_buf_size = 0x400;
5130 cp->l2_rx_ring_size = 3;
5131
5132 spin_lock_init(&cp->cnic_ulp_lock);
5133
5134 netdev_info(dev, "Added CNIC device\n");
5135
5136 return cdev;
5137 }
5138
5139 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
5140 {
5141 struct pci_dev *pdev;
5142 struct cnic_dev *cdev;
5143 struct cnic_local *cp;
5144 struct cnic_eth_dev *ethdev = NULL;
5145 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5146
5147 probe = symbol_get(bnx2_cnic_probe);
5148 if (probe) {
5149 ethdev = (*probe)(dev);
5150 symbol_put(bnx2_cnic_probe);
5151 }
5152 if (!ethdev)
5153 return NULL;
5154
5155 pdev = ethdev->pdev;
5156 if (!pdev)
5157 return NULL;
5158
5159 dev_hold(dev);
5160 pci_dev_get(pdev);
5161 if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
5162 pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
5163 (pdev->revision < 0x10)) {
5164 pci_dev_put(pdev);
5165 goto cnic_err;
5166 }
5167 pci_dev_put(pdev);
5168
5169 cdev = cnic_alloc_dev(dev, pdev);
5170 if (cdev == NULL)
5171 goto cnic_err;
5172
5173 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
5174 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
5175
5176 cp = cdev->cnic_priv;
5177 cp->ethdev = ethdev;
5178 cdev->pcidev = pdev;
5179 cp->chip_id = ethdev->chip_id;
5180
5181 cp->cnic_ops = &cnic_bnx2_ops;
5182 cp->start_hw = cnic_start_bnx2_hw;
5183 cp->stop_hw = cnic_stop_bnx2_hw;
5184 cp->setup_pgtbl = cnic_setup_page_tbl;
5185 cp->alloc_resc = cnic_alloc_bnx2_resc;
5186 cp->free_resc = cnic_free_resc;
5187 cp->start_cm = cnic_cm_init_bnx2_hw;
5188 cp->stop_cm = cnic_cm_stop_bnx2_hw;
5189 cp->enable_int = cnic_enable_bnx2_int;
5190 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
5191 cp->close_conn = cnic_close_bnx2_conn;
5192 cp->next_idx = cnic_bnx2_next_idx;
5193 cp->hw_idx = cnic_bnx2_hw_idx;
5194 return cdev;
5195
5196 cnic_err:
5197 dev_put(dev);
5198 return NULL;
5199 }
5200
5201 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
5202 {
5203 struct pci_dev *pdev;
5204 struct cnic_dev *cdev;
5205 struct cnic_local *cp;
5206 struct cnic_eth_dev *ethdev = NULL;
5207 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5208
5209 probe = symbol_get(bnx2x_cnic_probe);
5210 if (probe) {
5211 ethdev = (*probe)(dev);
5212 symbol_put(bnx2x_cnic_probe);
5213 }
5214 if (!ethdev)
5215 return NULL;
5216
5217 pdev = ethdev->pdev;
5218 if (!pdev)
5219 return NULL;
5220
5221 dev_hold(dev);
5222 cdev = cnic_alloc_dev(dev, pdev);
5223 if (cdev == NULL) {
5224 dev_put(dev);
5225 return NULL;
5226 }
5227
5228 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
5229 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
5230
5231 cp = cdev->cnic_priv;
5232 cp->ethdev = ethdev;
5233 cdev->pcidev = pdev;
5234 cp->chip_id = ethdev->chip_id;
5235
5236 if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
5237 cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5238 if (BNX2X_CHIP_IS_E2(cp->chip_id) &&
5239 !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
5240 cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
5241
5242 memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
5243
5244 cp->cnic_ops = &cnic_bnx2x_ops;
5245 cp->start_hw = cnic_start_bnx2x_hw;
5246 cp->stop_hw = cnic_stop_bnx2x_hw;
5247 cp->setup_pgtbl = cnic_setup_page_tbl_le;
5248 cp->alloc_resc = cnic_alloc_bnx2x_resc;
5249 cp->free_resc = cnic_free_resc;
5250 cp->start_cm = cnic_cm_init_bnx2x_hw;
5251 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
5252 cp->enable_int = cnic_enable_bnx2x_int;
5253 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
5254 if (BNX2X_CHIP_IS_E2(cp->chip_id))
5255 cp->ack_int = cnic_ack_bnx2x_e2_msix;
5256 else
5257 cp->ack_int = cnic_ack_bnx2x_msix;
5258 cp->close_conn = cnic_close_bnx2x_conn;
5259 cp->next_idx = cnic_bnx2x_next_idx;
5260 cp->hw_idx = cnic_bnx2x_hw_idx;
5261 return cdev;
5262 }
5263
5264 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
5265 {
5266 struct ethtool_drvinfo drvinfo;
5267 struct cnic_dev *cdev = NULL;
5268
5269 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5270 memset(&drvinfo, 0, sizeof(drvinfo));
5271 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5272
5273 if (!strcmp(drvinfo.driver, "bnx2"))
5274 cdev = init_bnx2_cnic(dev);
5275 if (!strcmp(drvinfo.driver, "bnx2x"))
5276 cdev = init_bnx2x_cnic(dev);
5277 if (cdev) {
5278 write_lock(&cnic_dev_lock);
5279 list_add(&cdev->list, &cnic_dev_list);
5280 write_unlock(&cnic_dev_lock);
5281 }
5282 }
5283 return cdev;
5284 }
5285
5286 /**
5287 * netdev event handler
5288 */
5289 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
5290 void *ptr)
5291 {
5292 struct net_device *netdev = ptr;
5293 struct cnic_dev *dev;
5294 int if_type;
5295 int new_dev = 0;
5296
5297 dev = cnic_from_netdev(netdev);
5298
5299 if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
5300 /* Check for the hot-plug device */
5301 dev = is_cnic_dev(netdev);
5302 if (dev) {
5303 new_dev = 1;
5304 cnic_hold(dev);
5305 }
5306 }
5307 if (dev) {
5308 struct cnic_local *cp = dev->cnic_priv;
5309
5310 if (new_dev)
5311 cnic_ulp_init(dev);
5312 else if (event == NETDEV_UNREGISTER)
5313 cnic_ulp_exit(dev);
5314
5315 if (event == NETDEV_UP) {
5316 if (cnic_register_netdev(dev) != 0) {
5317 cnic_put(dev);
5318 goto done;
5319 }
5320 if (!cnic_start_hw(dev))
5321 cnic_ulp_start(dev);
5322 }
5323
5324 rcu_read_lock();
5325 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
5326 struct cnic_ulp_ops *ulp_ops;
5327 void *ctx;
5328
5329 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
5330 if (!ulp_ops || !ulp_ops->indicate_netevent)
5331 continue;
5332
5333 ctx = cp->ulp_handle[if_type];
5334
5335 ulp_ops->indicate_netevent(ctx, event);
5336 }
5337 rcu_read_unlock();
5338
5339 if (event == NETDEV_GOING_DOWN) {
5340 cnic_ulp_stop(dev);
5341 cnic_stop_hw(dev);
5342 cnic_unregister_netdev(dev);
5343 } else if (event == NETDEV_UNREGISTER) {
5344 write_lock(&cnic_dev_lock);
5345 list_del_init(&dev->list);
5346 write_unlock(&cnic_dev_lock);
5347
5348 cnic_put(dev);
5349 cnic_free_dev(dev);
5350 goto done;
5351 }
5352 cnic_put(dev);
5353 }
5354 done:
5355 return NOTIFY_DONE;
5356 }
5357
5358 static struct notifier_block cnic_netdev_notifier = {
5359 .notifier_call = cnic_netdev_event
5360 };
5361
5362 static void cnic_release(void)
5363 {
5364 struct cnic_dev *dev;
5365 struct cnic_uio_dev *udev;
5366
5367 while (!list_empty(&cnic_dev_list)) {
5368 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
5369 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5370 cnic_ulp_stop(dev);
5371 cnic_stop_hw(dev);
5372 }
5373
5374 cnic_ulp_exit(dev);
5375 cnic_unregister_netdev(dev);
5376 list_del_init(&dev->list);
5377 cnic_free_dev(dev);
5378 }
5379 while (!list_empty(&cnic_udev_list)) {
5380 udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
5381 list);
5382 cnic_free_uio(udev);
5383 }
5384 }
5385
5386 static int __init cnic_init(void)
5387 {
5388 int rc = 0;
5389
5390 pr_info("%s", version);
5391
5392 rc = register_netdevice_notifier(&cnic_netdev_notifier);
5393 if (rc) {
5394 cnic_release();
5395 return rc;
5396 }
5397
5398 cnic_wq = create_singlethread_workqueue("cnic_wq");
5399 if (!cnic_wq) {
5400 cnic_release();
5401 unregister_netdevice_notifier(&cnic_netdev_notifier);
5402 return -ENOMEM;
5403 }
5404
5405 return 0;
5406 }
5407
5408 static void __exit cnic_exit(void)
5409 {
5410 unregister_netdevice_notifier(&cnic_netdev_notifier);
5411 cnic_release();
5412 destroy_workqueue(cnic_wq);
5413 }
5414
5415 module_init(cnic_init);
5416 module_exit(cnic_exit);
x86 "subsystem" repository