?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB (5651): Dibusb-mb: convert pll handling to properly use dvb-pll
[linux-2.6/x86.git] / drivers / ieee1394 / pcilynx.c
blobd1a5bcdb5e0be9c5bab2facb893e996731cda317
1 /*
2 * pcilynx.c - Texas Instruments PCILynx driver
3 * Copyright (C) 1999,2000 Andreas Bombe <andreas.bombe@munich.netsurf.de>,
4 * Stephan Linz <linz@mazet.de>
5 * Manfred Weihs <weihs@ict.tuwien.ac.at>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software Foundation,
19 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 /*
23 * Contributions:
24 *
25 * Manfred Weihs <weihs@ict.tuwien.ac.at>
26 * reading bus info block (containing GUID) from serial
27 * eeprom via i2c and storing it in config ROM
28 * Reworked code for initiating bus resets
29 * (long, short, with or without hold-off)
30 * Enhancements in async and iso send code
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/wait.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/moduleparam.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/fs.h>
43 #include <linux/poll.h>
44 #include <linux/kdev_t.h>
45 #include <linux/dma-mapping.h>
46 #include <asm/byteorder.h>
47 #include <asm/atomic.h>
48 #include <asm/io.h>
49 #include <asm/uaccess.h>
50 #include <asm/irq.h>
51
52 #include "csr1212.h"
53 #include "ieee1394.h"
54 #include "ieee1394_types.h"
55 #include "hosts.h"
56 #include "ieee1394_core.h"
57 #include "highlevel.h"
58 #include "pcilynx.h"
59
60 #include <linux/i2c.h>
61 #include <linux/i2c-algo-bit.h>
62
63 /* print general (card independent) information */
64 #define PRINT_G(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args)
65 /* print card specific information */
66 #define PRINT(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args)
67
68 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
69 #define PRINT_GD(level, fmt, args...) printk(level "pcilynx: " fmt "\n" , ## args)
70 #define PRINTD(level, card, fmt, args...) printk(level "pcilynx%d: " fmt "\n" , card , ## args)
71 #else
72 #define PRINT_GD(level, fmt, args...) do {} while (0)
73 #define PRINTD(level, card, fmt, args...) do {} while (0)
74 #endif
75
76
77 /* Module Parameters */
78 static int skip_eeprom;
79 module_param(skip_eeprom, int, 0444);
80 MODULE_PARM_DESC(skip_eeprom, "Use generic bus info block instead of serial eeprom (default = 0).");
81
82
83 static struct hpsb_host_driver lynx_driver;
84 static unsigned int card_id;
85
86
87
88 /*
89 * I2C stuff
90 */
91
92 /* the i2c stuff was inspired by i2c-philips-par.c */
93
94 static void bit_setscl(void *data, int state)
95 {
96 if (state) {
97 ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000040;
98 } else {
99 ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000040;
100 }
101 reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state);
102 }
103
104 static void bit_setsda(void *data, int state)
105 {
106 if (state) {
107 ((struct ti_lynx *) data)->i2c_driven_state |= 0x00000010;
108 } else {
109 ((struct ti_lynx *) data)->i2c_driven_state &= ~0x00000010;
110 }
111 reg_write((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL, ((struct ti_lynx *) data)->i2c_driven_state);
112 }
113
114 static int bit_getscl(void *data)
115 {
116 return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000040;
117 }
118
119 static int bit_getsda(void *data)
120 {
121 return reg_read((struct ti_lynx *) data, SERIAL_EEPROM_CONTROL) & 0x00000010;
122 }
123
124 static int bit_reg(struct i2c_client *client)
125 {
126 return 0;
127 }
128
129 static int bit_unreg(struct i2c_client *client)
130 {
131 return 0;
132 }
133
134 static struct i2c_algo_bit_data bit_data = {
135 .setsda = bit_setsda,
136 .setscl = bit_setscl,
137 .getsda = bit_getsda,
138 .getscl = bit_getscl,
139 .udelay = 5,
140 .timeout = 100,
141 };
142
143 static struct i2c_adapter bit_ops = {
144 .id = 0xAA, //FIXME: probably we should get an id in i2c-id.h
145 .client_register = bit_reg,
146 .client_unregister = bit_unreg,
147 .name = "PCILynx I2C",
148 };
149
150
151
152 /*
153 * PCL handling functions.
154 */
155
156 static pcl_t alloc_pcl(struct ti_lynx *lynx)
157 {
158 u8 m;
159 int i, j;
160
161 spin_lock(&lynx->lock);
162 /* FIXME - use ffz() to make this readable */
163 for (i = 0; i < (LOCALRAM_SIZE / 1024); i++) {
164 m = lynx->pcl_bmap[i];
165 for (j = 0; j < 8; j++) {
166 if (m & 1<<j) {
167 continue;
168 }
169 m |= 1<<j;
170 lynx->pcl_bmap[i] = m;
171 spin_unlock(&lynx->lock);
172 return 8 * i + j;
173 }
174 }
175 spin_unlock(&lynx->lock);
176
177 return -1;
178 }
179
180
181 #if 0
182 static void free_pcl(struct ti_lynx *lynx, pcl_t pclid)
183 {
184 int off, bit;
185
186 off = pclid / 8;
187 bit = pclid % 8;
188
189 if (pclid < 0) {
190 return;
191 }
192
193 spin_lock(&lynx->lock);
194 if (lynx->pcl_bmap[off] & 1<<bit) {
195 lynx->pcl_bmap[off] &= ~(1<<bit);
196 } else {
197 PRINT(KERN_ERR, lynx->id,
198 "attempted to free unallocated PCL %d", pclid);
199 }
200 spin_unlock(&lynx->lock);
201 }
202
203 /* functions useful for debugging */
204 static void pretty_print_pcl(const struct ti_pcl *pcl)
205 {
206 int i;
207
208 printk("PCL next %08x, userdata %08x, status %08x, remtrans %08x, nextbuf %08x\n",
209 pcl->next, pcl->user_data, pcl->pcl_status,
210 pcl->remaining_transfer_count, pcl->next_data_buffer);
211
212 printk("PCL");
213 for (i=0; i<13; i++) {
214 printk(" c%x:%08x d%x:%08x",
215 i, pcl->buffer[i].control, i, pcl->buffer[i].pointer);
216 if (!(i & 0x3) && (i != 12)) printk("\nPCL");
217 }
218 printk("\n");
219 }
220
221 static void print_pcl(const struct ti_lynx *lynx, pcl_t pclid)
222 {
223 struct ti_pcl pcl;
224
225 get_pcl(lynx, pclid, &pcl);
226 pretty_print_pcl(&pcl);
227 }
228 #endif
229
230
231
232 /***********************************
233 * IEEE-1394 functionality section *
234 ***********************************/
235
236
237 static int get_phy_reg(struct ti_lynx *lynx, int addr)
238 {
239 int retval;
240 int i = 0;
241
242 unsigned long flags;
243
244 if (addr > 15) {
245 PRINT(KERN_ERR, lynx->id,
246 "%s: PHY register address %d out of range",
247 __FUNCTION__, addr);
248 return -1;
249 }
250
251 spin_lock_irqsave(&lynx->phy_reg_lock, flags);
252
253 reg_write(lynx, LINK_PHY, LINK_PHY_READ | LINK_PHY_ADDR(addr));
254 do {
255 retval = reg_read(lynx, LINK_PHY);
256
257 if (i > 10000) {
258 PRINT(KERN_ERR, lynx->id, "%s: runaway loop, aborting",
259 __FUNCTION__);
260 retval = -1;
261 break;
262 }
263 i++;
264 } while ((retval & 0xf00) != LINK_PHY_RADDR(addr));
265
266 reg_write(lynx, LINK_INT_STATUS, LINK_INT_PHY_REG_RCVD);
267 spin_unlock_irqrestore(&lynx->phy_reg_lock, flags);
268
269 if (retval != -1) {
270 return retval & 0xff;
271 } else {
272 return -1;
273 }
274 }
275
276 static int set_phy_reg(struct ti_lynx *lynx, int addr, int val)
277 {
278 unsigned long flags;
279
280 if (addr > 15) {
281 PRINT(KERN_ERR, lynx->id,
282 "%s: PHY register address %d out of range", __FUNCTION__, addr);
283 return -1;
284 }
285
286 if (val > 0xff) {
287 PRINT(KERN_ERR, lynx->id,
288 "%s: PHY register value %d out of range", __FUNCTION__, val);
289 return -1;
290 }
291
292 spin_lock_irqsave(&lynx->phy_reg_lock, flags);
293
294 reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | LINK_PHY_ADDR(addr)
295 | LINK_PHY_WDATA(val));
296
297 spin_unlock_irqrestore(&lynx->phy_reg_lock, flags);
298
299 return 0;
300 }
301
302 static int sel_phy_reg_page(struct ti_lynx *lynx, int page)
303 {
304 int reg;
305
306 if (page > 7) {
307 PRINT(KERN_ERR, lynx->id,
308 "%s: PHY page %d out of range", __FUNCTION__, page);
309 return -1;
310 }
311
312 reg = get_phy_reg(lynx, 7);
313 if (reg != -1) {
314 reg &= 0x1f;
315 reg |= (page << 5);
316 set_phy_reg(lynx, 7, reg);
317 return 0;
318 } else {
319 return -1;
320 }
321 }
322
323 #if 0 /* not needed at this time */
324 static int sel_phy_reg_port(struct ti_lynx *lynx, int port)
325 {
326 int reg;
327
328 if (port > 15) {
329 PRINT(KERN_ERR, lynx->id,
330 "%s: PHY port %d out of range", __FUNCTION__, port);
331 return -1;
332 }
333
334 reg = get_phy_reg(lynx, 7);
335 if (reg != -1) {
336 reg &= 0xf0;
337 reg |= port;
338 set_phy_reg(lynx, 7, reg);
339 return 0;
340 } else {
341 return -1;
342 }
343 }
344 #endif
345
346 static u32 get_phy_vendorid(struct ti_lynx *lynx)
347 {
348 u32 pvid = 0;
349 sel_phy_reg_page(lynx, 1);
350 pvid |= (get_phy_reg(lynx, 10) << 16);
351 pvid |= (get_phy_reg(lynx, 11) << 8);
352 pvid |= get_phy_reg(lynx, 12);
353 PRINT(KERN_INFO, lynx->id, "PHY vendor id 0x%06x", pvid);
354 return pvid;
355 }
356
357 static u32 get_phy_productid(struct ti_lynx *lynx)
358 {
359 u32 id = 0;
360 sel_phy_reg_page(lynx, 1);
361 id |= (get_phy_reg(lynx, 13) << 16);
362 id |= (get_phy_reg(lynx, 14) << 8);
363 id |= get_phy_reg(lynx, 15);
364 PRINT(KERN_INFO, lynx->id, "PHY product id 0x%06x", id);
365 return id;
366 }
367
368 static quadlet_t generate_own_selfid(struct ti_lynx *lynx,
369 struct hpsb_host *host)
370 {
371 quadlet_t lsid;
372 char phyreg[7];
373 int i;
374
375 phyreg[0] = lynx->phy_reg0;
376 for (i = 1; i < 7; i++) {
377 phyreg[i] = get_phy_reg(lynx, i);
378 }
379
380 /* FIXME? We assume a TSB21LV03A phy here. This code doesn't support
381 more than 3 ports on the PHY anyway. */
382
383 lsid = 0x80400000 | ((phyreg[0] & 0xfc) << 22);
384 lsid |= (phyreg[1] & 0x3f) << 16; /* gap count */
385 lsid |= (phyreg[2] & 0xc0) << 8; /* max speed */
386 if (!hpsb_disable_irm)
387 lsid |= (phyreg[6] & 0x01) << 11; /* contender (phy dependent) */
388 /* lsid |= 1 << 11; *//* set contender (hack) */
389 lsid |= (phyreg[6] & 0x10) >> 3; /* initiated reset */
390
391 for (i = 0; i < (phyreg[2] & 0xf); i++) { /* ports */
392 if (phyreg[3 + i] & 0x4) {
393 lsid |= (((phyreg[3 + i] & 0x8) | 0x10) >> 3)
394 << (6 - i*2);
395 } else {
396 lsid |= 1 << (6 - i*2);
397 }
398 }
399
400 cpu_to_be32s(&lsid);
401 PRINT(KERN_DEBUG, lynx->id, "generated own selfid 0x%x", lsid);
402 return lsid;
403 }
404
405 static void handle_selfid(struct ti_lynx *lynx, struct hpsb_host *host)
406 {
407 quadlet_t *q = lynx->rcv_page;
408 int phyid, isroot, size;
409 quadlet_t lsid = 0;
410 int i;
411
412 if (lynx->phy_reg0 == -1 || lynx->selfid_size == -1) return;
413
414 size = lynx->selfid_size;
415 phyid = lynx->phy_reg0;
416
417 i = (size > 16 ? 16 : size) / 4 - 1;
418 while (i >= 0) {
419 cpu_to_be32s(&q[i]);
420 i--;
421 }
422
423 if (!lynx->phyic.reg_1394a) {
424 lsid = generate_own_selfid(lynx, host);
425 }
426
427 isroot = (phyid & 2) != 0;
428 phyid >>= 2;
429 PRINT(KERN_INFO, lynx->id, "SelfID process finished (phyid %d, %s)",
430 phyid, (isroot ? "root" : "not root"));
431 reg_write(lynx, LINK_ID, (0xffc0 | phyid) << 16);
432
433 if (!lynx->phyic.reg_1394a && !size) {
434 hpsb_selfid_received(host, lsid);
435 }
436
437 while (size > 0) {
438 struct selfid *sid = (struct selfid *)q;
439
440 if (!lynx->phyic.reg_1394a && !sid->extended
441 && (sid->phy_id == (phyid + 1))) {
442 hpsb_selfid_received(host, lsid);
443 }
444
445 if (q[0] == ~q[1]) {
446 PRINT(KERN_DEBUG, lynx->id, "SelfID packet 0x%x rcvd",
447 q[0]);
448 hpsb_selfid_received(host, q[0]);
449 } else {
450 PRINT(KERN_INFO, lynx->id,
451 "inconsistent selfid 0x%x/0x%x", q[0], q[1]);
452 }
453 q += 2;
454 size -= 8;
455 }
456
457 if (!lynx->phyic.reg_1394a && isroot && phyid != 0) {
458 hpsb_selfid_received(host, lsid);
459 }
460
461 hpsb_selfid_complete(host, phyid, isroot);
462
463 if (host->in_bus_reset) return; /* in bus reset again */
464
465 if (isroot) reg_set_bits(lynx, LINK_CONTROL, LINK_CONTROL_CYCMASTER); //FIXME: I do not think, we need this here
466 reg_set_bits(lynx, LINK_CONTROL,
467 LINK_CONTROL_RCV_CMP_VALID | LINK_CONTROL_TX_ASYNC_EN
468 | LINK_CONTROL_RX_ASYNC_EN | LINK_CONTROL_CYCTIMEREN);
469 }
470
471
472
473 /* This must be called with the respective queue_lock held. */
474 static void send_next(struct ti_lynx *lynx, int what)
475 {
476 struct ti_pcl pcl;
477 struct lynx_send_data *d;
478 struct hpsb_packet *packet;
479
480 #if 0 /* has been removed from ieee1394 core */
481 d = (what == hpsb_iso ? &lynx->iso_send : &lynx->async);
482 #else
483 d = &lynx->async;
484 #endif
485 if (!list_empty(&d->pcl_queue)) {
486 PRINT(KERN_ERR, lynx->id, "trying to queue a new packet in nonempty fifo");
487 BUG();
488 }
489
490 packet = driver_packet(d->queue.next);
491 list_move_tail(&packet->driver_list, &d->pcl_queue);
492
493 d->header_dma = pci_map_single(lynx->dev, packet->header,
494 packet->header_size, PCI_DMA_TODEVICE);
495 if (packet->data_size) {
496 d->data_dma = pci_map_single(lynx->dev, packet->data,
497 packet->data_size,
498 PCI_DMA_TODEVICE);
499 } else {
500 d->data_dma = 0;
501 }
502
503 pcl.next = PCL_NEXT_INVALID;
504 pcl.async_error_next = PCL_NEXT_INVALID;
505 pcl.pcl_status = 0;
506 pcl.buffer[0].control = packet->speed_code << 14 | packet->header_size;
507 #ifndef __BIG_ENDIAN
508 pcl.buffer[0].control |= PCL_BIGENDIAN;
509 #endif
510 pcl.buffer[0].pointer = d->header_dma;
511 pcl.buffer[1].control = PCL_LAST_BUFF | packet->data_size;
512 pcl.buffer[1].pointer = d->data_dma;
513
514 switch (packet->type) {
515 case hpsb_async:
516 pcl.buffer[0].control |= PCL_CMD_XMT;
517 break;
518 #if 0 /* has been removed from ieee1394 core */
519 case hpsb_iso:
520 pcl.buffer[0].control |= PCL_CMD_XMT | PCL_ISOMODE;
521 break;
522 #endif
523 case hpsb_raw:
524 pcl.buffer[0].control |= PCL_CMD_UNFXMT;
525 break;
526 }
527
528 put_pcl(lynx, d->pcl, &pcl);
529 run_pcl(lynx, d->pcl_start, d->channel);
530 }
531
532
533 /* called from subsystem core */
534 static int lynx_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
535 {
536 struct ti_lynx *lynx = host->hostdata;
537 struct lynx_send_data *d;
538 unsigned long flags;
539
540 if (packet->data_size >= 4096) {
541 PRINT(KERN_ERR, lynx->id, "transmit packet data too big (%Zd)",
542 packet->data_size);
543 return -EOVERFLOW;
544 }
545
546 switch (packet->type) {
547 case hpsb_async:
548 case hpsb_raw:
549 d = &lynx->async;
550 break;
551 #if 0 /* has been removed from ieee1394 core */
552 case hpsb_iso:
553 d = &lynx->iso_send;
554 break;
555 #endif
556 default:
557 PRINT(KERN_ERR, lynx->id, "invalid packet type %d",
558 packet->type);
559 return -EINVAL;
560 }
561
562 if (packet->tcode == TCODE_WRITEQ
563 || packet->tcode == TCODE_READQ_RESPONSE) {
564 cpu_to_be32s(&packet->header[3]);
565 }
566
567 spin_lock_irqsave(&d->queue_lock, flags);
568
569 list_add_tail(&packet->driver_list, &d->queue);
570 if (list_empty(&d->pcl_queue))
571 send_next(lynx, packet->type);
572
573 spin_unlock_irqrestore(&d->queue_lock, flags);
574
575 return 0;
576 }
577
578
579 /* called from subsystem core */
580 static int lynx_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
581 {
582 struct ti_lynx *lynx = host->hostdata;
583 int retval = 0;
584 struct hpsb_packet *packet;
585 LIST_HEAD(packet_list);
586 unsigned long flags;
587 int phy_reg;
588
589 switch (cmd) {
590 case RESET_BUS:
591 if (reg_read(lynx, LINK_INT_STATUS) & LINK_INT_PHY_BUSRESET) {
592 retval = 0;
593 break;
594 }
595
596 switch (arg) {
597 case SHORT_RESET:
598 if (lynx->phyic.reg_1394a) {
599 phy_reg = get_phy_reg(lynx, 5);
600 if (phy_reg == -1) {
601 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
602 retval = -1;
603 break;
604 }
605 phy_reg |= 0x40;
606
607 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset) on request");
608
609 lynx->selfid_size = -1;
610 lynx->phy_reg0 = -1;
611 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
612 break;
613 } else {
614 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
615 /* fall through to long bus reset */
616 }
617 case LONG_RESET:
618 phy_reg = get_phy_reg(lynx, 1);
619 if (phy_reg == -1) {
620 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
621 retval = -1;
622 break;
623 }
624 phy_reg |= 0x40;
625
626 PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset) on request");
627
628 lynx->selfid_size = -1;
629 lynx->phy_reg0 = -1;
630 set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */
631 break;
632 case SHORT_RESET_NO_FORCE_ROOT:
633 if (lynx->phyic.reg_1394a) {
634 phy_reg = get_phy_reg(lynx, 1);
635 if (phy_reg == -1) {
636 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
637 retval = -1;
638 break;
639 }
640 if (phy_reg & 0x80) {
641 phy_reg &= ~0x80;
642 set_phy_reg(lynx, 1, phy_reg); /* clear RHB */
643 }
644
645 phy_reg = get_phy_reg(lynx, 5);
646 if (phy_reg == -1) {
647 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
648 retval = -1;
649 break;
650 }
651 phy_reg |= 0x40;
652
653 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, no force_root) on request");
654
655 lynx->selfid_size = -1;
656 lynx->phy_reg0 = -1;
657 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
658 break;
659 } else {
660 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
661 /* fall through to long bus reset */
662 }
663 case LONG_RESET_NO_FORCE_ROOT:
664 phy_reg = get_phy_reg(lynx, 1);
665 if (phy_reg == -1) {
666 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
667 retval = -1;
668 break;
669 }
670 phy_reg &= ~0x80;
671 phy_reg |= 0x40;
672
673 PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, no force_root) on request");
674
675 lynx->selfid_size = -1;
676 lynx->phy_reg0 = -1;
677 set_phy_reg(lynx, 1, phy_reg); /* clear RHB, set IBR */
678 break;
679 case SHORT_RESET_FORCE_ROOT:
680 if (lynx->phyic.reg_1394a) {
681 phy_reg = get_phy_reg(lynx, 1);
682 if (phy_reg == -1) {
683 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
684 retval = -1;
685 break;
686 }
687 if (!(phy_reg & 0x80)) {
688 phy_reg |= 0x80;
689 set_phy_reg(lynx, 1, phy_reg); /* set RHB */
690 }
691
692 phy_reg = get_phy_reg(lynx, 5);
693 if (phy_reg == -1) {
694 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
695 retval = -1;
696 break;
697 }
698 phy_reg |= 0x40;
699
700 PRINT(KERN_INFO, lynx->id, "resetting bus (short bus reset, force_root set) on request");
701
702 lynx->selfid_size = -1;
703 lynx->phy_reg0 = -1;
704 set_phy_reg(lynx, 5, phy_reg); /* set ISBR */
705 break;
706 } else {
707 PRINT(KERN_INFO, lynx->id, "cannot do short bus reset, because of old phy");
708 /* fall through to long bus reset */
709 }
710 case LONG_RESET_FORCE_ROOT:
711 phy_reg = get_phy_reg(lynx, 1);
712 if (phy_reg == -1) {
713 PRINT(KERN_ERR, lynx->id, "cannot reset bus, because read phy reg failed");
714 retval = -1;
715 break;
716 }
717 phy_reg |= 0xc0;
718
719 PRINT(KERN_INFO, lynx->id, "resetting bus (long bus reset, force_root set) on request");
720
721 lynx->selfid_size = -1;
722 lynx->phy_reg0 = -1;
723 set_phy_reg(lynx, 1, phy_reg); /* set IBR and RHB */
724 break;
725 default:
726 PRINT(KERN_ERR, lynx->id, "unknown argument for reset_bus command %d", arg);
727 retval = -1;
728 }
729
730 break;
731
732 case GET_CYCLE_COUNTER:
733 retval = reg_read(lynx, CYCLE_TIMER);
734 break;
735
736 case SET_CYCLE_COUNTER:
737 reg_write(lynx, CYCLE_TIMER, arg);
738 break;
739
740 case SET_BUS_ID:
741 reg_write(lynx, LINK_ID,
742 (arg << 22) | (reg_read(lynx, LINK_ID) & 0x003f0000));
743 break;
744
745 case ACT_CYCLE_MASTER:
746 if (arg) {
747 reg_set_bits(lynx, LINK_CONTROL,
748 LINK_CONTROL_CYCMASTER);
749 } else {
750 reg_clear_bits(lynx, LINK_CONTROL,
751 LINK_CONTROL_CYCMASTER);
752 }
753 break;
754
755 case CANCEL_REQUESTS:
756 spin_lock_irqsave(&lynx->async.queue_lock, flags);
757
758 reg_write(lynx, DMA_CHAN_CTRL(CHANNEL_ASYNC_SEND), 0);
759 list_splice(&lynx->async.queue, &packet_list);
760 INIT_LIST_HEAD(&lynx->async.queue);
761
762 if (list_empty(&lynx->async.pcl_queue)) {
763 spin_unlock_irqrestore(&lynx->async.queue_lock, flags);
764 PRINTD(KERN_DEBUG, lynx->id, "no async packet in PCL to cancel");
765 } else {
766 struct ti_pcl pcl;
767 u32 ack;
768 struct hpsb_packet *packet;
769
770 PRINT(KERN_INFO, lynx->id, "cancelling async packet, that was already in PCL");
771
772 get_pcl(lynx, lynx->async.pcl, &pcl);
773
774 packet = driver_packet(lynx->async.pcl_queue.next);
775 list_del_init(&packet->driver_list);
776
777 pci_unmap_single(lynx->dev, lynx->async.header_dma,
778 packet->header_size, PCI_DMA_TODEVICE);
779 if (packet->data_size) {
780 pci_unmap_single(lynx->dev, lynx->async.data_dma,
781 packet->data_size, PCI_DMA_TODEVICE);
782 }
783
784 spin_unlock_irqrestore(&lynx->async.queue_lock, flags);
785
786 if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
787 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
788 ack = (pcl.pcl_status >> 15) & 0xf;
789 PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
790 ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
791 } else {
792 ack = (pcl.pcl_status >> 15) & 0xf;
793 }
794 } else {
795 PRINT(KERN_INFO, lynx->id, "async packet was not completed");
796 ack = ACKX_ABORTED;
797 }
798 hpsb_packet_sent(host, packet, ack);
799 }
800
801 while (!list_empty(&packet_list)) {
802 packet = driver_packet(packet_list.next);
803 list_del_init(&packet->driver_list);
804 hpsb_packet_sent(host, packet, ACKX_ABORTED);
805 }
806
807 break;
808 #if 0 /* has been removed from ieee1394 core */
809 case ISO_LISTEN_CHANNEL:
810 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
811
812 if (lynx->iso_rcv.chan_count++ == 0) {
813 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
814 DMA_WORD1_CMP_ENABLE_MASTER);
815 }
816
817 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
818 break;
819
820 case ISO_UNLISTEN_CHANNEL:
821 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
822
823 if (--lynx->iso_rcv.chan_count == 0) {
824 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
825 0);
826 }
827
828 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
829 break;
830 #endif
831 default:
832 PRINT(KERN_ERR, lynx->id, "unknown devctl command %d", cmd);
833 retval = -1;
834 }
835
836 return retval;
837 }
838
839
840 /***************************************
841 * IEEE-1394 functionality section END *
842 ***************************************/
843
844
845 /********************************************************
846 * Global stuff (interrupt handler, init/shutdown code) *
847 ********************************************************/
848
849
850 static irqreturn_t lynx_irq_handler(int irq, void *dev_id)
851 {
852 struct ti_lynx *lynx = (struct ti_lynx *)dev_id;
853 struct hpsb_host *host = lynx->host;
854 u32 intmask;
855 u32 linkint;
856
857 linkint = reg_read(lynx, LINK_INT_STATUS);
858 intmask = reg_read(lynx, PCI_INT_STATUS);
859
860 if (!(intmask & PCI_INT_INT_PEND))
861 return IRQ_NONE;
862
863 PRINTD(KERN_DEBUG, lynx->id, "interrupt: 0x%08x / 0x%08x", intmask,
864 linkint);
865
866 reg_write(lynx, LINK_INT_STATUS, linkint);
867 reg_write(lynx, PCI_INT_STATUS, intmask);
868
869 if (intmask & PCI_INT_1394) {
870 if (linkint & LINK_INT_PHY_TIMEOUT) {
871 PRINT(KERN_INFO, lynx->id, "PHY timeout occurred");
872 }
873 if (linkint & LINK_INT_PHY_BUSRESET) {
874 PRINT(KERN_INFO, lynx->id, "bus reset interrupt");
875 lynx->selfid_size = -1;
876 lynx->phy_reg0 = -1;
877 if (!host->in_bus_reset)
878 hpsb_bus_reset(host);
879 }
880 if (linkint & LINK_INT_PHY_REG_RCVD) {
881 u32 reg;
882
883 spin_lock(&lynx->phy_reg_lock);
884 reg = reg_read(lynx, LINK_PHY);
885 spin_unlock(&lynx->phy_reg_lock);
886
887 if (!host->in_bus_reset) {
888 PRINT(KERN_INFO, lynx->id,
889 "phy reg received without reset");
890 } else if (reg & 0xf00) {
891 PRINT(KERN_INFO, lynx->id,
892 "unsolicited phy reg %d received",
893 (reg >> 8) & 0xf);
894 } else {
895 lynx->phy_reg0 = reg & 0xff;
896 handle_selfid(lynx, host);
897 }
898 }
899 if (linkint & LINK_INT_ISO_STUCK) {
900 PRINT(KERN_INFO, lynx->id, "isochronous transmitter stuck");
901 }
902 if (linkint & LINK_INT_ASYNC_STUCK) {
903 PRINT(KERN_INFO, lynx->id, "asynchronous transmitter stuck");
904 }
905 if (linkint & LINK_INT_SENT_REJECT) {
906 PRINT(KERN_INFO, lynx->id, "sent reject");
907 }
908 if (linkint & LINK_INT_TX_INVALID_TC) {
909 PRINT(KERN_INFO, lynx->id, "invalid transaction code");
910 }
911 if (linkint & LINK_INT_GRF_OVERFLOW) {
912 /* flush FIFO if overflow happens during reset */
913 if (host->in_bus_reset)
914 reg_write(lynx, FIFO_CONTROL,
915 FIFO_CONTROL_GRF_FLUSH);
916 PRINT(KERN_INFO, lynx->id, "GRF overflow");
917 }
918 if (linkint & LINK_INT_ITF_UNDERFLOW) {
919 PRINT(KERN_INFO, lynx->id, "ITF underflow");
920 }
921 if (linkint & LINK_INT_ATF_UNDERFLOW) {
922 PRINT(KERN_INFO, lynx->id, "ATF underflow");
923 }
924 }
925
926 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_RCV)) {
927 PRINTD(KERN_DEBUG, lynx->id, "iso receive");
928
929 spin_lock(&lynx->iso_rcv.lock);
930
931 lynx->iso_rcv.stat[lynx->iso_rcv.next] =
932 reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ISO_RCV));
933
934 lynx->iso_rcv.used++;
935 lynx->iso_rcv.next = (lynx->iso_rcv.next + 1) % NUM_ISORCV_PCL;
936
937 if ((lynx->iso_rcv.next == lynx->iso_rcv.last)
938 || !lynx->iso_rcv.chan_count) {
939 PRINTD(KERN_DEBUG, lynx->id, "stopped");
940 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0);
941 }
942
943 run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, lynx->iso_rcv.next,
944 CHANNEL_ISO_RCV);
945
946 spin_unlock(&lynx->iso_rcv.lock);
947
948 tasklet_schedule(&lynx->iso_rcv.tq);
949 }
950
951 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_SEND)) {
952 PRINTD(KERN_DEBUG, lynx->id, "async sent");
953 spin_lock(&lynx->async.queue_lock);
954
955 if (list_empty(&lynx->async.pcl_queue)) {
956 spin_unlock(&lynx->async.queue_lock);
957 PRINT(KERN_WARNING, lynx->id, "async dma halted, but no queued packet (maybe it was cancelled)");
958 } else {
959 struct ti_pcl pcl;
960 u32 ack;
961 struct hpsb_packet *packet;
962
963 get_pcl(lynx, lynx->async.pcl, &pcl);
964
965 packet = driver_packet(lynx->async.pcl_queue.next);
966 list_del_init(&packet->driver_list);
967
968 pci_unmap_single(lynx->dev, lynx->async.header_dma,
969 packet->header_size, PCI_DMA_TODEVICE);
970 if (packet->data_size) {
971 pci_unmap_single(lynx->dev, lynx->async.data_dma,
972 packet->data_size, PCI_DMA_TODEVICE);
973 }
974
975 if (!list_empty(&lynx->async.queue)) {
976 send_next(lynx, hpsb_async);
977 }
978
979 spin_unlock(&lynx->async.queue_lock);
980
981 if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
982 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
983 ack = (pcl.pcl_status >> 15) & 0xf;
984 PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
985 ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
986 } else {
987 ack = (pcl.pcl_status >> 15) & 0xf;
988 }
989 } else {
990 PRINT(KERN_INFO, lynx->id, "async packet was not completed");
991 ack = ACKX_SEND_ERROR;
992 }
993 hpsb_packet_sent(host, packet, ack);
994 }
995 }
996
997 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ISO_SEND)) {
998 PRINTD(KERN_DEBUG, lynx->id, "iso sent");
999 spin_lock(&lynx->iso_send.queue_lock);
1000
1001 if (list_empty(&lynx->iso_send.pcl_queue)) {
1002 spin_unlock(&lynx->iso_send.queue_lock);
1003 PRINT(KERN_ERR, lynx->id, "iso send dma halted, but no queued packet");
1004 } else {
1005 struct ti_pcl pcl;
1006 u32 ack;
1007 struct hpsb_packet *packet;
1008
1009 get_pcl(lynx, lynx->iso_send.pcl, &pcl);
1010
1011 packet = driver_packet(lynx->iso_send.pcl_queue.next);
1012 list_del_init(&packet->driver_list);
1013
1014 pci_unmap_single(lynx->dev, lynx->iso_send.header_dma,
1015 packet->header_size, PCI_DMA_TODEVICE);
1016 if (packet->data_size) {
1017 pci_unmap_single(lynx->dev, lynx->iso_send.data_dma,
1018 packet->data_size, PCI_DMA_TODEVICE);
1019 }
1020 #if 0 /* has been removed from ieee1394 core */
1021 if (!list_empty(&lynx->iso_send.queue)) {
1022 send_next(lynx, hpsb_iso);
1023 }
1024 #endif
1025 spin_unlock(&lynx->iso_send.queue_lock);
1026
1027 if (pcl.pcl_status & DMA_CHAN_STAT_PKTCMPL) {
1028 if (pcl.pcl_status & DMA_CHAN_STAT_SPECIALACK) {
1029 ack = (pcl.pcl_status >> 15) & 0xf;
1030 PRINTD(KERN_INFO, lynx->id, "special ack %d", ack);
1031 ack = (ack == 1 ? ACKX_TIMEOUT : ACKX_SEND_ERROR);
1032 } else {
1033 ack = (pcl.pcl_status >> 15) & 0xf;
1034 }
1035 } else {
1036 PRINT(KERN_INFO, lynx->id, "iso send packet was not completed");
1037 ack = ACKX_SEND_ERROR;
1038 }
1039
1040 hpsb_packet_sent(host, packet, ack); //FIXME: maybe we should just use ACK_COMPLETE and ACKX_SEND_ERROR
1041 }
1042 }
1043
1044 if (intmask & PCI_INT_DMA_HLT(CHANNEL_ASYNC_RCV)) {
1045 /* general receive DMA completed */
1046 int stat = reg_read(lynx, DMA_CHAN_STAT(CHANNEL_ASYNC_RCV));
1047
1048 PRINTD(KERN_DEBUG, lynx->id, "received packet size %d",
1049 stat & 0x1fff);
1050
1051 if (stat & DMA_CHAN_STAT_SELFID) {
1052 lynx->selfid_size = stat & 0x1fff;
1053 handle_selfid(lynx, host);
1054 } else {
1055 quadlet_t *q_data = lynx->rcv_page;
1056 if ((*q_data >> 4 & 0xf) == TCODE_READQ_RESPONSE
1057 || (*q_data >> 4 & 0xf) == TCODE_WRITEQ) {
1058 cpu_to_be32s(q_data + 3);
1059 }
1060 hpsb_packet_received(host, q_data, stat & 0x1fff, 0);
1061 }
1062
1063 run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV);
1064 }
1065
1066 return IRQ_HANDLED;
1067 }
1068
1069
1070 static void iso_rcv_bh(struct ti_lynx *lynx)
1071 {
1072 unsigned int idx;
1073 quadlet_t *data;
1074 unsigned long flags;
1075
1076 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
1077
1078 while (lynx->iso_rcv.used) {
1079 idx = lynx->iso_rcv.last;
1080 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
1081
1082 data = lynx->iso_rcv.page[idx / ISORCV_PER_PAGE]
1083 + (idx % ISORCV_PER_PAGE) * MAX_ISORCV_SIZE;
1084
1085 if ((*data >> 16) + 4 != (lynx->iso_rcv.stat[idx] & 0x1fff)) {
1086 PRINT(KERN_ERR, lynx->id,
1087 "iso length mismatch 0x%08x/0x%08x", *data,
1088 lynx->iso_rcv.stat[idx]);
1089 }
1090
1091 if (lynx->iso_rcv.stat[idx]
1092 & (DMA_CHAN_STAT_PCIERR | DMA_CHAN_STAT_PKTERR)) {
1093 PRINT(KERN_INFO, lynx->id,
1094 "iso receive error on %d to 0x%p", idx, data);
1095 } else {
1096 hpsb_packet_received(lynx->host, data,
1097 lynx->iso_rcv.stat[idx] & 0x1fff,
1098 0);
1099 }
1100
1101 spin_lock_irqsave(&lynx->iso_rcv.lock, flags);
1102 lynx->iso_rcv.last = (idx + 1) % NUM_ISORCV_PCL;
1103 lynx->iso_rcv.used--;
1104 }
1105
1106 if (lynx->iso_rcv.chan_count) {
1107 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV),
1108 DMA_WORD1_CMP_ENABLE_MASTER);
1109 }
1110 spin_unlock_irqrestore(&lynx->iso_rcv.lock, flags);
1111 }
1112
1113
1114 static void remove_card(struct pci_dev *dev)
1115 {
1116 struct ti_lynx *lynx;
1117 struct device *lynx_dev;
1118 int i;
1119
1120 lynx = pci_get_drvdata(dev);
1121 if (!lynx) return;
1122 pci_set_drvdata(dev, NULL);
1123
1124 lynx_dev = get_device(&lynx->host->device);
1125
1126 switch (lynx->state) {
1127 case is_host:
1128 reg_write(lynx, PCI_INT_ENABLE, 0);
1129 hpsb_remove_host(lynx->host);
1130 case have_intr:
1131 reg_write(lynx, PCI_INT_ENABLE, 0);
1132 free_irq(lynx->dev->irq, lynx);
1133
1134 /* Disable IRM Contender and LCtrl */
1135 if (lynx->phyic.reg_1394a)
1136 set_phy_reg(lynx, 4, ~0xc0 & get_phy_reg(lynx, 4));
1137
1138 /* Let all other nodes know to ignore us */
1139 lynx_devctl(lynx->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT);
1140
1141 case have_iomappings:
1142 reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET);
1143 /* Fix buggy cards with autoboot pin not tied low: */
1144 reg_write(lynx, DMA0_CHAN_CTRL, 0);
1145 iounmap(lynx->registers);
1146 iounmap(lynx->local_rom);
1147 iounmap(lynx->local_ram);
1148 iounmap(lynx->aux_port);
1149 case have_1394_buffers:
1150 for (i = 0; i < ISORCV_PAGES; i++) {
1151 if (lynx->iso_rcv.page[i]) {
1152 pci_free_consistent(lynx->dev, PAGE_SIZE,
1153 lynx->iso_rcv.page[i],
1154 lynx->iso_rcv.page_dma[i]);
1155 }
1156 }
1157 pci_free_consistent(lynx->dev, PAGE_SIZE, lynx->rcv_page,
1158 lynx->rcv_page_dma);
1159 case have_aux_buf:
1160 case have_pcl_mem:
1161 pci_free_consistent(lynx->dev, LOCALRAM_SIZE, lynx->pcl_mem,
1162 lynx->pcl_mem_dma);
1163 case clear:
1164 /* do nothing - already freed */
1165 ;
1166 }
1167
1168 tasklet_kill(&lynx->iso_rcv.tq);
1169
1170 if (lynx_dev)
1171 put_device(lynx_dev);
1172 }
1173
1174
1175 static int __devinit add_card(struct pci_dev *dev,
1176 const struct pci_device_id *devid_is_unused)
1177 {
1178 #define FAIL(fmt, args...) do { \
1179 PRINT_G(KERN_ERR, fmt , ## args); \
1180 remove_card(dev); \
1181 return error; \
1182 } while (0)
1183
1184 char irq_buf[16];
1185 struct hpsb_host *host;
1186 struct ti_lynx *lynx; /* shortcut to currently handled device */
1187 struct ti_pcl pcl;
1188 u32 *pcli;
1189 int i;
1190 int error;
1191
1192 error = -ENXIO;
1193
1194 if (pci_set_dma_mask(dev, DMA_32BIT_MASK))
1195 FAIL("DMA address limits not supported for PCILynx hardware");
1196 if (pci_enable_device(dev))
1197 FAIL("failed to enable PCILynx hardware");
1198 pci_set_master(dev);
1199
1200 error = -ENOMEM;
1201
1202 host = hpsb_alloc_host(&lynx_driver, sizeof(struct ti_lynx), &dev->dev);
1203 if (!host) FAIL("failed to allocate control structure memory");
1204
1205 lynx = host->hostdata;
1206 lynx->id = card_id++;
1207 lynx->dev = dev;
1208 lynx->state = clear;
1209 lynx->host = host;
1210 host->pdev = dev;
1211 pci_set_drvdata(dev, lynx);
1212
1213 spin_lock_init(&lynx->lock);
1214 spin_lock_init(&lynx->phy_reg_lock);
1215
1216 lynx->pcl_mem = pci_alloc_consistent(dev, LOCALRAM_SIZE,
1217 &lynx->pcl_mem_dma);
1218
1219 if (lynx->pcl_mem != NULL) {
1220 lynx->state = have_pcl_mem;
1221 PRINT(KERN_INFO, lynx->id,
1222 "allocated PCL memory %d Bytes @ 0x%p", LOCALRAM_SIZE,
1223 lynx->pcl_mem);
1224 } else {
1225 FAIL("failed to allocate PCL memory area");
1226 }
1227
1228 lynx->rcv_page = pci_alloc_consistent(dev, PAGE_SIZE,
1229 &lynx->rcv_page_dma);
1230 if (lynx->rcv_page == NULL) {
1231 FAIL("failed to allocate receive buffer");
1232 }
1233 lynx->state = have_1394_buffers;
1234
1235 for (i = 0; i < ISORCV_PAGES; i++) {
1236 lynx->iso_rcv.page[i] =
1237 pci_alloc_consistent(dev, PAGE_SIZE,
1238 &lynx->iso_rcv.page_dma[i]);
1239 if (lynx->iso_rcv.page[i] == NULL) {
1240 FAIL("failed to allocate iso receive buffers");
1241 }
1242 }
1243
1244 lynx->registers = ioremap_nocache(pci_resource_start(dev,0),
1245 PCILYNX_MAX_REGISTER);
1246 lynx->local_ram = ioremap(pci_resource_start(dev,1), PCILYNX_MAX_MEMORY);
1247 lynx->aux_port = ioremap(pci_resource_start(dev,2), PCILYNX_MAX_MEMORY);
1248 lynx->local_rom = ioremap(pci_resource_start(dev,PCI_ROM_RESOURCE),
1249 PCILYNX_MAX_MEMORY);
1250 lynx->state = have_iomappings;
1251
1252 if (lynx->registers == NULL) {
1253 FAIL("failed to remap registers - card not accessible");
1254 }
1255
1256 reg_set_bits(lynx, MISC_CONTROL, MISC_CONTROL_SWRESET);
1257 /* Fix buggy cards with autoboot pin not tied low: */
1258 reg_write(lynx, DMA0_CHAN_CTRL, 0);
1259
1260 sprintf (irq_buf, "%d", dev->irq);
1261
1262 if (!request_irq(dev->irq, lynx_irq_handler, IRQF_SHARED,
1263 PCILYNX_DRIVER_NAME, lynx)) {
1264 PRINT(KERN_INFO, lynx->id, "allocated interrupt %s", irq_buf);
1265 lynx->state = have_intr;
1266 } else {
1267 FAIL("failed to allocate shared interrupt %s", irq_buf);
1268 }
1269
1270 /* alloc_pcl return values are not checked, it is expected that the
1271 * provided PCL space is sufficient for the initial allocations */
1272 lynx->rcv_pcl = alloc_pcl(lynx);
1273 lynx->rcv_pcl_start = alloc_pcl(lynx);
1274 lynx->async.pcl = alloc_pcl(lynx);
1275 lynx->async.pcl_start = alloc_pcl(lynx);
1276 lynx->iso_send.pcl = alloc_pcl(lynx);
1277 lynx->iso_send.pcl_start = alloc_pcl(lynx);
1278
1279 for (i = 0; i < NUM_ISORCV_PCL; i++) {
1280 lynx->iso_rcv.pcl[i] = alloc_pcl(lynx);
1281 }
1282 lynx->iso_rcv.pcl_start = alloc_pcl(lynx);
1283
1284 /* all allocations successful - simple init stuff follows */
1285
1286 reg_write(lynx, PCI_INT_ENABLE, PCI_INT_DMA_ALL);
1287
1288 tasklet_init(&lynx->iso_rcv.tq, (void (*)(unsigned long))iso_rcv_bh,
1289 (unsigned long)lynx);
1290
1291 spin_lock_init(&lynx->iso_rcv.lock);
1292
1293 spin_lock_init(&lynx->async.queue_lock);
1294 lynx->async.channel = CHANNEL_ASYNC_SEND;
1295 spin_lock_init(&lynx->iso_send.queue_lock);
1296 lynx->iso_send.channel = CHANNEL_ISO_SEND;
1297
1298 PRINT(KERN_INFO, lynx->id, "remapped memory spaces reg 0x%p, rom 0x%p, "
1299 "ram 0x%p, aux 0x%p", lynx->registers, lynx->local_rom,
1300 lynx->local_ram, lynx->aux_port);
1301
1302 /* now, looking for PHY register set */
1303 if ((get_phy_reg(lynx, 2) & 0xe0) == 0xe0) {
1304 lynx->phyic.reg_1394a = 1;
1305 PRINT(KERN_INFO, lynx->id,
1306 "found 1394a conform PHY (using extended register set)");
1307 lynx->phyic.vendor = get_phy_vendorid(lynx);
1308 lynx->phyic.product = get_phy_productid(lynx);
1309 } else {
1310 lynx->phyic.reg_1394a = 0;
1311 PRINT(KERN_INFO, lynx->id, "found old 1394 PHY");
1312 }
1313
1314 lynx->selfid_size = -1;
1315 lynx->phy_reg0 = -1;
1316
1317 INIT_LIST_HEAD(&lynx->async.queue);
1318 INIT_LIST_HEAD(&lynx->async.pcl_queue);
1319 INIT_LIST_HEAD(&lynx->iso_send.queue);
1320 INIT_LIST_HEAD(&lynx->iso_send.pcl_queue);
1321
1322 pcl.next = pcl_bus(lynx, lynx->rcv_pcl);
1323 put_pcl(lynx, lynx->rcv_pcl_start, &pcl);
1324
1325 pcl.next = PCL_NEXT_INVALID;
1326 pcl.async_error_next = PCL_NEXT_INVALID;
1327
1328 pcl.buffer[0].control = PCL_CMD_RCV | 16;
1329 #ifndef __BIG_ENDIAN
1330 pcl.buffer[0].control |= PCL_BIGENDIAN;
1331 #endif
1332 pcl.buffer[1].control = PCL_LAST_BUFF | 4080;
1333
1334 pcl.buffer[0].pointer = lynx->rcv_page_dma;
1335 pcl.buffer[1].pointer = lynx->rcv_page_dma + 16;
1336 put_pcl(lynx, lynx->rcv_pcl, &pcl);
1337
1338 pcl.next = pcl_bus(lynx, lynx->async.pcl);
1339 pcl.async_error_next = pcl_bus(lynx, lynx->async.pcl);
1340 put_pcl(lynx, lynx->async.pcl_start, &pcl);
1341
1342 pcl.next = pcl_bus(lynx, lynx->iso_send.pcl);
1343 pcl.async_error_next = PCL_NEXT_INVALID;
1344 put_pcl(lynx, lynx->iso_send.pcl_start, &pcl);
1345
1346 pcl.next = PCL_NEXT_INVALID;
1347 pcl.async_error_next = PCL_NEXT_INVALID;
1348 pcl.buffer[0].control = PCL_CMD_RCV | 4;
1349 #ifndef __BIG_ENDIAN
1350 pcl.buffer[0].control |= PCL_BIGENDIAN;
1351 #endif
1352 pcl.buffer[1].control = PCL_LAST_BUFF | 2044;
1353
1354 for (i = 0; i < NUM_ISORCV_PCL; i++) {
1355 int page = i / ISORCV_PER_PAGE;
1356 int sec = i % ISORCV_PER_PAGE;
1357
1358 pcl.buffer[0].pointer = lynx->iso_rcv.page_dma[page]
1359 + sec * MAX_ISORCV_SIZE;
1360 pcl.buffer[1].pointer = pcl.buffer[0].pointer + 4;
1361 put_pcl(lynx, lynx->iso_rcv.pcl[i], &pcl);
1362 }
1363
1364 pcli = (u32 *)&pcl;
1365 for (i = 0; i < NUM_ISORCV_PCL; i++) {
1366 pcli[i] = pcl_bus(lynx, lynx->iso_rcv.pcl[i]);
1367 }
1368 put_pcl(lynx, lynx->iso_rcv.pcl_start, &pcl);
1369
1370 /* FIFO sizes from left to right: ITF=48 ATF=48 GRF=160 */
1371 reg_write(lynx, FIFO_SIZES, 0x003030a0);
1372 /* 20 byte threshold before triggering PCI transfer */
1373 reg_write(lynx, DMA_GLOBAL_REGISTER, 0x2<<24);
1374 /* threshold on both send FIFOs before transmitting:
1375 FIFO size - cache line size - 1 */
1376 i = reg_read(lynx, PCI_LATENCY_CACHELINE) & 0xff;
1377 i = 0x30 - i - 1;
1378 reg_write(lynx, FIFO_XMIT_THRESHOLD, (i << 8) | i);
1379
1380 reg_set_bits(lynx, PCI_INT_ENABLE, PCI_INT_1394);
1381
1382 reg_write(lynx, LINK_INT_ENABLE, LINK_INT_PHY_TIMEOUT
1383 | LINK_INT_PHY_REG_RCVD | LINK_INT_PHY_BUSRESET
1384 | LINK_INT_ISO_STUCK | LINK_INT_ASYNC_STUCK
1385 | LINK_INT_SENT_REJECT | LINK_INT_TX_INVALID_TC
1386 | LINK_INT_GRF_OVERFLOW | LINK_INT_ITF_UNDERFLOW
1387 | LINK_INT_ATF_UNDERFLOW);
1388
1389 reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ASYNC_RCV), 0);
1390 reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ASYNC_RCV), 0xa<<4);
1391 reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ASYNC_RCV), 0);
1392 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ASYNC_RCV),
1393 DMA_WORD1_CMP_MATCH_LOCAL_NODE | DMA_WORD1_CMP_MATCH_BROADCAST
1394 | DMA_WORD1_CMP_MATCH_EXACT | DMA_WORD1_CMP_MATCH_BUS_BCAST
1395 | DMA_WORD1_CMP_ENABLE_SELF_ID | DMA_WORD1_CMP_ENABLE_MASTER);
1396
1397 run_pcl(lynx, lynx->rcv_pcl_start, CHANNEL_ASYNC_RCV);
1398
1399 reg_write(lynx, DMA_WORD0_CMP_VALUE(CHANNEL_ISO_RCV), 0);
1400 reg_write(lynx, DMA_WORD0_CMP_ENABLE(CHANNEL_ISO_RCV), 0x9<<4);
1401 reg_write(lynx, DMA_WORD1_CMP_VALUE(CHANNEL_ISO_RCV), 0);
1402 reg_write(lynx, DMA_WORD1_CMP_ENABLE(CHANNEL_ISO_RCV), 0);
1403
1404 run_sub_pcl(lynx, lynx->iso_rcv.pcl_start, 0, CHANNEL_ISO_RCV);
1405
1406 reg_write(lynx, LINK_CONTROL, LINK_CONTROL_RCV_CMP_VALID
1407 | LINK_CONTROL_TX_ISO_EN | LINK_CONTROL_RX_ISO_EN
1408 | LINK_CONTROL_TX_ASYNC_EN | LINK_CONTROL_RX_ASYNC_EN
1409 | LINK_CONTROL_RESET_TX | LINK_CONTROL_RESET_RX);
1410
1411 if (!lynx->phyic.reg_1394a) {
1412 if (!hpsb_disable_irm) {
1413 /* attempt to enable contender bit -FIXME- would this
1414 * work elsewhere? */
1415 reg_set_bits(lynx, GPIO_CTRL_A, 0x1);
1416 reg_write(lynx, GPIO_DATA_BASE + 0x3c, 0x1);
1417 }
1418 } else {
1419 /* set the contender (if appropriate) and LCtrl bit in the
1420 * extended PHY register set. (Should check that PHY_02_EXTENDED
1421 * is set in register 2?)
1422 */
1423 i = get_phy_reg(lynx, 4);
1424 i |= PHY_04_LCTRL;
1425 if (hpsb_disable_irm)
1426 i &= ~PHY_04_CONTENDER;
1427 else
1428 i |= PHY_04_CONTENDER;
1429 if (i != -1) set_phy_reg(lynx, 4, i);
1430 }
1431
1432 if (!skip_eeprom)
1433 {
1434 /* needed for i2c communication with serial eeprom */
1435 struct i2c_adapter *i2c_ad;
1436 struct i2c_algo_bit_data i2c_adapter_data;
1437
1438 error = -ENOMEM;
1439 i2c_ad = kmemdup(&bit_ops, sizeof(*i2c_ad), GFP_KERNEL);
1440 if (!i2c_ad) FAIL("failed to allocate I2C adapter memory");
1441
1442 i2c_adapter_data = bit_data;
1443 i2c_ad->algo_data = &i2c_adapter_data;
1444 i2c_adapter_data.data = lynx;
1445 i2c_ad->dev.parent = &dev->dev;
1446
1447 PRINTD(KERN_DEBUG, lynx->id,"original eeprom control: %d",
1448 reg_read(lynx, SERIAL_EEPROM_CONTROL));
1449
1450 /* reset hardware to sane state */
1451 lynx->i2c_driven_state = 0x00000070;
1452 reg_write(lynx, SERIAL_EEPROM_CONTROL, lynx->i2c_driven_state);
1453
1454 if (i2c_bit_add_bus(i2c_ad) < 0)
1455 {
1456 kfree(i2c_ad);
1457 error = -ENXIO;
1458 FAIL("unable to register i2c");
1459 }
1460 else
1461 {
1462 /* do i2c stuff */
1463 unsigned char i2c_cmd = 0x10;
1464 struct i2c_msg msg[2] = { { 0x50, 0, 1, &i2c_cmd },
1465 { 0x50, I2C_M_RD, 20, (unsigned char*) lynx->bus_info_block }
1466 };
1467
1468 /* we use i2c_transfer, because i2c_smbus_read_block_data does not work properly and we
1469 do it more efficiently in one transaction rather then using several reads */
1470 if (i2c_transfer(i2c_ad, msg, 2) < 0) {
1471 PRINT(KERN_ERR, lynx->id, "unable to read bus info block from i2c");
1472 } else {
1473 int i;
1474
1475 PRINT(KERN_INFO, lynx->id, "got bus info block from serial eeprom");
1476 /* FIXME: probably we shoud rewrite the max_rec, max_ROM(1394a),
1477 * generation(1394a) and link_spd(1394a) field and recalculate
1478 * the CRC */
1479
1480 for (i = 0; i < 5 ; i++)
1481 PRINTD(KERN_DEBUG, lynx->id, "Businfo block quadlet %i: %08x",
1482 i, be32_to_cpu(lynx->bus_info_block[i]));
1483
1484 /* info_length, crc_length and 1394 magic number to check, if it is really a bus info block */
1485 if (((be32_to_cpu(lynx->bus_info_block[0]) & 0xffff0000) == 0x04040000) &&
1486 (lynx->bus_info_block[1] == __constant_cpu_to_be32(0x31333934)))
1487 {
1488 PRINT(KERN_DEBUG, lynx->id, "read a valid bus info block from");
1489 } else {
1490 kfree(i2c_ad);
1491 error = -ENXIO;
1492 FAIL("read something from serial eeprom, but it does not seem to be a valid bus info block");
1493 }
1494
1495 }
1496
1497 i2c_del_adapter(i2c_ad);
1498 kfree(i2c_ad);
1499 }
1500 }
1501
1502 host->csr.guid_hi = be32_to_cpu(lynx->bus_info_block[3]);
1503 host->csr.guid_lo = be32_to_cpu(lynx->bus_info_block[4]);
1504 host->csr.cyc_clk_acc = (be32_to_cpu(lynx->bus_info_block[2]) >> 16) & 0xff;
1505 host->csr.max_rec = (be32_to_cpu(lynx->bus_info_block[2]) >> 12) & 0xf;
1506 if (!lynx->phyic.reg_1394a)
1507 host->csr.lnk_spd = (get_phy_reg(lynx, 2) & 0xc0) >> 6;
1508 else
1509 host->csr.lnk_spd = be32_to_cpu(lynx->bus_info_block[2]) & 0x7;
1510
1511 if (hpsb_add_host(host)) {
1512 error = -ENOMEM;
1513 FAIL("Failed to register host with highlevel");
1514 }
1515
1516 lynx->state = is_host;
1517
1518 return 0;
1519 #undef FAIL
1520 }
1521
1522
1523 static struct pci_device_id pci_table[] = {
1524 {
1525 .vendor = PCI_VENDOR_ID_TI,
1526 .device = PCI_DEVICE_ID_TI_PCILYNX,
1527 .subvendor = PCI_ANY_ID,
1528 .subdevice = PCI_ANY_ID,
1529 },
1530 { } /* Terminating entry */
1531 };
1532
1533 static struct pci_driver lynx_pci_driver = {
1534 .name = PCILYNX_DRIVER_NAME,
1535 .id_table = pci_table,
1536 .probe = add_card,
1537 .remove = remove_card,
1538 };
1539
1540 static struct hpsb_host_driver lynx_driver = {
1541 .owner = THIS_MODULE,
1542 .name = PCILYNX_DRIVER_NAME,
1543 .set_hw_config_rom = NULL,
1544 .transmit_packet = lynx_transmit,
1545 .devctl = lynx_devctl,
1546 .isoctl = NULL,
1547 };
1548
1549 MODULE_AUTHOR("Andreas E. Bombe <andreas.bombe@munich.netsurf.de>");
1550 MODULE_DESCRIPTION("driver for Texas Instruments PCI Lynx IEEE-1394 controller");
1551 MODULE_LICENSE("GPL");
1552 MODULE_SUPPORTED_DEVICE("pcilynx");
1553 MODULE_DEVICE_TABLE(pci, pci_table);
1554
1555 static int __init pcilynx_init(void)
1556 {
1557 int ret;
1558
1559 ret = pci_register_driver(&lynx_pci_driver);
1560 if (ret < 0) {
1561 PRINT_G(KERN_ERR, "PCI module init failed");
1562 return ret;
1563 }
1564
1565 return 0;
1566 }
1567
1568 static void __exit pcilynx_cleanup(void)
1569 {
1570 pci_unregister_driver(&lynx_pci_driver);
1571 }
1572
1573
1574 module_init(pcilynx_init);
1575 module_exit(pcilynx_cleanup);
x86 "subsystem" repository