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b43: Split PHY alloc and init
[linux-2.6/x86.git] / drivers / net / wireless / b43 / main.c
blob156e8f3151d544fd1fde7d7ffde0c2721bb532bd
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
43
44 #include "b43.h"
45 #include "main.h"
46 #include "debugfs.h"
47 #include "phy_common.h"
48 #include "phy_g.h"
49 #include "phy_n.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "lo.h"
55 #include "pcmcia.h"
56
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
65
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
91
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
100 SSB_DEVTABLE_END
101 };
102
103 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
104
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
110 { \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
113 .flags = (_flags), \
114 }
115
116 /*
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
119 */
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
133 };
134
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
141
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
146 .flags = (_flags), \
147 .max_antenna_gain = 0, \
148 .max_power = 30, \
149 }
150 static struct ieee80211_channel b43_2ghz_chantable[] = {
151 CHAN4G(1, 2412, 0),
152 CHAN4G(2, 2417, 0),
153 CHAN4G(3, 2422, 0),
154 CHAN4G(4, 2427, 0),
155 CHAN4G(5, 2432, 0),
156 CHAN4G(6, 2437, 0),
157 CHAN4G(7, 2442, 0),
158 CHAN4G(8, 2447, 0),
159 CHAN4G(9, 2452, 0),
160 CHAN4G(10, 2457, 0),
161 CHAN4G(11, 2462, 0),
162 CHAN4G(12, 2467, 0),
163 CHAN4G(13, 2472, 0),
164 CHAN4G(14, 2484, 0),
165 };
166 #undef CHAN4G
167
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
172 .flags = (_flags), \
173 .max_antenna_gain = 0, \
174 .max_power = 30, \
175 }
176 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
232 };
233
234 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
253 CHAN5G(216, 0),
254 };
255 #undef CHAN5G
256
257 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
263 };
264
265 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
271 };
272
273 static struct ieee80211_supported_band b43_band_2GHz = {
274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
279 };
280
281 static void b43_wireless_core_exit(struct b43_wldev *dev);
282 static int b43_wireless_core_init(struct b43_wldev *dev);
283 static void b43_wireless_core_stop(struct b43_wldev *dev);
284 static int b43_wireless_core_start(struct b43_wldev *dev);
285
286 static int b43_ratelimit(struct b43_wl *wl)
287 {
288 if (!wl || !wl->current_dev)
289 return 1;
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
291 return 1;
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
295 }
296
297 void b43info(struct b43_wl *wl, const char *fmt, ...)
298 {
299 va_list args;
300
301 if (!b43_ratelimit(wl))
302 return;
303 va_start(args, fmt);
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 vprintk(fmt, args);
307 va_end(args);
308 }
309
310 void b43err(struct b43_wl *wl, const char *fmt, ...)
311 {
312 va_list args;
313
314 if (!b43_ratelimit(wl))
315 return;
316 va_start(args, fmt);
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 vprintk(fmt, args);
320 va_end(args);
321 }
322
323 void b43warn(struct b43_wl *wl, const char *fmt, ...)
324 {
325 va_list args;
326
327 if (!b43_ratelimit(wl))
328 return;
329 va_start(args, fmt);
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
332 vprintk(fmt, args);
333 va_end(args);
334 }
335
336 #if B43_DEBUG
337 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338 {
339 va_list args;
340
341 va_start(args, fmt);
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344 vprintk(fmt, args);
345 va_end(args);
346 }
347 #endif /* DEBUG */
348
349 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
350 {
351 u32 macctl;
352
353 B43_WARN_ON(offset % 4 != 0);
354
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
357 val = swab32(val);
358
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
360 mmiowb();
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
362 }
363
364 static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
366 {
367 u32 control;
368
369 /* "offset" is the WORD offset. */
370 control = routing;
371 control <<= 16;
372 control |= offset;
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
374 }
375
376 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
377 {
378 u32 ret;
379
380 if (routing == B43_SHM_SHARED) {
381 B43_WARN_ON(offset & 0x0001);
382 if (offset & 0x0003) {
383 /* Unaligned access */
384 b43_shm_control_word(dev, routing, offset >> 2);
385 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
386 ret <<= 16;
387 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
388 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
389
390 goto out;
391 }
392 offset >>= 2;
393 }
394 b43_shm_control_word(dev, routing, offset);
395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
396 out:
397 return ret;
398 }
399
400 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
401 {
402 struct b43_wl *wl = dev->wl;
403 unsigned long flags;
404 u32 ret;
405
406 spin_lock_irqsave(&wl->shm_lock, flags);
407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
409
410 return ret;
411 }
412
413 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
414 {
415 u16 ret;
416
417 if (routing == B43_SHM_SHARED) {
418 B43_WARN_ON(offset & 0x0001);
419 if (offset & 0x0003) {
420 /* Unaligned access */
421 b43_shm_control_word(dev, routing, offset >> 2);
422 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
423
424 goto out;
425 }
426 offset >>= 2;
427 }
428 b43_shm_control_word(dev, routing, offset);
429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
430 out:
431 return ret;
432 }
433
434 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
435 {
436 struct b43_wl *wl = dev->wl;
437 unsigned long flags;
438 u16 ret;
439
440 spin_lock_irqsave(&wl->shm_lock, flags);
441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
443
444 return ret;
445 }
446
447 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
448 {
449 if (routing == B43_SHM_SHARED) {
450 B43_WARN_ON(offset & 0x0001);
451 if (offset & 0x0003) {
452 /* Unaligned access */
453 b43_shm_control_word(dev, routing, offset >> 2);
454 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
455 (value >> 16) & 0xffff);
456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
458 return;
459 }
460 offset >>= 2;
461 }
462 b43_shm_control_word(dev, routing, offset);
463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
464 }
465
466 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
467 {
468 struct b43_wl *wl = dev->wl;
469 unsigned long flags;
470
471 spin_lock_irqsave(&wl->shm_lock, flags);
472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
474 }
475
476 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
477 {
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
484 return;
485 }
486 offset >>= 2;
487 }
488 b43_shm_control_word(dev, routing, offset);
489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
490 }
491
492 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
493 {
494 struct b43_wl *wl = dev->wl;
495 unsigned long flags;
496
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
499 spin_unlock_irqrestore(&wl->shm_lock, flags);
500 }
501
502 /* Read HostFlags */
503 u64 b43_hf_read(struct b43_wldev * dev)
504 {
505 u64 ret;
506
507 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
508 ret <<= 16;
509 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
510 ret <<= 16;
511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
512
513 return ret;
514 }
515
516 /* Write HostFlags */
517 void b43_hf_write(struct b43_wldev *dev, u64 value)
518 {
519 u16 lo, mi, hi;
520
521 lo = (value & 0x00000000FFFFULL);
522 mi = (value & 0x0000FFFF0000ULL) >> 16;
523 hi = (value & 0xFFFF00000000ULL) >> 32;
524 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
527 }
528
529 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
530 {
531 /* We need to be careful. As we read the TSF from multiple
532 * registers, we should take care of register overflows.
533 * In theory, the whole tsf read process should be atomic.
534 * We try to be atomic here, by restaring the read process,
535 * if any of the high registers changed (overflew).
536 */
537 if (dev->dev->id.revision >= 3) {
538 u32 low, high, high2;
539
540 do {
541 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
542 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
543 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
544 } while (unlikely(high != high2));
545
546 *tsf = high;
547 *tsf <<= 32;
548 *tsf |= low;
549 } else {
550 u64 tmp;
551 u16 v0, v1, v2, v3;
552 u16 test1, test2, test3;
553
554 do {
555 v3 = b43_read16(dev, B43_MMIO_TSF_3);
556 v2 = b43_read16(dev, B43_MMIO_TSF_2);
557 v1 = b43_read16(dev, B43_MMIO_TSF_1);
558 v0 = b43_read16(dev, B43_MMIO_TSF_0);
559
560 test3 = b43_read16(dev, B43_MMIO_TSF_3);
561 test2 = b43_read16(dev, B43_MMIO_TSF_2);
562 test1 = b43_read16(dev, B43_MMIO_TSF_1);
563 } while (v3 != test3 || v2 != test2 || v1 != test1);
564
565 *tsf = v3;
566 *tsf <<= 48;
567 tmp = v2;
568 tmp <<= 32;
569 *tsf |= tmp;
570 tmp = v1;
571 tmp <<= 16;
572 *tsf |= tmp;
573 *tsf |= v0;
574 }
575 }
576
577 static void b43_time_lock(struct b43_wldev *dev)
578 {
579 u32 macctl;
580
581 macctl = b43_read32(dev, B43_MMIO_MACCTL);
582 macctl |= B43_MACCTL_TBTTHOLD;
583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
586 }
587
588 static void b43_time_unlock(struct b43_wldev *dev)
589 {
590 u32 macctl;
591
592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
593 macctl &= ~B43_MACCTL_TBTTHOLD;
594 b43_write32(dev, B43_MMIO_MACCTL, macctl);
595 /* Commit the write */
596 b43_read32(dev, B43_MMIO_MACCTL);
597 }
598
599 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
600 {
601 /* Be careful with the in-progress timer.
602 * First zero out the low register, so we have a full
603 * register-overflow duration to complete the operation.
604 */
605 if (dev->dev->id.revision >= 3) {
606 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
607 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
608
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
610 mmiowb();
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
612 mmiowb();
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
614 } else {
615 u16 v0 = (tsf & 0x000000000000FFFFULL);
616 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
617 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
618 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
619
620 b43_write16(dev, B43_MMIO_TSF_0, 0);
621 mmiowb();
622 b43_write16(dev, B43_MMIO_TSF_3, v3);
623 mmiowb();
624 b43_write16(dev, B43_MMIO_TSF_2, v2);
625 mmiowb();
626 b43_write16(dev, B43_MMIO_TSF_1, v1);
627 mmiowb();
628 b43_write16(dev, B43_MMIO_TSF_0, v0);
629 }
630 }
631
632 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
633 {
634 b43_time_lock(dev);
635 b43_tsf_write_locked(dev, tsf);
636 b43_time_unlock(dev);
637 }
638
639 static
640 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
641 {
642 static const u8 zero_addr[ETH_ALEN] = { 0 };
643 u16 data;
644
645 if (!mac)
646 mac = zero_addr;
647
648 offset |= 0x0020;
649 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
650
651 data = mac[0];
652 data |= mac[1] << 8;
653 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
654 data = mac[2];
655 data |= mac[3] << 8;
656 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
657 data = mac[4];
658 data |= mac[5] << 8;
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
660 }
661
662 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
663 {
664 const u8 *mac;
665 const u8 *bssid;
666 u8 mac_bssid[ETH_ALEN * 2];
667 int i;
668 u32 tmp;
669
670 bssid = dev->wl->bssid;
671 mac = dev->wl->mac_addr;
672
673 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
674
675 memcpy(mac_bssid, mac, ETH_ALEN);
676 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
677
678 /* Write our MAC address and BSSID to template ram */
679 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
680 tmp = (u32) (mac_bssid[i + 0]);
681 tmp |= (u32) (mac_bssid[i + 1]) << 8;
682 tmp |= (u32) (mac_bssid[i + 2]) << 16;
683 tmp |= (u32) (mac_bssid[i + 3]) << 24;
684 b43_ram_write(dev, 0x20 + i, tmp);
685 }
686 }
687
688 static void b43_upload_card_macaddress(struct b43_wldev *dev)
689 {
690 b43_write_mac_bssid_templates(dev);
691 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
692 }
693
694 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
695 {
696 /* slot_time is in usec. */
697 if (dev->phy.type != B43_PHYTYPE_G)
698 return;
699 b43_write16(dev, 0x684, 510 + slot_time);
700 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
701 }
702
703 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
704 {
705 b43_set_slot_time(dev, 9);
706 dev->short_slot = 1;
707 }
708
709 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
710 {
711 b43_set_slot_time(dev, 20);
712 dev->short_slot = 0;
713 }
714
715 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
716 * Returns the _previously_ enabled IRQ mask.
717 */
718 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
719 {
720 u32 old_mask;
721
722 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
723 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
724
725 return old_mask;
726 }
727
728 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
729 * Returns the _previously_ enabled IRQ mask.
730 */
731 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
732 {
733 u32 old_mask;
734
735 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
736 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
737
738 return old_mask;
739 }
740
741 /* Synchronize IRQ top- and bottom-half.
742 * IRQs must be masked before calling this.
743 * This must not be called with the irq_lock held.
744 */
745 static void b43_synchronize_irq(struct b43_wldev *dev)
746 {
747 synchronize_irq(dev->dev->irq);
748 tasklet_kill(&dev->isr_tasklet);
749 }
750
751 /* DummyTransmission function, as documented on
752 * http://bcm-specs.sipsolutions.net/DummyTransmission
753 */
754 void b43_dummy_transmission(struct b43_wldev *dev)
755 {
756 struct b43_wl *wl = dev->wl;
757 struct b43_phy *phy = &dev->phy;
758 unsigned int i, max_loop;
759 u16 value;
760 u32 buffer[5] = {
761 0x00000000,
762 0x00D40000,
763 0x00000000,
764 0x01000000,
765 0x00000000,
766 };
767
768 switch (phy->type) {
769 case B43_PHYTYPE_A:
770 max_loop = 0x1E;
771 buffer[0] = 0x000201CC;
772 break;
773 case B43_PHYTYPE_B:
774 case B43_PHYTYPE_G:
775 max_loop = 0xFA;
776 buffer[0] = 0x000B846E;
777 break;
778 default:
779 B43_WARN_ON(1);
780 return;
781 }
782
783 spin_lock_irq(&wl->irq_lock);
784 write_lock(&wl->tx_lock);
785
786 for (i = 0; i < 5; i++)
787 b43_ram_write(dev, i * 4, buffer[i]);
788
789 /* Commit writes */
790 b43_read32(dev, B43_MMIO_MACCTL);
791
792 b43_write16(dev, 0x0568, 0x0000);
793 b43_write16(dev, 0x07C0, 0x0000);
794 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
795 b43_write16(dev, 0x050C, value);
796 b43_write16(dev, 0x0508, 0x0000);
797 b43_write16(dev, 0x050A, 0x0000);
798 b43_write16(dev, 0x054C, 0x0000);
799 b43_write16(dev, 0x056A, 0x0014);
800 b43_write16(dev, 0x0568, 0x0826);
801 b43_write16(dev, 0x0500, 0x0000);
802 b43_write16(dev, 0x0502, 0x0030);
803
804 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
805 b43_radio_write16(dev, 0x0051, 0x0017);
806 for (i = 0x00; i < max_loop; i++) {
807 value = b43_read16(dev, 0x050E);
808 if (value & 0x0080)
809 break;
810 udelay(10);
811 }
812 for (i = 0x00; i < 0x0A; i++) {
813 value = b43_read16(dev, 0x050E);
814 if (value & 0x0400)
815 break;
816 udelay(10);
817 }
818 for (i = 0x00; i < 0x0A; i++) {
819 value = b43_read16(dev, 0x0690);
820 if (!(value & 0x0100))
821 break;
822 udelay(10);
823 }
824 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
825 b43_radio_write16(dev, 0x0051, 0x0037);
826
827 write_unlock(&wl->tx_lock);
828 spin_unlock_irq(&wl->irq_lock);
829 }
830
831 static void key_write(struct b43_wldev *dev,
832 u8 index, u8 algorithm, const u8 * key)
833 {
834 unsigned int i;
835 u32 offset;
836 u16 value;
837 u16 kidx;
838
839 /* Key index/algo block */
840 kidx = b43_kidx_to_fw(dev, index);
841 value = ((kidx << 4) | algorithm);
842 b43_shm_write16(dev, B43_SHM_SHARED,
843 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
844
845 /* Write the key to the Key Table Pointer offset */
846 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
847 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
848 value = key[i];
849 value |= (u16) (key[i + 1]) << 8;
850 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
851 }
852 }
853
854 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
855 {
856 u32 addrtmp[2] = { 0, 0, };
857 u8 per_sta_keys_start = 8;
858
859 if (b43_new_kidx_api(dev))
860 per_sta_keys_start = 4;
861
862 B43_WARN_ON(index < per_sta_keys_start);
863 /* We have two default TX keys and possibly two default RX keys.
864 * Physical mac 0 is mapped to physical key 4 or 8, depending
865 * on the firmware version.
866 * So we must adjust the index here.
867 */
868 index -= per_sta_keys_start;
869
870 if (addr) {
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
877 }
878
879 if (dev->dev->id.revision >= 5) {
880 /* Receive match transmitter address mechanism */
881 b43_shm_write32(dev, B43_SHM_RCMTA,
882 (index * 2) + 0, addrtmp[0]);
883 b43_shm_write16(dev, B43_SHM_RCMTA,
884 (index * 2) + 1, addrtmp[1]);
885 } else {
886 /* RXE (Receive Engine) and
887 * PSM (Programmable State Machine) mechanism
888 */
889 if (index < 8) {
890 /* TODO write to RCM 16, 19, 22 and 25 */
891 } else {
892 b43_shm_write32(dev, B43_SHM_SHARED,
893 B43_SHM_SH_PSM + (index * 6) + 0,
894 addrtmp[0]);
895 b43_shm_write16(dev, B43_SHM_SHARED,
896 B43_SHM_SH_PSM + (index * 6) + 4,
897 addrtmp[1]);
898 }
899 }
900 }
901
902 static void do_key_write(struct b43_wldev *dev,
903 u8 index, u8 algorithm,
904 const u8 * key, size_t key_len, const u8 * mac_addr)
905 {
906 u8 buf[B43_SEC_KEYSIZE] = { 0, };
907 u8 per_sta_keys_start = 8;
908
909 if (b43_new_kidx_api(dev))
910 per_sta_keys_start = 4;
911
912 B43_WARN_ON(index >= dev->max_nr_keys);
913 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
914
915 if (index >= per_sta_keys_start)
916 keymac_write(dev, index, NULL); /* First zero out mac. */
917 if (key)
918 memcpy(buf, key, key_len);
919 key_write(dev, index, algorithm, buf);
920 if (index >= per_sta_keys_start)
921 keymac_write(dev, index, mac_addr);
922
923 dev->key[index].algorithm = algorithm;
924 }
925
926 static int b43_key_write(struct b43_wldev *dev,
927 int index, u8 algorithm,
928 const u8 * key, size_t key_len,
929 const u8 * mac_addr,
930 struct ieee80211_key_conf *keyconf)
931 {
932 int i;
933 int sta_keys_start;
934
935 if (key_len > B43_SEC_KEYSIZE)
936 return -EINVAL;
937 for (i = 0; i < dev->max_nr_keys; i++) {
938 /* Check that we don't already have this key. */
939 B43_WARN_ON(dev->key[i].keyconf == keyconf);
940 }
941 if (index < 0) {
942 /* Either pairwise key or address is 00:00:00:00:00:00
943 * for transmit-only keys. Search the index. */
944 if (b43_new_kidx_api(dev))
945 sta_keys_start = 4;
946 else
947 sta_keys_start = 8;
948 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
949 if (!dev->key[i].keyconf) {
950 /* found empty */
951 index = i;
952 break;
953 }
954 }
955 if (index < 0) {
956 b43err(dev->wl, "Out of hardware key memory\n");
957 return -ENOSPC;
958 }
959 } else
960 B43_WARN_ON(index > 3);
961
962 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
963 if ((index <= 3) && !b43_new_kidx_api(dev)) {
964 /* Default RX key */
965 B43_WARN_ON(mac_addr);
966 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
967 }
968 keyconf->hw_key_idx = index;
969 dev->key[index].keyconf = keyconf;
970
971 return 0;
972 }
973
974 static int b43_key_clear(struct b43_wldev *dev, int index)
975 {
976 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
977 return -EINVAL;
978 do_key_write(dev, index, B43_SEC_ALGO_NONE,
979 NULL, B43_SEC_KEYSIZE, NULL);
980 if ((index <= 3) && !b43_new_kidx_api(dev)) {
981 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
982 NULL, B43_SEC_KEYSIZE, NULL);
983 }
984 dev->key[index].keyconf = NULL;
985
986 return 0;
987 }
988
989 static void b43_clear_keys(struct b43_wldev *dev)
990 {
991 int i;
992
993 for (i = 0; i < dev->max_nr_keys; i++)
994 b43_key_clear(dev, i);
995 }
996
997 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
998 {
999 u32 macctl;
1000 u16 ucstat;
1001 bool hwps;
1002 bool awake;
1003 int i;
1004
1005 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1006 (ps_flags & B43_PS_DISABLED));
1007 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1008
1009 if (ps_flags & B43_PS_ENABLED) {
1010 hwps = 1;
1011 } else if (ps_flags & B43_PS_DISABLED) {
1012 hwps = 0;
1013 } else {
1014 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1015 // and thus is not an AP and we are associated, set bit 25
1016 }
1017 if (ps_flags & B43_PS_AWAKE) {
1018 awake = 1;
1019 } else if (ps_flags & B43_PS_ASLEEP) {
1020 awake = 0;
1021 } else {
1022 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1023 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1024 // successful, set bit26
1025 }
1026
1027 /* FIXME: For now we force awake-on and hwps-off */
1028 hwps = 0;
1029 awake = 1;
1030
1031 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1032 if (hwps)
1033 macctl |= B43_MACCTL_HWPS;
1034 else
1035 macctl &= ~B43_MACCTL_HWPS;
1036 if (awake)
1037 macctl |= B43_MACCTL_AWAKE;
1038 else
1039 macctl &= ~B43_MACCTL_AWAKE;
1040 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1041 /* Commit write */
1042 b43_read32(dev, B43_MMIO_MACCTL);
1043 if (awake && dev->dev->id.revision >= 5) {
1044 /* Wait for the microcode to wake up. */
1045 for (i = 0; i < 100; i++) {
1046 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1047 B43_SHM_SH_UCODESTAT);
1048 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1049 break;
1050 udelay(10);
1051 }
1052 }
1053 }
1054
1055 /* Turn the Analog ON/OFF */
1056 static void b43_switch_analog(struct b43_wldev *dev, int on)
1057 {
1058 switch (dev->phy.type) {
1059 case B43_PHYTYPE_A:
1060 case B43_PHYTYPE_G:
1061 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1062 break;
1063 case B43_PHYTYPE_N:
1064 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1065 on ? 0 : 0x7FFF);
1066 break;
1067 default:
1068 B43_WARN_ON(1);
1069 }
1070 }
1071
1072 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1073 {
1074 u32 tmslow;
1075 u32 macctl;
1076
1077 flags |= B43_TMSLOW_PHYCLKEN;
1078 flags |= B43_TMSLOW_PHYRESET;
1079 ssb_device_enable(dev->dev, flags);
1080 msleep(2); /* Wait for the PLL to turn on. */
1081
1082 /* Now take the PHY out of Reset again */
1083 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1084 tmslow |= SSB_TMSLOW_FGC;
1085 tmslow &= ~B43_TMSLOW_PHYRESET;
1086 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1087 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1088 msleep(1);
1089 tmslow &= ~SSB_TMSLOW_FGC;
1090 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1091 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1092 msleep(1);
1093
1094 /* Turn Analog ON, but only if we already know the PHY-type.
1095 * This protects against very early setup where we don't know the
1096 * PHY-type, yet. wireless_core_reset will be called once again later,
1097 * when we know the PHY-type. */
1098 if (dev->phy.ops)
1099 b43_switch_analog(dev, 1);
1100
1101 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1102 macctl &= ~B43_MACCTL_GMODE;
1103 if (flags & B43_TMSLOW_GMODE)
1104 macctl |= B43_MACCTL_GMODE;
1105 macctl |= B43_MACCTL_IHR_ENABLED;
1106 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1107 }
1108
1109 static void handle_irq_transmit_status(struct b43_wldev *dev)
1110 {
1111 u32 v0, v1;
1112 u16 tmp;
1113 struct b43_txstatus stat;
1114
1115 while (1) {
1116 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1117 if (!(v0 & 0x00000001))
1118 break;
1119 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1120
1121 stat.cookie = (v0 >> 16);
1122 stat.seq = (v1 & 0x0000FFFF);
1123 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1124 tmp = (v0 & 0x0000FFFF);
1125 stat.frame_count = ((tmp & 0xF000) >> 12);
1126 stat.rts_count = ((tmp & 0x0F00) >> 8);
1127 stat.supp_reason = ((tmp & 0x001C) >> 2);
1128 stat.pm_indicated = !!(tmp & 0x0080);
1129 stat.intermediate = !!(tmp & 0x0040);
1130 stat.for_ampdu = !!(tmp & 0x0020);
1131 stat.acked = !!(tmp & 0x0002);
1132
1133 b43_handle_txstatus(dev, &stat);
1134 }
1135 }
1136
1137 static void drain_txstatus_queue(struct b43_wldev *dev)
1138 {
1139 u32 dummy;
1140
1141 if (dev->dev->id.revision < 5)
1142 return;
1143 /* Read all entries from the microcode TXstatus FIFO
1144 * and throw them away.
1145 */
1146 while (1) {
1147 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1148 if (!(dummy & 0x00000001))
1149 break;
1150 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1151 }
1152 }
1153
1154 static u32 b43_jssi_read(struct b43_wldev *dev)
1155 {
1156 u32 val = 0;
1157
1158 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1159 val <<= 16;
1160 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1161
1162 return val;
1163 }
1164
1165 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1166 {
1167 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1168 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1169 }
1170
1171 static void b43_generate_noise_sample(struct b43_wldev *dev)
1172 {
1173 b43_jssi_write(dev, 0x7F7F7F7F);
1174 b43_write32(dev, B43_MMIO_MACCMD,
1175 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1176 }
1177
1178 static void b43_calculate_link_quality(struct b43_wldev *dev)
1179 {
1180 /* Top half of Link Quality calculation. */
1181
1182 if (dev->phy.type != B43_PHYTYPE_G)
1183 return;
1184 if (dev->noisecalc.calculation_running)
1185 return;
1186 dev->noisecalc.calculation_running = 1;
1187 dev->noisecalc.nr_samples = 0;
1188
1189 b43_generate_noise_sample(dev);
1190 }
1191
1192 static void handle_irq_noise(struct b43_wldev *dev)
1193 {
1194 struct b43_phy_g *phy = dev->phy.g;
1195 u16 tmp;
1196 u8 noise[4];
1197 u8 i, j;
1198 s32 average;
1199
1200 /* Bottom half of Link Quality calculation. */
1201
1202 if (dev->phy.type != B43_PHYTYPE_G)
1203 return;
1204
1205 /* Possible race condition: It might be possible that the user
1206 * changed to a different channel in the meantime since we
1207 * started the calculation. We ignore that fact, since it's
1208 * not really that much of a problem. The background noise is
1209 * an estimation only anyway. Slightly wrong results will get damped
1210 * by the averaging of the 8 sample rounds. Additionally the
1211 * value is shortlived. So it will be replaced by the next noise
1212 * calculation round soon. */
1213
1214 B43_WARN_ON(!dev->noisecalc.calculation_running);
1215 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1216 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1217 noise[2] == 0x7F || noise[3] == 0x7F)
1218 goto generate_new;
1219
1220 /* Get the noise samples. */
1221 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1222 i = dev->noisecalc.nr_samples;
1223 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1224 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1225 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1226 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1227 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1228 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1229 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1230 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1231 dev->noisecalc.nr_samples++;
1232 if (dev->noisecalc.nr_samples == 8) {
1233 /* Calculate the Link Quality by the noise samples. */
1234 average = 0;
1235 for (i = 0; i < 8; i++) {
1236 for (j = 0; j < 4; j++)
1237 average += dev->noisecalc.samples[i][j];
1238 }
1239 average /= (8 * 4);
1240 average *= 125;
1241 average += 64;
1242 average /= 128;
1243 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1244 tmp = (tmp / 128) & 0x1F;
1245 if (tmp >= 8)
1246 average += 2;
1247 else
1248 average -= 25;
1249 if (tmp == 8)
1250 average -= 72;
1251 else
1252 average -= 48;
1253
1254 dev->stats.link_noise = average;
1255 dev->noisecalc.calculation_running = 0;
1256 return;
1257 }
1258 generate_new:
1259 b43_generate_noise_sample(dev);
1260 }
1261
1262 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1263 {
1264 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1265 ///TODO: PS TBTT
1266 } else {
1267 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1268 b43_power_saving_ctl_bits(dev, 0);
1269 }
1270 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1271 dev->dfq_valid = 1;
1272 }
1273
1274 static void handle_irq_atim_end(struct b43_wldev *dev)
1275 {
1276 if (dev->dfq_valid) {
1277 b43_write32(dev, B43_MMIO_MACCMD,
1278 b43_read32(dev, B43_MMIO_MACCMD)
1279 | B43_MACCMD_DFQ_VALID);
1280 dev->dfq_valid = 0;
1281 }
1282 }
1283
1284 static void handle_irq_pmq(struct b43_wldev *dev)
1285 {
1286 u32 tmp;
1287
1288 //TODO: AP mode.
1289
1290 while (1) {
1291 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1292 if (!(tmp & 0x00000008))
1293 break;
1294 }
1295 /* 16bit write is odd, but correct. */
1296 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1297 }
1298
1299 static void b43_write_template_common(struct b43_wldev *dev,
1300 const u8 * data, u16 size,
1301 u16 ram_offset,
1302 u16 shm_size_offset, u8 rate)
1303 {
1304 u32 i, tmp;
1305 struct b43_plcp_hdr4 plcp;
1306
1307 plcp.data = 0;
1308 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1309 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1310 ram_offset += sizeof(u32);
1311 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1312 * So leave the first two bytes of the next write blank.
1313 */
1314 tmp = (u32) (data[0]) << 16;
1315 tmp |= (u32) (data[1]) << 24;
1316 b43_ram_write(dev, ram_offset, tmp);
1317 ram_offset += sizeof(u32);
1318 for (i = 2; i < size; i += sizeof(u32)) {
1319 tmp = (u32) (data[i + 0]);
1320 if (i + 1 < size)
1321 tmp |= (u32) (data[i + 1]) << 8;
1322 if (i + 2 < size)
1323 tmp |= (u32) (data[i + 2]) << 16;
1324 if (i + 3 < size)
1325 tmp |= (u32) (data[i + 3]) << 24;
1326 b43_ram_write(dev, ram_offset + i - 2, tmp);
1327 }
1328 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1329 size + sizeof(struct b43_plcp_hdr6));
1330 }
1331
1332 /* Check if the use of the antenna that ieee80211 told us to
1333 * use is possible. This will fall back to DEFAULT.
1334 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1335 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1336 u8 antenna_nr)
1337 {
1338 u8 antenna_mask;
1339
1340 if (antenna_nr == 0) {
1341 /* Zero means "use default antenna". That's always OK. */
1342 return 0;
1343 }
1344
1345 /* Get the mask of available antennas. */
1346 if (dev->phy.gmode)
1347 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1348 else
1349 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1350
1351 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1352 /* This antenna is not available. Fall back to default. */
1353 return 0;
1354 }
1355
1356 return antenna_nr;
1357 }
1358
1359 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
1360 {
1361 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
1362 switch (antenna) {
1363 case 0: /* default/diversity */
1364 return B43_ANTENNA_DEFAULT;
1365 case 1: /* Antenna 0 */
1366 return B43_ANTENNA0;
1367 case 2: /* Antenna 1 */
1368 return B43_ANTENNA1;
1369 case 3: /* Antenna 2 */
1370 return B43_ANTENNA2;
1371 case 4: /* Antenna 3 */
1372 return B43_ANTENNA3;
1373 default:
1374 return B43_ANTENNA_DEFAULT;
1375 }
1376 }
1377
1378 /* Convert a b43 antenna number value to the PHY TX control value. */
1379 static u16 b43_antenna_to_phyctl(int antenna)
1380 {
1381 switch (antenna) {
1382 case B43_ANTENNA0:
1383 return B43_TXH_PHY_ANT0;
1384 case B43_ANTENNA1:
1385 return B43_TXH_PHY_ANT1;
1386 case B43_ANTENNA2:
1387 return B43_TXH_PHY_ANT2;
1388 case B43_ANTENNA3:
1389 return B43_TXH_PHY_ANT3;
1390 case B43_ANTENNA_AUTO:
1391 return B43_TXH_PHY_ANT01AUTO;
1392 }
1393 B43_WARN_ON(1);
1394 return 0;
1395 }
1396
1397 static void b43_write_beacon_template(struct b43_wldev *dev,
1398 u16 ram_offset,
1399 u16 shm_size_offset)
1400 {
1401 unsigned int i, len, variable_len;
1402 const struct ieee80211_mgmt *bcn;
1403 const u8 *ie;
1404 bool tim_found = 0;
1405 unsigned int rate;
1406 u16 ctl;
1407 int antenna;
1408 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1409
1410 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1411 len = min((size_t) dev->wl->current_beacon->len,
1412 0x200 - sizeof(struct b43_plcp_hdr6));
1413 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1414
1415 b43_write_template_common(dev, (const u8 *)bcn,
1416 len, ram_offset, shm_size_offset, rate);
1417
1418 /* Write the PHY TX control parameters. */
1419 antenna = b43_antenna_from_ieee80211(dev, info->antenna_sel_tx);
1420 antenna = b43_antenna_to_phyctl(antenna);
1421 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1422 /* We can't send beacons with short preamble. Would get PHY errors. */
1423 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1424 ctl &= ~B43_TXH_PHY_ANT;
1425 ctl &= ~B43_TXH_PHY_ENC;
1426 ctl |= antenna;
1427 if (b43_is_cck_rate(rate))
1428 ctl |= B43_TXH_PHY_ENC_CCK;
1429 else
1430 ctl |= B43_TXH_PHY_ENC_OFDM;
1431 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1432
1433 /* Find the position of the TIM and the DTIM_period value
1434 * and write them to SHM. */
1435 ie = bcn->u.beacon.variable;
1436 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1437 for (i = 0; i < variable_len - 2; ) {
1438 uint8_t ie_id, ie_len;
1439
1440 ie_id = ie[i];
1441 ie_len = ie[i + 1];
1442 if (ie_id == 5) {
1443 u16 tim_position;
1444 u16 dtim_period;
1445 /* This is the TIM Information Element */
1446
1447 /* Check whether the ie_len is in the beacon data range. */
1448 if (variable_len < ie_len + 2 + i)
1449 break;
1450 /* A valid TIM is at least 4 bytes long. */
1451 if (ie_len < 4)
1452 break;
1453 tim_found = 1;
1454
1455 tim_position = sizeof(struct b43_plcp_hdr6);
1456 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1457 tim_position += i;
1458
1459 dtim_period = ie[i + 3];
1460
1461 b43_shm_write16(dev, B43_SHM_SHARED,
1462 B43_SHM_SH_TIMBPOS, tim_position);
1463 b43_shm_write16(dev, B43_SHM_SHARED,
1464 B43_SHM_SH_DTIMPER, dtim_period);
1465 break;
1466 }
1467 i += ie_len + 2;
1468 }
1469 if (!tim_found) {
1470 /*
1471 * If ucode wants to modify TIM do it behind the beacon, this
1472 * will happen, for example, when doing mesh networking.
1473 */
1474 b43_shm_write16(dev, B43_SHM_SHARED,
1475 B43_SHM_SH_TIMBPOS,
1476 len + sizeof(struct b43_plcp_hdr6));
1477 b43_shm_write16(dev, B43_SHM_SHARED,
1478 B43_SHM_SH_DTIMPER, 0);
1479 }
1480 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1481 }
1482
1483 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1484 u16 shm_offset, u16 size,
1485 struct ieee80211_rate *rate)
1486 {
1487 struct b43_plcp_hdr4 plcp;
1488 u32 tmp;
1489 __le16 dur;
1490
1491 plcp.data = 0;
1492 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1493 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1494 dev->wl->vif, size,
1495 rate);
1496 /* Write PLCP in two parts and timing for packet transfer */
1497 tmp = le32_to_cpu(plcp.data);
1498 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1499 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1500 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1501 }
1502
1503 /* Instead of using custom probe response template, this function
1504 * just patches custom beacon template by:
1505 * 1) Changing packet type
1506 * 2) Patching duration field
1507 * 3) Stripping TIM
1508 */
1509 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1510 u16 *dest_size,
1511 struct ieee80211_rate *rate)
1512 {
1513 const u8 *src_data;
1514 u8 *dest_data;
1515 u16 src_size, elem_size, src_pos, dest_pos;
1516 __le16 dur;
1517 struct ieee80211_hdr *hdr;
1518 size_t ie_start;
1519
1520 src_size = dev->wl->current_beacon->len;
1521 src_data = (const u8 *)dev->wl->current_beacon->data;
1522
1523 /* Get the start offset of the variable IEs in the packet. */
1524 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1525 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1526
1527 if (B43_WARN_ON(src_size < ie_start))
1528 return NULL;
1529
1530 dest_data = kmalloc(src_size, GFP_ATOMIC);
1531 if (unlikely(!dest_data))
1532 return NULL;
1533
1534 /* Copy the static data and all Information Elements, except the TIM. */
1535 memcpy(dest_data, src_data, ie_start);
1536 src_pos = ie_start;
1537 dest_pos = ie_start;
1538 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1539 elem_size = src_data[src_pos + 1] + 2;
1540 if (src_data[src_pos] == 5) {
1541 /* This is the TIM. */
1542 continue;
1543 }
1544 memcpy(dest_data + dest_pos, src_data + src_pos,
1545 elem_size);
1546 dest_pos += elem_size;
1547 }
1548 *dest_size = dest_pos;
1549 hdr = (struct ieee80211_hdr *)dest_data;
1550
1551 /* Set the frame control. */
1552 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1553 IEEE80211_STYPE_PROBE_RESP);
1554 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1555 dev->wl->vif, *dest_size,
1556 rate);
1557 hdr->duration_id = dur;
1558
1559 return dest_data;
1560 }
1561
1562 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1563 u16 ram_offset,
1564 u16 shm_size_offset,
1565 struct ieee80211_rate *rate)
1566 {
1567 const u8 *probe_resp_data;
1568 u16 size;
1569
1570 size = dev->wl->current_beacon->len;
1571 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1572 if (unlikely(!probe_resp_data))
1573 return;
1574
1575 /* Looks like PLCP headers plus packet timings are stored for
1576 * all possible basic rates
1577 */
1578 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1579 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1580 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1581 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1582
1583 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1584 b43_write_template_common(dev, probe_resp_data,
1585 size, ram_offset, shm_size_offset,
1586 rate->hw_value);
1587 kfree(probe_resp_data);
1588 }
1589
1590 static void b43_upload_beacon0(struct b43_wldev *dev)
1591 {
1592 struct b43_wl *wl = dev->wl;
1593
1594 if (wl->beacon0_uploaded)
1595 return;
1596 b43_write_beacon_template(dev, 0x68, 0x18);
1597 /* FIXME: Probe resp upload doesn't really belong here,
1598 * but we don't use that feature anyway. */
1599 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1600 &__b43_ratetable[3]);
1601 wl->beacon0_uploaded = 1;
1602 }
1603
1604 static void b43_upload_beacon1(struct b43_wldev *dev)
1605 {
1606 struct b43_wl *wl = dev->wl;
1607
1608 if (wl->beacon1_uploaded)
1609 return;
1610 b43_write_beacon_template(dev, 0x468, 0x1A);
1611 wl->beacon1_uploaded = 1;
1612 }
1613
1614 static void handle_irq_beacon(struct b43_wldev *dev)
1615 {
1616 struct b43_wl *wl = dev->wl;
1617 u32 cmd, beacon0_valid, beacon1_valid;
1618
1619 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP) &&
1620 !b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT))
1621 return;
1622
1623 /* This is the bottom half of the asynchronous beacon update. */
1624
1625 /* Ignore interrupt in the future. */
1626 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1627
1628 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1629 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1630 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1631
1632 /* Schedule interrupt manually, if busy. */
1633 if (beacon0_valid && beacon1_valid) {
1634 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1635 dev->irq_savedstate |= B43_IRQ_BEACON;
1636 return;
1637 }
1638
1639 if (unlikely(wl->beacon_templates_virgin)) {
1640 /* We never uploaded a beacon before.
1641 * Upload both templates now, but only mark one valid. */
1642 wl->beacon_templates_virgin = 0;
1643 b43_upload_beacon0(dev);
1644 b43_upload_beacon1(dev);
1645 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1646 cmd |= B43_MACCMD_BEACON0_VALID;
1647 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1648 } else {
1649 if (!beacon0_valid) {
1650 b43_upload_beacon0(dev);
1651 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1652 cmd |= B43_MACCMD_BEACON0_VALID;
1653 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1654 } else if (!beacon1_valid) {
1655 b43_upload_beacon1(dev);
1656 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1657 cmd |= B43_MACCMD_BEACON1_VALID;
1658 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1659 }
1660 }
1661 }
1662
1663 static void b43_beacon_update_trigger_work(struct work_struct *work)
1664 {
1665 struct b43_wl *wl = container_of(work, struct b43_wl,
1666 beacon_update_trigger);
1667 struct b43_wldev *dev;
1668
1669 mutex_lock(&wl->mutex);
1670 dev = wl->current_dev;
1671 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1672 spin_lock_irq(&wl->irq_lock);
1673 /* update beacon right away or defer to irq */
1674 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1675 handle_irq_beacon(dev);
1676 /* The handler might have updated the IRQ mask. */
1677 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1678 dev->irq_savedstate);
1679 mmiowb();
1680 spin_unlock_irq(&wl->irq_lock);
1681 }
1682 mutex_unlock(&wl->mutex);
1683 }
1684
1685 /* Asynchronously update the packet templates in template RAM.
1686 * Locking: Requires wl->irq_lock to be locked. */
1687 static void b43_update_templates(struct b43_wl *wl)
1688 {
1689 struct sk_buff *beacon;
1690
1691 /* This is the top half of the ansynchronous beacon update.
1692 * The bottom half is the beacon IRQ.
1693 * Beacon update must be asynchronous to avoid sending an
1694 * invalid beacon. This can happen for example, if the firmware
1695 * transmits a beacon while we are updating it. */
1696
1697 /* We could modify the existing beacon and set the aid bit in
1698 * the TIM field, but that would probably require resizing and
1699 * moving of data within the beacon template.
1700 * Simply request a new beacon and let mac80211 do the hard work. */
1701 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1702 if (unlikely(!beacon))
1703 return;
1704
1705 if (wl->current_beacon)
1706 dev_kfree_skb_any(wl->current_beacon);
1707 wl->current_beacon = beacon;
1708 wl->beacon0_uploaded = 0;
1709 wl->beacon1_uploaded = 0;
1710 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1711 }
1712
1713 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1714 {
1715 u32 tmp;
1716 u16 i, len;
1717
1718 len = min((u16) ssid_len, (u16) 0x100);
1719 for (i = 0; i < len; i += sizeof(u32)) {
1720 tmp = (u32) (ssid[i + 0]);
1721 if (i + 1 < len)
1722 tmp |= (u32) (ssid[i + 1]) << 8;
1723 if (i + 2 < len)
1724 tmp |= (u32) (ssid[i + 2]) << 16;
1725 if (i + 3 < len)
1726 tmp |= (u32) (ssid[i + 3]) << 24;
1727 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1728 }
1729 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1730 }
1731
1732 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1733 {
1734 b43_time_lock(dev);
1735 if (dev->dev->id.revision >= 3) {
1736 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1737 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1738 } else {
1739 b43_write16(dev, 0x606, (beacon_int >> 6));
1740 b43_write16(dev, 0x610, beacon_int);
1741 }
1742 b43_time_unlock(dev);
1743 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1744 }
1745
1746 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1747 {
1748 u16 reason;
1749
1750 /* Read the register that contains the reason code for the panic. */
1751 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1752 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1753
1754 switch (reason) {
1755 default:
1756 b43dbg(dev->wl, "The panic reason is unknown.\n");
1757 /* fallthrough */
1758 case B43_FWPANIC_DIE:
1759 /* Do not restart the controller or firmware.
1760 * The device is nonfunctional from now on.
1761 * Restarting would result in this panic to trigger again,
1762 * so we avoid that recursion. */
1763 break;
1764 case B43_FWPANIC_RESTART:
1765 b43_controller_restart(dev, "Microcode panic");
1766 break;
1767 }
1768 }
1769
1770 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1771 {
1772 unsigned int i, cnt;
1773 u16 reason, marker_id, marker_line;
1774 __le16 *buf;
1775
1776 /* The proprietary firmware doesn't have this IRQ. */
1777 if (!dev->fw.opensource)
1778 return;
1779
1780 /* Read the register that contains the reason code for this IRQ. */
1781 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1782
1783 switch (reason) {
1784 case B43_DEBUGIRQ_PANIC:
1785 b43_handle_firmware_panic(dev);
1786 break;
1787 case B43_DEBUGIRQ_DUMP_SHM:
1788 if (!B43_DEBUG)
1789 break; /* Only with driver debugging enabled. */
1790 buf = kmalloc(4096, GFP_ATOMIC);
1791 if (!buf) {
1792 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1793 goto out;
1794 }
1795 for (i = 0; i < 4096; i += 2) {
1796 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1797 buf[i / 2] = cpu_to_le16(tmp);
1798 }
1799 b43info(dev->wl, "Shared memory dump:\n");
1800 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1801 16, 2, buf, 4096, 1);
1802 kfree(buf);
1803 break;
1804 case B43_DEBUGIRQ_DUMP_REGS:
1805 if (!B43_DEBUG)
1806 break; /* Only with driver debugging enabled. */
1807 b43info(dev->wl, "Microcode register dump:\n");
1808 for (i = 0, cnt = 0; i < 64; i++) {
1809 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1810 if (cnt == 0)
1811 printk(KERN_INFO);
1812 printk("r%02u: 0x%04X ", i, tmp);
1813 cnt++;
1814 if (cnt == 6) {
1815 printk("\n");
1816 cnt = 0;
1817 }
1818 }
1819 printk("\n");
1820 break;
1821 case B43_DEBUGIRQ_MARKER:
1822 if (!B43_DEBUG)
1823 break; /* Only with driver debugging enabled. */
1824 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1825 B43_MARKER_ID_REG);
1826 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1827 B43_MARKER_LINE_REG);
1828 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1829 "at line number %u\n",
1830 marker_id, marker_line);
1831 break;
1832 default:
1833 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1834 reason);
1835 }
1836 out:
1837 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1838 b43_shm_write16(dev, B43_SHM_SCRATCH,
1839 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1840 }
1841
1842 /* Interrupt handler bottom-half */
1843 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1844 {
1845 u32 reason;
1846 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1847 u32 merged_dma_reason = 0;
1848 int i;
1849 unsigned long flags;
1850
1851 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1852
1853 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1854
1855 reason = dev->irq_reason;
1856 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1857 dma_reason[i] = dev->dma_reason[i];
1858 merged_dma_reason |= dma_reason[i];
1859 }
1860
1861 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1862 b43err(dev->wl, "MAC transmission error\n");
1863
1864 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1865 b43err(dev->wl, "PHY transmission error\n");
1866 rmb();
1867 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1868 atomic_set(&dev->phy.txerr_cnt,
1869 B43_PHY_TX_BADNESS_LIMIT);
1870 b43err(dev->wl, "Too many PHY TX errors, "
1871 "restarting the controller\n");
1872 b43_controller_restart(dev, "PHY TX errors");
1873 }
1874 }
1875
1876 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1877 B43_DMAIRQ_NONFATALMASK))) {
1878 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1879 b43err(dev->wl, "Fatal DMA error: "
1880 "0x%08X, 0x%08X, 0x%08X, "
1881 "0x%08X, 0x%08X, 0x%08X\n",
1882 dma_reason[0], dma_reason[1],
1883 dma_reason[2], dma_reason[3],
1884 dma_reason[4], dma_reason[5]);
1885 b43_controller_restart(dev, "DMA error");
1886 mmiowb();
1887 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1888 return;
1889 }
1890 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1891 b43err(dev->wl, "DMA error: "
1892 "0x%08X, 0x%08X, 0x%08X, "
1893 "0x%08X, 0x%08X, 0x%08X\n",
1894 dma_reason[0], dma_reason[1],
1895 dma_reason[2], dma_reason[3],
1896 dma_reason[4], dma_reason[5]);
1897 }
1898 }
1899
1900 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1901 handle_irq_ucode_debug(dev);
1902 if (reason & B43_IRQ_TBTT_INDI)
1903 handle_irq_tbtt_indication(dev);
1904 if (reason & B43_IRQ_ATIM_END)
1905 handle_irq_atim_end(dev);
1906 if (reason & B43_IRQ_BEACON)
1907 handle_irq_beacon(dev);
1908 if (reason & B43_IRQ_PMQ)
1909 handle_irq_pmq(dev);
1910 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1911 ;/* TODO */
1912 if (reason & B43_IRQ_NOISESAMPLE_OK)
1913 handle_irq_noise(dev);
1914
1915 /* Check the DMA reason registers for received data. */
1916 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1917 if (b43_using_pio_transfers(dev))
1918 b43_pio_rx(dev->pio.rx_queue);
1919 else
1920 b43_dma_rx(dev->dma.rx_ring);
1921 }
1922 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1923 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1924 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1925 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1926 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1927
1928 if (reason & B43_IRQ_TX_OK)
1929 handle_irq_transmit_status(dev);
1930
1931 b43_interrupt_enable(dev, dev->irq_savedstate);
1932 mmiowb();
1933 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1934 }
1935
1936 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1937 {
1938 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1939
1940 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1941 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1942 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1943 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1944 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1945 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1946 }
1947
1948 /* Interrupt handler top-half */
1949 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1950 {
1951 irqreturn_t ret = IRQ_NONE;
1952 struct b43_wldev *dev = dev_id;
1953 u32 reason;
1954
1955 if (!dev)
1956 return IRQ_NONE;
1957
1958 spin_lock(&dev->wl->irq_lock);
1959
1960 if (b43_status(dev) < B43_STAT_STARTED)
1961 goto out;
1962 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1963 if (reason == 0xffffffff) /* shared IRQ */
1964 goto out;
1965 ret = IRQ_HANDLED;
1966 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1967 if (!reason)
1968 goto out;
1969
1970 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1971 & 0x0001DC00;
1972 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1973 & 0x0000DC00;
1974 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1975 & 0x0000DC00;
1976 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1977 & 0x0001DC00;
1978 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1979 & 0x0000DC00;
1980 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1981 & 0x0000DC00;
1982
1983 b43_interrupt_ack(dev, reason);
1984 /* disable all IRQs. They are enabled again in the bottom half. */
1985 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1986 /* save the reason code and call our bottom half. */
1987 dev->irq_reason = reason;
1988 tasklet_schedule(&dev->isr_tasklet);
1989 out:
1990 mmiowb();
1991 spin_unlock(&dev->wl->irq_lock);
1992
1993 return ret;
1994 }
1995
1996 static void do_release_fw(struct b43_firmware_file *fw)
1997 {
1998 release_firmware(fw->data);
1999 fw->data = NULL;
2000 fw->filename = NULL;
2001 }
2002
2003 static void b43_release_firmware(struct b43_wldev *dev)
2004 {
2005 do_release_fw(&dev->fw.ucode);
2006 do_release_fw(&dev->fw.pcm);
2007 do_release_fw(&dev->fw.initvals);
2008 do_release_fw(&dev->fw.initvals_band);
2009 }
2010
2011 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2012 {
2013 const char *text;
2014
2015 text = "You must go to "
2016 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
2017 "and download the latest firmware (version 4).\n";
2018 if (error)
2019 b43err(wl, text);
2020 else
2021 b43warn(wl, text);
2022 }
2023
2024 static int do_request_fw(struct b43_wldev *dev,
2025 const char *name,
2026 struct b43_firmware_file *fw,
2027 bool silent)
2028 {
2029 char path[sizeof(modparam_fwpostfix) + 32];
2030 const struct firmware *blob;
2031 struct b43_fw_header *hdr;
2032 u32 size;
2033 int err;
2034
2035 if (!name) {
2036 /* Don't fetch anything. Free possibly cached firmware. */
2037 do_release_fw(fw);
2038 return 0;
2039 }
2040 if (fw->filename) {
2041 if (strcmp(fw->filename, name) == 0)
2042 return 0; /* Already have this fw. */
2043 /* Free the cached firmware first. */
2044 do_release_fw(fw);
2045 }
2046
2047 snprintf(path, ARRAY_SIZE(path),
2048 "b43%s/%s.fw",
2049 modparam_fwpostfix, name);
2050 err = request_firmware(&blob, path, dev->dev->dev);
2051 if (err == -ENOENT) {
2052 if (!silent) {
2053 b43err(dev->wl, "Firmware file \"%s\" not found\n",
2054 path);
2055 }
2056 return err;
2057 } else if (err) {
2058 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2059 path, err);
2060 return err;
2061 }
2062 if (blob->size < sizeof(struct b43_fw_header))
2063 goto err_format;
2064 hdr = (struct b43_fw_header *)(blob->data);
2065 switch (hdr->type) {
2066 case B43_FW_TYPE_UCODE:
2067 case B43_FW_TYPE_PCM:
2068 size = be32_to_cpu(hdr->size);
2069 if (size != blob->size - sizeof(struct b43_fw_header))
2070 goto err_format;
2071 /* fallthrough */
2072 case B43_FW_TYPE_IV:
2073 if (hdr->ver != 1)
2074 goto err_format;
2075 break;
2076 default:
2077 goto err_format;
2078 }
2079
2080 fw->data = blob;
2081 fw->filename = name;
2082
2083 return 0;
2084
2085 err_format:
2086 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
2087 release_firmware(blob);
2088
2089 return -EPROTO;
2090 }
2091
2092 static int b43_request_firmware(struct b43_wldev *dev)
2093 {
2094 struct b43_firmware *fw = &dev->fw;
2095 const u8 rev = dev->dev->id.revision;
2096 const char *filename;
2097 u32 tmshigh;
2098 int err;
2099
2100 /* Get microcode */
2101 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2102 if ((rev >= 5) && (rev <= 10))
2103 filename = "ucode5";
2104 else if ((rev >= 11) && (rev <= 12))
2105 filename = "ucode11";
2106 else if (rev >= 13)
2107 filename = "ucode13";
2108 else
2109 goto err_no_ucode;
2110 err = do_request_fw(dev, filename, &fw->ucode, 0);
2111 if (err)
2112 goto err_load;
2113
2114 /* Get PCM code */
2115 if ((rev >= 5) && (rev <= 10))
2116 filename = "pcm5";
2117 else if (rev >= 11)
2118 filename = NULL;
2119 else
2120 goto err_no_pcm;
2121 fw->pcm_request_failed = 0;
2122 err = do_request_fw(dev, filename, &fw->pcm, 1);
2123 if (err == -ENOENT) {
2124 /* We did not find a PCM file? Not fatal, but
2125 * core rev <= 10 must do without hwcrypto then. */
2126 fw->pcm_request_failed = 1;
2127 } else if (err)
2128 goto err_load;
2129
2130 /* Get initvals */
2131 switch (dev->phy.type) {
2132 case B43_PHYTYPE_A:
2133 if ((rev >= 5) && (rev <= 10)) {
2134 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2135 filename = "a0g1initvals5";
2136 else
2137 filename = "a0g0initvals5";
2138 } else
2139 goto err_no_initvals;
2140 break;
2141 case B43_PHYTYPE_G:
2142 if ((rev >= 5) && (rev <= 10))
2143 filename = "b0g0initvals5";
2144 else if (rev >= 13)
2145 filename = "b0g0initvals13";
2146 else
2147 goto err_no_initvals;
2148 break;
2149 case B43_PHYTYPE_N:
2150 if ((rev >= 11) && (rev <= 12))
2151 filename = "n0initvals11";
2152 else
2153 goto err_no_initvals;
2154 break;
2155 default:
2156 goto err_no_initvals;
2157 }
2158 err = do_request_fw(dev, filename, &fw->initvals, 0);
2159 if (err)
2160 goto err_load;
2161
2162 /* Get bandswitch initvals */
2163 switch (dev->phy.type) {
2164 case B43_PHYTYPE_A:
2165 if ((rev >= 5) && (rev <= 10)) {
2166 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2167 filename = "a0g1bsinitvals5";
2168 else
2169 filename = "a0g0bsinitvals5";
2170 } else if (rev >= 11)
2171 filename = NULL;
2172 else
2173 goto err_no_initvals;
2174 break;
2175 case B43_PHYTYPE_G:
2176 if ((rev >= 5) && (rev <= 10))
2177 filename = "b0g0bsinitvals5";
2178 else if (rev >= 11)
2179 filename = NULL;
2180 else
2181 goto err_no_initvals;
2182 break;
2183 case B43_PHYTYPE_N:
2184 if ((rev >= 11) && (rev <= 12))
2185 filename = "n0bsinitvals11";
2186 else
2187 goto err_no_initvals;
2188 break;
2189 default:
2190 goto err_no_initvals;
2191 }
2192 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
2193 if (err)
2194 goto err_load;
2195
2196 return 0;
2197
2198 err_load:
2199 b43_print_fw_helptext(dev->wl, 1);
2200 goto error;
2201
2202 err_no_ucode:
2203 err = -ENODEV;
2204 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2205 goto error;
2206
2207 err_no_pcm:
2208 err = -ENODEV;
2209 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2210 goto error;
2211
2212 err_no_initvals:
2213 err = -ENODEV;
2214 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2215 "core rev %u\n", dev->phy.type, rev);
2216 goto error;
2217
2218 error:
2219 b43_release_firmware(dev);
2220 return err;
2221 }
2222
2223 static int b43_upload_microcode(struct b43_wldev *dev)
2224 {
2225 const size_t hdr_len = sizeof(struct b43_fw_header);
2226 const __be32 *data;
2227 unsigned int i, len;
2228 u16 fwrev, fwpatch, fwdate, fwtime;
2229 u32 tmp, macctl;
2230 int err = 0;
2231
2232 /* Jump the microcode PSM to offset 0 */
2233 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2234 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2235 macctl |= B43_MACCTL_PSM_JMP0;
2236 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2237 /* Zero out all microcode PSM registers and shared memory. */
2238 for (i = 0; i < 64; i++)
2239 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2240 for (i = 0; i < 4096; i += 2)
2241 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2242
2243 /* Upload Microcode. */
2244 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2245 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2246 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2247 for (i = 0; i < len; i++) {
2248 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2249 udelay(10);
2250 }
2251
2252 if (dev->fw.pcm.data) {
2253 /* Upload PCM data. */
2254 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2255 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2256 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2257 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2258 /* No need for autoinc bit in SHM_HW */
2259 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2260 for (i = 0; i < len; i++) {
2261 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2262 udelay(10);
2263 }
2264 }
2265
2266 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2267
2268 /* Start the microcode PSM */
2269 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2270 macctl &= ~B43_MACCTL_PSM_JMP0;
2271 macctl |= B43_MACCTL_PSM_RUN;
2272 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2273
2274 /* Wait for the microcode to load and respond */
2275 i = 0;
2276 while (1) {
2277 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2278 if (tmp == B43_IRQ_MAC_SUSPENDED)
2279 break;
2280 i++;
2281 if (i >= 20) {
2282 b43err(dev->wl, "Microcode not responding\n");
2283 b43_print_fw_helptext(dev->wl, 1);
2284 err = -ENODEV;
2285 goto error;
2286 }
2287 msleep_interruptible(50);
2288 if (signal_pending(current)) {
2289 err = -EINTR;
2290 goto error;
2291 }
2292 }
2293 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2294
2295 /* Get and check the revisions. */
2296 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2297 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2298 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2299 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2300
2301 if (fwrev <= 0x128) {
2302 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2303 "binary drivers older than version 4.x is unsupported. "
2304 "You must upgrade your firmware files.\n");
2305 b43_print_fw_helptext(dev->wl, 1);
2306 err = -EOPNOTSUPP;
2307 goto error;
2308 }
2309 dev->fw.rev = fwrev;
2310 dev->fw.patch = fwpatch;
2311 dev->fw.opensource = (fwdate == 0xFFFF);
2312
2313 if (dev->fw.opensource) {
2314 /* Patchlevel info is encoded in the "time" field. */
2315 dev->fw.patch = fwtime;
2316 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2317 dev->fw.rev, dev->fw.patch,
2318 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
2319 } else {
2320 b43info(dev->wl, "Loading firmware version %u.%u "
2321 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2322 fwrev, fwpatch,
2323 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2324 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2325 if (dev->fw.pcm_request_failed) {
2326 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2327 "Hardware accelerated cryptography is disabled.\n");
2328 b43_print_fw_helptext(dev->wl, 0);
2329 }
2330 }
2331
2332 if (b43_is_old_txhdr_format(dev)) {
2333 b43warn(dev->wl, "You are using an old firmware image. "
2334 "Support for old firmware will be removed in July 2008.\n");
2335 b43_print_fw_helptext(dev->wl, 0);
2336 }
2337
2338 return 0;
2339
2340 error:
2341 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2342 macctl &= ~B43_MACCTL_PSM_RUN;
2343 macctl |= B43_MACCTL_PSM_JMP0;
2344 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2345
2346 return err;
2347 }
2348
2349 static int b43_write_initvals(struct b43_wldev *dev,
2350 const struct b43_iv *ivals,
2351 size_t count,
2352 size_t array_size)
2353 {
2354 const struct b43_iv *iv;
2355 u16 offset;
2356 size_t i;
2357 bool bit32;
2358
2359 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2360 iv = ivals;
2361 for (i = 0; i < count; i++) {
2362 if (array_size < sizeof(iv->offset_size))
2363 goto err_format;
2364 array_size -= sizeof(iv->offset_size);
2365 offset = be16_to_cpu(iv->offset_size);
2366 bit32 = !!(offset & B43_IV_32BIT);
2367 offset &= B43_IV_OFFSET_MASK;
2368 if (offset >= 0x1000)
2369 goto err_format;
2370 if (bit32) {
2371 u32 value;
2372
2373 if (array_size < sizeof(iv->data.d32))
2374 goto err_format;
2375 array_size -= sizeof(iv->data.d32);
2376
2377 value = get_unaligned_be32(&iv->data.d32);
2378 b43_write32(dev, offset, value);
2379
2380 iv = (const struct b43_iv *)((const uint8_t *)iv +
2381 sizeof(__be16) +
2382 sizeof(__be32));
2383 } else {
2384 u16 value;
2385
2386 if (array_size < sizeof(iv->data.d16))
2387 goto err_format;
2388 array_size -= sizeof(iv->data.d16);
2389
2390 value = be16_to_cpu(iv->data.d16);
2391 b43_write16(dev, offset, value);
2392
2393 iv = (const struct b43_iv *)((const uint8_t *)iv +
2394 sizeof(__be16) +
2395 sizeof(__be16));
2396 }
2397 }
2398 if (array_size)
2399 goto err_format;
2400
2401 return 0;
2402
2403 err_format:
2404 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2405 b43_print_fw_helptext(dev->wl, 1);
2406
2407 return -EPROTO;
2408 }
2409
2410 static int b43_upload_initvals(struct b43_wldev *dev)
2411 {
2412 const size_t hdr_len = sizeof(struct b43_fw_header);
2413 const struct b43_fw_header *hdr;
2414 struct b43_firmware *fw = &dev->fw;
2415 const struct b43_iv *ivals;
2416 size_t count;
2417 int err;
2418
2419 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2420 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2421 count = be32_to_cpu(hdr->size);
2422 err = b43_write_initvals(dev, ivals, count,
2423 fw->initvals.data->size - hdr_len);
2424 if (err)
2425 goto out;
2426 if (fw->initvals_band.data) {
2427 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2428 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2429 count = be32_to_cpu(hdr->size);
2430 err = b43_write_initvals(dev, ivals, count,
2431 fw->initvals_band.data->size - hdr_len);
2432 if (err)
2433 goto out;
2434 }
2435 out:
2436
2437 return err;
2438 }
2439
2440 /* Initialize the GPIOs
2441 * http://bcm-specs.sipsolutions.net/GPIO
2442 */
2443 static int b43_gpio_init(struct b43_wldev *dev)
2444 {
2445 struct ssb_bus *bus = dev->dev->bus;
2446 struct ssb_device *gpiodev, *pcidev = NULL;
2447 u32 mask, set;
2448
2449 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2450 & ~B43_MACCTL_GPOUTSMSK);
2451
2452 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2453 | 0x000F);
2454
2455 mask = 0x0000001F;
2456 set = 0x0000000F;
2457 if (dev->dev->bus->chip_id == 0x4301) {
2458 mask |= 0x0060;
2459 set |= 0x0060;
2460 }
2461 if (0 /* FIXME: conditional unknown */ ) {
2462 b43_write16(dev, B43_MMIO_GPIO_MASK,
2463 b43_read16(dev, B43_MMIO_GPIO_MASK)
2464 | 0x0100);
2465 mask |= 0x0180;
2466 set |= 0x0180;
2467 }
2468 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2469 b43_write16(dev, B43_MMIO_GPIO_MASK,
2470 b43_read16(dev, B43_MMIO_GPIO_MASK)
2471 | 0x0200);
2472 mask |= 0x0200;
2473 set |= 0x0200;
2474 }
2475 if (dev->dev->id.revision >= 2)
2476 mask |= 0x0010; /* FIXME: This is redundant. */
2477
2478 #ifdef CONFIG_SSB_DRIVER_PCICORE
2479 pcidev = bus->pcicore.dev;
2480 #endif
2481 gpiodev = bus->chipco.dev ? : pcidev;
2482 if (!gpiodev)
2483 return 0;
2484 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2485 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2486 & mask) | set);
2487
2488 return 0;
2489 }
2490
2491 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2492 static void b43_gpio_cleanup(struct b43_wldev *dev)
2493 {
2494 struct ssb_bus *bus = dev->dev->bus;
2495 struct ssb_device *gpiodev, *pcidev = NULL;
2496
2497 #ifdef CONFIG_SSB_DRIVER_PCICORE
2498 pcidev = bus->pcicore.dev;
2499 #endif
2500 gpiodev = bus->chipco.dev ? : pcidev;
2501 if (!gpiodev)
2502 return;
2503 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2504 }
2505
2506 /* http://bcm-specs.sipsolutions.net/EnableMac */
2507 void b43_mac_enable(struct b43_wldev *dev)
2508 {
2509 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2510 u16 fwstate;
2511
2512 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2513 B43_SHM_SH_UCODESTAT);
2514 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2515 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2516 b43err(dev->wl, "b43_mac_enable(): The firmware "
2517 "should be suspended, but current state is %u\n",
2518 fwstate);
2519 }
2520 }
2521
2522 dev->mac_suspended--;
2523 B43_WARN_ON(dev->mac_suspended < 0);
2524 if (dev->mac_suspended == 0) {
2525 b43_write32(dev, B43_MMIO_MACCTL,
2526 b43_read32(dev, B43_MMIO_MACCTL)
2527 | B43_MACCTL_ENABLED);
2528 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2529 B43_IRQ_MAC_SUSPENDED);
2530 /* Commit writes */
2531 b43_read32(dev, B43_MMIO_MACCTL);
2532 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2533 b43_power_saving_ctl_bits(dev, 0);
2534 }
2535 }
2536
2537 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2538 void b43_mac_suspend(struct b43_wldev *dev)
2539 {
2540 int i;
2541 u32 tmp;
2542
2543 might_sleep();
2544 B43_WARN_ON(dev->mac_suspended < 0);
2545
2546 if (dev->mac_suspended == 0) {
2547 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2548 b43_write32(dev, B43_MMIO_MACCTL,
2549 b43_read32(dev, B43_MMIO_MACCTL)
2550 & ~B43_MACCTL_ENABLED);
2551 /* force pci to flush the write */
2552 b43_read32(dev, B43_MMIO_MACCTL);
2553 for (i = 35; i; i--) {
2554 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2555 if (tmp & B43_IRQ_MAC_SUSPENDED)
2556 goto out;
2557 udelay(10);
2558 }
2559 /* Hm, it seems this will take some time. Use msleep(). */
2560 for (i = 40; i; i--) {
2561 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2562 if (tmp & B43_IRQ_MAC_SUSPENDED)
2563 goto out;
2564 msleep(1);
2565 }
2566 b43err(dev->wl, "MAC suspend failed\n");
2567 }
2568 out:
2569 dev->mac_suspended++;
2570 }
2571
2572 static void b43_adjust_opmode(struct b43_wldev *dev)
2573 {
2574 struct b43_wl *wl = dev->wl;
2575 u32 ctl;
2576 u16 cfp_pretbtt;
2577
2578 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2579 /* Reset status to STA infrastructure mode. */
2580 ctl &= ~B43_MACCTL_AP;
2581 ctl &= ~B43_MACCTL_KEEP_CTL;
2582 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2583 ctl &= ~B43_MACCTL_KEEP_BAD;
2584 ctl &= ~B43_MACCTL_PROMISC;
2585 ctl &= ~B43_MACCTL_BEACPROMISC;
2586 ctl |= B43_MACCTL_INFRA;
2587
2588 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) ||
2589 b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT))
2590 ctl |= B43_MACCTL_AP;
2591 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2592 ctl &= ~B43_MACCTL_INFRA;
2593
2594 if (wl->filter_flags & FIF_CONTROL)
2595 ctl |= B43_MACCTL_KEEP_CTL;
2596 if (wl->filter_flags & FIF_FCSFAIL)
2597 ctl |= B43_MACCTL_KEEP_BAD;
2598 if (wl->filter_flags & FIF_PLCPFAIL)
2599 ctl |= B43_MACCTL_KEEP_BADPLCP;
2600 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2601 ctl |= B43_MACCTL_PROMISC;
2602 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2603 ctl |= B43_MACCTL_BEACPROMISC;
2604
2605 /* Workaround: On old hardware the HW-MAC-address-filter
2606 * doesn't work properly, so always run promisc in filter
2607 * it in software. */
2608 if (dev->dev->id.revision <= 4)
2609 ctl |= B43_MACCTL_PROMISC;
2610
2611 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2612
2613 cfp_pretbtt = 2;
2614 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2615 if (dev->dev->bus->chip_id == 0x4306 &&
2616 dev->dev->bus->chip_rev == 3)
2617 cfp_pretbtt = 100;
2618 else
2619 cfp_pretbtt = 50;
2620 }
2621 b43_write16(dev, 0x612, cfp_pretbtt);
2622 }
2623
2624 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2625 {
2626 u16 offset;
2627
2628 if (is_ofdm) {
2629 offset = 0x480;
2630 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2631 } else {
2632 offset = 0x4C0;
2633 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2634 }
2635 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2636 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2637 }
2638
2639 static void b43_rate_memory_init(struct b43_wldev *dev)
2640 {
2641 switch (dev->phy.type) {
2642 case B43_PHYTYPE_A:
2643 case B43_PHYTYPE_G:
2644 case B43_PHYTYPE_N:
2645 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2646 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2647 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2648 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2649 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2650 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2651 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2652 if (dev->phy.type == B43_PHYTYPE_A)
2653 break;
2654 /* fallthrough */
2655 case B43_PHYTYPE_B:
2656 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2657 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2658 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2659 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2660 break;
2661 default:
2662 B43_WARN_ON(1);
2663 }
2664 }
2665
2666 /* Set the default values for the PHY TX Control Words. */
2667 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2668 {
2669 u16 ctl = 0;
2670
2671 ctl |= B43_TXH_PHY_ENC_CCK;
2672 ctl |= B43_TXH_PHY_ANT01AUTO;
2673 ctl |= B43_TXH_PHY_TXPWR;
2674
2675 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2676 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2677 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2678 }
2679
2680 /* Set the TX-Antenna for management frames sent by firmware. */
2681 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2682 {
2683 u16 ant;
2684 u16 tmp;
2685
2686 ant = b43_antenna_to_phyctl(antenna);
2687
2688 /* For ACK/CTS */
2689 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2690 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2691 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2692 /* For Probe Resposes */
2693 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2694 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2695 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2696 }
2697
2698 /* This is the opposite of b43_chip_init() */
2699 static void b43_chip_exit(struct b43_wldev *dev)
2700 {
2701 b43_phy_exit(dev);
2702 b43_gpio_cleanup(dev);
2703 /* firmware is released later */
2704 }
2705
2706 /* Initialize the chip
2707 * http://bcm-specs.sipsolutions.net/ChipInit
2708 */
2709 static int b43_chip_init(struct b43_wldev *dev)
2710 {
2711 struct b43_phy *phy = &dev->phy;
2712 int err;
2713 u32 value32, macctl;
2714 u16 value16;
2715
2716 /* Initialize the MAC control */
2717 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2718 if (dev->phy.gmode)
2719 macctl |= B43_MACCTL_GMODE;
2720 macctl |= B43_MACCTL_INFRA;
2721 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2722
2723 err = b43_request_firmware(dev);
2724 if (err)
2725 goto out;
2726 err = b43_upload_microcode(dev);
2727 if (err)
2728 goto out; /* firmware is released later */
2729
2730 err = b43_gpio_init(dev);
2731 if (err)
2732 goto out; /* firmware is released later */
2733
2734 err = b43_upload_initvals(dev);
2735 if (err)
2736 goto err_gpio_clean;
2737
2738 b43_write16(dev, 0x03E6, 0x0000);
2739 err = b43_phy_init(dev);
2740 if (err)
2741 goto err_gpio_clean;
2742
2743 /* Disable Interference Mitigation. */
2744 if (phy->ops->interf_mitigation)
2745 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2746
2747 /* Select the antennae */
2748 if (phy->ops->set_rx_antenna)
2749 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2750 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2751
2752 if (phy->type == B43_PHYTYPE_B) {
2753 value16 = b43_read16(dev, 0x005E);
2754 value16 |= 0x0004;
2755 b43_write16(dev, 0x005E, value16);
2756 }
2757 b43_write32(dev, 0x0100, 0x01000000);
2758 if (dev->dev->id.revision < 5)
2759 b43_write32(dev, 0x010C, 0x01000000);
2760
2761 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2762 & ~B43_MACCTL_INFRA);
2763 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2764 | B43_MACCTL_INFRA);
2765
2766 /* Probe Response Timeout value */
2767 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2768 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2769
2770 /* Initially set the wireless operation mode. */
2771 b43_adjust_opmode(dev);
2772
2773 if (dev->dev->id.revision < 3) {
2774 b43_write16(dev, 0x060E, 0x0000);
2775 b43_write16(dev, 0x0610, 0x8000);
2776 b43_write16(dev, 0x0604, 0x0000);
2777 b43_write16(dev, 0x0606, 0x0200);
2778 } else {
2779 b43_write32(dev, 0x0188, 0x80000000);
2780 b43_write32(dev, 0x018C, 0x02000000);
2781 }
2782 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2783 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2784 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2785 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2786 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2787 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2788 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2789
2790 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2791 value32 |= 0x00100000;
2792 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2793
2794 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2795 dev->dev->bus->chipco.fast_pwrup_delay);
2796
2797 err = 0;
2798 b43dbg(dev->wl, "Chip initialized\n");
2799 out:
2800 return err;
2801
2802 err_gpio_clean:
2803 b43_gpio_cleanup(dev);
2804 return err;
2805 }
2806
2807 static void b43_periodic_every60sec(struct b43_wldev *dev)
2808 {
2809 const struct b43_phy_operations *ops = dev->phy.ops;
2810
2811 if (ops->pwork_60sec)
2812 ops->pwork_60sec(dev);
2813
2814 /* Force check the TX power emission now. */
2815 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2816 }
2817
2818 static void b43_periodic_every30sec(struct b43_wldev *dev)
2819 {
2820 /* Update device statistics. */
2821 b43_calculate_link_quality(dev);
2822 }
2823
2824 static void b43_periodic_every15sec(struct b43_wldev *dev)
2825 {
2826 struct b43_phy *phy = &dev->phy;
2827 u16 wdr;
2828
2829 if (dev->fw.opensource) {
2830 /* Check if the firmware is still alive.
2831 * It will reset the watchdog counter to 0 in its idle loop. */
2832 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2833 if (unlikely(wdr)) {
2834 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2835 b43_controller_restart(dev, "Firmware watchdog");
2836 return;
2837 } else {
2838 b43_shm_write16(dev, B43_SHM_SCRATCH,
2839 B43_WATCHDOG_REG, 1);
2840 }
2841 }
2842
2843 if (phy->ops->pwork_15sec)
2844 phy->ops->pwork_15sec(dev);
2845
2846 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2847 wmb();
2848 }
2849
2850 static void do_periodic_work(struct b43_wldev *dev)
2851 {
2852 unsigned int state;
2853
2854 state = dev->periodic_state;
2855 if (state % 4 == 0)
2856 b43_periodic_every60sec(dev);
2857 if (state % 2 == 0)
2858 b43_periodic_every30sec(dev);
2859 b43_periodic_every15sec(dev);
2860 }
2861
2862 /* Periodic work locking policy:
2863 * The whole periodic work handler is protected by
2864 * wl->mutex. If another lock is needed somewhere in the
2865 * pwork callchain, it's aquired in-place, where it's needed.
2866 */
2867 static void b43_periodic_work_handler(struct work_struct *work)
2868 {
2869 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2870 periodic_work.work);
2871 struct b43_wl *wl = dev->wl;
2872 unsigned long delay;
2873
2874 mutex_lock(&wl->mutex);
2875
2876 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2877 goto out;
2878 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2879 goto out_requeue;
2880
2881 do_periodic_work(dev);
2882
2883 dev->periodic_state++;
2884 out_requeue:
2885 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2886 delay = msecs_to_jiffies(50);
2887 else
2888 delay = round_jiffies_relative(HZ * 15);
2889 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2890 out:
2891 mutex_unlock(&wl->mutex);
2892 }
2893
2894 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2895 {
2896 struct delayed_work *work = &dev->periodic_work;
2897
2898 dev->periodic_state = 0;
2899 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2900 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2901 }
2902
2903 /* Check if communication with the device works correctly. */
2904 static int b43_validate_chipaccess(struct b43_wldev *dev)
2905 {
2906 u32 v, backup;
2907
2908 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2909
2910 /* Check for read/write and endianness problems. */
2911 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2912 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2913 goto error;
2914 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2915 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2916 goto error;
2917
2918 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2919
2920 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2921 /* The 32bit register shadows the two 16bit registers
2922 * with update sideeffects. Validate this. */
2923 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2924 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2925 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2926 goto error;
2927 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2928 goto error;
2929 }
2930 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2931
2932 v = b43_read32(dev, B43_MMIO_MACCTL);
2933 v |= B43_MACCTL_GMODE;
2934 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2935 goto error;
2936
2937 return 0;
2938 error:
2939 b43err(dev->wl, "Failed to validate the chipaccess\n");
2940 return -ENODEV;
2941 }
2942
2943 static void b43_security_init(struct b43_wldev *dev)
2944 {
2945 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2946 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2947 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2948 /* KTP is a word address, but we address SHM bytewise.
2949 * So multiply by two.
2950 */
2951 dev->ktp *= 2;
2952 if (dev->dev->id.revision >= 5) {
2953 /* Number of RCMTA address slots */
2954 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2955 }
2956 b43_clear_keys(dev);
2957 }
2958
2959 static int b43_rng_read(struct hwrng *rng, u32 * data)
2960 {
2961 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2962 unsigned long flags;
2963
2964 /* Don't take wl->mutex here, as it could deadlock with
2965 * hwrng internal locking. It's not needed to take
2966 * wl->mutex here, anyway. */
2967
2968 spin_lock_irqsave(&wl->irq_lock, flags);
2969 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2970 spin_unlock_irqrestore(&wl->irq_lock, flags);
2971
2972 return (sizeof(u16));
2973 }
2974
2975 static void b43_rng_exit(struct b43_wl *wl)
2976 {
2977 if (wl->rng_initialized)
2978 hwrng_unregister(&wl->rng);
2979 }
2980
2981 static int b43_rng_init(struct b43_wl *wl)
2982 {
2983 int err;
2984
2985 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2986 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2987 wl->rng.name = wl->rng_name;
2988 wl->rng.data_read = b43_rng_read;
2989 wl->rng.priv = (unsigned long)wl;
2990 wl->rng_initialized = 1;
2991 err = hwrng_register(&wl->rng);
2992 if (err) {
2993 wl->rng_initialized = 0;
2994 b43err(wl, "Failed to register the random "
2995 "number generator (%d)\n", err);
2996 }
2997
2998 return err;
2999 }
3000
3001 static int b43_op_tx(struct ieee80211_hw *hw,
3002 struct sk_buff *skb)
3003 {
3004 struct b43_wl *wl = hw_to_b43_wl(hw);
3005 struct b43_wldev *dev = wl->current_dev;
3006 unsigned long flags;
3007 int err;
3008
3009 if (unlikely(skb->len < 2 + 2 + 6)) {
3010 /* Too short, this can't be a valid frame. */
3011 goto drop_packet;
3012 }
3013 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3014 if (unlikely(!dev))
3015 goto drop_packet;
3016
3017 /* Transmissions on seperate queues can run concurrently. */
3018 read_lock_irqsave(&wl->tx_lock, flags);
3019
3020 err = -ENODEV;
3021 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3022 if (b43_using_pio_transfers(dev))
3023 err = b43_pio_tx(dev, skb);
3024 else
3025 err = b43_dma_tx(dev, skb);
3026 }
3027
3028 read_unlock_irqrestore(&wl->tx_lock, flags);
3029
3030 if (unlikely(err))
3031 goto drop_packet;
3032 return NETDEV_TX_OK;
3033
3034 drop_packet:
3035 /* We can not transmit this packet. Drop it. */
3036 dev_kfree_skb_any(skb);
3037 return NETDEV_TX_OK;
3038 }
3039
3040 /* Locking: wl->irq_lock */
3041 static void b43_qos_params_upload(struct b43_wldev *dev,
3042 const struct ieee80211_tx_queue_params *p,
3043 u16 shm_offset)
3044 {
3045 u16 params[B43_NR_QOSPARAMS];
3046 int bslots, tmp;
3047 unsigned int i;
3048
3049 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3050
3051 memset(&params, 0, sizeof(params));
3052
3053 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3054 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3055 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3056 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3057 params[B43_QOSPARAM_AIFS] = p->aifs;
3058 params[B43_QOSPARAM_BSLOTS] = bslots;
3059 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3060
3061 for (i = 0; i < ARRAY_SIZE(params); i++) {
3062 if (i == B43_QOSPARAM_STATUS) {
3063 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3064 shm_offset + (i * 2));
3065 /* Mark the parameters as updated. */
3066 tmp |= 0x100;
3067 b43_shm_write16(dev, B43_SHM_SHARED,
3068 shm_offset + (i * 2),
3069 tmp);
3070 } else {
3071 b43_shm_write16(dev, B43_SHM_SHARED,
3072 shm_offset + (i * 2),
3073 params[i]);
3074 }
3075 }
3076 }
3077
3078 /* Update the QOS parameters in hardware. */
3079 static void b43_qos_update(struct b43_wldev *dev)
3080 {
3081 struct b43_wl *wl = dev->wl;
3082 struct b43_qos_params *params;
3083 unsigned long flags;
3084 unsigned int i;
3085
3086 /* Mapping of mac80211 queues to b43 SHM offsets. */
3087 static const u16 qos_shm_offsets[] = {
3088 [0] = B43_QOS_VOICE,
3089 [1] = B43_QOS_VIDEO,
3090 [2] = B43_QOS_BESTEFFORT,
3091 [3] = B43_QOS_BACKGROUND,
3092 };
3093 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
3094
3095 b43_mac_suspend(dev);
3096 spin_lock_irqsave(&wl->irq_lock, flags);
3097
3098 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3099 params = &(wl->qos_params[i]);
3100 if (params->need_hw_update) {
3101 b43_qos_params_upload(dev, &(params->p),
3102 qos_shm_offsets[i]);
3103 params->need_hw_update = 0;
3104 }
3105 }
3106
3107 spin_unlock_irqrestore(&wl->irq_lock, flags);
3108 b43_mac_enable(dev);
3109 }
3110
3111 static void b43_qos_clear(struct b43_wl *wl)
3112 {
3113 struct b43_qos_params *params;
3114 unsigned int i;
3115
3116 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3117 params = &(wl->qos_params[i]);
3118
3119 memset(&(params->p), 0, sizeof(params->p));
3120 params->p.aifs = -1;
3121 params->need_hw_update = 1;
3122 }
3123 }
3124
3125 /* Initialize the core's QOS capabilities */
3126 static void b43_qos_init(struct b43_wldev *dev)
3127 {
3128 struct b43_wl *wl = dev->wl;
3129 unsigned int i;
3130
3131 /* Upload the current QOS parameters. */
3132 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
3133 wl->qos_params[i].need_hw_update = 1;
3134 b43_qos_update(dev);
3135
3136 /* Enable QOS support. */
3137 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3138 b43_write16(dev, B43_MMIO_IFSCTL,
3139 b43_read16(dev, B43_MMIO_IFSCTL)
3140 | B43_MMIO_IFSCTL_USE_EDCF);
3141 }
3142
3143 static void b43_qos_update_work(struct work_struct *work)
3144 {
3145 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
3146 struct b43_wldev *dev;
3147
3148 mutex_lock(&wl->mutex);
3149 dev = wl->current_dev;
3150 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
3151 b43_qos_update(dev);
3152 mutex_unlock(&wl->mutex);
3153 }
3154
3155 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3156 const struct ieee80211_tx_queue_params *params)
3157 {
3158 struct b43_wl *wl = hw_to_b43_wl(hw);
3159 unsigned long flags;
3160 unsigned int queue = (unsigned int)_queue;
3161 struct b43_qos_params *p;
3162
3163 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3164 /* Queue not available or don't support setting
3165 * params on this queue. Return success to not
3166 * confuse mac80211. */
3167 return 0;
3168 }
3169
3170 spin_lock_irqsave(&wl->irq_lock, flags);
3171 p = &(wl->qos_params[queue]);
3172 memcpy(&(p->p), params, sizeof(p->p));
3173 p->need_hw_update = 1;
3174 spin_unlock_irqrestore(&wl->irq_lock, flags);
3175
3176 queue_work(hw->workqueue, &wl->qos_update_work);
3177
3178 return 0;
3179 }
3180
3181 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3182 struct ieee80211_tx_queue_stats *stats)
3183 {
3184 struct b43_wl *wl = hw_to_b43_wl(hw);
3185 struct b43_wldev *dev = wl->current_dev;
3186 unsigned long flags;
3187 int err = -ENODEV;
3188
3189 if (!dev)
3190 goto out;
3191 spin_lock_irqsave(&wl->irq_lock, flags);
3192 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3193 if (b43_using_pio_transfers(dev))
3194 b43_pio_get_tx_stats(dev, stats);
3195 else
3196 b43_dma_get_tx_stats(dev, stats);
3197 err = 0;
3198 }
3199 spin_unlock_irqrestore(&wl->irq_lock, flags);
3200 out:
3201 return err;
3202 }
3203
3204 static int b43_op_get_stats(struct ieee80211_hw *hw,
3205 struct ieee80211_low_level_stats *stats)
3206 {
3207 struct b43_wl *wl = hw_to_b43_wl(hw);
3208 unsigned long flags;
3209
3210 spin_lock_irqsave(&wl->irq_lock, flags);
3211 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3212 spin_unlock_irqrestore(&wl->irq_lock, flags);
3213
3214 return 0;
3215 }
3216
3217 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3218 {
3219 struct ssb_device *sdev = dev->dev;
3220 u32 tmslow;
3221
3222 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3223 tmslow &= ~B43_TMSLOW_GMODE;
3224 tmslow |= B43_TMSLOW_PHYRESET;
3225 tmslow |= SSB_TMSLOW_FGC;
3226 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3227 msleep(1);
3228
3229 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3230 tmslow &= ~SSB_TMSLOW_FGC;
3231 tmslow |= B43_TMSLOW_PHYRESET;
3232 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3233 msleep(1);
3234 }
3235
3236 static const char * band_to_string(enum ieee80211_band band)
3237 {
3238 switch (band) {
3239 case IEEE80211_BAND_5GHZ:
3240 return "5";
3241 case IEEE80211_BAND_2GHZ:
3242 return "2.4";
3243 default:
3244 break;
3245 }
3246 B43_WARN_ON(1);
3247 return "";
3248 }
3249
3250 /* Expects wl->mutex locked */
3251 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3252 {
3253 struct b43_wldev *up_dev = NULL;
3254 struct b43_wldev *down_dev;
3255 struct b43_wldev *d;
3256 int err;
3257 bool gmode;
3258 int prev_status;
3259
3260 /* Find a device and PHY which supports the band. */
3261 list_for_each_entry(d, &wl->devlist, list) {
3262 switch (chan->band) {
3263 case IEEE80211_BAND_5GHZ:
3264 if (d->phy.supports_5ghz) {
3265 up_dev = d;
3266 gmode = 0;
3267 }
3268 break;
3269 case IEEE80211_BAND_2GHZ:
3270 if (d->phy.supports_2ghz) {
3271 up_dev = d;
3272 gmode = 1;
3273 }
3274 break;
3275 default:
3276 B43_WARN_ON(1);
3277 return -EINVAL;
3278 }
3279 if (up_dev)
3280 break;
3281 }
3282 if (!up_dev) {
3283 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3284 band_to_string(chan->band));
3285 return -ENODEV;
3286 }
3287 if ((up_dev == wl->current_dev) &&
3288 (!!wl->current_dev->phy.gmode == !!gmode)) {
3289 /* This device is already running. */
3290 return 0;
3291 }
3292 b43dbg(wl, "Switching to %s-GHz band\n",
3293 band_to_string(chan->band));
3294 down_dev = wl->current_dev;
3295
3296 prev_status = b43_status(down_dev);
3297 /* Shutdown the currently running core. */
3298 if (prev_status >= B43_STAT_STARTED)
3299 b43_wireless_core_stop(down_dev);
3300 if (prev_status >= B43_STAT_INITIALIZED)
3301 b43_wireless_core_exit(down_dev);
3302
3303 if (down_dev != up_dev) {
3304 /* We switch to a different core, so we put PHY into
3305 * RESET on the old core. */
3306 b43_put_phy_into_reset(down_dev);
3307 }
3308
3309 /* Now start the new core. */
3310 up_dev->phy.gmode = gmode;
3311 if (prev_status >= B43_STAT_INITIALIZED) {
3312 err = b43_wireless_core_init(up_dev);
3313 if (err) {
3314 b43err(wl, "Fatal: Could not initialize device for "
3315 "selected %s-GHz band\n",
3316 band_to_string(chan->band));
3317 goto init_failure;
3318 }
3319 }
3320 if (prev_status >= B43_STAT_STARTED) {
3321 err = b43_wireless_core_start(up_dev);
3322 if (err) {
3323 b43err(wl, "Fatal: Coult not start device for "
3324 "selected %s-GHz band\n",
3325 band_to_string(chan->band));
3326 b43_wireless_core_exit(up_dev);
3327 goto init_failure;
3328 }
3329 }
3330 B43_WARN_ON(b43_status(up_dev) != prev_status);
3331
3332 wl->current_dev = up_dev;
3333
3334 return 0;
3335 init_failure:
3336 /* Whoops, failed to init the new core. No core is operating now. */
3337 wl->current_dev = NULL;
3338 return err;
3339 }
3340
3341 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3342 {
3343 struct b43_wl *wl = hw_to_b43_wl(hw);
3344 struct b43_wldev *dev;
3345 struct b43_phy *phy;
3346 unsigned long flags;
3347 int antenna;
3348 int err = 0;
3349 u32 savedirqs;
3350
3351 mutex_lock(&wl->mutex);
3352
3353 /* Switch the band (if necessary). This might change the active core. */
3354 err = b43_switch_band(wl, conf->channel);
3355 if (err)
3356 goto out_unlock_mutex;
3357 dev = wl->current_dev;
3358 phy = &dev->phy;
3359
3360 /* Disable IRQs while reconfiguring the device.
3361 * This makes it possible to drop the spinlock throughout
3362 * the reconfiguration process. */
3363 spin_lock_irqsave(&wl->irq_lock, flags);
3364 if (b43_status(dev) < B43_STAT_STARTED) {
3365 spin_unlock_irqrestore(&wl->irq_lock, flags);
3366 goto out_unlock_mutex;
3367 }
3368 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3369 spin_unlock_irqrestore(&wl->irq_lock, flags);
3370 b43_synchronize_irq(dev);
3371
3372 /* Switch to the requested channel.
3373 * The firmware takes care of races with the TX handler. */
3374 if (conf->channel->hw_value != phy->channel)
3375 b43_switch_channel(dev, conf->channel->hw_value);
3376
3377 /* Enable/Disable ShortSlot timing. */
3378 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3379 dev->short_slot) {
3380 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3381 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3382 b43_short_slot_timing_enable(dev);
3383 else
3384 b43_short_slot_timing_disable(dev);
3385 }
3386
3387 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3388
3389 /* Adjust the desired TX power level. */
3390 if (conf->power_level != 0) {
3391 spin_lock_irqsave(&wl->irq_lock, flags);
3392 if (conf->power_level != phy->desired_txpower) {
3393 phy->desired_txpower = conf->power_level;
3394 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3395 B43_TXPWR_IGNORE_TSSI);
3396 }
3397 spin_unlock_irqrestore(&wl->irq_lock, flags);
3398 }
3399
3400 /* Antennas for RX and management frame TX. */
3401 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3402 b43_mgmtframe_txantenna(dev, antenna);
3403 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3404 if (phy->ops->set_rx_antenna)
3405 phy->ops->set_rx_antenna(dev, antenna);
3406
3407 /* Update templates for AP/mesh mode. */
3408 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) ||
3409 b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT))
3410 b43_set_beacon_int(dev, conf->beacon_int);
3411
3412 if (!!conf->radio_enabled != phy->radio_on) {
3413 if (conf->radio_enabled) {
3414 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
3415 b43info(dev->wl, "Radio turned on by software\n");
3416 if (!dev->radio_hw_enable) {
3417 b43info(dev->wl, "The hardware RF-kill button "
3418 "still turns the radio physically off. "
3419 "Press the button to turn it on.\n");
3420 }
3421 } else {
3422 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
3423 b43info(dev->wl, "Radio turned off by software\n");
3424 }
3425 }
3426
3427 spin_lock_irqsave(&wl->irq_lock, flags);
3428 b43_interrupt_enable(dev, savedirqs);
3429 mmiowb();
3430 spin_unlock_irqrestore(&wl->irq_lock, flags);
3431 out_unlock_mutex:
3432 mutex_unlock(&wl->mutex);
3433
3434 return err;
3435 }
3436
3437 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3438 const u8 *local_addr, const u8 *addr,
3439 struct ieee80211_key_conf *key)
3440 {
3441 struct b43_wl *wl = hw_to_b43_wl(hw);
3442 struct b43_wldev *dev;
3443 unsigned long flags;
3444 u8 algorithm;
3445 u8 index;
3446 int err;
3447 DECLARE_MAC_BUF(mac);
3448
3449 if (modparam_nohwcrypt)
3450 return -ENOSPC; /* User disabled HW-crypto */
3451
3452 mutex_lock(&wl->mutex);
3453 spin_lock_irqsave(&wl->irq_lock, flags);
3454
3455 dev = wl->current_dev;
3456 err = -ENODEV;
3457 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3458 goto out_unlock;
3459
3460 if (dev->fw.pcm_request_failed) {
3461 /* We don't have firmware for the crypto engine.
3462 * Must use software-crypto. */
3463 err = -EOPNOTSUPP;
3464 goto out_unlock;
3465 }
3466
3467 err = -EINVAL;
3468 switch (key->alg) {
3469 case ALG_WEP:
3470 if (key->keylen == 5)
3471 algorithm = B43_SEC_ALGO_WEP40;
3472 else
3473 algorithm = B43_SEC_ALGO_WEP104;
3474 break;
3475 case ALG_TKIP:
3476 algorithm = B43_SEC_ALGO_TKIP;
3477 break;
3478 case ALG_CCMP:
3479 algorithm = B43_SEC_ALGO_AES;
3480 break;
3481 default:
3482 B43_WARN_ON(1);
3483 goto out_unlock;
3484 }
3485 index = (u8) (key->keyidx);
3486 if (index > 3)
3487 goto out_unlock;
3488
3489 switch (cmd) {
3490 case SET_KEY:
3491 if (algorithm == B43_SEC_ALGO_TKIP) {
3492 /* FIXME: No TKIP hardware encryption for now. */
3493 err = -EOPNOTSUPP;
3494 goto out_unlock;
3495 }
3496
3497 if (is_broadcast_ether_addr(addr)) {
3498 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3499 err = b43_key_write(dev, index, algorithm,
3500 key->key, key->keylen, NULL, key);
3501 } else {
3502 /*
3503 * either pairwise key or address is 00:00:00:00:00:00
3504 * for transmit-only keys
3505 */
3506 err = b43_key_write(dev, -1, algorithm,
3507 key->key, key->keylen, addr, key);
3508 }
3509 if (err)
3510 goto out_unlock;
3511
3512 if (algorithm == B43_SEC_ALGO_WEP40 ||
3513 algorithm == B43_SEC_ALGO_WEP104) {
3514 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3515 } else {
3516 b43_hf_write(dev,
3517 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3518 }
3519 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3520 break;
3521 case DISABLE_KEY: {
3522 err = b43_key_clear(dev, key->hw_key_idx);
3523 if (err)
3524 goto out_unlock;
3525 break;
3526 }
3527 default:
3528 B43_WARN_ON(1);
3529 }
3530 out_unlock:
3531 spin_unlock_irqrestore(&wl->irq_lock, flags);
3532 mutex_unlock(&wl->mutex);
3533 if (!err) {
3534 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3535 "mac: %s\n",
3536 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3537 print_mac(mac, addr));
3538 }
3539 return err;
3540 }
3541
3542 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3543 unsigned int changed, unsigned int *fflags,
3544 int mc_count, struct dev_addr_list *mc_list)
3545 {
3546 struct b43_wl *wl = hw_to_b43_wl(hw);
3547 struct b43_wldev *dev = wl->current_dev;
3548 unsigned long flags;
3549
3550 if (!dev) {
3551 *fflags = 0;
3552 return;
3553 }
3554
3555 spin_lock_irqsave(&wl->irq_lock, flags);
3556 *fflags &= FIF_PROMISC_IN_BSS |
3557 FIF_ALLMULTI |
3558 FIF_FCSFAIL |
3559 FIF_PLCPFAIL |
3560 FIF_CONTROL |
3561 FIF_OTHER_BSS |
3562 FIF_BCN_PRBRESP_PROMISC;
3563
3564 changed &= FIF_PROMISC_IN_BSS |
3565 FIF_ALLMULTI |
3566 FIF_FCSFAIL |
3567 FIF_PLCPFAIL |
3568 FIF_CONTROL |
3569 FIF_OTHER_BSS |
3570 FIF_BCN_PRBRESP_PROMISC;
3571
3572 wl->filter_flags = *fflags;
3573
3574 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3575 b43_adjust_opmode(dev);
3576 spin_unlock_irqrestore(&wl->irq_lock, flags);
3577 }
3578
3579 static int b43_op_config_interface(struct ieee80211_hw *hw,
3580 struct ieee80211_vif *vif,
3581 struct ieee80211_if_conf *conf)
3582 {
3583 struct b43_wl *wl = hw_to_b43_wl(hw);
3584 struct b43_wldev *dev = wl->current_dev;
3585 unsigned long flags;
3586
3587 if (!dev)
3588 return -ENODEV;
3589 mutex_lock(&wl->mutex);
3590 spin_lock_irqsave(&wl->irq_lock, flags);
3591 B43_WARN_ON(wl->vif != vif);
3592 if (conf->bssid)
3593 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3594 else
3595 memset(wl->bssid, 0, ETH_ALEN);
3596 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3597 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) ||
3598 b43_is_mode(wl, IEEE80211_IF_TYPE_MESH_POINT)) {
3599 B43_WARN_ON(vif->type != wl->if_type);
3600 if (conf->changed & IEEE80211_IFCC_SSID)
3601 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3602 if (conf->changed & IEEE80211_IFCC_BEACON)
3603 b43_update_templates(wl);
3604 } else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) {
3605 if (conf->changed & IEEE80211_IFCC_BEACON)
3606 b43_update_templates(wl);
3607 }
3608 b43_write_mac_bssid_templates(dev);
3609 }
3610 spin_unlock_irqrestore(&wl->irq_lock, flags);
3611 mutex_unlock(&wl->mutex);
3612
3613 return 0;
3614 }
3615
3616 /* Locking: wl->mutex */
3617 static void b43_wireless_core_stop(struct b43_wldev *dev)
3618 {
3619 struct b43_wl *wl = dev->wl;
3620 unsigned long flags;
3621
3622 if (b43_status(dev) < B43_STAT_STARTED)
3623 return;
3624
3625 /* Disable and sync interrupts. We must do this before than
3626 * setting the status to INITIALIZED, as the interrupt handler
3627 * won't care about IRQs then. */
3628 spin_lock_irqsave(&wl->irq_lock, flags);
3629 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3630 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3631 spin_unlock_irqrestore(&wl->irq_lock, flags);
3632 b43_synchronize_irq(dev);
3633
3634 write_lock_irqsave(&wl->tx_lock, flags);
3635 b43_set_status(dev, B43_STAT_INITIALIZED);
3636 write_unlock_irqrestore(&wl->tx_lock, flags);
3637
3638 b43_pio_stop(dev);
3639 mutex_unlock(&wl->mutex);
3640 /* Must unlock as it would otherwise deadlock. No races here.
3641 * Cancel the possibly running self-rearming periodic work. */
3642 cancel_delayed_work_sync(&dev->periodic_work);
3643 mutex_lock(&wl->mutex);
3644
3645 b43_mac_suspend(dev);
3646 free_irq(dev->dev->irq, dev);
3647 b43dbg(wl, "Wireless interface stopped\n");
3648 }
3649
3650 /* Locking: wl->mutex */
3651 static int b43_wireless_core_start(struct b43_wldev *dev)
3652 {
3653 int err;
3654
3655 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3656
3657 drain_txstatus_queue(dev);
3658 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3659 IRQF_SHARED, KBUILD_MODNAME, dev);
3660 if (err) {
3661 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3662 goto out;
3663 }
3664
3665 /* We are ready to run. */
3666 b43_set_status(dev, B43_STAT_STARTED);
3667
3668 /* Start data flow (TX/RX). */
3669 b43_mac_enable(dev);
3670 b43_interrupt_enable(dev, dev->irq_savedstate);
3671
3672 /* Start maintainance work */
3673 b43_periodic_tasks_setup(dev);
3674
3675 b43dbg(dev->wl, "Wireless interface started\n");
3676 out:
3677 return err;
3678 }
3679
3680 /* Get PHY and RADIO versioning numbers */
3681 static int b43_phy_versioning(struct b43_wldev *dev)
3682 {
3683 struct b43_phy *phy = &dev->phy;
3684 u32 tmp;
3685 u8 analog_type;
3686 u8 phy_type;
3687 u8 phy_rev;
3688 u16 radio_manuf;
3689 u16 radio_ver;
3690 u16 radio_rev;
3691 int unsupported = 0;
3692
3693 /* Get PHY versioning */
3694 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3695 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3696 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3697 phy_rev = (tmp & B43_PHYVER_VERSION);
3698 switch (phy_type) {
3699 case B43_PHYTYPE_A:
3700 if (phy_rev >= 4)
3701 unsupported = 1;
3702 break;
3703 case B43_PHYTYPE_B:
3704 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3705 && phy_rev != 7)
3706 unsupported = 1;
3707 break;
3708 case B43_PHYTYPE_G:
3709 if (phy_rev > 9)
3710 unsupported = 1;
3711 break;
3712 #ifdef CONFIG_B43_NPHY
3713 case B43_PHYTYPE_N:
3714 if (phy_rev > 1)
3715 unsupported = 1;
3716 break;
3717 #endif
3718 default:
3719 unsupported = 1;
3720 };
3721 if (unsupported) {
3722 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3723 "(Analog %u, Type %u, Revision %u)\n",
3724 analog_type, phy_type, phy_rev);
3725 return -EOPNOTSUPP;
3726 }
3727 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3728 analog_type, phy_type, phy_rev);
3729
3730 /* Get RADIO versioning */
3731 if (dev->dev->bus->chip_id == 0x4317) {
3732 if (dev->dev->bus->chip_rev == 0)
3733 tmp = 0x3205017F;
3734 else if (dev->dev->bus->chip_rev == 1)
3735 tmp = 0x4205017F;
3736 else
3737 tmp = 0x5205017F;
3738 } else {
3739 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3740 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3741 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3742 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3743 }
3744 radio_manuf = (tmp & 0x00000FFF);
3745 radio_ver = (tmp & 0x0FFFF000) >> 12;
3746 radio_rev = (tmp & 0xF0000000) >> 28;
3747 if (radio_manuf != 0x17F /* Broadcom */)
3748 unsupported = 1;
3749 switch (phy_type) {
3750 case B43_PHYTYPE_A:
3751 if (radio_ver != 0x2060)
3752 unsupported = 1;
3753 if (radio_rev != 1)
3754 unsupported = 1;
3755 if (radio_manuf != 0x17F)
3756 unsupported = 1;
3757 break;
3758 case B43_PHYTYPE_B:
3759 if ((radio_ver & 0xFFF0) != 0x2050)
3760 unsupported = 1;
3761 break;
3762 case B43_PHYTYPE_G:
3763 if (radio_ver != 0x2050)
3764 unsupported = 1;
3765 break;
3766 case B43_PHYTYPE_N:
3767 if (radio_ver != 0x2055)
3768 unsupported = 1;
3769 break;
3770 default:
3771 B43_WARN_ON(1);
3772 }
3773 if (unsupported) {
3774 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3775 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3776 radio_manuf, radio_ver, radio_rev);
3777 return -EOPNOTSUPP;
3778 }
3779 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3780 radio_manuf, radio_ver, radio_rev);
3781
3782 phy->radio_manuf = radio_manuf;
3783 phy->radio_ver = radio_ver;
3784 phy->radio_rev = radio_rev;
3785
3786 phy->analog = analog_type;
3787 phy->type = phy_type;
3788 phy->rev = phy_rev;
3789
3790 return 0;
3791 }
3792
3793 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3794 struct b43_phy *phy)
3795 {
3796 phy->hardware_power_control = !!modparam_hwpctl;
3797 phy->next_txpwr_check_time = jiffies;
3798 /* PHY TX errors counter. */
3799 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3800 }
3801
3802 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3803 {
3804 dev->dfq_valid = 0;
3805
3806 /* Assume the radio is enabled. If it's not enabled, the state will
3807 * immediately get fixed on the first periodic work run. */
3808 dev->radio_hw_enable = 1;
3809
3810 /* Stats */
3811 memset(&dev->stats, 0, sizeof(dev->stats));
3812
3813 setup_struct_phy_for_init(dev, &dev->phy);
3814
3815 /* IRQ related flags */
3816 dev->irq_reason = 0;
3817 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3818 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3819
3820 dev->mac_suspended = 1;
3821
3822 /* Noise calculation context */
3823 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3824 }
3825
3826 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3827 {
3828 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3829 u64 hf;
3830
3831 if (!modparam_btcoex)
3832 return;
3833 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3834 return;
3835 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3836 return;
3837
3838 hf = b43_hf_read(dev);
3839 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3840 hf |= B43_HF_BTCOEXALT;
3841 else
3842 hf |= B43_HF_BTCOEX;
3843 b43_hf_write(dev, hf);
3844 }
3845
3846 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3847 {
3848 if (!modparam_btcoex)
3849 return;
3850 //TODO
3851 }
3852
3853 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3854 {
3855 #ifdef CONFIG_SSB_DRIVER_PCICORE
3856 struct ssb_bus *bus = dev->dev->bus;
3857 u32 tmp;
3858
3859 if (bus->pcicore.dev &&
3860 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3861 bus->pcicore.dev->id.revision <= 5) {
3862 /* IMCFGLO timeouts workaround. */
3863 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3864 tmp &= ~SSB_IMCFGLO_REQTO;
3865 tmp &= ~SSB_IMCFGLO_SERTO;
3866 switch (bus->bustype) {
3867 case SSB_BUSTYPE_PCI:
3868 case SSB_BUSTYPE_PCMCIA:
3869 tmp |= 0x32;
3870 break;
3871 case SSB_BUSTYPE_SSB:
3872 tmp |= 0x53;
3873 break;
3874 }
3875 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3876 }
3877 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3878 }
3879
3880 /* Write the short and long frame retry limit values. */
3881 static void b43_set_retry_limits(struct b43_wldev *dev,
3882 unsigned int short_retry,
3883 unsigned int long_retry)
3884 {
3885 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3886 * the chip-internal counter. */
3887 short_retry = min(short_retry, (unsigned int)0xF);
3888 long_retry = min(long_retry, (unsigned int)0xF);
3889
3890 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3891 short_retry);
3892 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3893 long_retry);
3894 }
3895
3896 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3897 {
3898 u16 pu_delay;
3899
3900 /* The time value is in microseconds. */
3901 if (dev->phy.type == B43_PHYTYPE_A)
3902 pu_delay = 3700;
3903 else
3904 pu_delay = 1050;
3905 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
3906 pu_delay = 500;
3907 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3908 pu_delay = max(pu_delay, (u16)2400);
3909
3910 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3911 }
3912
3913 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3914 static void b43_set_pretbtt(struct b43_wldev *dev)
3915 {
3916 u16 pretbtt;
3917
3918 /* The time value is in microseconds. */
3919 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
3920 pretbtt = 2;
3921 } else {
3922 if (dev->phy.type == B43_PHYTYPE_A)
3923 pretbtt = 120;
3924 else
3925 pretbtt = 250;
3926 }
3927 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3928 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3929 }
3930
3931 /* Shutdown a wireless core */
3932 /* Locking: wl->mutex */
3933 static void b43_wireless_core_exit(struct b43_wldev *dev)
3934 {
3935 u32 macctl;
3936
3937 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3938 if (b43_status(dev) != B43_STAT_INITIALIZED)
3939 return;
3940 b43_set_status(dev, B43_STAT_UNINIT);
3941
3942 /* Stop the microcode PSM. */
3943 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3944 macctl &= ~B43_MACCTL_PSM_RUN;
3945 macctl |= B43_MACCTL_PSM_JMP0;
3946 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3947
3948 if (!dev->suspend_in_progress) {
3949 b43_leds_exit(dev);
3950 b43_rng_exit(dev->wl);
3951 }
3952 b43_dma_free(dev);
3953 b43_pio_free(dev);
3954 b43_chip_exit(dev);
3955 b43_switch_analog(dev, 0);
3956 if (dev->wl->current_beacon) {
3957 dev_kfree_skb_any(dev->wl->current_beacon);
3958 dev->wl->current_beacon = NULL;
3959 }
3960
3961 ssb_device_disable(dev->dev, 0);
3962 ssb_bus_may_powerdown(dev->dev->bus);
3963 }
3964
3965 /* Initialize a wireless core */
3966 static int b43_wireless_core_init(struct b43_wldev *dev)
3967 {
3968 struct b43_wl *wl = dev->wl;
3969 struct ssb_bus *bus = dev->dev->bus;
3970 struct ssb_sprom *sprom = &bus->sprom;
3971 struct b43_phy *phy = &dev->phy;
3972 int err;
3973 u64 hf;
3974 u32 tmp;
3975
3976 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3977
3978 err = ssb_bus_powerup(bus, 0);
3979 if (err)
3980 goto out;
3981 if (!ssb_device_is_enabled(dev->dev)) {
3982 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3983 b43_wireless_core_reset(dev, tmp);
3984 }
3985
3986 /* Reset all data structures. */
3987 setup_struct_wldev_for_init(dev);
3988 phy->ops->prepare_structs(dev);
3989
3990 /* Enable IRQ routing to this device. */
3991 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3992
3993 b43_imcfglo_timeouts_workaround(dev);
3994 b43_bluetooth_coext_disable(dev);
3995 if (phy->ops->prepare_hardware) {
3996 err = phy->ops->prepare_hardware(dev);
3997 if (err)
3998 goto err_busdown;
3999 }
4000 err = b43_chip_init(dev);
4001 if (err)
4002 goto err_busdown;
4003 b43_shm_write16(dev, B43_SHM_SHARED,
4004 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4005 hf = b43_hf_read(dev);
4006 if (phy->type == B43_PHYTYPE_G) {
4007 hf |= B43_HF_SYMW;
4008 if (phy->rev == 1)
4009 hf |= B43_HF_GDCW;
4010 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4011 hf |= B43_HF_OFDMPABOOST;
4012 } else if (phy->type == B43_PHYTYPE_B) {
4013 hf |= B43_HF_SYMW;
4014 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4015 hf &= ~B43_HF_GDCW;
4016 }
4017 b43_hf_write(dev, hf);
4018
4019 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4020 B43_DEFAULT_LONG_RETRY_LIMIT);
4021 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4022 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4023
4024 /* Disable sending probe responses from firmware.
4025 * Setting the MaxTime to one usec will always trigger
4026 * a timeout, so we never send any probe resp.
4027 * A timeout of zero is infinite. */
4028 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4029
4030 b43_rate_memory_init(dev);
4031 b43_set_phytxctl_defaults(dev);
4032
4033 /* Minimum Contention Window */
4034 if (phy->type == B43_PHYTYPE_B) {
4035 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4036 } else {
4037 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4038 }
4039 /* Maximum Contention Window */
4040 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4041
4042 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4043 dev->__using_pio_transfers = 1;
4044 err = b43_pio_init(dev);
4045 } else {
4046 dev->__using_pio_transfers = 0;
4047 err = b43_dma_init(dev);
4048 }
4049 if (err)
4050 goto err_chip_exit;
4051 b43_qos_init(dev);
4052 b43_set_synth_pu_delay(dev, 1);
4053 b43_bluetooth_coext_enable(dev);
4054
4055 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4056 b43_upload_card_macaddress(dev);
4057 b43_security_init(dev);
4058 if (!dev->suspend_in_progress)
4059 b43_rng_init(wl);
4060
4061 b43_set_status(dev, B43_STAT_INITIALIZED);
4062
4063 if (!dev->suspend_in_progress)
4064 b43_leds_init(dev);
4065 out:
4066 return err;
4067
4068 err_chip_exit:
4069 b43_chip_exit(dev);
4070 err_busdown:
4071 ssb_bus_may_powerdown(bus);
4072 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4073 return err;
4074 }
4075
4076 static int b43_op_add_interface(struct ieee80211_hw *hw,
4077 struct ieee80211_if_init_conf *conf)
4078 {
4079 struct b43_wl *wl = hw_to_b43_wl(hw);
4080 struct b43_wldev *dev;
4081 unsigned long flags;
4082 int err = -EOPNOTSUPP;
4083
4084 /* TODO: allow WDS/AP devices to coexist */
4085
4086 if (conf->type != IEEE80211_IF_TYPE_AP &&
4087 conf->type != IEEE80211_IF_TYPE_MESH_POINT &&
4088 conf->type != IEEE80211_IF_TYPE_STA &&
4089 conf->type != IEEE80211_IF_TYPE_WDS &&
4090 conf->type != IEEE80211_IF_TYPE_IBSS)
4091 return -EOPNOTSUPP;
4092
4093 mutex_lock(&wl->mutex);
4094 if (wl->operating)
4095 goto out_mutex_unlock;
4096
4097 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4098
4099 dev = wl->current_dev;
4100 wl->operating = 1;
4101 wl->vif = conf->vif;
4102 wl->if_type = conf->type;
4103 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4104
4105 spin_lock_irqsave(&wl->irq_lock, flags);
4106 b43_adjust_opmode(dev);
4107 b43_set_pretbtt(dev);
4108 b43_set_synth_pu_delay(dev, 0);
4109 b43_upload_card_macaddress(dev);
4110 spin_unlock_irqrestore(&wl->irq_lock, flags);
4111
4112 err = 0;
4113 out_mutex_unlock:
4114 mutex_unlock(&wl->mutex);
4115
4116 return err;
4117 }
4118
4119 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4120 struct ieee80211_if_init_conf *conf)
4121 {
4122 struct b43_wl *wl = hw_to_b43_wl(hw);
4123 struct b43_wldev *dev = wl->current_dev;
4124 unsigned long flags;
4125
4126 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4127
4128 mutex_lock(&wl->mutex);
4129
4130 B43_WARN_ON(!wl->operating);
4131 B43_WARN_ON(wl->vif != conf->vif);
4132 wl->vif = NULL;
4133
4134 wl->operating = 0;
4135
4136 spin_lock_irqsave(&wl->irq_lock, flags);
4137 b43_adjust_opmode(dev);
4138 memset(wl->mac_addr, 0, ETH_ALEN);
4139 b43_upload_card_macaddress(dev);
4140 spin_unlock_irqrestore(&wl->irq_lock, flags);
4141
4142 mutex_unlock(&wl->mutex);
4143 }
4144
4145 static int b43_op_start(struct ieee80211_hw *hw)
4146 {
4147 struct b43_wl *wl = hw_to_b43_wl(hw);
4148 struct b43_wldev *dev = wl->current_dev;
4149 int did_init = 0;
4150 int err = 0;
4151 bool do_rfkill_exit = 0;
4152
4153 /* Kill all old instance specific information to make sure
4154 * the card won't use it in the short timeframe between start
4155 * and mac80211 reconfiguring it. */
4156 memset(wl->bssid, 0, ETH_ALEN);
4157 memset(wl->mac_addr, 0, ETH_ALEN);
4158 wl->filter_flags = 0;
4159 wl->radiotap_enabled = 0;
4160 b43_qos_clear(wl);
4161 wl->beacon0_uploaded = 0;
4162 wl->beacon1_uploaded = 0;
4163 wl->beacon_templates_virgin = 1;
4164
4165 /* First register RFkill.
4166 * LEDs that are registered later depend on it. */
4167 b43_rfkill_init(dev);
4168
4169 mutex_lock(&wl->mutex);
4170
4171 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4172 err = b43_wireless_core_init(dev);
4173 if (err) {
4174 do_rfkill_exit = 1;
4175 goto out_mutex_unlock;
4176 }
4177 did_init = 1;
4178 }
4179
4180 if (b43_status(dev) < B43_STAT_STARTED) {
4181 err = b43_wireless_core_start(dev);
4182 if (err) {
4183 if (did_init)
4184 b43_wireless_core_exit(dev);
4185 do_rfkill_exit = 1;
4186 goto out_mutex_unlock;
4187 }
4188 }
4189
4190 out_mutex_unlock:
4191 mutex_unlock(&wl->mutex);
4192
4193 if (do_rfkill_exit)
4194 b43_rfkill_exit(dev);
4195
4196 return err;
4197 }
4198
4199 static void b43_op_stop(struct ieee80211_hw *hw)
4200 {
4201 struct b43_wl *wl = hw_to_b43_wl(hw);
4202 struct b43_wldev *dev = wl->current_dev;
4203
4204 b43_rfkill_exit(dev);
4205 cancel_work_sync(&(wl->qos_update_work));
4206 cancel_work_sync(&(wl->beacon_update_trigger));
4207
4208 mutex_lock(&wl->mutex);
4209 if (b43_status(dev) >= B43_STAT_STARTED)
4210 b43_wireless_core_stop(dev);
4211 b43_wireless_core_exit(dev);
4212 mutex_unlock(&wl->mutex);
4213
4214 cancel_work_sync(&(wl->txpower_adjust_work));
4215 }
4216
4217 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4218 u32 short_retry_limit, u32 long_retry_limit)
4219 {
4220 struct b43_wl *wl = hw_to_b43_wl(hw);
4221 struct b43_wldev *dev;
4222 int err = 0;
4223
4224 mutex_lock(&wl->mutex);
4225 dev = wl->current_dev;
4226 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4227 err = -ENODEV;
4228 goto out_unlock;
4229 }
4230 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4231 out_unlock:
4232 mutex_unlock(&wl->mutex);
4233
4234 return err;
4235 }
4236
4237 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4238 {
4239 struct b43_wl *wl = hw_to_b43_wl(hw);
4240 unsigned long flags;
4241
4242 spin_lock_irqsave(&wl->irq_lock, flags);
4243 b43_update_templates(wl);
4244 spin_unlock_irqrestore(&wl->irq_lock, flags);
4245
4246 return 0;
4247 }
4248
4249 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4250 struct ieee80211_vif *vif,
4251 enum sta_notify_cmd notify_cmd,
4252 const u8 *addr)
4253 {
4254 struct b43_wl *wl = hw_to_b43_wl(hw);
4255
4256 B43_WARN_ON(!vif || wl->vif != vif);
4257 }
4258
4259 static const struct ieee80211_ops b43_hw_ops = {
4260 .tx = b43_op_tx,
4261 .conf_tx = b43_op_conf_tx,
4262 .add_interface = b43_op_add_interface,
4263 .remove_interface = b43_op_remove_interface,
4264 .config = b43_op_config,
4265 .config_interface = b43_op_config_interface,
4266 .configure_filter = b43_op_configure_filter,
4267 .set_key = b43_op_set_key,
4268 .get_stats = b43_op_get_stats,
4269 .get_tx_stats = b43_op_get_tx_stats,
4270 .start = b43_op_start,
4271 .stop = b43_op_stop,
4272 .set_retry_limit = b43_op_set_retry_limit,
4273 .set_tim = b43_op_beacon_set_tim,
4274 .sta_notify = b43_op_sta_notify,
4275 };
4276
4277 /* Hard-reset the chip. Do not call this directly.
4278 * Use b43_controller_restart()
4279 */
4280 static void b43_chip_reset(struct work_struct *work)
4281 {
4282 struct b43_wldev *dev =
4283 container_of(work, struct b43_wldev, restart_work);
4284 struct b43_wl *wl = dev->wl;
4285 int err = 0;
4286 int prev_status;
4287
4288 mutex_lock(&wl->mutex);
4289
4290 prev_status = b43_status(dev);
4291 /* Bring the device down... */
4292 if (prev_status >= B43_STAT_STARTED)
4293 b43_wireless_core_stop(dev);
4294 if (prev_status >= B43_STAT_INITIALIZED)
4295 b43_wireless_core_exit(dev);
4296
4297 /* ...and up again. */
4298 if (prev_status >= B43_STAT_INITIALIZED) {
4299 err = b43_wireless_core_init(dev);
4300 if (err)
4301 goto out;
4302 }
4303 if (prev_status >= B43_STAT_STARTED) {
4304 err = b43_wireless_core_start(dev);
4305 if (err) {
4306 b43_wireless_core_exit(dev);
4307 goto out;
4308 }
4309 }
4310 out:
4311 if (err)
4312 wl->current_dev = NULL; /* Failed to init the dev. */
4313 mutex_unlock(&wl->mutex);
4314 if (err)
4315 b43err(wl, "Controller restart FAILED\n");
4316 else
4317 b43info(wl, "Controller restarted\n");
4318 }
4319
4320 static int b43_setup_bands(struct b43_wldev *dev,
4321 bool have_2ghz_phy, bool have_5ghz_phy)
4322 {
4323 struct ieee80211_hw *hw = dev->wl->hw;
4324
4325 if (have_2ghz_phy)
4326 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4327 if (dev->phy.type == B43_PHYTYPE_N) {
4328 if (have_5ghz_phy)
4329 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4330 } else {
4331 if (have_5ghz_phy)
4332 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4333 }
4334
4335 dev->phy.supports_2ghz = have_2ghz_phy;
4336 dev->phy.supports_5ghz = have_5ghz_phy;
4337
4338 return 0;
4339 }
4340
4341 static void b43_wireless_core_detach(struct b43_wldev *dev)
4342 {
4343 /* We release firmware that late to not be required to re-request
4344 * is all the time when we reinit the core. */
4345 b43_release_firmware(dev);
4346 b43_phy_free(dev);
4347 }
4348
4349 static int b43_wireless_core_attach(struct b43_wldev *dev)
4350 {
4351 struct b43_wl *wl = dev->wl;
4352 struct ssb_bus *bus = dev->dev->bus;
4353 struct pci_dev *pdev = bus->host_pci;
4354 int err;
4355 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4356 u32 tmp;
4357
4358 /* Do NOT do any device initialization here.
4359 * Do it in wireless_core_init() instead.
4360 * This function is for gathering basic information about the HW, only.
4361 * Also some structs may be set up here. But most likely you want to have
4362 * that in core_init(), too.
4363 */
4364
4365 err = ssb_bus_powerup(bus, 0);
4366 if (err) {
4367 b43err(wl, "Bus powerup failed\n");
4368 goto out;
4369 }
4370 /* Get the PHY type. */
4371 if (dev->dev->id.revision >= 5) {
4372 u32 tmshigh;
4373
4374 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4375 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4376 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4377 } else
4378 B43_WARN_ON(1);
4379
4380 dev->phy.gmode = have_2ghz_phy;
4381 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4382 b43_wireless_core_reset(dev, tmp);
4383
4384 err = b43_phy_versioning(dev);
4385 if (err)
4386 goto err_powerdown;
4387 /* Check if this device supports multiband. */
4388 if (!pdev ||
4389 (pdev->device != 0x4312 &&
4390 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4391 /* No multiband support. */
4392 have_2ghz_phy = 0;
4393 have_5ghz_phy = 0;
4394 switch (dev->phy.type) {
4395 case B43_PHYTYPE_A:
4396 have_5ghz_phy = 1;
4397 break;
4398 case B43_PHYTYPE_G:
4399 case B43_PHYTYPE_N:
4400 have_2ghz_phy = 1;
4401 break;
4402 default:
4403 B43_WARN_ON(1);
4404 }
4405 }
4406 if (dev->phy.type == B43_PHYTYPE_A) {
4407 /* FIXME */
4408 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4409 err = -EOPNOTSUPP;
4410 goto err_powerdown;
4411 }
4412 if (1 /* disable A-PHY */) {
4413 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4414 if (dev->phy.type != B43_PHYTYPE_N) {
4415 have_2ghz_phy = 1;
4416 have_5ghz_phy = 0;
4417 }
4418 }
4419
4420 err = b43_phy_allocate(dev);
4421 if (err)
4422 goto err_powerdown;
4423
4424 dev->phy.gmode = have_2ghz_phy;
4425 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4426 b43_wireless_core_reset(dev, tmp);
4427
4428 err = b43_validate_chipaccess(dev);
4429 if (err)
4430 goto err_phy_free;
4431 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4432 if (err)
4433 goto err_phy_free;
4434
4435 /* Now set some default "current_dev" */
4436 if (!wl->current_dev)
4437 wl->current_dev = dev;
4438 INIT_WORK(&dev->restart_work, b43_chip_reset);
4439
4440 b43_switch_analog(dev, 0);
4441 ssb_device_disable(dev->dev, 0);
4442 ssb_bus_may_powerdown(bus);
4443
4444 out:
4445 return err;
4446
4447 err_phy_free:
4448 b43_phy_free(dev);
4449 err_powerdown:
4450 ssb_bus_may_powerdown(bus);
4451 return err;
4452 }
4453
4454 static void b43_one_core_detach(struct ssb_device *dev)
4455 {
4456 struct b43_wldev *wldev;
4457 struct b43_wl *wl;
4458
4459 /* Do not cancel ieee80211-workqueue based work here.
4460 * See comment in b43_remove(). */
4461
4462 wldev = ssb_get_drvdata(dev);
4463 wl = wldev->wl;
4464 b43_debugfs_remove_device(wldev);
4465 b43_wireless_core_detach(wldev);
4466 list_del(&wldev->list);
4467 wl->nr_devs--;
4468 ssb_set_drvdata(dev, NULL);
4469 kfree(wldev);
4470 }
4471
4472 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4473 {
4474 struct b43_wldev *wldev;
4475 struct pci_dev *pdev;
4476 int err = -ENOMEM;
4477
4478 if (!list_empty(&wl->devlist)) {
4479 /* We are not the first core on this chip. */
4480 pdev = dev->bus->host_pci;
4481 /* Only special chips support more than one wireless
4482 * core, although some of the other chips have more than
4483 * one wireless core as well. Check for this and
4484 * bail out early.
4485 */
4486 if (!pdev ||
4487 ((pdev->device != 0x4321) &&
4488 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4489 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4490 return -ENODEV;
4491 }
4492 }
4493
4494 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4495 if (!wldev)
4496 goto out;
4497
4498 wldev->dev = dev;
4499 wldev->wl = wl;
4500 b43_set_status(wldev, B43_STAT_UNINIT);
4501 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4502 tasklet_init(&wldev->isr_tasklet,
4503 (void (*)(unsigned long))b43_interrupt_tasklet,
4504 (unsigned long)wldev);
4505 INIT_LIST_HEAD(&wldev->list);
4506
4507 err = b43_wireless_core_attach(wldev);
4508 if (err)
4509 goto err_kfree_wldev;
4510
4511 list_add(&wldev->list, &wl->devlist);
4512 wl->nr_devs++;
4513 ssb_set_drvdata(dev, wldev);
4514 b43_debugfs_add_device(wldev);
4515
4516 out:
4517 return err;
4518
4519 err_kfree_wldev:
4520 kfree(wldev);
4521 return err;
4522 }
4523
4524 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4525 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4526 (pdev->device == _device) && \
4527 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4528 (pdev->subsystem_device == _subdevice) )
4529
4530 static void b43_sprom_fixup(struct ssb_bus *bus)
4531 {
4532 struct pci_dev *pdev;
4533
4534 /* boardflags workarounds */
4535 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4536 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4537 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4538 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4539 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4540 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4541 if (bus->bustype == SSB_BUSTYPE_PCI) {
4542 pdev = bus->host_pci;
4543 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4544 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4545 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4546 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4547 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
4548 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4549 }
4550 }
4551
4552 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4553 {
4554 struct ieee80211_hw *hw = wl->hw;
4555
4556 ssb_set_devtypedata(dev, NULL);
4557 ieee80211_free_hw(hw);
4558 }
4559
4560 static int b43_wireless_init(struct ssb_device *dev)
4561 {
4562 struct ssb_sprom *sprom = &dev->bus->sprom;
4563 struct ieee80211_hw *hw;
4564 struct b43_wl *wl;
4565 int err = -ENOMEM;
4566
4567 b43_sprom_fixup(dev->bus);
4568
4569 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4570 if (!hw) {
4571 b43err(NULL, "Could not allocate ieee80211 device\n");
4572 goto out;
4573 }
4574
4575 /* fill hw info */
4576 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4577 IEEE80211_HW_SIGNAL_DBM |
4578 IEEE80211_HW_NOISE_DBM;
4579
4580 hw->wiphy->interface_modes =
4581 BIT(NL80211_IFTYPE_AP) |
4582 BIT(NL80211_IFTYPE_MESH_POINT) |
4583 BIT(NL80211_IFTYPE_STATION) |
4584 BIT(NL80211_IFTYPE_WDS) |
4585 BIT(NL80211_IFTYPE_ADHOC);
4586
4587 hw->queues = b43_modparam_qos ? 4 : 1;
4588 SET_IEEE80211_DEV(hw, dev->dev);
4589 if (is_valid_ether_addr(sprom->et1mac))
4590 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4591 else
4592 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4593
4594 /* Get and initialize struct b43_wl */
4595 wl = hw_to_b43_wl(hw);
4596 memset(wl, 0, sizeof(*wl));
4597 wl->hw = hw;
4598 spin_lock_init(&wl->irq_lock);
4599 rwlock_init(&wl->tx_lock);
4600 spin_lock_init(&wl->leds_lock);
4601 spin_lock_init(&wl->shm_lock);
4602 mutex_init(&wl->mutex);
4603 INIT_LIST_HEAD(&wl->devlist);
4604 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
4605 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4606 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4607
4608 ssb_set_devtypedata(dev, wl);
4609 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4610 err = 0;
4611 out:
4612 return err;
4613 }
4614
4615 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4616 {
4617 struct b43_wl *wl;
4618 int err;
4619 int first = 0;
4620
4621 wl = ssb_get_devtypedata(dev);
4622 if (!wl) {
4623 /* Probing the first core. Must setup common struct b43_wl */
4624 first = 1;
4625 err = b43_wireless_init(dev);
4626 if (err)
4627 goto out;
4628 wl = ssb_get_devtypedata(dev);
4629 B43_WARN_ON(!wl);
4630 }
4631 err = b43_one_core_attach(dev, wl);
4632 if (err)
4633 goto err_wireless_exit;
4634
4635 if (first) {
4636 err = ieee80211_register_hw(wl->hw);
4637 if (err)
4638 goto err_one_core_detach;
4639 }
4640
4641 out:
4642 return err;
4643
4644 err_one_core_detach:
4645 b43_one_core_detach(dev);
4646 err_wireless_exit:
4647 if (first)
4648 b43_wireless_exit(dev, wl);
4649 return err;
4650 }
4651
4652 static void b43_remove(struct ssb_device *dev)
4653 {
4654 struct b43_wl *wl = ssb_get_devtypedata(dev);
4655 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4656
4657 /* We must cancel any work here before unregistering from ieee80211,
4658 * as the ieee80211 unreg will destroy the workqueue. */
4659 cancel_work_sync(&wldev->restart_work);
4660
4661 B43_WARN_ON(!wl);
4662 if (wl->current_dev == wldev)
4663 ieee80211_unregister_hw(wl->hw);
4664
4665 b43_one_core_detach(dev);
4666
4667 if (list_empty(&wl->devlist)) {
4668 /* Last core on the chip unregistered.
4669 * We can destroy common struct b43_wl.
4670 */
4671 b43_wireless_exit(dev, wl);
4672 }
4673 }
4674
4675 /* Perform a hardware reset. This can be called from any context. */
4676 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4677 {
4678 /* Must avoid requeueing, if we are in shutdown. */
4679 if (b43_status(dev) < B43_STAT_INITIALIZED)
4680 return;
4681 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4682 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4683 }
4684
4685 #ifdef CONFIG_PM
4686
4687 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4688 {
4689 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4690 struct b43_wl *wl = wldev->wl;
4691
4692 b43dbg(wl, "Suspending...\n");
4693
4694 mutex_lock(&wl->mutex);
4695 wldev->suspend_in_progress = true;
4696 wldev->suspend_init_status = b43_status(wldev);
4697 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4698 b43_wireless_core_stop(wldev);
4699 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4700 b43_wireless_core_exit(wldev);
4701 mutex_unlock(&wl->mutex);
4702
4703 b43dbg(wl, "Device suspended.\n");
4704
4705 return 0;
4706 }
4707
4708 static int b43_resume(struct ssb_device *dev)
4709 {
4710 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4711 struct b43_wl *wl = wldev->wl;
4712 int err = 0;
4713
4714 b43dbg(wl, "Resuming...\n");
4715
4716 mutex_lock(&wl->mutex);
4717 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4718 err = b43_wireless_core_init(wldev);
4719 if (err) {
4720 b43err(wl, "Resume failed at core init\n");
4721 goto out;
4722 }
4723 }
4724 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4725 err = b43_wireless_core_start(wldev);
4726 if (err) {
4727 b43_leds_exit(wldev);
4728 b43_rng_exit(wldev->wl);
4729 b43_wireless_core_exit(wldev);
4730 b43err(wl, "Resume failed at core start\n");
4731 goto out;
4732 }
4733 }
4734 b43dbg(wl, "Device resumed.\n");
4735 out:
4736 wldev->suspend_in_progress = false;
4737 mutex_unlock(&wl->mutex);
4738 return err;
4739 }
4740
4741 #else /* CONFIG_PM */
4742 # define b43_suspend NULL
4743 # define b43_resume NULL
4744 #endif /* CONFIG_PM */
4745
4746 static struct ssb_driver b43_ssb_driver = {
4747 .name = KBUILD_MODNAME,
4748 .id_table = b43_ssb_tbl,
4749 .probe = b43_probe,
4750 .remove = b43_remove,
4751 .suspend = b43_suspend,
4752 .resume = b43_resume,
4753 };
4754
4755 static void b43_print_driverinfo(void)
4756 {
4757 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4758 *feat_leds = "", *feat_rfkill = "";
4759
4760 #ifdef CONFIG_B43_PCI_AUTOSELECT
4761 feat_pci = "P";
4762 #endif
4763 #ifdef CONFIG_B43_PCMCIA
4764 feat_pcmcia = "M";
4765 #endif
4766 #ifdef CONFIG_B43_NPHY
4767 feat_nphy = "N";
4768 #endif
4769 #ifdef CONFIG_B43_LEDS
4770 feat_leds = "L";
4771 #endif
4772 #ifdef CONFIG_B43_RFKILL
4773 feat_rfkill = "R";
4774 #endif
4775 printk(KERN_INFO "Broadcom 43xx driver loaded "
4776 "[ Features: %s%s%s%s%s, Firmware-ID: "
4777 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4778 feat_pci, feat_pcmcia, feat_nphy,
4779 feat_leds, feat_rfkill);
4780 }
4781
4782 static int __init b43_init(void)
4783 {
4784 int err;
4785
4786 b43_debugfs_init();
4787 err = b43_pcmcia_init();
4788 if (err)
4789 goto err_dfs_exit;
4790 err = ssb_driver_register(&b43_ssb_driver);
4791 if (err)
4792 goto err_pcmcia_exit;
4793 b43_print_driverinfo();
4794
4795 return err;
4796
4797 err_pcmcia_exit:
4798 b43_pcmcia_exit();
4799 err_dfs_exit:
4800 b43_debugfs_exit();
4801 return err;
4802 }
4803
4804 static void __exit b43_exit(void)
4805 {
4806 ssb_driver_unregister(&b43_ssb_driver);
4807 b43_pcmcia_exit();
4808 b43_debugfs_exit();
4809 }
4810
4811 module_init(b43_init)
4812 module_exit(b43_exit)
x86 "subsystem" repository