arch/x86/include/asm/summit/apic.h

   1 #ifndef __ASM_SUMMIT_APIC_H
   2 #define __ASM_SUMMIT_APIC_H
   3
   4 #include <asm/smp.h>
   5 #include <linux/gfp.h>
   6
   7 #define NO_BALANCE_IRQ (0)
   8
   9 /* In clustered mode, the high nibble of APIC ID is a cluster number.
  10  * The low nibble is a 4-bit bitmap. */
  11 #define XAPIC_DEST_CPUS_SHIFT   4
  12 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
  13 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
  14
  15 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
  16
  17 static inline const cpumask_t *summit_target_cpus(void)
  18 {
  19         /* CPU_MASK_ALL (0xff) has undefined behaviour with
  20          * dest_LowestPrio mode logical clustered apic interrupt routing
  21          * Just start on cpu 0.  IRQ balancing will spread load
  22          */
  23         return &cpumask_of_cpu(0);
  24 }
  25
  26 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  27 {
  28         return 0;
  29 }
  30
  31 /* we don't use the phys_cpu_present_map to indicate apicid presence */
  32 static inline unsigned long check_apicid_present(int bit)
  33 {
  34         return 1;
  35 }
  36
  37 #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
  38
  39 extern u8 cpu_2_logical_apicid[];
  40
  41 static inline void init_apic_ldr(void)
  42 {
  43         unsigned long val, id;
  44         int count = 0;
  45         u8 my_id = (u8)hard_smp_processor_id();
  46         u8 my_cluster = (u8)apicid_cluster(my_id);
  47 #ifdef CONFIG_SMP
  48         u8 lid;
  49         int i;
  50
  51         /* Create logical APIC IDs by counting CPUs already in cluster. */
  52         for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
  53                 lid = cpu_2_logical_apicid[i];
  54                 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
  55                         ++count;
  56         }
  57 #endif
  58         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
  59          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
  60         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
  61         id = my_cluster | (1UL << count);
  62         apic_write(APIC_DFR, APIC_DFR_VALUE);
  63         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  64         val |= SET_APIC_LOGICAL_ID(id);
  65         apic_write(APIC_LDR, val);
  66 }
  67
  68 static inline int multi_timer_check(int apic, int irq)
  69 {
  70         return 0;
  71 }
  72
  73 static inline int summit_apic_id_registered(void)
  74 {
  75         return 1;
  76 }
  77
  78 static inline void setup_apic_routing(void)
  79 {
  80         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
  81                                                 nr_ioapics);
  82 }
  83
  84 static inline int apicid_to_node(int logical_apicid)
  85 {
  86 #ifdef CONFIG_SMP
  87         return apicid_2_node[hard_smp_processor_id()];
  88 #else
  89         return 0;
  90 #endif
  91 }
  92
  93 /* Mapping from cpu number to logical apicid */
  94 static inline int cpu_to_logical_apicid(int cpu)
  95 {
  96 #ifdef CONFIG_SMP
  97         if (cpu >= nr_cpu_ids)
  98                 return BAD_APICID;
  99         return (int)cpu_2_logical_apicid[cpu];
 100 #else
 101         return logical_smp_processor_id();
 102 #endif
 103 }
 104
 105 static inline int cpu_present_to_apicid(int mps_cpu)
 106 {
 107         if (mps_cpu < nr_cpu_ids)
 108                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 109         else
 110                 return BAD_APICID;
 111 }
 112
 113 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
 114 {
 115         /* For clustered we don't have a good way to do this yet - hack */
 116         return physids_promote(0x0F);
 117 }
 118
 119 static inline physid_mask_t apicid_to_cpu_present(int apicid)
 120 {
 121         return physid_mask_of_physid(0);
 122 }
 123
 124 static inline void setup_portio_remap(void)
 125 {
 126 }
 127
 128 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 129 {
 130         return 1;
 131 }
 132
 133 static inline void enable_apic_mode(void)
 134 {
 135 }
 136
 137 static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask)
 138 {
 139         int num_bits_set;
 140         int cpus_found = 0;
 141         int cpu;
 142         int apicid;
 143
 144         num_bits_set = cpus_weight(*cpumask);
 145         /* Return id to all */
 146         if (num_bits_set >= nr_cpu_ids)
 147                 return (int) 0xFF;
 148         /*
 149          * The cpus in the mask must all be on the apic cluster.  If are not
 150          * on the same apicid cluster return default value of target_cpus():
 151          */
 152         cpu = first_cpu(*cpumask);
 153         apicid = cpu_to_logical_apicid(cpu);
 154         while (cpus_found < num_bits_set) {
 155                 if (cpu_isset(cpu, *cpumask)) {
 156                         int new_apicid = cpu_to_logical_apicid(cpu);
 157                         if (apicid_cluster(apicid) !=
 158                                         apicid_cluster(new_apicid)){
 159                                 printk ("%s: Not a valid mask!\n", __func__);
 160                                 return 0xFF;
 161                         }
 162                         apicid = apicid | new_apicid;
 163                         cpus_found++;
 164                 }
 165                 cpu++;
 166         }
 167         return apicid;
 168 }
 169
 170 static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *inmask,
 171                                                   const struct cpumask *andmask)
 172 {
 173         int apicid = cpu_to_logical_apicid(0);
 174         cpumask_var_t cpumask;
 175
 176         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
 177                 return apicid;
 178
 179         cpumask_and(cpumask, inmask, andmask);
 180         cpumask_and(cpumask, cpumask, cpu_online_mask);
 181         apicid = cpu_mask_to_apicid(cpumask);
 182
 183         free_cpumask_var(cpumask);
 184         return apicid;
 185 }
 186
 187 /* cpuid returns the value latched in the HW at reset, not the APIC ID
 188  * register's value.  For any box whose BIOS changes APIC IDs, like
 189  * clustered APIC systems, we must use hard_smp_processor_id.
 190  *
 191  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 192  */
 193 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 194 {
 195         return hard_smp_processor_id() >> index_msb;
 196 }
 197
 198 #endif /* __ASM_SUMMIT_APIC_H */