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Staging: otus: use ARRAY_SIZE
[linux-2.6/x86.git] / drivers / staging / otus / hal / hpreg.c
blob9b04653c1c53b091ca812771c184d7fd322803da
1 /*
2 * Copyright (c) 2000-2005 ZyDAS Technology Corporation
3 * Copyright (c) 2007-2008 Atheros Communications Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17 /* */
18 /* Module Name : hpreg.c */
19 /* */
20 /* Abstract */
21 /* This module contains Regulatory Table and related function. */
22 /* */
23 /* NOTES */
24 /* None */
25 /* */
26 /************************************************************************/
27 #include "../80211core/cprecomp.h"
28 #include "hpani.h"
29 #include "hpreg.h"
30 #include "hpusb.h"
31
32 #define HAL_MODE_11A_TURBO HAL_MODE_108A
33 #define HAL_MODE_11G_TURBO HAL_MODE_108G
34
35 #if 0
36 enum {
37 /* test groups */
38 FCC = 0x10,
39 MKK = 0x40,
40 ETSI = 0x30,
41 SD_NO_CTL = 0xe0,
42 NO_CTL = 0xff,
43 /* test modes */
44 CTL_MODE_M = 0x0f,
45 CTL_11A = 0,
46 CTL_11B = 1,
47 CTL_11G = 2,
48 CTL_TURBO = 3,
49 CTL_108G = 4,
50 CTL_2GHT20 = 5,
51 CTL_5GHT20 = 6,
52 CTL_2GHT40 = 7,
53 CTL_5GHT40 = 8
54 };
55 #endif
56
57 /*
58 * The following are flags for different requirements per reg domain.
59 * These requirements are either inhereted from the reg domain pair or
60 * from the unitary reg domain if the reg domain pair flags value is
61 * 0
62 */
63
64 enum {
65 NO_REQ = 0x00000000,
66 DISALLOW_ADHOC_11A = 0x00000001,
67 DISALLOW_ADHOC_11A_TURB = 0x00000002,
68 NEED_NFC = 0x00000004,
69
70 ADHOC_PER_11D = 0x00000008, /* Start Ad-Hoc mode */
71 ADHOC_NO_11A = 0x00000010,
72
73 PUBLIC_SAFETY_DOMAIN = 0x00000020, /* public safety domain */
74 LIMIT_FRAME_4MS = 0x00000040, /* 4msec limit on the frame length */
75 };
76
77 #define MKK5GHZ_FLAG1 (DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS)
78 #define MKK5GHZ_FLAG2 (DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS)
79
80 typedef enum {
81 DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */
82 DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */
83 DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */
84 } HAL_DFS_DOMAIN;
85
86 /*
87 * Used to set the RegDomain bitmask which chooses which frequency
88 * band specs are used.
89 */
90
91 #define BMLEN 2 /* Use 2 64 bit uint for channel bitmask
92 NB: Must agree with macro below (BM) */
93 #define BMZERO {(u64_t) 0, (u64_t) 0} /* BMLEN zeros */
94
95 #if 0
96
97 #define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
98 {((((_fa >= 0) && (_fa < 64)) ? (((u64_t) 1) << _fa) : (u64_t) 0) | \
99 (((_fb >= 0) && (_fb < 64)) ? (((u64_t) 1) << _fb) : (u64_t) 0) | \
100 (((_fc >= 0) && (_fc < 64)) ? (((u64_t) 1) << _fc) : (u64_t) 0) | \
101 (((_fd >= 0) && (_fd < 64)) ? (((u64_t) 1) << _fd) : (u64_t) 0) | \
102 (((_fe >= 0) && (_fe < 64)) ? (((u64_t) 1) << _fe) : (u64_t) 0) | \
103 (((_ff >= 0) && (_ff < 64)) ? (((u64_t) 1) << _ff) : (u64_t) 0) | \
104 (((_fg >= 0) && (_fg < 64)) ? (((u64_t) 1) << _fg) : (u64_t) 0) | \
105 (((_fh >= 0) && (_fh < 64)) ? (((u64_t) 1) << _fh) : (u64_t) 0) | \
106 (((_fi >= 0) && (_fi < 64)) ? (((u64_t) 1) << _fi) : (u64_t) 0) | \
107 (((_fj >= 0) && (_fj < 64)) ? (((u64_t) 1) << _fj) : (u64_t) 0) | \
108 (((_fk >= 0) && (_fk < 64)) ? (((u64_t) 1) << _fk) : (u64_t) 0) | \
109 (((_fl >= 0) && (_fl < 64)) ? (((u64_t) 1) << _fl) : (u64_t) 0) | \
110 ((((_fa > 63) && (_fa < 128)) ? (((u64_t) 1) << (_fa - 64)) : (u64_t) 0) | \
111 (((_fb > 63) && (_fb < 128)) ? (((u64_t) 1) << (_fb - 64)) : (u64_t) 0) | \
112 (((_fc > 63) && (_fc < 128)) ? (((u64_t) 1) << (_fc - 64)) : (u64_t) 0) | \
113 (((_fd > 63) && (_fd < 128)) ? (((u64_t) 1) << (_fd - 64)) : (u64_t) 0) | \
114 (((_fe > 63) && (_fe < 128)) ? (((u64_t) 1) << (_fe - 64)) : (u64_t) 0) | \
115 (((_ff > 63) && (_ff < 128)) ? (((u64_t) 1) << (_ff - 64)) : (u64_t) 0) | \
116 (((_fg > 63) && (_fg < 128)) ? (((u64_t) 1) << (_fg - 64)) : (u64_t) 0) | \
117 (((_fh > 63) && (_fh < 128)) ? (((u64_t) 1) << (_fh - 64)) : (u64_t) 0) | \
118 (((_fi > 63) && (_fi < 128)) ? (((u64_t) 1) << (_fi - 64)) : (u64_t) 0) | \
119 (((_fj > 63) && (_fj < 128)) ? (((u64_t) 1) << (_fj - 64)) : (u64_t) 0) | \
120 (((_fk > 63) && (_fk < 128)) ? (((u64_t) 1) << (_fk - 64)) : (u64_t) 0) | \
121 (((_fl > 63) && (_fl < 128)) ? (((u64_t) 1) << (_fl - 64)) : (u64_t) 0)))}
122
123 #else
124
125 #define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \
126 {((((_fa >= 0) && (_fa < 64)) ? (((u64_t) 1) << (_fa&0x3f)) : (u64_t) 0) | \
127 (((_fb >= 0) && (_fb < 64)) ? (((u64_t) 1) << (_fb&0x3f)) : (u64_t) 0) | \
128 (((_fc >= 0) && (_fc < 64)) ? (((u64_t) 1) << (_fc&0x3f)) : (u64_t) 0) | \
129 (((_fd >= 0) && (_fd < 64)) ? (((u64_t) 1) << (_fd&0x3f)) : (u64_t) 0) | \
130 (((_fe >= 0) && (_fe < 64)) ? (((u64_t) 1) << (_fe&0x3f)) : (u64_t) 0) | \
131 (((_ff >= 0) && (_ff < 64)) ? (((u64_t) 1) << (_ff&0x3f)) : (u64_t) 0) | \
132 (((_fg >= 0) && (_fg < 64)) ? (((u64_t) 1) << (_fg&0x3f)) : (u64_t) 0) | \
133 (((_fh >= 0) && (_fh < 64)) ? (((u64_t) 1) << (_fh&0x3f)) : (u64_t) 0) | \
134 (((_fi >= 0) && (_fi < 64)) ? (((u64_t) 1) << (_fi&0x3f)) : (u64_t) 0) | \
135 (((_fj >= 0) && (_fj < 64)) ? (((u64_t) 1) << (_fj&0x3f)) : (u64_t) 0) | \
136 (((_fk >= 0) && (_fk < 64)) ? (((u64_t) 1) << (_fk&0x3f)) : (u64_t) 0) | \
137 (((_fl >= 0) && (_fl < 64)) ? (((u64_t) 1) << (_fl&0x3f)) : (u64_t) 0) | \
138 ((((_fa > 63) && (_fa < 128)) ? (((u64_t) 1) << ((_fa - 64)&0x3f)) : (u64_t) 0) | \
139 (((_fb > 63) && (_fb < 128)) ? (((u64_t) 1) << ((_fb - 64)&0x3f)) : (u64_t) 0) | \
140 (((_fc > 63) && (_fc < 128)) ? (((u64_t) 1) << ((_fc - 64)&0x3f)) : (u64_t) 0) | \
141 (((_fd > 63) && (_fd < 128)) ? (((u64_t) 1) << ((_fd - 64)&0x3f)) : (u64_t) 0) | \
142 (((_fe > 63) && (_fe < 128)) ? (((u64_t) 1) << ((_fe - 64)&0x3f)) : (u64_t) 0) | \
143 (((_ff > 63) && (_ff < 128)) ? (((u64_t) 1) << ((_ff - 64)&0x3f)) : (u64_t) 0) | \
144 (((_fg > 63) && (_fg < 128)) ? (((u64_t) 1) << ((_fg - 64)&0x3f)) : (u64_t) 0) | \
145 (((_fh > 63) && (_fh < 128)) ? (((u64_t) 1) << ((_fh - 64)&0x3f)) : (u64_t) 0) | \
146 (((_fi > 63) && (_fi < 128)) ? (((u64_t) 1) << ((_fi - 64)&0x3f)) : (u64_t) 0) | \
147 (((_fj > 63) && (_fj < 128)) ? (((u64_t) 1) << ((_fj - 64)&0x3f)) : (u64_t) 0) | \
148 (((_fk > 63) && (_fk < 128)) ? (((u64_t) 1) << ((_fk - 64)&0x3f)) : (u64_t) 0) | \
149 (((_fl > 63) && (_fl < 128)) ? (((u64_t) 1) << ((_fl - 64)&0x3f)) : (u64_t) 0)))}
150
151 #endif
152
153 /* Mask to check whether a domain is a multidomain or a single
154 domain */
155
156 #define MULTI_DOMAIN_MASK 0xFF00
157
158
159 /*
160 * The following describe the bit masks for different passive scan
161 * capability/requirements per regdomain.
162 */
163 #define NO_PSCAN 0x0ULL
164 #define PSCAN_FCC 0x0000000000000001ULL
165 #define PSCAN_FCC_T 0x0000000000000002ULL
166 #define PSCAN_ETSI 0x0000000000000004ULL
167 #define PSCAN_MKK1 0x0000000000000008ULL
168 #define PSCAN_MKK2 0x0000000000000010ULL
169 #define PSCAN_MKKA 0x0000000000000020ULL
170 #define PSCAN_MKKA_G 0x0000000000000040ULL
171 #define PSCAN_ETSIA 0x0000000000000080ULL
172 #define PSCAN_ETSIB 0x0000000000000100ULL
173 #define PSCAN_ETSIC 0x0000000000000200ULL
174 #define PSCAN_WWR 0x0000000000000400ULL
175 #define PSCAN_MKKA1 0x0000000000000800ULL
176 #define PSCAN_MKKA1_G 0x0000000000001000ULL
177 #define PSCAN_MKKA2 0x0000000000002000ULL
178 #define PSCAN_MKKA2_G 0x0000000000004000ULL
179 #define PSCAN_MKK3 0x0000000000008000ULL
180 #define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL
181 #define IS_ECM_CHAN 0x8000000000000000ULL
182
183 /*
184 * THE following table is the mapping of regdomain pairs specified by
185 * an 8 bit regdomain value to the individual unitary reg domains
186 */
187
188 typedef struct reg_dmn_pair_mapping {
189 u16_t regDmnEnum; /* 16 bit reg domain pair */
190 u16_t regDmn5GHz; /* 5GHz reg domain */
191 u16_t regDmn2GHz; /* 2GHz reg domain */
192 u32_t flags5GHz; /* Requirements flags (AdHoc
193 disallow, noise floor cal needed,
194 etc) */
195 u32_t flags2GHz; /* Requirements flags (AdHoc
196 disallow, noise floor cal needed,
197 etc) */
198 u64_t pscanMask; /* Passive Scan flags which
199 can override unitary domain
200 passive scan flags. This
201 value is used as a mask on
202 the unitary flags*/
203 u16_t singleCC; /* Country code of single country if
204 a one-on-one mapping exists */
205 } REG_DMN_PAIR_MAPPING;
206
207 static REG_DMN_PAIR_MAPPING regDomainPairs[] = {
208 {NO_ENUMRD, FCC2, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
209 {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
210 {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
211 {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
212
213 {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
214 {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
215 {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
216 {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
217 {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
218 {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
219 {FCC5_FCCA, FCC5, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
220 {FCC6_FCCA, FCC6, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
221 {FCC6_WORLD, FCC6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
222
223 {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
224 {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
225 {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
226 {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
227 {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
228 {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
229
230 {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
231 {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
232
233 {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
234 {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
235 {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
236 {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
237 {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
238 {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
239 {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
240 {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
241 {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
242 {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
243
244 {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
245 {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
246 {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
247 {APL2_FCCA, APL2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
248 {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0},
249 {APL7_FCCA, APL7, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
250
251 {MKK1_MKKA, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN },
252 {MKK1_MKKB, MKK1, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 },
253 {MKK1_FCCA, MKK1, FCCA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 },
254 {MKK1_MKKA1, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 },
255 {MKK1_MKKA2, MKK1, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 },
256 {MKK1_MKKC, MKK1, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 },
257
258 /* MKK2 */
259 {MKK2_MKKA, MKK2, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 },
260
261 /* MKK3 */
262 {MKK3_MKKA, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN25 },
263 {MKK3_MKKB, MKK3, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 },
264 {MKK3_MKKA1, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN26 },
265 {MKK3_MKKA2, MKK3, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 },
266 {MKK3_MKKC, MKK3, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 },
267 {MKK3_FCCA, MKK3, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN27 },
268
269 /* MKK4 */
270 {MKK4_MKKB, MKK4, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 },
271 {MKK4_MKKA1, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN28 },
272 {MKK4_MKKA2, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 },
273 {MKK4_MKKC, MKK4, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 },
274 {MKK4_FCCA, MKK4, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN29 },
275 {MKK4_MKKA, MKK4, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA, CTRY_JAPAN36 },
276
277 /* MKK5 */
278 {MKK5_MKKB, MKK5, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 },
279 {MKK5_MKKA2, MKK5, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 },
280 {MKK5_MKKC, MKK5, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 },
281
282 /* MKK6 */
283 {MKK6_MKKB, MKK6, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 },
284 {MKK6_MKKA2, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 },
285 {MKK6_MKKC, MKK6, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 },
286 {MKK6_MKKA1, MKK6, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN30 },
287 {MKK6_FCCA, MKK6, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN31 },
288
289 /* MKK7 */
290 {MKK7_MKKB, MKK7, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 },
291 {MKK7_MKKA, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 },
292 {MKK7_MKKC, MKK7, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 },
293 {MKK7_MKKA1, MKK7, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN32 },
294 {MKK7_FCCA, MKK7, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN33 },
295
296 /* MKK8 */
297 {MKK8_MKKB, MKK8, MKKA, MKK5GHZ_FLAG2, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 },
298 {MKK8_MKKA2, MKK8, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 },
299 {MKK8_MKKC, MKK8, MKKC, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 },
300
301 /* MKK9 */
302 {MKK9_MKKA, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN34 },
303 {MKK9_FCCA, MKK9, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN37 },
304 {MKK9_MKKA1, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN38 },
305 {MKK9_MKKC, MKK9, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN39 },
306 {MKK9_MKKA2, MKK9, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN40 },
307
308 /* MKK10 */
309 {MKK10_MKKA, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN35 },
310 {MKK10_FCCA, MKK10, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN41 },
311 {MKK10_MKKA1, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN42 },
312 {MKK10_MKKC, MKK10, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN43 },
313 {MKK10_MKKA2, MKK10, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN44 },
314
315 /* MKK11 */
316 {MKK11_MKKA, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN45 },
317 {MKK11_FCCA, MKK11, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN46 },
318 {MKK11_MKKA1, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN47 },
319 {MKK11_MKKC, MKK11, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN48 },
320 {MKK11_MKKA2, MKK11, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN49 },
321
322 /* MKK12 */
323 {MKK12_MKKA, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN50 },
324 {MKK12_FCCA, MKK12, FCCA, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN51 },
325 {MKK12_MKKA1, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN52 },
326 {MKK12_MKKC, MKK12, MKKC, MKK5GHZ_FLAG1, NEED_NFC, NO_PSCAN, CTRY_JAPAN53 },
327 {MKK12_MKKA2, MKK12, MKKA, MKK5GHZ_FLAG1, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN54 },
328
329
330 /* These are super domains */
331 {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
332 {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
333 {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
334 {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
335 {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
336 {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
337 {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
338 {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
339 {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 },
340 {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
341 {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 },
342 };
343
344 /*
345 * The following table is the master list for all different freqeuncy
346 * bands with the complete matrix of all possible flags and settings
347 * for each band if it is used in ANY reg domain.
348 */
349
350 #define DEF_REGDMN FCC1_FCCA
351 #define DEF_DMN_5 FCC1
352 #define DEF_DMN_2 FCCA
353 #define COUNTRY_ERD_FLAG 0x8000
354 #define WORLDWIDE_ROAMING_FLAG 0x4000
355 #define SUPER_DOMAIN_MASK 0x0fff
356 #define COUNTRY_CODE_MASK 0x03ff
357 #define CF_INTERFERENCE (CHANNEL_CW_INT | CHANNEL_RADAR_INT)
358 #define CHANNEL_14 (2484) /* 802.11g operation is not permitted on channel 14 */
359 #define IS_11G_CH14(_ch, _cf) \
360 (((_ch) == CHANNEL_14) && ((_cf) == CHANNEL_G))
361
362 #define YES TRUE
363 #define NO FALSE
364
365 enum {
366 CTRY_DEBUG = 0x1ff, /* debug country code */
367 CTRY_DEFAULT = 0 /* default country code */
368 };
369
370 typedef struct {
371 HAL_CTRY_CODE countryCode;
372 HAL_REG_DOMAIN regDmnEnum;
373 const char *isoName;
374 const char *name;
375 HAL_BOOL allow11g;
376 HAL_BOOL allow11aTurbo;
377 HAL_BOOL allow11gTurbo;
378 HAL_BOOL allow11na; /* HT-40 allowed in 5GHz? */
379 HAL_BOOL allow11ng; /* HT-40 allowed in 2GHz? */
380 u16_t outdoorChanStart;
381 } COUNTRY_CODE_TO_ENUM_RD;
382
383 static COUNTRY_CODE_TO_ENUM_RD allCountries[] = {
384 {CTRY_DEBUG, NO_ENUMRD, "DB", "DEBUG", YES, YES, YES, YES, YES, 7000 },
385 {CTRY_DEFAULT, DEF_REGDMN, "NA", "NO_COUNTRY_SET", YES, YES, YES, YES, YES, 7000 },
386 {CTRY_ALBANIA, NULL1_WORLD, "AL", "ALBANIA", YES, NO, YES, NO, YES, 7000 },
387 {CTRY_ALGERIA, NULL1_WORLD, "DZ", "ALGERIA", YES, NO, YES, NO, YES, 7000 },
388 {CTRY_ARGENTINA, APL3_WORLD, "AR", "ARGENTINA", YES, NO, NO, NO, NO, 7000 },
389 {CTRY_ARMENIA, ETSI4_WORLD, "AM", "ARMENIA", YES, NO, YES, NO, YES, 7000 },
390 {CTRY_AUSTRALIA, FCC6_WORLD, "AU", "AUSTRALIA", YES, YES, YES, YES, YES, 7000 },
391 {CTRY_AUSTRIA, ETSI2_WORLD, "AT", "AUSTRIA", YES, NO, YES, YES, YES, 7000 },
392 {CTRY_AZERBAIJAN, ETSI4_WORLD, "AZ", "AZERBAIJAN", YES, YES, YES, YES, YES, 7000 },
393 {CTRY_BAHRAIN, APL6_WORLD, "BH", "BAHRAIN", YES, NO, YES, NO, YES, 7000 },
394 {CTRY_BELARUS, ETSI1_WORLD, "BY", "BELARUS", YES, NO, YES, YES, YES, 7000 },
395 {CTRY_BELGIUM, ETSI1_WORLD, "BE", "BELGIUM", YES, NO, YES, YES, YES, 7000 },
396 {CTRY_BELIZE, APL1_ETSIC, "BZ", "BELIZE", YES, YES, YES, YES, YES, 7000 },
397 {CTRY_BOLIVIA, APL1_ETSIC, "BO", "BOLVIA", YES, YES, YES, YES, YES, 7000 },
398 {CTRY_BRAZIL, FCC3_WORLD, "BR", "BRAZIL", NO, NO, NO, NO, NO, 7000 },
399 {CTRY_BRUNEI_DARUSSALAM, APL1_WORLD, "BN", "BRUNEI DARUSSALAM", YES, YES, YES, YES, YES, 7000 },
400 {CTRY_BULGARIA, ETSI6_WORLD, "BG", "BULGARIA", YES, NO, YES, YES, YES, 7000 },
401 {CTRY_CANADA, FCC6_FCCA, "CA", "CANADA", YES, YES, YES, YES, YES, 7000 },
402 {CTRY_CHILE, APL6_WORLD, "CL", "CHILE", YES, YES, YES, YES, YES, 7000 },
403 {CTRY_CHINA, APL1_WORLD, "CN", "CHINA", YES, YES, YES, YES, YES, 7000 },
404 {CTRY_COLOMBIA, FCC1_FCCA, "CO", "COLOMBIA", YES, NO, YES, NO, YES, 7000 },
405 {CTRY_COSTA_RICA, FCC1_WORLD, "CR", "COSTA RICA", YES, NO, YES, NO, YES, 7000 },
406 {CTRY_CROATIA, ETSI3_WORLD, "HR", "CROATIA", YES, NO, YES, NO, YES, 7000 },
407 {CTRY_CYPRUS, ETSI3_WORLD, "CY", "CYPRUS", YES, YES, YES, YES, YES, 7000 },
408 {CTRY_CZECH, ETSI3_WORLD, "CZ", "CZECH REPUBLIC", YES, NO, YES, YES, YES, 7000 },
409 {CTRY_DENMARK, ETSI1_WORLD, "DK", "DENMARK", YES, NO, YES, YES, YES, 7000 },
410 {CTRY_DOMINICAN_REPUBLIC, FCC1_FCCA, "DO", "DOMINICAN REPUBLIC", YES, YES, YES, YES, YES, 7000 },
411 {CTRY_ECUADOR, FCC1_WORLD, "EC", "ECUADOR", YES, NO, NO, NO, YES, 7000 },
412 {CTRY_EGYPT, ETSI3_WORLD, "EG", "EGYPT", YES, NO, YES, NO, YES, 7000 },
413 {CTRY_EL_SALVADOR, FCC1_WORLD, "SV", "EL SALVADOR", YES, NO, YES, NO, YES, 7000 },
414 {CTRY_ESTONIA, ETSI1_WORLD, "EE", "ESTONIA", YES, NO, YES, YES, YES, 7000 },
415 {CTRY_FINLAND, ETSI1_WORLD, "FI", "FINLAND", YES, NO, YES, YES, YES, 7000 },
416 {CTRY_FRANCE, ETSI1_WORLD, "FR", "FRANCE", YES, NO, YES, YES, YES, 7000 },
417 {CTRY_FRANCE2, ETSI3_WORLD, "F2", "FRANCE_RES", YES, NO, YES, YES, YES, 7000 },
418 {CTRY_GEORGIA, ETSI4_WORLD, "GE", "GEORGIA", YES, YES, YES, YES, YES, 7000 },
419 {CTRY_GERMANY, ETSI1_WORLD, "DE", "GERMANY", YES, NO, YES, YES, YES, 7000 },
420 {CTRY_GREECE, ETSI1_WORLD, "GR", "GREECE", YES, NO, YES, YES, YES, 7000 },
421 {CTRY_GUATEMALA, FCC1_FCCA, "GT", "GUATEMALA", YES, YES, YES, YES, YES, 7000 },
422 {CTRY_HONDURAS, NULL1_WORLD, "HN", "HONDURAS", YES, NO, YES, NO, YES, 7000 },
423 {CTRY_HONG_KONG, FCC2_WORLD, "HK", "HONG KONG", YES, YES, YES, YES, YES, 7000 },
424 {CTRY_HUNGARY, ETSI4_WORLD, "HU", "HUNGARY", YES, NO, YES, YES, YES, 7000 },
425 {CTRY_ICELAND, ETSI1_WORLD, "IS", "ICELAND", YES, NO, YES, YES, YES, 7000 },
426 {CTRY_INDIA, APL6_WORLD, "IN", "INDIA", YES, NO, YES, NO, YES, 7000 },
427 {CTRY_INDONESIA, APL1_WORLD, "ID", "INDONESIA", YES, NO, YES, NO, YES, 7000 },
428 {CTRY_IRAN, APL1_WORLD, "IR", "IRAN", YES, YES, YES, YES, YES, 7000 },
429 {CTRY_IRELAND, ETSI1_WORLD, "IE", "IRELAND", YES, NO, YES, YES, YES, 7000 },
430 {CTRY_ISRAEL, ETSI3_WORLD, "IL", "ISRAEL", YES, NO, YES, NO, YES, 7000 },
431 {CTRY_ISRAEL2, NULL1_ETSIB, "ISR", "ISRAEL_RES", YES, NO, YES, NO, YES, 7000 },
432 {CTRY_ITALY, ETSI1_WORLD, "IT", "ITALY", YES, NO, YES, YES, YES, 7000 },
433 {CTRY_JAMAICA, ETSI1_WORLD, "JM", "JAMAICA", YES, NO, YES, YES, YES, 7000 },
434 {CTRY_JAPAN, MKK1_MKKA, "JP", "JAPAN", YES, NO, NO, NO, NO, 7000 },
435 {CTRY_JAPAN1, MKK1_MKKB, "J1", "JAPAN1", YES, NO, NO, NO, NO, 7000 },
436 {CTRY_JAPAN2, MKK1_FCCA, "J2", "JAPAN2", YES, NO, NO, NO, NO, 7000 },
437 {CTRY_JAPAN3, MKK2_MKKA, "J3", "JAPAN3", YES, NO, NO, NO, NO, 7000 },
438 {CTRY_JAPAN4, MKK1_MKKA1, "J4", "JAPAN4", YES, NO, NO, NO, NO, 7000 },
439 {CTRY_JAPAN5, MKK1_MKKA2, "J5", "JAPAN5", YES, NO, NO, NO, NO, 7000 },
440 {CTRY_JAPAN6, MKK1_MKKC, "J6", "JAPAN6", YES, NO, NO, NO, NO, 7000 },
441 {CTRY_JAPAN7, MKK3_MKKB, "J7", "JAPAN7", YES, NO, NO, NO, NO, 7000 },
442 {CTRY_JAPAN8, MKK3_MKKA2, "J8", "JAPAN8", YES, NO, NO, NO, NO, 7000 },
443 {CTRY_JAPAN9, MKK3_MKKC, "J9", "JAPAN9", YES, NO, NO, NO, NO, 7000 },
444 {CTRY_JAPAN10, MKK4_MKKB, "J10", "JAPAN10", YES, NO, NO, NO, NO, 7000 },
445 {CTRY_JAPAN11, MKK4_MKKA2, "J11", "JAPAN11", YES, NO, NO, NO, NO, 7000 },
446 {CTRY_JAPAN12, MKK4_MKKC, "J12", "JAPAN12", YES, NO, NO, NO, NO, 7000 },
447 {CTRY_JAPAN13, MKK5_MKKB, "J13", "JAPAN13", YES, NO, NO, NO, NO, 7000 },
448 {CTRY_JAPAN14, MKK5_MKKA2, "J14", "JAPAN14", YES, NO, NO, NO, NO, 7000 },
449 {CTRY_JAPAN15, MKK5_MKKC, "J15", "JAPAN15", YES, NO, NO, NO, NO, 7000 },
450 {CTRY_JAPAN16, MKK6_MKKB, "J16", "JAPAN16", YES, NO, NO, NO, NO, 7000 },
451 {CTRY_JAPAN17, MKK6_MKKA2, "J17", "JAPAN17", YES, NO, NO, NO, NO, 7000 },
452 {CTRY_JAPAN18, MKK6_MKKC, "J18", "JAPAN18", YES, NO, NO, NO, NO, 7000 },
453 {CTRY_JAPAN19, MKK7_MKKB, "J19", "JAPAN19", YES, NO, NO, NO, NO, 7000 },
454 {CTRY_JAPAN20, MKK7_MKKA, "J20", "JAPAN20", YES, NO, NO, NO, NO, 7000 },
455 {CTRY_JAPAN21, MKK7_MKKC, "J21", "JAPAN21", YES, NO, NO, NO, NO, 7000 },
456 {CTRY_JAPAN22, MKK8_MKKB, "J22", "JAPAN22", YES, NO, NO, NO, NO, 7000 },
457 {CTRY_JAPAN23, MKK8_MKKA2, "J23", "JAPAN23", YES, NO, NO, NO, NO, 7000 },
458 {CTRY_JAPAN24, MKK8_MKKC, "J24", "JAPAN24", YES, NO, NO, NO, NO, 7000 },
459 {CTRY_JAPAN25, MKK3_MKKA, "J25", "JAPAN25", YES, NO, NO, NO, NO, 7000 },
460 {CTRY_JAPAN26, MKK3_MKKA1, "J26", "JAPAN26", YES, NO, NO, NO, NO, 7000 },
461 {CTRY_JAPAN27, MKK3_FCCA, "J27", "JAPAN27", YES, NO, NO, NO, NO, 7000 },
462 {CTRY_JAPAN28, MKK4_MKKA1, "J28", "JAPAN28", YES, NO, NO, NO, NO, 7000 },
463 {CTRY_JAPAN29, MKK4_FCCA, "J29", "JAPAN29", YES, NO, NO, NO, NO, 7000 },
464 {CTRY_JAPAN30, MKK6_MKKA1, "J30", "JAPAN30", YES, NO, NO, NO, NO, 7000 },
465 {CTRY_JAPAN31, MKK6_FCCA, "J31", "JAPAN31", YES, NO, NO, NO, NO, 7000 },
466 {CTRY_JAPAN32, MKK7_MKKA1, "J32", "JAPAN32", YES, NO, NO, NO, NO, 7000 },
467 {CTRY_JAPAN33, MKK7_FCCA, "J33", "JAPAN33", YES, NO, NO, NO, NO, 7000 },
468 {CTRY_JAPAN34, MKK9_MKKA, "J34", "JAPAN34", YES, NO, NO, NO, NO, 7000 },
469 {CTRY_JAPAN35, MKK10_MKKA, "J35", "JAPAN35", YES, NO, NO, NO, NO, 7000 },
470 {CTRY_JAPAN36, MKK4_MKKA, "J36", "JAPAN36", YES, NO, NO, NO, NO, 7000 },
471 {CTRY_JAPAN37, MKK9_FCCA, "J37", "JAPAN37", YES, NO, NO, NO, NO, 7000 },
472 {CTRY_JAPAN38, MKK9_MKKA1, "J38", "JAPAN38", YES, NO, NO, NO, NO, 7000 },
473 {CTRY_JAPAN39, MKK9_MKKC, "J39", "JAPAN39", YES, NO, NO, NO, NO, 7000 },
474 {CTRY_JAPAN40, MKK10_MKKA2, "J40", "JAPAN40", YES, NO, NO, NO, NO, 7000 },
475 {CTRY_JAPAN41, MKK10_FCCA, "J41", "JAPAN41", YES, NO, NO, NO, NO, 7000 },
476 {CTRY_JAPAN42, MKK10_MKKA1, "J42", "JAPAN42", YES, NO, NO, NO, NO, 7000 },
477 {CTRY_JAPAN43, MKK10_MKKC, "J43", "JAPAN43", YES, NO, NO, NO, NO, 7000 },
478 {CTRY_JAPAN44, MKK10_MKKA2, "J44", "JAPAN44", YES, NO, NO, NO, NO, 7000 },
479 {CTRY_JAPAN45, MKK11_MKKA, "J45", "JAPAN45", YES, NO, NO, NO, NO, 7000 },
480 {CTRY_JAPAN46, MKK11_FCCA, "J46", "JAPAN46", YES, NO, NO, NO, NO, 7000 },
481 {CTRY_JAPAN47, MKK11_MKKA1, "J47", "JAPAN47", YES, NO, NO, NO, NO, 7000 },
482 {CTRY_JAPAN48, MKK11_MKKC, "J48", "JAPAN48", YES, NO, NO, NO, NO, 7000 },
483 {CTRY_JAPAN49, MKK11_MKKA2, "J49", "JAPAN49", YES, NO, NO, NO, NO, 7000 },
484 {CTRY_JAPAN50, MKK12_MKKA, "J50", "JAPAN50", YES, NO, NO, NO, NO, 7000 },
485 {CTRY_JAPAN51, MKK12_FCCA, "J51", "JAPAN51", YES, NO, NO, NO, NO, 7000 },
486 {CTRY_JAPAN52, MKK12_MKKA1, "J52", "JAPAN52", YES, NO, NO, NO, NO, 7000 },
487 {CTRY_JAPAN53, MKK12_MKKC, "J53", "JAPAN53", YES, NO, NO, NO, NO, 7000 },
488 {CTRY_JAPAN54, MKK12_MKKA2, "J54", "JAPAN54", YES, NO, NO, NO, NO, 7000 },
489 {CTRY_JORDAN, ETSI2_WORLD, "JO", "JORDAN", YES, NO, YES, NO, YES, 7000 },
490 {CTRY_KAZAKHSTAN, NULL1_WORLD, "KZ", "KAZAKHSTAN", YES, NO, YES, NO, YES, 7000 },
491 {CTRY_KOREA_NORTH, APL9_WORLD, "KP", "NORTH KOREA", YES, NO, NO, YES, YES, 7000 },
492 {CTRY_KOREA_ROC, APL9_WORLD, "KR", "KOREA REPUBLIC", YES, NO, NO, NO, NO, 7000 },
493 {CTRY_KOREA_ROC2, APL2_APLD, "K2", "KOREA REPUBLIC2", YES, NO, NO, NO, NO, 7000 },
494 {CTRY_KOREA_ROC3, APL9_WORLD, "K3", "KOREA REPUBLIC3", YES, NO, NO, NO, NO, 7000 },
495 {CTRY_KUWAIT, NULL1_WORLD, "KW", "KUWAIT", YES, NO, YES, NO, YES, 7000 },
496 {CTRY_LATVIA, ETSI1_WORLD, "LV", "LATVIA", YES, NO, YES, YES, YES, 7000 },
497 {CTRY_LEBANON, NULL1_WORLD, "LB", "LEBANON", YES, NO, YES, NO, YES, 7000 },
498 {CTRY_LIECHTENSTEIN, ETSI1_WORLD, "LI", "LIECHTENSTEIN", YES, NO, YES, YES, YES, 7000 },
499 {CTRY_LITHUANIA, ETSI1_WORLD, "LT", "LITHUANIA", YES, NO, YES, YES, YES, 7000 },
500 {CTRY_LUXEMBOURG, ETSI1_WORLD, "LU", "LUXEMBOURG", YES, NO, YES, YES, YES, 7000 },
501 {CTRY_MACAU, FCC2_WORLD, "MO", "MACAU", YES, YES, YES, YES, YES, 7000 },
502 {CTRY_MACEDONIA, NULL1_WORLD, "MK", "MACEDONIA", YES, NO, YES, NO, YES, 7000 },
503 {CTRY_MALAYSIA, APL8_WORLD, "MY", "MALAYSIA", NO, NO, NO, NO, NO, 7000 },
504 {CTRY_MALTA, ETSI1_WORLD, "MT", "MALTA", YES, NO, YES, YES, YES, 7000 },
505 {CTRY_MEXICO, FCC1_FCCA, "MX", "MEXICO", YES, YES, YES, YES, YES, 7000 },
506 {CTRY_MONACO, ETSI4_WORLD, "MC", "MONACO", YES, YES, YES, YES, YES, 7000 },
507 {CTRY_MOROCCO, NULL1_WORLD, "MA", "MOROCCO", YES, NO, YES, NO, YES, 7000 },
508 {CTRY_NETHERLANDS, ETSI1_WORLD, "NL", "NETHERLANDS", YES, NO, YES, YES, YES, 7000 },
509 {CTRY_NETHERLANDS_ANT, ETSI1_WORLD, "AN", "NETHERLANDS-ANTILLES", YES, NO, YES, YES, YES, 7000 },
510 {CTRY_NEW_ZEALAND, FCC2_ETSIC, "NZ", "NEW ZEALAND", YES, NO, YES, NO, YES, 7000 },
511 {CTRY_NORWAY, ETSI1_WORLD, "NO", "NORWAY", YES, NO, YES, YES, YES, 7000 },
512 {CTRY_OMAN, APL6_WORLD, "OM", "OMAN", YES, NO, YES, NO, YES, 7000 },
513 {CTRY_PAKISTAN, NULL1_WORLD, "PK", "PAKISTAN", YES, NO, YES, NO, YES, 7000 },
514 {CTRY_PANAMA, FCC1_FCCA, "PA", "PANAMA", YES, YES, YES, YES, YES, 7000 },
515 {CTRY_PERU, APL1_WORLD, "PE", "PERU", YES, NO, YES, NO, YES, 7000 },
516 {CTRY_PHILIPPINES, APL1_WORLD, "PH", "PHILIPPINES", YES, YES, YES, YES, YES, 7000 },
517 {CTRY_POLAND, ETSI1_WORLD, "PL", "POLAND", YES, NO, YES, YES, YES, 7000 },
518 {CTRY_PORTUGAL, ETSI1_WORLD, "PT", "PORTUGAL", YES, NO, YES, YES, YES, 7000 },
519 {CTRY_PUERTO_RICO, FCC1_FCCA, "PR", "PUERTO RICO", YES, YES, YES, YES, YES, 7000 },
520 {CTRY_QATAR, NULL1_WORLD, "QA", "QATAR", YES, NO, YES, NO, YES, 7000 },
521 {CTRY_ROMANIA, NULL1_WORLD, "RO", "ROMANIA", YES, NO, YES, NO, YES, 7000 },
522 {CTRY_RUSSIA, NULL1_WORLD, "RU", "RUSSIA", YES, NO, YES, NO, YES, 7000 },
523 {CTRY_SAUDI_ARABIA, NULL1_WORLD, "SA", "SAUDI ARABIA", YES, NO, YES, NO, YES, 7000 },
524 {CTRY_SERBIA_MONT, ETSI1_WORLD, "CS", "SERBIA & MONTENEGRO", YES, NO, YES, YES, YES, 7000 },
525 {CTRY_SINGAPORE, APL6_WORLD, "SG", "SINGAPORE", YES, YES, YES, YES, YES, 7000 },
526 {CTRY_SLOVAKIA, ETSI1_WORLD, "SK", "SLOVAK REPUBLIC", YES, NO, YES, YES, YES, 7000 },
527 {CTRY_SLOVENIA, ETSI1_WORLD, "SI", "SLOVENIA", YES, NO, YES, YES, YES, 7000 },
528 {CTRY_SOUTH_AFRICA, FCC3_WORLD, "ZA", "SOUTH AFRICA", YES, NO, YES, NO, YES, 7000 },
529 {CTRY_SPAIN, ETSI1_WORLD, "ES", "SPAIN", YES, NO, YES, YES, YES, 7000 },
530 {CTRY_SRILANKA, FCC3_WORLD, "LK", "SRI LANKA", YES, NO, YES, NO, YES, 7000 },
531 {CTRY_SWEDEN, ETSI1_WORLD, "SE", "SWEDEN", YES, NO, YES, YES, YES, 7000 },
532 {CTRY_SWITZERLAND, ETSI1_WORLD, "CH", "SWITZERLAND", YES, NO, YES, YES, YES, 7000 },
533 {CTRY_SYRIA, NULL1_WORLD, "SY", "SYRIA", YES, NO, YES, NO, YES, 7000 },
534 {CTRY_TAIWAN, APL3_FCCA, "TW", "TAIWAN", YES, YES, YES, YES, YES, 7000 },
535 {CTRY_THAILAND, NULL1_WORLD, "TH", "THAILAND", YES, NO, YES, NO, YES, 7000 },
536 {CTRY_TRINIDAD_Y_TOBAGO, ETSI4_WORLD, "TT", "TRINIDAD & TOBAGO", YES, NO, YES, NO, YES, 7000 },
537 {CTRY_TUNISIA, ETSI3_WORLD, "TN", "TUNISIA", YES, NO, YES, NO, YES, 7000 },
538 {CTRY_TURKEY, ETSI3_WORLD, "TR", "TURKEY", YES, NO, YES, NO, YES, 7000 },
539 {CTRY_UKRAINE, NULL1_WORLD, "UA", "UKRAINE", YES, NO, YES, NO, YES, 7000 },
540 {CTRY_UAE, NULL1_WORLD, "AE", "UNITED ARAB EMIRATES", YES, NO, YES, NO, YES, 7000 },
541 {CTRY_UNITED_KINGDOM, ETSI1_WORLD, "GB", "UNITED KINGDOM", YES, NO, YES, NO, YES, 7000 },
542 {CTRY_UNITED_STATES, FCC3_FCCA, "US", "UNITED STATES", YES, YES, YES, YES, YES, 5825 },
543 {CTRY_UNITED_STATES_FCC49, FCC4_FCCA, "PS", "UNITED STATES (PUBLIC SAFETY)", YES, YES, YES, YES, YES, 7000 },
544 {CTRY_URUGUAY, FCC1_WORLD, "UY", "URUGUAY", YES, NO, YES, NO, YES, 7000 },
545 {CTRY_UZBEKISTAN, FCC3_FCCA, "UZ", "UZBEKISTAN", YES, YES, YES, YES, YES, 7000 },
546 {CTRY_VENEZUELA, APL2_ETSIC, "VE", "VENEZUELA", YES, NO, YES, NO, YES, 7000 },
547 {CTRY_VIET_NAM, NULL1_WORLD, "VN", "VIET NAM", YES, NO, YES, NO, YES, 7000 },
548 {CTRY_YEMEN, NULL1_WORLD, "YE", "YEMEN", YES, NO, YES, NO, YES, 7000 },
549 {CTRY_ZIMBABWE, NULL1_WORLD, "ZW", "ZIMBABWE", YES, NO, YES, NO, YES, 7000 }
550 };
551
552 typedef struct RegDmnFreqBand {
553 u16_t lowChannel; /* Low channel center in MHz */
554 u16_t highChannel; /* High Channel center in MHz */
555 u8_t powerDfs; /* Max power (dBm) for channel
556 range when using DFS */
557 u8_t antennaMax; /* Max allowed antenna gain */
558 u8_t channelBW; /* Bandwidth of the channel */
559 u8_t channelSep; /* Channel separation within
560 the band */
561 u64_t useDfs; /* Use DFS in the RegDomain
562 if corresponding bit is set */
563 u64_t usePassScan; /* Use Passive Scan in the RegDomain
564 if corresponding bit is set */
565 u8_t regClassId; /* Regulatory class id */
566 u8_t useExtChanDfs; /* Regulatory class id */
567 } REG_DMN_FREQ_BAND;
568
569 /* Bit masks for DFS per regdomain */
570
571 enum {
572 NO_DFS = 0x0000000000000000ULL,
573 DFS_FCC3 = 0x0000000000000001ULL,
574 DFS_ETSI = 0x0000000000000002ULL,
575 DFS_MKK4 = 0x0000000000000004ULL,
576 };
577
578 /* The table of frequency bands is indexed by a bitmask. The ordering
579 * must be consistent with the enum below. When adding a new
580 * frequency band, be sure to match the location in the enum with the
581 * comments
582 */
583
584 /*
585 * 5GHz 11A channel tags
586 */
587
588 enum {
589 F1_4915_4925,
590 F1_4935_4945,
591 F1_4920_4980,
592 F1_4942_4987,
593 F1_4945_4985,
594 F1_4950_4980,
595 F1_5035_5040,
596 F1_5040_5080,
597 F1_5055_5055,
598
599 F1_5120_5240,
600
601 F1_5170_5230,
602 F2_5170_5230,
603
604 F1_5180_5240,
605 F2_5180_5240,
606 F3_5180_5240,
607 F4_5180_5240,
608 F5_5180_5240,
609 F6_5180_5240,
610 F7_5180_5240,
611
612 F1_5180_5320,
613
614 F1_5240_5280,
615
616 F1_5260_5280,
617
618 F1_5260_5320,
619 F2_5260_5320,
620 F3_5260_5320,
621 F4_5260_5320,
622 F5_5260_5320,
623 F6_5260_5320,
624 F7_5260_5320,
625
626 F1_5260_5700,
627
628 F1_5280_5320,
629
630 F1_5500_5580,
631
632 F1_5500_5620,
633
634 F1_5500_5700,
635 F2_5500_5700,
636 F3_5500_5700,
637 F4_5500_5700,
638
639 F1_5660_5700,
640
641 F1_5745_5805,
642 F2_5745_5805,
643 F3_5745_5805,
644
645 F1_5745_5825,
646 F2_5745_5825,
647 F3_5745_5825,
648 F4_5745_5825,
649 F5_5745_5825,
650 F6_5745_5825,
651
652 W1_4920_4980,
653 W1_5040_5080,
654 W1_5170_5230,
655 W1_5180_5240,
656 W1_5260_5320,
657 W1_5745_5825,
658 W1_5500_5700,
659 W2_5260_5320,
660 W2_5180_5240,
661 W2_5825_5825,
662 };
663
664 static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = {
665 { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4915_4925 */
666 { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 16, 0 }, /* F1_4935_4945 */
667 { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 7, 0 }, /* F1_4920_4980 */
668 { 4942, 4987, 27, 6, 5, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4942_4987 */
669 { 4945, 4985, 30, 6, 10, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4945_4985 */
670 { 4950, 4980, 33, 6, 20, 5, DFS_FCC3, PSCAN_FCC, 0, 0 }, /* F1_4950_4980 */
671 { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5035_5040 */
672 { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2, 2, 0 }, /* F1_5040_5080 */
673 { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2, 12, 0 }, /* F1_5055_5055 */
674
675 { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5120_5240 */
676
677 { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F1_5170_5230 */
678 { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2, 1, 0 }, /* F2_5170_5230 */
679
680 { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5180_5240 */
681 { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC, 1, 0 }, /* F2_5180_5240 */
682 { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5180_5240 */
683 { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F4_5180_5240 */
684 { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F5_5180_5240 */
685 { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC, 0, 0 }, /* F6_5180_5240 */
686 { 5180, 5240, 23, 6, 20, 20, NO_DFS, NO_PSCAN, 0 }, /* F7_5180_5240 */
687
688 { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5180_5320 */
689
690 { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5240_5280 */
691
692 { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5280 */
693
694 { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F1_5260_5320 */
695
696 { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 , 0, 0 },
697 /* F2_5260_5320 */
698
699 { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F3_5260_5320 */
700 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 2, 0 }, /* F4_5260_5320 */
701 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F5_5260_5320 */
702 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5260_5320 */
703 { 5260, 5320, 17, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F7_5260_5320 */
704
705 { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN, 0, 0 }, /* F1_5260_5700 */
706
707 { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 0, 0 }, /* F1_5280_5320 */
708
709 { 5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5500_5580 */
710
711 { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F1_5500_5620 */
712
713 { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC, 4, 0 }, /* F1_5500_5700 */
714 { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F2_5500_5700 */
715 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI, 0, 0 }, /* F3_5500_5700 */
716 { 5500, 5700, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC, 0, 0 },
717 /* F4_5500_5700 */
718
719 { 5660, 5700, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC, 0}, /* F1_5660_5700 */
720
721 { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5805 */
722 { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5805 */
723 { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI, 0, 0 }, /* F3_5745_5805 */
724 { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F1_5745_5825 */
725 { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F2_5745_5825 */
726 { 5745, 5825, 20, 0, 20, 20, DFS_ETSI, NO_PSCAN, 0, 0 }, /* F3_5745_5825 */
727 { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F4_5745_5825 */
728 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 3, 0 }, /* F5_5745_5825 */
729 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* F6_5745_5825 */
730
731 /*
732 * Below are the world roaming channels
733 * All WWR domains have no power limit, instead use the card's CTL
734 * or max power settings.
735 */
736 { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_4920_4980 */
737 { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0 }, /* W1_5040_5080 */
738 { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5170_5230 */
739 { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5180_5240 */
740 { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5260_5320 */
741 { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W1_5745_5825 */
742 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, 0, 0 }, /* W1_5500_5700 */
743 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5260_5320 */
744 { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN, 0, 0 }, /* W2_5180_5240 */
745 { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR, 0, 0 }, /* W2_5825_5825 */
746 };
747 /*
748 * 5GHz Turbo (dynamic & static) tags
749 */
750
751 enum {
752 T1_5130_5210,
753 T1_5250_5330,
754 T1_5370_5490,
755 T1_5530_5650,
756
757 T1_5150_5190,
758 T1_5230_5310,
759 T1_5350_5470,
760 T1_5510_5670,
761
762 T1_5200_5240,
763 T2_5200_5240,
764 T1_5210_5210,
765 T2_5210_5210,
766
767 T1_5280_5280,
768 T2_5280_5280,
769 T1_5250_5250,
770 T1_5290_5290,
771 T1_5250_5290,
772 T2_5250_5290,
773
774 T1_5540_5660,
775 T1_5760_5800,
776 T2_5760_5800,
777
778 T1_5765_5805,
779
780 WT1_5210_5250,
781 WT1_5290_5290,
782 WT1_5540_5660,
783 WT1_5760_5800,
784 };
785
786 /*
787 * 2GHz 11b channel tags
788 */
789 enum {
790 F1_2312_2372,
791 F2_2312_2372,
792
793 F1_2412_2472,
794 F2_2412_2472,
795 F3_2412_2472,
796
797 F1_2412_2462,
798 F2_2412_2462,
799
800 F1_2432_2442,
801
802 F1_2457_2472,
803
804 F1_2467_2472,
805
806 F1_2484_2484,
807 F2_2484_2484,
808
809 F1_2512_2732,
810
811 W1_2312_2372,
812 W1_2412_2412,
813 W1_2417_2432,
814 W1_2437_2442,
815 W1_2447_2457,
816 W1_2462_2462,
817 W1_2467_2467,
818 W2_2467_2467,
819 W1_2472_2472,
820 W2_2472_2472,
821 W1_2484_2484,
822 W2_2484_2484,
823 };
824
825
826 /*
827 * 2GHz 11g channel tags
828 */
829
830 enum {
831 G1_2312_2372,
832 G2_2312_2372,
833
834 G1_2412_2472,
835 G2_2412_2472,
836 G3_2412_2472,
837
838 G1_2412_2462,
839 G2_2412_2462,
840
841 G1_2432_2442,
842
843 G1_2457_2472,
844
845 G1_2512_2732,
846
847 G1_2467_2472 ,
848
849 WG1_2312_2372,
850 WG1_2412_2412,
851 WG1_2417_2432,
852 WG1_2437_2442,
853 WG1_2447_2457,
854 WG1_2462_2462,
855 WG1_2467_2467,
856 WG2_2467_2467,
857 WG1_2472_2472,
858 WG2_2472_2472,
859
860 };
861 static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = {
862 { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2312_2372 */
863 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G2_2312_2372 */
864
865 { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2472 */
866 { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2472 */
867 { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G3_2412_2472 */
868
869 { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2412_2462 */
870 { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G, 0, 0}, /* G2_2412_2462 */
871 { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2432_2442 */
872
873 { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2457_2472 */
874
875 { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* G1_2512_2732 */
876
877 { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA, 0, 0 }, /* G1_2467_2472 */
878
879 /*
880 * WWR open up the power to 20dBm
881 */
882
883 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2312_2372 */
884 { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2412_2412 */
885 { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2417_2432 */
886 { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2437_2442 */
887 { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2447_2457 */
888 { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN, 0, 0}, /* WG1_2462_2462 */
889 { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2467_2467 */
890 { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2467_2467 */
891 { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN, 0, 0}, /* WG1_2472_2472 */
892 { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN, 0, 0}, /* WG2_2472_2472 */
893 };
894 /*
895 * 2GHz Dynamic turbo tags
896 */
897
898 enum {
899 T1_2312_2372,
900 T1_2437_2437,
901 T2_2437_2437,
902 T3_2437_2437,
903 T1_2512_2732
904 };
905
906 /*
907 * 2GHz 11n frequency tags
908 */
909 enum {
910 NG1_2422_2452,
911 NG2_2422_2452,
912 NG3_2422_2452,
913
914 NG_DEMO_ALL_CHANNELS,
915 };
916
917 /*
918 * 5GHz 11n frequency tags
919 */
920 enum {
921 NA1_5190_5230,
922 NA2_5190_5230,
923 NA3_5190_5230,
924 NA4_5190_5230,
925 NA5_5190_5230,
926
927 NA1_5270_5270,
928
929 NA1_5270_5310,
930 NA2_5270_5310,
931 NA3_5270_5310,
932 NA4_5270_5310,
933
934 NA1_5310_5310,
935
936 NA1_5510_5630,
937
938 NA1_5510_5670,
939 NA2_5510_5670,
940 NA3_5510_5670,
941
942 NA1_5755_5795,
943 NA2_5755_5795,
944 NA3_5755_5795,
945 NA4_5755_5795,
946 NA5_5755_5795,
947
948 NA1_5795_5795,
949
950 NA_DEMO_ALL_CHANNELS,
951 };
952
953 typedef struct regDomain {
954 u16_t regDmnEnum; /* value from EnumRd table */
955 u8_t conformanceTestLimit;
956 u64_t dfsMask; /* DFS bitmask for 5Ghz tables */
957 u64_t pscan; /* Bitmask for passive scan */
958 u32_t flags; /* Requirement flags (AdHoc disallow, noise
959 floor cal needed, etc) */
960 u64_t chan11a[BMLEN];/* 128 bit bitmask for channel/band
961 selection */
962 u64_t chan11a_turbo[BMLEN];/* 128 bit bitmask for channel/band
963 selection */
964 u64_t chan11a_dyn_turbo[BMLEN]; /* 128 bit bitmask for channel/band
965 selection */
966 u64_t chan11b[BMLEN];/* 128 bit bitmask for channel/band
967 selection */
968 u64_t chan11g[BMLEN];/* 128 bit bitmask for channel/band
969 selection */
970 u64_t chan11g_turbo[BMLEN];/* 128 bit bitmask for channel/band
971 selection */
972 u64_t chan11ng[BMLEN];/* 128 bit bitmask for 11n in 2GHz */
973 u64_t chan11na[BMLEN];/* 128 bit bitmask for 11n in 5GHz */
974 } REG_DOMAIN;
975
976 static REG_DOMAIN regDomains[] = {
977
978 {DEBUG_REG_DMN, FCC, NO_DFS, NO_PSCAN, NO_REQ,
979 BM(F1_5120_5240, F1_5260_5700, F1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
980 BM(T1_5130_5210, T1_5250_5330, T1_5370_5490, T1_5530_5650, T1_5150_5190, T1_5230_5310, T1_5350_5470, T1_5510_5670, -1, -1, -1, -1),
981 BM(T1_5200_5240, T1_5280_5280, T1_5540_5660, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1),
982 BM(F1_2312_2372, F1_2412_2472, F1_2484_2484, F1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1),
983 BM(G1_2312_2372, G1_2412_2472, G1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1),
984 BM(T1_2312_2372, T1_2437_2437, T1_2512_2732, -1, -1, -1, -1, -1, -1, -1, -1, -1),
985 BM(NG_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
986 BM(NA_DEMO_ALL_CHANNELS, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
987
988 {APL1, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
989 BM(F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
990 BMZERO,
991 BMZERO,
992 BMZERO,
993 BMZERO,
994 BMZERO,
995 BMZERO,
996 BM(NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
997
998 {APL2, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
999 BM(F1_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1000 BMZERO,
1001 BMZERO,
1002 BMZERO,
1003 BMZERO,
1004 BMZERO,
1005 BMZERO,
1006 BM(NA3_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1007
1008 {APL3, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1009 BM(F1_5280_5320, F2_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1010 BMZERO,
1011 BMZERO,
1012 BMZERO,
1013 BMZERO,
1014 BMZERO,
1015 BMZERO,
1016 BM(NA1_5310_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1017
1018 {APL4, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1019 BM(F4_5180_5240, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1020 BMZERO,
1021 BMZERO,
1022 BMZERO,
1023 BMZERO,
1024 BMZERO,
1025 BMZERO,
1026 BM(NA4_5190_5230, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1027
1028 {APL5, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1029 BM(F2_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1030 BMZERO,
1031 BMZERO,
1032 BMZERO,
1033 BMZERO,
1034 BMZERO,
1035 BMZERO,
1036 BM(NA1_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1037
1038 {APL6, ETSI, DFS_ETSI, PSCAN_FCC_T | PSCAN_FCC , NO_REQ,
1039 BM(F4_5180_5240, F2_5260_5320, F3_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1040 BM(T2_5210_5210, T1_5250_5290, T1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1041 BMZERO,
1042 BMZERO,
1043 BMZERO,
1044 BMZERO,
1045 BMZERO,
1046 BM(NA4_5190_5230, NA2_5270_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1047
1048 {APL7, FCC, NO_DFS, PSCAN_FCC_T | PSCAN_FCC , NO_REQ,
1049 BM(F7_5260_5320, F4_5500_5700, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1050 BMZERO,
1051 BMZERO,
1052 BMZERO,
1053 BMZERO,
1054 BMZERO,
1055 BMZERO,
1056 BM(NA1_5310_5310, NA2_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1057 {APL8, ETSI, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
1058 BM(F6_5260_5320, F4_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1059 BMZERO,
1060 BMZERO,
1061 BMZERO,
1062 BMZERO,
1063 BMZERO,
1064 BMZERO,
1065 BM(NA4_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1066
1067 {APL9, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
1068 BM(F1_5180_5320, F1_5500_5620, F3_5745_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1069 BMZERO,
1070 BMZERO,
1071 BMZERO,
1072 BMZERO,
1073 BMZERO,
1074 BMZERO,
1075 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5630, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)},
1076
1077 {ETSI1, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1078 BM(W2_5180_5240, F2_5260_5320, F2_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1079 BMZERO,
1080 BMZERO,
1081 BMZERO,
1082 BMZERO,
1083 BMZERO,
1084 BMZERO,
1085 BM(NA4_5190_5230, NA2_5270_5310, NA2_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1086
1087 {ETSI2, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1088 BM(F3_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1089 BMZERO,
1090 BMZERO,
1091 BMZERO,
1092 BMZERO,
1093 BMZERO,
1094 BMZERO,
1095 BM(NA3_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1096
1097 {ETSI3, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1098 BM(W2_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1099 BMZERO,
1100 BMZERO,
1101 BMZERO,
1102 BMZERO,
1103 BMZERO,
1104 BMZERO,
1105 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1106
1107 {ETSI4, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1108 BM(F3_5180_5240, F1_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1109 BMZERO,
1110 BMZERO,
1111 BMZERO,
1112 BMZERO,
1113 BMZERO,
1114 BMZERO,
1115 BM(NA3_5190_5230, NA1_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1116
1117 {ETSI5, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1118 BM(F1_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1119 BMZERO,
1120 BMZERO,
1121 BMZERO,
1122 BMZERO,
1123 BMZERO,
1124 BMZERO,
1125 BM(NA1_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1126
1127 {ETSI6, ETSI, DFS_ETSI, PSCAN_ETSI, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1128 BM(F5_5180_5240, F1_5260_5280, F3_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1129 BMZERO,
1130 BMZERO,
1131 BMZERO,
1132 BMZERO,
1133 BMZERO,
1134 BMZERO,
1135 BM(NA5_5190_5230, NA1_5270_5270, NA3_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1136
1137 {FCC1, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1138 BM(F2_5180_5240, F4_5260_5320, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1139 BM(T1_5210_5210, T2_5250_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1140 BM(T1_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1141 BMZERO,
1142 BMZERO,
1143 BMZERO,
1144 BMZERO,
1145 BM(NA2_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1146
1147 {FCC2, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1148 BM(F6_5180_5240, F5_5260_5320, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1149 BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1150 BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1151 BMZERO,
1152 BMZERO,
1153 BMZERO,
1154 BMZERO,
1155 BM(NA5_5190_5230, NA3_5270_5310, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1156
1157 {FCC3, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ,
1158 BM(F2_5180_5240, F3_5260_5320, F1_5500_5700, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1),
1159 BM(T1_5210_5210, T1_5250_5250, T1_5290_5290, T2_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1),
1160 BM(T1_5200_5240, T2_5280_5280, T1_5540_5660, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1161 BMZERO,
1162 BMZERO,
1163 BMZERO,
1164 BMZERO,
1165 BM(NA2_5190_5230, NA2_5270_5310, NA3_5510_5670, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1)},
1166
1167 {FCC4, FCC, DFS_FCC3, PSCAN_FCC | PSCAN_FCC_T, NO_REQ,
1168 BM(F1_4942_4987, F1_4945_4985, F1_4950_4980, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1169 BMZERO,
1170 BMZERO,
1171 BMZERO,
1172 BMZERO,
1173 BMZERO,
1174 BMZERO,
1175 BMZERO},
1176
1177 {FCC5, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1178 BM(F2_5180_5240, F5_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1179 BMZERO,
1180 BMZERO,
1181 BMZERO,
1182 BMZERO,
1183 BMZERO,
1184 BMZERO,
1185 BM(NA2_5190_5230, NA4_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1186
1187 {FCC6, FCC, DFS_FCC3, PSCAN_FCC, NO_REQ,
1188 BM(F7_5180_5240, F5_5260_5320, F1_5500_5580, F1_5660_5700, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1),
1189 BM(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1190 BM(T2_5200_5240, T1_5280_5280, T1_5765_5805, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1191 BMZERO,
1192 BMZERO,
1193 BMZERO,
1194 BMZERO,
1195 BM(NA5_5190_5230, NA5_5755_5795, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1196
1197 {MKK1, MKK, NO_DFS, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1198 BM(F1_5170_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1199 BMZERO,
1200 BMZERO,
1201 BMZERO,
1202 BMZERO,
1203 BMZERO,
1204 BMZERO,
1205 BMZERO},
1206
1207 {MKK2, MKK, NO_DFS, PSCAN_MKK2, DISALLOW_ADHOC_11A_TURB,
1208 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, -1, -1, -1, -1, -1),
1209 BMZERO,
1210 BMZERO,
1211 BMZERO,
1212 BMZERO,
1213 BMZERO,
1214 BMZERO,
1215 BMZERO},
1216
1217 /* UNI-1 even */
1218 {MKK3, MKK, NO_DFS, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1219 BM(F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1220 BMZERO,
1221 BMZERO,
1222 BMZERO,
1223 BMZERO,
1224 BMZERO,
1225 BMZERO,
1226 BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1227
1228 /* UNI-1 even + UNI-2 */
1229 {MKK4, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1230 BM(F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1231 BMZERO,
1232 BMZERO,
1233 BMZERO,
1234 BMZERO,
1235 BMZERO,
1236 BMZERO,
1237 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1238
1239 /* UNI-1 even + UNI-2 + mid-band */
1240 {MKK5, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1241 BM(F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1242 BMZERO,
1243 BMZERO,
1244 BMZERO,
1245 BMZERO,
1246 BMZERO,
1247 BMZERO,
1248 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1249
1250 /* UNI-1 odd + even */
1251 {MKK6, MKK, DFS_MKK4, PSCAN_MKK1, DISALLOW_ADHOC_11A_TURB,
1252 BM(F2_5170_5230, F4_5180_5240, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1253 BMZERO,
1254 BMZERO,
1255 BMZERO,
1256 BMZERO,
1257 BMZERO,
1258 BMZERO,
1259 BM(NA4_5190_5230, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1260
1261 /* UNI-1 odd + UNI-1 even + UNI-2 */
1262 {MKK7, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB,
1263 BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1264 BMZERO,
1265 BMZERO,
1266 BMZERO,
1267 BMZERO,
1268 BMZERO,
1269 BMZERO,
1270 BM(NA4_5190_5230, NA2_5270_5310, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1271
1272 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */
1273 {MKK8, MKK, DFS_MKK4, PSCAN_MKK1 | PSCAN_MKK3 , DISALLOW_ADHOC_11A_TURB,
1274 BM(F2_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1),
1275 BMZERO,
1276 BMZERO,
1277 BMZERO,
1278 BMZERO,
1279 BMZERO,
1280 BMZERO,
1281 BM(NA4_5190_5230, NA2_5270_5310, NA1_5510_5670, -1, -1, -1, -1, -1, -1, -1, -1, -1)},
1282
1283 /* UNI-1 even + 4.9 GHZ */
1284 {MKK9, MKK, NO_DFS, NO_PSCAN, DISALLOW_ADHOC_11A_TURB,
1285 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, -1, -1, -1, -1, -1),
1286 BMZERO,
1287 BMZERO,
1288 BMZERO,
1289 BMZERO,
1290 BMZERO,
1291 BMZERO,
1292 BMZERO},
1293
1294 /* UNI-1 even + UNI-2 + 4.9 GHZ */
1295 {MKK10, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1296 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, -1, -1, -1, -1),
1297 BMZERO,
1298 BMZERO,
1299 BMZERO,
1300 BMZERO,
1301 BMZERO,
1302 BMZERO,
1303 BMZERO},
1304
1305 /* UNI-1 even + UNI-2 + 4.9 GHZ + mid-band */
1306 {MKK11, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1307 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1, -1),
1308 BMZERO,
1309 BMZERO,
1310 BMZERO,
1311 BMZERO,
1312 BMZERO,
1313 BMZERO,
1314 BMZERO},
1315
1316 /* UNI-1 even + UNI-1 odd + UNI-2 + 4.9 GHZ + mid-band */
1317 {MKK12, MKK, DFS_MKK4, PSCAN_MKK3, DISALLOW_ADHOC_11A_TURB,
1318 BM(F1_4915_4925, F1_4935_4945, F1_4920_4980, F1_5035_5040, F1_5055_5055, F1_5040_5080, F1_5170_5230, F4_5180_5240, F2_5260_5320, F4_5500_5700, -1, -1),
1319 BMZERO,
1320 BMZERO,
1321 BMZERO,
1322 BMZERO,
1323 BMZERO,
1324 BMZERO,
1325 BMZERO},
1326
1327 /* Defined here to use when 2G channels are authorised for country K2 */
1328 {APLD, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ,
1329 BMZERO,
1330 BMZERO,
1331 BMZERO,
1332 BM(F2_2312_2372, F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1333 BM(G2_2312_2372, G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1334 BMZERO,
1335 BMZERO,
1336 BMZERO},
1337
1338 {ETSIA, NO_CTL, NO_DFS, PSCAN_ETSIA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1339 BMZERO,
1340 BMZERO,
1341 BMZERO,
1342 BM(F1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1343 BM(G1_2457_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1344 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1345 BMZERO,
1346 BMZERO},
1347
1348 {ETSIB, ETSI, NO_DFS, PSCAN_ETSIB, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1349 BMZERO,
1350 BMZERO,
1351 BMZERO,
1352 BM(F1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1353 BM(G1_2432_2442, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1354 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1355 BMZERO,
1356 BMZERO},
1357
1358 {ETSIC, ETSI, NO_DFS, PSCAN_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
1359 BMZERO,
1360 BMZERO,
1361 BMZERO,
1362 BM(F3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1363 BM(G3_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1364 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1365 BMZERO,
1366 BMZERO},
1367
1368 {FCCA, FCC, NO_DFS, NO_PSCAN, NO_REQ,
1369 BMZERO,
1370 BMZERO,
1371 BMZERO,
1372 BM(F1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1373 BM(G1_2412_2462, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1374 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1375 BM(NG2_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1376 BMZERO},
1377
1378 {MKKA, MKK, NO_DFS, PSCAN_MKKA | PSCAN_MKKA_G | PSCAN_MKKA1 | PSCAN_MKKA1_G | PSCAN_MKKA2 | PSCAN_MKKA2_G, DISALLOW_ADHOC_11A_TURB,
1379 BMZERO,
1380 BMZERO,
1381 BMZERO,
1382 BM(F2_2412_2462, F1_2467_2472, F2_2484_2484, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1383 BM(G2_2412_2462, G1_2467_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1384 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1385 BM(NG1_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1386 BMZERO},
1387
1388 {MKKC, MKK, NO_DFS, NO_PSCAN, NO_REQ,
1389 BMZERO,
1390 BMZERO,
1391 BMZERO,
1392 BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1393 BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1394 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1395 BM(NG1_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1396 BMZERO},
1397
1398 {WORLD, ETSI, NO_DFS, NO_PSCAN, NO_REQ,
1399 BMZERO,
1400 BMZERO,
1401 BMZERO,
1402 BM(F2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1403 BM(G2_2412_2472, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1404 BM(T2_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1405 BM(NG1_2422_2452, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1406 BMZERO},
1407
1408 {WOR0_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1409 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1410 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1411 BMZERO,
1412 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1),
1413 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1414 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1415 BMZERO,
1416 BMZERO},
1417
1418 {WOR01_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1419 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1420 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1421 BMZERO,
1422 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1423 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1424 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1425 BMZERO,
1426 BMZERO},
1427
1428 {WOR02_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1429 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1430 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1431 BMZERO,
1432 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1433 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1434 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1435 BMZERO,
1436 BMZERO},
1437
1438 {EU1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1439 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1440 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1441 BMZERO,
1442 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1),
1443 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG2_2472_2472, WG1_2417_2432, WG1_2447_2457, WG2_2467_2467, -1, -1, -1, -1, -1),
1444 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1445 BMZERO,
1446 BMZERO},
1447
1448 {WOR1_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1449 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1450 BMZERO,
1451 BMZERO,
1452 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1),
1453 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1454 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1455 BMZERO,
1456 BMZERO},
1457
1458 {WOR2_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1459 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1),
1460 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1461 BMZERO,
1462 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, W1_2484_2484, -1, -1, -1, -1),
1463 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1464 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1465 BMZERO,
1466 BMZERO},
1467
1468 {WOR3_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_PER_11D,
1469 BM(W1_5260_5320, W1_5180_5240, W1_5170_5230, W1_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1),
1470 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1471 BMZERO,
1472 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1473 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1474 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1475 BMZERO,
1476 BMZERO},
1477
1478 {WOR4_WORLD, NO_CTL, DFS_FCC3, PSCAN_WWR, ADHOC_NO_11A,
1479 BM(W2_5260_5320, W2_5180_5240, F2_5745_5805, W2_5825_5825, -1, -1, -1, -1, -1, -1, -1, -1),
1480 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1481 BMZERO,
1482 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1483 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1484 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1485 BMZERO,
1486 BMZERO},
1487
1488 {WOR5_ETSIC, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1489 BM(W1_5260_5320, W2_5180_5240, F6_5745_5825, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1490 BMZERO,
1491 BMZERO,
1492 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W2_2472_2472, W1_2417_2432, W1_2447_2457, W2_2467_2467, -1, -1, -1, -1, -1),
1493 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1494 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1495 BMZERO,
1496 BMZERO},
1497
1498 {WOR9_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1499 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1),
1500 BM(WT1_5210_5250, WT1_5290_5290, WT1_5760_5800, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1501 BMZERO,
1502 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2417_2432, W1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1503 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2417_2432, WG1_2447_2457, -1, -1, -1, -1, -1, -1, -1),
1504 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1505 BMZERO,
1506 BMZERO},
1507
1508 {WORA_WORLD, NO_CTL, DFS_FCC3 | DFS_ETSI, PSCAN_WWR, ADHOC_NO_11A,
1509 BM(W1_5260_5320, W1_5180_5240, W1_5745_5825, W1_5500_5700, -1, -1, -1, -1, -1, -1, -1, -1),
1510 BMZERO,
1511 BMZERO,
1512 BM(W1_2412_2412, W1_2437_2442, W1_2462_2462, W1_2472_2472, W1_2417_2432, W1_2447_2457, W1_2467_2467, -1, -1, -1, -1, -1),
1513 BM(WG1_2412_2412, WG1_2437_2442, WG1_2462_2462, WG1_2472_2472, WG1_2417_2432, WG1_2447_2457, WG1_2467_2467, -1, -1, -1, -1, -1),
1514 BM(T3_2437_2437, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1515 BMZERO,
1516 BMZERO},
1517
1518 {NULL1, NO_CTL, NO_DFS, NO_PSCAN, NO_REQ,
1519 BMZERO,
1520 BMZERO,
1521 BMZERO,
1522 BMZERO,
1523 BMZERO,
1524 BMZERO,
1525 BMZERO,
1526 BMZERO},
1527 };
1528
1529 struct cmode {
1530 u16_t mode;
1531 u32_t flags;
1532 };
1533
1534 static const struct cmode modes[] = {
1535 { HAL_MODE_TURBO, CHANNEL_ST}, /* TURBO means 11a Static Turbo */
1536 { HAL_MODE_11A, CHANNEL_A},
1537 { HAL_MODE_11B, CHANNEL_B},
1538 { HAL_MODE_11G, CHANNEL_G},
1539 { HAL_MODE_11G_TURBO, CHANNEL_108G},
1540 { HAL_MODE_11A_TURBO, CHANNEL_108A},
1541 { HAL_MODE_11NA, CHANNEL_A_HT40},
1542 { HAL_MODE_11NA, CHANNEL_A_HT20},
1543 { HAL_MODE_11NG, CHANNEL_G_HT40},
1544 { HAL_MODE_11NG, CHANNEL_G_HT20},
1545 };
1546
1547 /*
1548 * Return the Wireless Mode Regulatory Domain based
1549 * on the country code and the wireless mode.
1550 */
1551 u8_t GetWmRD(u16_t regionCode, u16_t channelFlag, REG_DOMAIN *rd)
1552 {
1553 s16_t i, found, regDmn;
1554 u64_t flags = NO_REQ;
1555 REG_DMN_PAIR_MAPPING *regPair = NULL;
1556
1557 for (i = 0, found = 0; (i < ARRAY_SIZE(regDomainPairs)) && (!found); i++) {
1558 if (regDomainPairs[i].regDmnEnum == regionCode) {
1559 regPair = &regDomainPairs[i];
1560 found = 1;
1561 }
1562 }
1563 if (!found) {
1564 zm_debug_msg1("Failed to find reg domain pair ", regionCode);
1565 return FALSE;
1566 }
1567
1568 if (channelFlag & ZM_REG_FLAG_CHANNEL_2GHZ) {
1569 regDmn = regPair->regDmn2GHz;
1570 flags = regPair->flags2GHz;
1571 } else {
1572 regDmn = regPair->regDmn5GHz;
1573 flags = regPair->flags5GHz;
1574 }
1575
1576 /*
1577 * We either started with a unitary reg domain or we've found the
1578 * unitary reg domain of the pair
1579 */
1580
1581 for (i = 0 ; i < ARRAY_SIZE(regDomains) ; i++) {
1582 if (regDomains[i].regDmnEnum == regDmn) {
1583 if (rd != NULL) {
1584 zfMemoryCopy((u8_t *)rd, (u8_t *)&regDomains[i],
1585 sizeof(REG_DOMAIN));
1586 }
1587 }
1588 }
1589 rd->pscan &= regPair->pscanMask;
1590 rd->flags = (u32_t)flags;
1591 return TRUE;
1592 }
1593
1594 /*
1595 * Test to see if the bitmask array is all zeros
1596 */
1597 u8_t isChanBitMaskZero(u64_t *bitmask)
1598 {
1599 u16_t i;
1600
1601 for (i = 0; i < BMLEN; i++) {
1602 if (bitmask[i] != 0)
1603 return FALSE;
1604 }
1605 return TRUE;
1606 }
1607
1608 u8_t IS_BIT_SET(u32_t bit, u64_t *bitmask)
1609 {
1610 u32_t byteOffset, bitnum;
1611 u64_t val;
1612
1613 byteOffset = bit/64;
1614 bitnum = bit - byteOffset*64;
1615 val = ((u64_t) 1) << bitnum;
1616 if (bitmask[byteOffset] & val)
1617 return TRUE;
1618 else
1619 return FALSE;
1620 }
1621
1622
1623 void zfHpGetRegulationTable(zdev_t *dev, u16_t regionCode, u16_t c_lo, u16_t c_hi)
1624 {
1625 REG_DOMAIN rd5GHz, rd2GHz;
1626 const struct cmode *cm;
1627 s16_t next = 0, b;
1628 struct zsHpPriv *hpPriv;
1629
1630 zmw_get_wlan_dev(dev);
1631 hpPriv = wd->hpPrivate;
1632
1633 zmw_declare_for_critical_section();
1634
1635 if (!GetWmRD(regionCode, ~ZM_REG_FLAG_CHANNEL_2GHZ, &rd5GHz)) {
1636 zm_debug_msg1("couldn't find unitary 5GHz reg domain for Region Code ", regionCode);
1637 return;
1638 }
1639 if (!GetWmRD(regionCode, ZM_REG_FLAG_CHANNEL_2GHZ, &rd2GHz)) {
1640 zm_debug_msg1("couldn't find unitary 2GHz reg domain for Region Code ", regionCode);
1641 return;
1642 }
1643 if (wd->regulationTable.regionCode == regionCode) {
1644 zm_debug_msg1("current region code is the same with Region Code ", regionCode);
1645 return;
1646 } else
1647 wd->regulationTable.regionCode = regionCode;
1648
1649 next = 0;
1650
1651 zmw_enter_critical_section(dev);
1652
1653 for (cm = modes; cm < &modes[ARRAY_SIZE(modes)]; cm++) {
1654 u16_t c;
1655 u64_t *channelBM = NULL;
1656 REG_DOMAIN *rd = NULL;
1657 REG_DMN_FREQ_BAND *fband = NULL, *freqs = NULL;
1658
1659 switch (cm->mode) {
1660 case HAL_MODE_TURBO:
1661 /* we don't have turbo mode so we disable it
1662 //zm_debug_msg0("CWY - HAL_MODE_TURBO"); */
1663 channelBM = NULL;
1664 /* rd = &rd5GHz;
1665 channelBM = rd->chan11a_turbo;
1666 freqs = &regDmn5GhzTurboFreq[0];
1667 ctl = rd->conformanceTestLimit | CTL_TURBO; */
1668 break;
1669 case HAL_MODE_11A:
1670 if ((hpPriv->OpFlags & 0x1) != 0) {
1671 rd = &rd5GHz;
1672 channelBM = rd->chan11a;
1673 freqs = &regDmn5GhzFreq[0];
1674 c_lo = 4920; /* from channel 184 */
1675 c_hi = 5825; /* to channel 165 */
1676 /* ctl = rd->conformanceTestLimit;
1677 zm_debug_msg2("CWY - HAL_MODE_11A, channelBM = 0x", *channelBM); */
1678 }
1679 /* else
1680 channelBM = NULL;
1681 */
1682 break;
1683 case HAL_MODE_11B:
1684 /* Disable 11B mode because it only has difference with 11G in PowerDFS Data,
1685 and we don't use this now.
1686 zm_debug_msg0("CWY - HAL_MODE_11B"); */
1687 channelBM = NULL;
1688 /* rd = &rd2GHz;
1689 channelBM = rd->chan11b;
1690 freqs = &regDmn2GhzFreq[0];
1691 ctl = rd->conformanceTestLimit | CTL_11B;
1692 zm_debug_msg2("CWY - HAL_MODE_11B, channelBM = 0x", *channelBM); */
1693 break;
1694 case HAL_MODE_11G:
1695 if ((hpPriv->OpFlags & 0x2) != 0) {
1696 rd = &rd2GHz;
1697 channelBM = rd->chan11g;
1698 freqs = &regDmn2Ghz11gFreq[0];
1699 c_lo = 2412; /* from channel 1 */
1700 /* c_hi = 2462; to channel 11 */
1701 c_hi = 2472; /* to channel 13 */
1702 /* ctl = rd->conformanceTestLimit | CTL_11G; */
1703 /* zm_debug_msg2("CWY - HAL_MODE_11G, channelBM = 0x", *channelBM); */
1704 }
1705 /* else
1706 channelBM = NULL;
1707 */
1708 break;
1709 case HAL_MODE_11G_TURBO:
1710 /* we don't have turbo mode so we disable it
1711 zm_debug_msg0("CWY - HAL_MODE_11G_TURBO"); */
1712 channelBM = NULL;
1713 /* rd = &rd2GHz;
1714 channelBM = rd->chan11g_turbo;
1715 freqs = &regDmn2Ghz11gTurboFreq[0];
1716 ctl = rd->conformanceTestLimit | CTL_108G; */
1717 break;
1718 case HAL_MODE_11A_TURBO:
1719 /* we don't have turbo mode so we disable it
1720 zm_debug_msg0("CWY - HAL_MODE_11A_TURBO"); */
1721 channelBM = NULL;
1722 /* rd = &rd5GHz;
1723 channelBM = rd->chan11a_dyn_turbo;
1724 freqs = &regDmn5GhzTurboFreq[0];
1725 ctl = rd->conformanceTestLimit | CTL_108G; */
1726 break;
1727 default:
1728 zm_debug_msg1("Unkonwn HAL mode ", cm->mode);
1729 continue;
1730 }
1731
1732 if (channelBM == NULL) {
1733 /* zm_debug_msg0("CWY - channelBM is NULL"); */
1734 continue;
1735 }
1736
1737 if (isChanBitMaskZero(channelBM)) {
1738 /* zm_debug_msg0("CWY - BitMask is Zero"); */
1739 continue;
1740 }
1741
1742 /* RAY:Is it ok?? */
1743 if (freqs == NULL)
1744 continue;
1745
1746 for (b = 0 ; b < 64*BMLEN ; b++) {
1747 if (IS_BIT_SET(b, channelBM)) {
1748 fband = &freqs[b];
1749
1750 /* zm_debug_msg1("CWY - lowChannel = ", fband->lowChannel);
1751 zm_debug_msg1("CWY - highChannel = ", fband->highChannel);
1752 zm_debug_msg1("CWY - channelSep = ", fband->channelSep); */
1753 for (c = fband->lowChannel; c <= fband->highChannel;
1754 c += fband->channelSep) {
1755 ZM_HAL_CHANNEL icv;
1756
1757 /* Disable all DFS channel */
1758 if ((hpPriv->disableDfsCh == 0) || (!(fband->useDfs & rd->dfsMask))) {
1759 if (fband->channelBW < 20) {
1760 /**************************************************************/
1761 /* */
1762 /* Temporary discard channel that BW < 20MHz (5 or 10MHz) */
1763 /* Our architecture does not implemnt it !!! */
1764 /* */
1765 /**************************************************************/
1766 continue;
1767 }
1768 if ((c >= c_lo) && (c <= c_hi)) {
1769 icv.channel = c;
1770 icv.channelFlags = cm->flags;
1771 icv.maxRegTxPower = fband->powerDfs;
1772 if (fband->usePassScan & rd->pscan)
1773 icv.channelFlags |= ZM_REG_FLAG_CHANNEL_PASSIVE;
1774 else
1775 icv.channelFlags &= ~ZM_REG_FLAG_CHANNEL_PASSIVE;
1776 if (fband->useDfs & rd->dfsMask)
1777 icv.privFlags = ZM_REG_FLAG_CHANNEL_DFS;
1778 else
1779 icv.privFlags = 0;
1780
1781 /* For now disable radar for FCC3 */
1782 if (fband->useDfs & rd->dfsMask & DFS_FCC3) {
1783 icv.privFlags &= ~ZM_REG_FLAG_CHANNEL_DFS;
1784 icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR;
1785 }
1786
1787 if (rd->flags & LIMIT_FRAME_4MS)
1788 icv.privFlags |= ZM_REG_FLAG_CHANNEL_DFS_CLEAR;
1789
1790 icv.minTxPower = 0;
1791 icv.maxTxPower = 0;
1792
1793 zm_assert(next < 60);
1794
1795 wd->regulationTable.allowChannel[next++] = icv;
1796 }
1797 }
1798 }
1799 }
1800 }
1801 }
1802 wd->regulationTable.allowChannelCnt = next;
1803
1804 #if 0
1805 {
1806 /* debug print */
1807 u32_t i;
1808 DbgPrint("\n-------------------------------------------\n");
1809 DbgPrint("zfHpGetRegulationTable print all channel info regincode = 0x%x\n", wd->regulationTable.regionCode);
1810 DbgPrint("index channel channelFlags maxRegTxPower privFlags useDFS\n");
1811
1812 for (i = 0 ; i < wd->regulationTable.allowChannelCnt ; i++) {
1813 DbgPrint("%02d %d %04x %02d %x %x\n", i,
1814 wd->regulationTable.allowChannel[i].channel,
1815 wd->regulationTable.allowChannel[i].channelFlags,
1816 wd->regulationTable.allowChannel[i].maxRegTxPower,
1817 wd->regulationTable.allowChannel[i].privFlags,
1818 wd->regulationTable.allowChannel[i].privFlags & ZM_REG_FLAG_CHANNEL_DFS);
1819 }
1820 }
1821 #endif
1822
1823 zmw_leave_critical_section(dev);
1824 }
1825
1826 void zfHpGetRegulationTablefromRegionCode(zdev_t *dev, u16_t regionCode)
1827 {
1828 u16_t c_lo = 2000, c_hi = 6000; /* default channel is all enable */
1829 u8_t isoName[3] = {'N', 'A', 0};
1830
1831 zfCoreSetIsoName(dev, isoName);
1832
1833 zfHpGetRegulationTable(dev, regionCode, c_lo, c_hi);
1834 }
1835
1836 void zfHpGetRegulationTablefromCountry(zdev_t *dev, u16_t CountryCode)
1837 {
1838 u16_t i;
1839 u16_t c_lo = 2000, c_hi = 6000; /* default channel is all enable */
1840 u16_t RegDomain;
1841
1842 zmw_get_wlan_dev(dev);
1843
1844 zmw_declare_for_critical_section();
1845
1846 for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
1847 if (CountryCode == allCountries[i].countryCode) {
1848 RegDomain = allCountries[i].regDmnEnum;
1849
1850 /* read the ACU country code from EEPROM */
1851 zfCoreSetIsoName(dev, (u8_t *)allCountries[i].isoName);
1852
1853 /* zm_debug_msg_s("CWY - Country Name = ", allCountries[i].name); */
1854
1855 if (wd->regulationTable.regionCode != RegDomain) {
1856 /* zm_debug_msg0("CWY - Change regulatory table"); */
1857 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi);
1858 }
1859 return;
1860 }
1861 }
1862 zm_debug_msg1("Invalid CountryCode = ", CountryCode);
1863 }
1864
1865 u8_t zfHpGetRegulationTablefromISO(zdev_t *dev, u8_t *countryInfo, u8_t length)
1866 {
1867 u16_t i;
1868 u16_t RegDomain;
1869 u16_t c_lo = 2000, c_hi = 6000; /* default channel is all enable */
1870 /* u8_t strLen = 2; */
1871
1872 zmw_get_wlan_dev(dev);
1873
1874 zmw_declare_for_critical_section();
1875
1876 if (countryInfo[4] != 0x20) {
1877 /* with (I)ndoor/(O)utdoor info
1878 strLen = 3; */
1879 }
1880 /* zm_debug_msg_s("Desired iso name = ", isoName); */
1881 for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
1882 /* zm_debug_msg_s("Current iso name = ", allCountries[i].isoName); */
1883 if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, (u8_t *)&countryInfo[2], length-1)) {
1884 /* DbgPrint("Set current iso name = %s\n", allCountries[i].isoName); */
1885 /* zm_debug_msg0("iso name hit!!"); */
1886
1887 RegDomain = allCountries[i].regDmnEnum;
1888
1889 if (wd->regulationTable.regionCode != RegDomain)
1890 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi);
1891 /*
1892 while (index < (countryInfo[1]+2)) {
1893 if (countryInfo[index] <= 14) {
1894 // calculate 2.4GHz low boundary channel frequency
1895 ch = countryInfo[index];
1896 if ( ch == 14 )
1897 c_lo = ZM_CH_G_14;
1898 else
1899 c_lo = ZM_CH_G_1 + (ch - 1) * 5;
1900 // calculate 2.4GHz high boundary channel frequency
1901 ch = countryInfo[index] + countryInfo[index + 1] - 1;
1902 if ( ch == 14 )
1903 c_hi = ZM_CH_G_14;
1904 else
1905 c_hi = ZM_CH_G_1 + (ch - 1) * 5;
1906 } else {
1907 // calculate 5GHz low boundary channel frequency
1908 ch = countryInfo[index];
1909 if ( (ch >= 184)&&(ch <= 196) )
1910 c_lo = 4000 + ch*5;
1911 else
1912 c_lo = 5000 + ch*5;
1913 // calculate 5GHz high boundary channel frequency
1914 ch = countryInfo[index] + countryInfo[index + 1] - 1;
1915 if ( (ch >= 184)&&(ch <= 196) )
1916 c_hi = 4000 + ch*5;
1917 else
1918 c_hi = 5000 + ch*5;
1919 }
1920
1921 zfHpGetRegulationTable(dev, RegDomain, c_lo, c_hi);
1922
1923 index+=3;
1924 }
1925 */
1926 return 0;
1927 }
1928 }
1929 /* zm_debug_msg_s("Invalid iso name = ", &countryInfo[2]); */
1930 return 1;
1931 }
1932
1933 const char *zfHpGetisoNamefromregionCode(zdev_t *dev, u16_t regionCode)
1934 {
1935 u16_t i;
1936
1937 for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
1938 if (allCountries[i].regDmnEnum == regionCode)
1939 return allCountries[i].isoName;
1940 }
1941 /* no matching item, return default */
1942 return allCountries[0].isoName;
1943 }
1944
1945 u16_t zfHpGetRegionCodeFromIsoName(zdev_t *dev, u8_t *countryIsoName)
1946 {
1947 u16_t i;
1948 u16_t regionCode;
1949
1950 /* if no matching item, return default */
1951 regionCode = DEF_REGDMN;
1952
1953 for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
1954 if (zfMemoryIsEqual((u8_t *)allCountries[i].isoName, countryIsoName, 2)) {
1955 regionCode = allCountries[i].regDmnEnum;
1956 break;
1957 }
1958 }
1959
1960 return regionCode;
1961 }
1962
1963 /************************************************************************/
1964 /* */
1965 /* FUNCTION DESCRIPTION zfHpDeleteAllowChannel */
1966 /* Delete Allow Channel. */
1967 /* */
1968 /* INPUTS */
1969 /* dev : device pointer */
1970 /* freq : frequency */
1971 /* */
1972 /* OUTPUTS */
1973 /* 0 : success */
1974 /* other : fail */
1975 /* */
1976 /* AUTHOR */
1977 /* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */
1978 /* */
1979 /************************************************************************/
1980 u16_t zfHpDeleteAllowChannel(zdev_t *dev, u16_t freq)
1981 {
1982 u16_t i, bandIndex = 0;
1983 u16_t dfs5GBand[][2] = { {5150, 5240}, {5260, 5350}, {5450, 5700}, {5725, 5825} };
1984
1985 zmw_get_wlan_dev(dev);
1986 /* Find which band does this frequency belong */
1987 for (i = 0; i < 4; i++) {
1988 if ((freq >= dfs5GBand[i][0]) && (freq <= dfs5GBand[i][1]))
1989 bandIndex = i + 1;
1990 }
1991
1992 if (bandIndex == 0) {
1993 /* 2.4G, don't care */
1994 return 0;
1995 } else
1996 bandIndex--;
1997 /* Set all channels in this band to passive scan */
1998 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) {
1999 if ((wd->regulationTable.allowChannel[i].channel >= dfs5GBand[bandIndex][0]) &&
2000 (wd->regulationTable.allowChannel[i].channel <= dfs5GBand[bandIndex][1])) {
2001 /* if channel is not passive, set it to be passive and mark it */
2002 if ((wd->regulationTable.allowChannel[i].channelFlags &
2003 ZM_REG_FLAG_CHANNEL_PASSIVE) == 0) {
2004 wd->regulationTable.allowChannel[i].channelFlags |=
2005 (ZM_REG_FLAG_CHANNEL_PASSIVE | ZM_REG_FLAG_CHANNEL_CSA);
2006 }
2007 }
2008 }
2009
2010 return 0;
2011 }
2012
2013 u16_t zfHpAddAllowChannel(zdev_t *dev, u16_t freq)
2014 {
2015 u16_t i, j, arrayIndex;
2016
2017 zmw_get_wlan_dev(dev);
2018
2019 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) {
2020 if (wd->regulationTable.allowChannel[i].channel == freq)
2021 break;
2022 }
2023
2024 if (i == wd->regulationTable.allowChannelCnt) {
2025 for (j = 0; j < wd->regulationTable.allowChannelCnt; j++) {
2026 if (wd->regulationTable.allowChannel[j].channel > freq)
2027 break;
2028 }
2029
2030 /* zm_debug_msg1("CWY - add frequency = ", freq);
2031 zm_debug_msg1("CWY - channel array index = ", j); */
2032
2033 arrayIndex = j;
2034
2035 if (arrayIndex < wd->regulationTable.allowChannelCnt) {
2036 for (j = wd->regulationTable.allowChannelCnt; j > arrayIndex; j--)
2037 wd->regulationTable.allowChannel[j] = wd->regulationTable.allowChannel[j - 1];
2038 }
2039 wd->regulationTable.allowChannel[arrayIndex].channel = freq;
2040
2041 wd->regulationTable.allowChannelCnt++;
2042 }
2043
2044 return 0;
2045 }
2046
2047 u16_t zfHpIsDfsChannelNCS(zdev_t *dev, u16_t freq)
2048 {
2049 u8_t flag = ZM_REG_FLAG_CHANNEL_DFS;
2050 u16_t i;
2051 zmw_get_wlan_dev(dev);
2052
2053 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) {
2054 /* DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel); */
2055 if (wd->regulationTable.allowChannel[i].channel == freq) {
2056 flag = wd->regulationTable.allowChannel[i].privFlags;
2057 break; }
2058 }
2059
2060 return flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR);
2061 }
2062
2063 u16_t zfHpIsDfsChannel(zdev_t *dev, u16_t freq)
2064 {
2065 u8_t flag = ZM_REG_FLAG_CHANNEL_DFS;
2066 u16_t i;
2067 zmw_get_wlan_dev(dev);
2068
2069 zmw_declare_for_critical_section();
2070
2071 zmw_enter_critical_section(dev);
2072
2073 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) {
2074 /* DbgPrint("DFS:freq=%d, chan=%d", freq, wd->regulationTable.allowChannel[i].channel); */
2075 if (wd->regulationTable.allowChannel[i].channel == freq) {
2076 flag = wd->regulationTable.allowChannel[i].privFlags;
2077 break;
2078 }
2079 }
2080
2081 zmw_leave_critical_section(dev);
2082
2083 return flag & (ZM_REG_FLAG_CHANNEL_DFS|ZM_REG_FLAG_CHANNEL_DFS_CLEAR);
2084 }
2085
2086 u16_t zfHpIsAllowedChannel(zdev_t *dev, u16_t freq)
2087 {
2088 u16_t i;
2089 zmw_get_wlan_dev(dev);
2090
2091 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) {
2092 if (wd->regulationTable.allowChannel[i].channel == freq)
2093 return 1;
2094 }
2095
2096 return 0;
2097 }
2098
2099 u16_t zfHpFindFirstNonDfsChannel(zdev_t *dev, u16_t aBand)
2100 {
2101 u16_t chan = 2412;
2102 u16_t i;
2103 zmw_get_wlan_dev(dev);
2104
2105 zmw_declare_for_critical_section();
2106
2107 zmw_enter_critical_section(dev);
2108
2109 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++) {
2110 if ((wd->regulationTable.allowChannel[i].privFlags & ZM_REG_FLAG_CHANNEL_DFS) != 0) {
2111 if (aBand) {
2112 if (wd->regulationTable.allowChannel[i].channel > 3000) {
2113 chan = wd->regulationTable.allowChannel[i].channel;
2114 break;
2115 }
2116 } else {
2117 if (wd->regulationTable.allowChannel[i].channel < 3000) {
2118 chan = wd->regulationTable.allowChannel[i].channel;
2119 break;
2120 }
2121 }
2122 }
2123 }
2124
2125 zmw_leave_critical_section(dev);
2126
2127 return chan;
2128 }
2129
2130
2131 /* porting from ACU */
2132 /* save RegulatoryDomain in hpriv */
2133 u8_t zfHpGetRegulatoryDomain(zdev_t *dev)
2134 {
2135 zmw_get_wlan_dev(dev);
2136
2137 switch (wd->regulationTable.regionCode) {
2138 case NO_ENUMRD:
2139 return 0;
2140 break;
2141 case FCC1_FCCA:
2142 case FCC1_WORLD:
2143 case FCC4_FCCA:
2144 case FCC5_FCCA:
2145 case FCC2_WORLD:
2146 case FCC2_ETSIC:
2147 case FCC3_FCCA:
2148 case FCC3_WORLD:
2149 case FCC1:
2150 case FCC2:
2151 case FCC3:
2152 case FCC4:
2153 case FCC5:
2154 case FCCA:
2155 return 0x10;/* WG_AMERICAS DOT11_REG_DOMAIN_FCC United States */
2156 break;
2157
2158 case FCC2_FCCA:
2159 return 0x20;/* DOT11_REG_DOMAIN_DOC Canada */
2160 break;
2161
2162 case ETSI1_WORLD:
2163 case ETSI3_ETSIA:
2164 case ETSI2_WORLD:
2165 case ETSI3_WORLD:
2166 case ETSI4_WORLD:
2167 case ETSI4_ETSIC:
2168 case ETSI5_WORLD:
2169 case ETSI6_WORLD:
2170 case ETSI_RESERVED:
2171 case ETSI1:
2172 case ETSI2:
2173 case ETSI3:
2174 case ETSI4:
2175 case ETSI5:
2176 case ETSI6:
2177 case ETSIA:
2178 case ETSIB:
2179 case ETSIC:
2180 return 0x30;/* WG_EMEA DOT11_REG_DOMAIN_ETSI Most of Europe */
2181 break;
2182
2183 case MKK1_MKKA:
2184 case MKK1_MKKB:
2185 case MKK2_MKKA:
2186 case MKK1_FCCA:
2187 case MKK1_MKKA1:
2188 case MKK1_MKKA2:
2189 case MKK1_MKKC:
2190 case MKK3_MKKB:
2191 case MKK3_MKKA2:
2192 case MKK3_MKKC:
2193 case MKK4_MKKB:
2194 case MKK4_MKKA2:
2195 case MKK4_MKKC:
2196 case MKK5_MKKB:
2197 case MKK5_MKKA2:
2198 case MKK5_MKKC:
2199 case MKK6_MKKB:
2200 case MKK6_MKKA2:
2201 case MKK6_MKKC:
2202 case MKK7_MKKB:
2203 case MKK7_MKKA:
2204 case MKK7_MKKC:
2205 case MKK8_MKKB:
2206 case MKK8_MKKA2:
2207 case MKK8_MKKC:
2208 case MKK6_MKKA1:
2209 case MKK6_FCCA:
2210 case MKK7_MKKA1:
2211 case MKK7_FCCA:
2212 case MKK9_FCCA:
2213 case MKK9_MKKA1:
2214 case MKK9_MKKC:
2215 case MKK9_MKKA2:
2216 case MKK10_FCCA:
2217 case MKK10_MKKA1:
2218 case MKK10_MKKC:
2219 case MKK10_MKKA2:
2220 case MKK11_MKKA:
2221 case MKK11_FCCA:
2222 case MKK11_MKKA1:
2223 case MKK11_MKKC:
2224 case MKK11_MKKA2:
2225 case MKK12_MKKA:
2226 case MKK12_FCCA:
2227 case MKK12_MKKA1:
2228 case MKK12_MKKC:
2229 case MKK12_MKKA2:
2230 case MKK3_MKKA:
2231 case MKK3_MKKA1:
2232 case MKK3_FCCA:
2233 case MKK4_MKKA:
2234 case MKK4_MKKA1:
2235 case MKK4_FCCA:
2236 case MKK9_MKKA:
2237 case MKK10_MKKA:
2238 case MKK1:
2239 case MKK2:
2240 case MKK3:
2241 case MKK4:
2242 case MKK5:
2243 case MKK6:
2244 case MKK7:
2245 case MKK8:
2246 case MKK9:
2247 case MKK10:
2248 case MKK11:
2249 case MKK12:
2250 case MKKA:
2251 case MKKC:
2252 return 0x40;/* WG_JAPAN DOT11_REG_DOMAIN_MKK Japan */
2253 break;
2254
2255 default:
2256 break;
2257 }
2258
2259 return 0xFF; /* Didn't input RegDmn by mean to distinguish by customer */
2260 }
2261
2262 void zfHpDisableDfsChannel(zdev_t *dev, u8_t disableFlag)
2263 {
2264 struct zsHpPriv *hpPriv;
2265
2266 zmw_get_wlan_dev(dev);
2267 hpPriv = wd->hpPrivate;
2268 hpPriv->disableDfsCh = disableFlag;
2269 return;
2270 }
x86 "subsystem" repository