arch/x86/include/asm/pgtable-3level.h

   1 #ifndef _ASM_X86_PGTABLE_3LEVEL_H
   2 #define _ASM_X86_PGTABLE_3LEVEL_H
   3
   4 /*
   5  * Intel Physical Address Extension (PAE) Mode - three-level page
   6  * tables on PPro+ CPUs.
   7  *
   8  * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
   9  */
  10
  11 #define pte_ERROR(e)                                                    \
  12         printk("%s:%d: bad pte %p(%08lx%08lx).\n",                      \
  13                __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
  14 #define pmd_ERROR(e)                                                    \
  15         printk("%s:%d: bad pmd %p(%016Lx).\n",                          \
  16                __FILE__, __LINE__, &(e), pmd_val(e))
  17 #define pgd_ERROR(e)                                                    \
  18         printk("%s:%d: bad pgd %p(%016Lx).\n",                          \
  19                __FILE__, __LINE__, &(e), pgd_val(e))
  20
  21 static inline int pud_none(pud_t pud)
  22 {
  23         return pud_val(pud) == 0;
  24 }
  25
  26 static inline int pud_bad(pud_t pud)
  27 {
  28         return (pud_val(pud) & ~(PTE_PFN_MASK | _KERNPG_TABLE | _PAGE_USER)) != 0;
  29 }
  30
  31 /* Rules for using set_pte: the pte being assigned *must* be
  32  * either not present or in a state where the hardware will
  33  * not attempt to update the pte.  In places where this is
  34  * not possible, use pte_get_and_clear to obtain the old pte
  35  * value and then use set_pte to update it.  -ben
  36  */
  37 static inline void native_set_pte(pte_t *ptep, pte_t pte)
  38 {
  39         ptep->pte_high = pte.pte_high;
  40         smp_wmb();
  41         ptep->pte_low = pte.pte_low;
  42 }
  43
  44 /*
  45  * Since this is only called on user PTEs, and the page fault handler
  46  * must handle the already racy situation of simultaneous page faults,
  47  * we are justified in merely clearing the PTE present bit, followed
  48  * by a set.  The ordering here is important.
  49  */
  50 static inline void native_set_pte_present(struct mm_struct *mm,
  51                                           unsigned long addr,
  52                                           pte_t *ptep, pte_t pte)
  53 {
  54         ptep->pte_low = 0;
  55         smp_wmb();
  56         ptep->pte_high = pte.pte_high;
  57         smp_wmb();
  58         ptep->pte_low = pte.pte_low;
  59 }
  60
  61 static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
  62 {
  63         set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
  64 }
  65
  66 static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
  67 {
  68         set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
  69 }
  70
  71 static inline void native_set_pud(pud_t *pudp, pud_t pud)
  72 {
  73         set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
  74 }
  75
  76 /*
  77  * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
  78  * entry, so clear the bottom half first and enforce ordering with a compiler
  79  * barrier.
  80  */
  81 static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
  82                                     pte_t *ptep)
  83 {
  84         ptep->pte_low = 0;
  85         smp_wmb();
  86         ptep->pte_high = 0;
  87 }
  88
  89 static inline void native_pmd_clear(pmd_t *pmd)
  90 {
  91         u32 *tmp = (u32 *)pmd;
  92         *tmp = 0;
  93         smp_wmb();
  94         *(tmp + 1) = 0;
  95 }
  96
  97 static inline void pud_clear(pud_t *pudp)
  98 {
  99         unsigned long pgd;
 100
 101         set_pud(pudp, __pud(0));
 102
 103         /*
 104          * According to Intel App note "TLBs, Paging-Structure Caches,
 105          * and Their Invalidation", April 2007, document 317080-001,
 106          * section 8.1: in PAE mode we explicitly have to flush the
 107          * TLB via cr3 if the top-level pgd is changed...
 108          *
 109          * Make sure the pud entry we're updating is within the
 110          * current pgd to avoid unnecessary TLB flushes.
 111          */
 112         pgd = read_cr3();
 113         if (__pa(pudp) >= pgd && __pa(pudp) <
 114             (pgd + sizeof(pgd_t)*PTRS_PER_PGD))
 115                 write_cr3(pgd);
 116 }
 117
 118 /* Find an entry in the second-level page table.. */
 119 #define pmd_offset(pud, address) ((pmd_t *)pud_page_vaddr(*(pud)) +     \
 120                                   pmd_index(address))
 121
 122 #ifdef CONFIG_SMP
 123 static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
 124 {
 125         pte_t res;
 126
 127         /* xchg acts as a barrier before the setting of the high bits */
 128         res.pte_low = xchg(&ptep->pte_low, 0);
 129         res.pte_high = ptep->pte_high;
 130         ptep->pte_high = 0;
 131
 132         return res;
 133 }
 134 #else
 135 #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
 136 #endif
 137
 138 /*
 139  * Bits 0, 6 and 7 are taken in the low part of the pte,
 140  * put the 32 bits of offset into the high part.
 141  */
 142 #define pte_to_pgoff(pte) ((pte).pte_high)
 143 #define pgoff_to_pte(off)                                               \
 144         ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
 145 #define PTE_FILE_MAX_BITS       32
 146
 147 /* Encode and de-code a swap entry */
 148 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
 149 #define __swp_type(x)                   (((x).val) & 0x1f)
 150 #define __swp_offset(x)                 ((x).val >> 5)
 151 #define __swp_entry(type, offset)       ((swp_entry_t){(type) | (offset) << 5})
 152 #define __pte_to_swp_entry(pte)         ((swp_entry_t){ (pte).pte_high })
 153 #define __swp_entry_to_pte(x)           ((pte_t){ { .pte_high = (x).val } })
 154
 155 #endif /* _ASM_X86_PGTABLE_3LEVEL_H */