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[PATCH] OHCI PM updates
[linux-2.6/x86.git] / drivers / scsi / sata_mv.c
blob422e0b6f603ac5b8960073def04a2757f8ed79e8
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 *
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/blkdev.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/dma-mapping.h>
32 #include "scsi.h"
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
35 #include <asm/io.h>
36
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.25"
39
40 enum {
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
45
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
48
49 MV_PCI_REG_BASE = 0,
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_SATAHC0_REG_BASE = 0x20000,
52
53 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
54 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
55 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
56 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
57
58 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
59
60 MV_MAX_Q_DEPTH = 32,
61 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
62
63 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
64 * CRPB needs alignment on a 256B boundary. Size == 256B
65 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
66 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
67 */
68 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
69 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
70 MV_MAX_SG_CT = 176,
71 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
72 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
73
74 /* Our DMA boundary is determined by an ePRD being unable to handle
75 * anything larger than 64KB
76 */
77 MV_DMA_BOUNDARY = 0xffffU,
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */
89 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
90 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
91 MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE |
92 MV_FLAG_GLBL_SFT_RST),
93
94 chip_504x = 0,
95 chip_508x = 1,
96 chip_604x = 2,
97 chip_608x = 3,
98
99 CRQB_FLAG_READ = (1 << 0),
100 CRQB_TAG_SHIFT = 1,
101 CRQB_CMD_ADDR_SHIFT = 8,
102 CRQB_CMD_CS = (0x2 << 11),
103 CRQB_CMD_LAST = (1 << 15),
104
105 CRPB_FLAG_STATUS_SHIFT = 8,
106
107 EPRD_FLAG_END_OF_TBL = (1 << 31),
108
109 /* PCI interface registers */
110
111 PCI_COMMAND_OFS = 0xc00,
112
113 PCI_MAIN_CMD_STS_OFS = 0xd30,
114 STOP_PCI_MASTER = (1 << 2),
115 PCI_MASTER_EMPTY = (1 << 3),
116 GLOB_SFT_RST = (1 << 4),
117
118 PCI_IRQ_CAUSE_OFS = 0x1d58,
119 PCI_IRQ_MASK_OFS = 0x1d5c,
120 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
121
122 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
123 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
124 PORT0_ERR = (1 << 0), /* shift by port # */
125 PORT0_DONE = (1 << 1), /* shift by port # */
126 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
127 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
128 PCI_ERR = (1 << 18),
129 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
130 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
131 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
132 GPIO_INT = (1 << 22),
133 SELF_INT = (1 << 23),
134 TWSI_INT = (1 << 24),
135 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
136 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
137 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
138 HC_MAIN_RSVD),
139
140 /* SATAHC registers */
141 HC_CFG_OFS = 0,
142
143 HC_IRQ_CAUSE_OFS = 0x14,
144 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
145 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
146 DEV_IRQ = (1 << 8), /* shift by port # */
147
148 /* Shadow block registers */
149 SHD_BLK_OFS = 0x100,
150 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
151
152 /* SATA registers */
153 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
154 SATA_ACTIVE_OFS = 0x350,
155
156 /* Port registers */
157 EDMA_CFG_OFS = 0,
158 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
159 EDMA_CFG_NCQ = (1 << 5),
160 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
161 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
162 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
163
164 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
165 EDMA_ERR_IRQ_MASK_OFS = 0xc,
166 EDMA_ERR_D_PAR = (1 << 0),
167 EDMA_ERR_PRD_PAR = (1 << 1),
168 EDMA_ERR_DEV = (1 << 2),
169 EDMA_ERR_DEV_DCON = (1 << 3),
170 EDMA_ERR_DEV_CON = (1 << 4),
171 EDMA_ERR_SERR = (1 << 5),
172 EDMA_ERR_SELF_DIS = (1 << 7),
173 EDMA_ERR_BIST_ASYNC = (1 << 8),
174 EDMA_ERR_CRBQ_PAR = (1 << 9),
175 EDMA_ERR_CRPB_PAR = (1 << 10),
176 EDMA_ERR_INTRL_PAR = (1 << 11),
177 EDMA_ERR_IORDY = (1 << 12),
178 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
179 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
180 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
181 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
182 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
183 EDMA_ERR_TRANS_PROTO = (1 << 31),
184 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
185 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
186 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
187 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
188 EDMA_ERR_LNK_DATA_RX |
189 EDMA_ERR_LNK_DATA_TX |
190 EDMA_ERR_TRANS_PROTO),
191
192 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
193 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
194 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
195
196 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
197 EDMA_REQ_Q_PTR_SHIFT = 5,
198
199 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
200 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
201 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
202 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
203 EDMA_RSP_Q_PTR_SHIFT = 3,
204
205 EDMA_CMD_OFS = 0x28,
206 EDMA_EN = (1 << 0),
207 EDMA_DS = (1 << 1),
208 ATA_RST = (1 << 2),
209
210 /* Host private flags (hp_flags) */
211 MV_HP_FLAG_MSI = (1 << 0),
212
213 /* Port private flags (pp_flags) */
214 MV_PP_FLAG_EDMA_EN = (1 << 0),
215 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
216 };
217
218 /* Command ReQuest Block: 32B */
219 struct mv_crqb {
220 u32 sg_addr;
221 u32 sg_addr_hi;
222 u16 ctrl_flags;
223 u16 ata_cmd[11];
224 };
225
226 /* Command ResPonse Block: 8B */
227 struct mv_crpb {
228 u16 id;
229 u16 flags;
230 u32 tmstmp;
231 };
232
233 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
234 struct mv_sg {
235 u32 addr;
236 u32 flags_size;
237 u32 addr_hi;
238 u32 reserved;
239 };
240
241 struct mv_port_priv {
242 struct mv_crqb *crqb;
243 dma_addr_t crqb_dma;
244 struct mv_crpb *crpb;
245 dma_addr_t crpb_dma;
246 struct mv_sg *sg_tbl;
247 dma_addr_t sg_tbl_dma;
248
249 unsigned req_producer; /* cp of req_in_ptr */
250 unsigned rsp_consumer; /* cp of rsp_out_ptr */
251 u32 pp_flags;
252 };
253
254 struct mv_host_priv {
255 u32 hp_flags;
256 };
257
258 static void mv_irq_clear(struct ata_port *ap);
259 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
260 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
261 static u8 mv_check_err(struct ata_port *ap);
262 static void mv_phy_reset(struct ata_port *ap);
263 static void mv_host_stop(struct ata_host_set *host_set);
264 static int mv_port_start(struct ata_port *ap);
265 static void mv_port_stop(struct ata_port *ap);
266 static void mv_qc_prep(struct ata_queued_cmd *qc);
267 static int mv_qc_issue(struct ata_queued_cmd *qc);
268 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
269 struct pt_regs *regs);
270 static void mv_eng_timeout(struct ata_port *ap);
271 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
272
273 static Scsi_Host_Template mv_sht = {
274 .module = THIS_MODULE,
275 .name = DRV_NAME,
276 .ioctl = ata_scsi_ioctl,
277 .queuecommand = ata_scsi_queuecmd,
278 .eh_strategy_handler = ata_scsi_error,
279 .can_queue = MV_USE_Q_DEPTH,
280 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = MV_MAX_SG_CT,
282 .max_sectors = ATA_MAX_SECTORS,
283 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
284 .emulated = ATA_SHT_EMULATED,
285 .use_clustering = ATA_SHT_USE_CLUSTERING,
286 .proc_name = DRV_NAME,
287 .dma_boundary = MV_DMA_BOUNDARY,
288 .slave_configure = ata_scsi_slave_config,
289 .bios_param = ata_std_bios_param,
290 .ordered_flush = 1,
291 };
292
293 static const struct ata_port_operations mv_ops = {
294 .port_disable = ata_port_disable,
295
296 .tf_load = ata_tf_load,
297 .tf_read = ata_tf_read,
298 .check_status = ata_check_status,
299 .check_err = mv_check_err,
300 .exec_command = ata_exec_command,
301 .dev_select = ata_std_dev_select,
302
303 .phy_reset = mv_phy_reset,
304
305 .qc_prep = mv_qc_prep,
306 .qc_issue = mv_qc_issue,
307
308 .eng_timeout = mv_eng_timeout,
309
310 .irq_handler = mv_interrupt,
311 .irq_clear = mv_irq_clear,
312
313 .scr_read = mv_scr_read,
314 .scr_write = mv_scr_write,
315
316 .port_start = mv_port_start,
317 .port_stop = mv_port_stop,
318 .host_stop = mv_host_stop,
319 };
320
321 static struct ata_port_info mv_port_info[] = {
322 { /* chip_504x */
323 .sht = &mv_sht,
324 .host_flags = MV_COMMON_FLAGS,
325 .pio_mask = 0x1f, /* pio0-4 */
326 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
327 .port_ops = &mv_ops,
328 },
329 { /* chip_508x */
330 .sht = &mv_sht,
331 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
332 .pio_mask = 0x1f, /* pio0-4 */
333 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
334 .port_ops = &mv_ops,
335 },
336 { /* chip_604x */
337 .sht = &mv_sht,
338 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = 0x7f, /* udma0-6 */
341 .port_ops = &mv_ops,
342 },
343 { /* chip_608x */
344 .sht = &mv_sht,
345 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
346 MV_FLAG_DUAL_HC),
347 .pio_mask = 0x1f, /* pio0-4 */
348 .udma_mask = 0x7f, /* udma0-6 */
349 .port_ops = &mv_ops,
350 },
351 };
352
353 static struct pci_device_id mv_pci_tbl[] = {
354 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
355 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
356 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x},
357 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
358
359 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
360 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
361 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
362 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
363 {} /* terminate list */
364 };
365
366 static struct pci_driver mv_pci_driver = {
367 .name = DRV_NAME,
368 .id_table = mv_pci_tbl,
369 .probe = mv_init_one,
370 .remove = ata_pci_remove_one,
371 };
372
373 /*
374 * Functions
375 */
376
377 static inline void writelfl(unsigned long data, void __iomem *addr)
378 {
379 writel(data, addr);
380 (void) readl(addr); /* flush to avoid PCI posted write */
381 }
382
383 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
384 {
385 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
386 }
387
388 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
389 {
390 return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) +
391 MV_SATAHC_ARBTR_REG_SZ +
392 ((port & MV_PORT_MASK) * MV_PORT_REG_SZ));
393 }
394
395 static inline void __iomem *mv_ap_base(struct ata_port *ap)
396 {
397 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
398 }
399
400 static inline int mv_get_hc_count(unsigned long hp_flags)
401 {
402 return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
403 }
404
405 static void mv_irq_clear(struct ata_port *ap)
406 {
407 }
408
409 /**
410 * mv_start_dma - Enable eDMA engine
411 * @base: port base address
412 * @pp: port private data
413 *
414 * Verify the local cache of the eDMA state is accurate with an
415 * assert.
416 *
417 * LOCKING:
418 * Inherited from caller.
419 */
420 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
421 {
422 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
423 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
424 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
425 }
426 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
427 }
428
429 /**
430 * mv_stop_dma - Disable eDMA engine
431 * @ap: ATA channel to manipulate
432 *
433 * Verify the local cache of the eDMA state is accurate with an
434 * assert.
435 *
436 * LOCKING:
437 * Inherited from caller.
438 */
439 static void mv_stop_dma(struct ata_port *ap)
440 {
441 void __iomem *port_mmio = mv_ap_base(ap);
442 struct mv_port_priv *pp = ap->private_data;
443 u32 reg;
444 int i;
445
446 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
447 /* Disable EDMA if active. The disable bit auto clears.
448 */
449 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
450 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
451 } else {
452 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
453 }
454
455 /* now properly wait for the eDMA to stop */
456 for (i = 1000; i > 0; i--) {
457 reg = readl(port_mmio + EDMA_CMD_OFS);
458 if (!(EDMA_EN & reg)) {
459 break;
460 }
461 udelay(100);
462 }
463
464 if (EDMA_EN & reg) {
465 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
466 /* FIXME: Consider doing a reset here to recover */
467 }
468 }
469
470 #ifdef ATA_DEBUG
471 static void mv_dump_mem(void __iomem *start, unsigned bytes)
472 {
473 int b, w;
474 for (b = 0; b < bytes; ) {
475 DPRINTK("%p: ", start + b);
476 for (w = 0; b < bytes && w < 4; w++) {
477 printk("%08x ",readl(start + b));
478 b += sizeof(u32);
479 }
480 printk("\n");
481 }
482 }
483 #endif
484
485 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
486 {
487 #ifdef ATA_DEBUG
488 int b, w;
489 u32 dw;
490 for (b = 0; b < bytes; ) {
491 DPRINTK("%02x: ", b);
492 for (w = 0; b < bytes && w < 4; w++) {
493 (void) pci_read_config_dword(pdev,b,&dw);
494 printk("%08x ",dw);
495 b += sizeof(u32);
496 }
497 printk("\n");
498 }
499 #endif
500 }
501 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
502 struct pci_dev *pdev)
503 {
504 #ifdef ATA_DEBUG
505 void __iomem *hc_base = mv_hc_base(mmio_base,
506 port >> MV_PORT_HC_SHIFT);
507 void __iomem *port_base;
508 int start_port, num_ports, p, start_hc, num_hcs, hc;
509
510 if (0 > port) {
511 start_hc = start_port = 0;
512 num_ports = 8; /* shld be benign for 4 port devs */
513 num_hcs = 2;
514 } else {
515 start_hc = port >> MV_PORT_HC_SHIFT;
516 start_port = port;
517 num_ports = num_hcs = 1;
518 }
519 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
520 num_ports > 1 ? num_ports - 1 : start_port);
521
522 if (NULL != pdev) {
523 DPRINTK("PCI config space regs:\n");
524 mv_dump_pci_cfg(pdev, 0x68);
525 }
526 DPRINTK("PCI regs:\n");
527 mv_dump_mem(mmio_base+0xc00, 0x3c);
528 mv_dump_mem(mmio_base+0xd00, 0x34);
529 mv_dump_mem(mmio_base+0xf00, 0x4);
530 mv_dump_mem(mmio_base+0x1d00, 0x6c);
531 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
532 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
533 DPRINTK("HC regs (HC %i):\n", hc);
534 mv_dump_mem(hc_base, 0x1c);
535 }
536 for (p = start_port; p < start_port + num_ports; p++) {
537 port_base = mv_port_base(mmio_base, p);
538 DPRINTK("EDMA regs (port %i):\n",p);
539 mv_dump_mem(port_base, 0x54);
540 DPRINTK("SATA regs (port %i):\n",p);
541 mv_dump_mem(port_base+0x300, 0x60);
542 }
543 #endif
544 }
545
546 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
547 {
548 unsigned int ofs;
549
550 switch (sc_reg_in) {
551 case SCR_STATUS:
552 case SCR_CONTROL:
553 case SCR_ERROR:
554 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
555 break;
556 case SCR_ACTIVE:
557 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
558 break;
559 default:
560 ofs = 0xffffffffU;
561 break;
562 }
563 return ofs;
564 }
565
566 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
567 {
568 unsigned int ofs = mv_scr_offset(sc_reg_in);
569
570 if (0xffffffffU != ofs) {
571 return readl(mv_ap_base(ap) + ofs);
572 } else {
573 return (u32) ofs;
574 }
575 }
576
577 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
578 {
579 unsigned int ofs = mv_scr_offset(sc_reg_in);
580
581 if (0xffffffffU != ofs) {
582 writelfl(val, mv_ap_base(ap) + ofs);
583 }
584 }
585
586 /**
587 * mv_global_soft_reset - Perform the 6xxx global soft reset
588 * @mmio_base: base address of the HBA
589 *
590 * This routine only applies to 6xxx parts.
591 *
592 * LOCKING:
593 * Inherited from caller.
594 */
595 static int mv_global_soft_reset(void __iomem *mmio_base)
596 {
597 void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
598 int i, rc = 0;
599 u32 t;
600
601 /* Following procedure defined in PCI "main command and status
602 * register" table.
603 */
604 t = readl(reg);
605 writel(t | STOP_PCI_MASTER, reg);
606
607 for (i = 0; i < 1000; i++) {
608 udelay(1);
609 t = readl(reg);
610 if (PCI_MASTER_EMPTY & t) {
611 break;
612 }
613 }
614 if (!(PCI_MASTER_EMPTY & t)) {
615 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
616 rc = 1;
617 goto done;
618 }
619
620 /* set reset */
621 i = 5;
622 do {
623 writel(t | GLOB_SFT_RST, reg);
624 t = readl(reg);
625 udelay(1);
626 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
627
628 if (!(GLOB_SFT_RST & t)) {
629 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
630 rc = 1;
631 goto done;
632 }
633
634 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
635 i = 5;
636 do {
637 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
638 t = readl(reg);
639 udelay(1);
640 } while ((GLOB_SFT_RST & t) && (i-- > 0));
641
642 if (GLOB_SFT_RST & t) {
643 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
644 rc = 1;
645 }
646 done:
647 return rc;
648 }
649
650 /**
651 * mv_host_stop - Host specific cleanup/stop routine.
652 * @host_set: host data structure
653 *
654 * Disable ints, cleanup host memory, call general purpose
655 * host_stop.
656 *
657 * LOCKING:
658 * Inherited from caller.
659 */
660 static void mv_host_stop(struct ata_host_set *host_set)
661 {
662 struct mv_host_priv *hpriv = host_set->private_data;
663 struct pci_dev *pdev = to_pci_dev(host_set->dev);
664
665 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
666 pci_disable_msi(pdev);
667 } else {
668 pci_intx(pdev, 0);
669 }
670 kfree(hpriv);
671 ata_host_stop(host_set);
672 }
673
674 /**
675 * mv_port_start - Port specific init/start routine.
676 * @ap: ATA channel to manipulate
677 *
678 * Allocate and point to DMA memory, init port private memory,
679 * zero indices.
680 *
681 * LOCKING:
682 * Inherited from caller.
683 */
684 static int mv_port_start(struct ata_port *ap)
685 {
686 struct device *dev = ap->host_set->dev;
687 struct mv_port_priv *pp;
688 void __iomem *port_mmio = mv_ap_base(ap);
689 void *mem;
690 dma_addr_t mem_dma;
691
692 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
693 if (!pp) {
694 return -ENOMEM;
695 }
696 memset(pp, 0, sizeof(*pp));
697
698 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
699 GFP_KERNEL);
700 if (!mem) {
701 kfree(pp);
702 return -ENOMEM;
703 }
704 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
705
706 /* First item in chunk of DMA memory:
707 * 32-slot command request table (CRQB), 32 bytes each in size
708 */
709 pp->crqb = mem;
710 pp->crqb_dma = mem_dma;
711 mem += MV_CRQB_Q_SZ;
712 mem_dma += MV_CRQB_Q_SZ;
713
714 /* Second item:
715 * 32-slot command response table (CRPB), 8 bytes each in size
716 */
717 pp->crpb = mem;
718 pp->crpb_dma = mem_dma;
719 mem += MV_CRPB_Q_SZ;
720 mem_dma += MV_CRPB_Q_SZ;
721
722 /* Third item:
723 * Table of scatter-gather descriptors (ePRD), 16 bytes each
724 */
725 pp->sg_tbl = mem;
726 pp->sg_tbl_dma = mem_dma;
727
728 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
729 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
730
731 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
732 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
733 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
734
735 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
736 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
737
738 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
739 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
740 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
741
742 pp->req_producer = pp->rsp_consumer = 0;
743
744 /* Don't turn on EDMA here...do it before DMA commands only. Else
745 * we'll be unable to send non-data, PIO, etc due to restricted access
746 * to shadow regs.
747 */
748 ap->private_data = pp;
749 return 0;
750 }
751
752 /**
753 * mv_port_stop - Port specific cleanup/stop routine.
754 * @ap: ATA channel to manipulate
755 *
756 * Stop DMA, cleanup port memory.
757 *
758 * LOCKING:
759 * This routine uses the host_set lock to protect the DMA stop.
760 */
761 static void mv_port_stop(struct ata_port *ap)
762 {
763 struct device *dev = ap->host_set->dev;
764 struct mv_port_priv *pp = ap->private_data;
765 unsigned long flags;
766
767 spin_lock_irqsave(&ap->host_set->lock, flags);
768 mv_stop_dma(ap);
769 spin_unlock_irqrestore(&ap->host_set->lock, flags);
770
771 ap->private_data = NULL;
772 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
773 kfree(pp);
774 }
775
776 /**
777 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
778 * @qc: queued command whose SG list to source from
779 *
780 * Populate the SG list and mark the last entry.
781 *
782 * LOCKING:
783 * Inherited from caller.
784 */
785 static void mv_fill_sg(struct ata_queued_cmd *qc)
786 {
787 struct mv_port_priv *pp = qc->ap->private_data;
788 unsigned int i;
789
790 for (i = 0; i < qc->n_elem; i++) {
791 u32 sg_len;
792 dma_addr_t addr;
793
794 addr = sg_dma_address(&qc->sg[i]);
795 sg_len = sg_dma_len(&qc->sg[i]);
796
797 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
798 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
799 assert(0 == (sg_len & ~MV_DMA_BOUNDARY));
800 pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len);
801 }
802 if (0 < qc->n_elem) {
803 pp->sg_tbl[qc->n_elem - 1].flags_size |=
804 cpu_to_le32(EPRD_FLAG_END_OF_TBL);
805 }
806 }
807
808 static inline unsigned mv_inc_q_index(unsigned *index)
809 {
810 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
811 return *index;
812 }
813
814 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
815 {
816 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
817 (last ? CRQB_CMD_LAST : 0);
818 }
819
820 /**
821 * mv_qc_prep - Host specific command preparation.
822 * @qc: queued command to prepare
823 *
824 * This routine simply redirects to the general purpose routine
825 * if command is not DMA. Else, it handles prep of the CRQB
826 * (command request block), does some sanity checking, and calls
827 * the SG load routine.
828 *
829 * LOCKING:
830 * Inherited from caller.
831 */
832 static void mv_qc_prep(struct ata_queued_cmd *qc)
833 {
834 struct ata_port *ap = qc->ap;
835 struct mv_port_priv *pp = ap->private_data;
836 u16 *cw;
837 struct ata_taskfile *tf;
838 u16 flags = 0;
839
840 if (ATA_PROT_DMA != qc->tf.protocol) {
841 return;
842 }
843
844 /* the req producer index should be the same as we remember it */
845 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
846 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
847 pp->req_producer);
848
849 /* Fill in command request block
850 */
851 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
852 flags |= CRQB_FLAG_READ;
853 }
854 assert(MV_MAX_Q_DEPTH > qc->tag);
855 flags |= qc->tag << CRQB_TAG_SHIFT;
856
857 pp->crqb[pp->req_producer].sg_addr =
858 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
859 pp->crqb[pp->req_producer].sg_addr_hi =
860 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
861 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
862
863 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
864 tf = &qc->tf;
865
866 /* Sadly, the CRQB cannot accomodate all registers--there are
867 * only 11 bytes...so we must pick and choose required
868 * registers based on the command. So, we drop feature and
869 * hob_feature for [RW] DMA commands, but they are needed for
870 * NCQ. NCQ will drop hob_nsect.
871 */
872 switch (tf->command) {
873 case ATA_CMD_READ:
874 case ATA_CMD_READ_EXT:
875 case ATA_CMD_WRITE:
876 case ATA_CMD_WRITE_EXT:
877 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
878 break;
879 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
880 case ATA_CMD_FPDMA_READ:
881 case ATA_CMD_FPDMA_WRITE:
882 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
883 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
884 break;
885 #endif /* FIXME: remove this line when NCQ added */
886 default:
887 /* The only other commands EDMA supports in non-queued and
888 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
889 * of which are defined/used by Linux. If we get here, this
890 * driver needs work.
891 *
892 * FIXME: modify libata to give qc_prep a return value and
893 * return error here.
894 */
895 BUG_ON(tf->command);
896 break;
897 }
898 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
899 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
900 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
901 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
902 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
903 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
904 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
905 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
906 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
907
908 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
909 return;
910 }
911 mv_fill_sg(qc);
912 }
913
914 /**
915 * mv_qc_issue - Initiate a command to the host
916 * @qc: queued command to start
917 *
918 * This routine simply redirects to the general purpose routine
919 * if command is not DMA. Else, it sanity checks our local
920 * caches of the request producer/consumer indices then enables
921 * DMA and bumps the request producer index.
922 *
923 * LOCKING:
924 * Inherited from caller.
925 */
926 static int mv_qc_issue(struct ata_queued_cmd *qc)
927 {
928 void __iomem *port_mmio = mv_ap_base(qc->ap);
929 struct mv_port_priv *pp = qc->ap->private_data;
930 u32 in_ptr;
931
932 if (ATA_PROT_DMA != qc->tf.protocol) {
933 /* We're about to send a non-EDMA capable command to the
934 * port. Turn off EDMA so there won't be problems accessing
935 * shadow block, etc registers.
936 */
937 mv_stop_dma(qc->ap);
938 return ata_qc_issue_prot(qc);
939 }
940
941 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
942
943 /* the req producer index should be the same as we remember it */
944 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
945 pp->req_producer);
946 /* until we do queuing, the queue should be empty at this point */
947 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
948 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
949 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
950
951 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
952
953 mv_start_dma(port_mmio, pp);
954
955 /* and write the request in pointer to kick the EDMA to life */
956 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
957 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
958 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
959
960 return 0;
961 }
962
963 /**
964 * mv_get_crpb_status - get status from most recently completed cmd
965 * @ap: ATA channel to manipulate
966 *
967 * This routine is for use when the port is in DMA mode, when it
968 * will be using the CRPB (command response block) method of
969 * returning command completion information. We assert indices
970 * are good, grab status, and bump the response consumer index to
971 * prove that we're up to date.
972 *
973 * LOCKING:
974 * Inherited from caller.
975 */
976 static u8 mv_get_crpb_status(struct ata_port *ap)
977 {
978 void __iomem *port_mmio = mv_ap_base(ap);
979 struct mv_port_priv *pp = ap->private_data;
980 u32 out_ptr;
981
982 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
983
984 /* the response consumer index should be the same as we remember it */
985 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
986 pp->rsp_consumer);
987
988 /* increment our consumer index... */
989 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
990
991 /* and, until we do NCQ, there should only be 1 CRPB waiting */
992 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
993 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
994 pp->rsp_consumer);
995
996 /* write out our inc'd consumer index so EDMA knows we're caught up */
997 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
998 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
999 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1000
1001 /* Return ATA status register for completed CRPB */
1002 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1003 }
1004
1005 /**
1006 * mv_err_intr - Handle error interrupts on the port
1007 * @ap: ATA channel to manipulate
1008 *
1009 * In most cases, just clear the interrupt and move on. However,
1010 * some cases require an eDMA reset, which is done right before
1011 * the COMRESET in mv_phy_reset(). The SERR case requires a
1012 * clear of pending errors in the SATA SERROR register. Finally,
1013 * if the port disabled DMA, update our cached copy to match.
1014 *
1015 * LOCKING:
1016 * Inherited from caller.
1017 */
1018 static void mv_err_intr(struct ata_port *ap)
1019 {
1020 void __iomem *port_mmio = mv_ap_base(ap);
1021 u32 edma_err_cause, serr = 0;
1022
1023 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1024
1025 if (EDMA_ERR_SERR & edma_err_cause) {
1026 serr = scr_read(ap, SCR_ERROR);
1027 scr_write_flush(ap, SCR_ERROR, serr);
1028 }
1029 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1030 struct mv_port_priv *pp = ap->private_data;
1031 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1032 }
1033 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1034 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1035
1036 /* Clear EDMA now that SERR cleanup done */
1037 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1038
1039 /* check for fatal here and recover if needed */
1040 if (EDMA_ERR_FATAL & edma_err_cause) {
1041 mv_phy_reset(ap);
1042 }
1043 }
1044
1045 /**
1046 * mv_host_intr - Handle all interrupts on the given host controller
1047 * @host_set: host specific structure
1048 * @relevant: port error bits relevant to this host controller
1049 * @hc: which host controller we're to look at
1050 *
1051 * Read then write clear the HC interrupt status then walk each
1052 * port connected to the HC and see if it needs servicing. Port
1053 * success ints are reported in the HC interrupt status reg, the
1054 * port error ints are reported in the higher level main
1055 * interrupt status register and thus are passed in via the
1056 * 'relevant' argument.
1057 *
1058 * LOCKING:
1059 * Inherited from caller.
1060 */
1061 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1062 unsigned int hc)
1063 {
1064 void __iomem *mmio = host_set->mmio_base;
1065 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1066 struct ata_port *ap;
1067 struct ata_queued_cmd *qc;
1068 u32 hc_irq_cause;
1069 int shift, port, port0, hard_port, handled;
1070 u8 ata_status = 0;
1071
1072 if (hc == 0) {
1073 port0 = 0;
1074 } else {
1075 port0 = MV_PORTS_PER_HC;
1076 }
1077
1078 /* we'll need the HC success int register in most cases */
1079 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1080 if (hc_irq_cause) {
1081 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1082 }
1083
1084 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1085 hc,relevant,hc_irq_cause);
1086
1087 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1088 ap = host_set->ports[port];
1089 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1090 handled = 0; /* ensure ata_status is set if handled++ */
1091
1092 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1093 /* new CRPB on the queue; just one at a time until NCQ
1094 */
1095 ata_status = mv_get_crpb_status(ap);
1096 handled++;
1097 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1098 /* received ATA IRQ; read the status reg to clear INTRQ
1099 */
1100 ata_status = readb((void __iomem *)
1101 ap->ioaddr.status_addr);
1102 handled++;
1103 }
1104
1105 shift = port << 1; /* (port * 2) */
1106 if (port >= MV_PORTS_PER_HC) {
1107 shift++; /* skip bit 8 in the HC Main IRQ reg */
1108 }
1109 if ((PORT0_ERR << shift) & relevant) {
1110 mv_err_intr(ap);
1111 /* OR in ATA_ERR to ensure libata knows we took one */
1112 ata_status = readb((void __iomem *)
1113 ap->ioaddr.status_addr) | ATA_ERR;
1114 handled++;
1115 }
1116
1117 if (handled && ap) {
1118 qc = ata_qc_from_tag(ap, ap->active_tag);
1119 if (NULL != qc) {
1120 VPRINTK("port %u IRQ found for qc, "
1121 "ata_status 0x%x\n", port,ata_status);
1122 /* mark qc status appropriately */
1123 ata_qc_complete(qc, ata_status);
1124 }
1125 }
1126 }
1127 VPRINTK("EXIT\n");
1128 }
1129
1130 /**
1131 * mv_interrupt -
1132 * @irq: unused
1133 * @dev_instance: private data; in this case the host structure
1134 * @regs: unused
1135 *
1136 * Read the read only register to determine if any host
1137 * controllers have pending interrupts. If so, call lower level
1138 * routine to handle. Also check for PCI errors which are only
1139 * reported here.
1140 *
1141 * LOCKING:
1142 * This routine holds the host_set lock while processing pending
1143 * interrupts.
1144 */
1145 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1146 struct pt_regs *regs)
1147 {
1148 struct ata_host_set *host_set = dev_instance;
1149 unsigned int hc, handled = 0, n_hcs;
1150 void __iomem *mmio = host_set->mmio_base;
1151 u32 irq_stat;
1152
1153 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1154
1155 /* check the cases where we either have nothing pending or have read
1156 * a bogus register value which can indicate HW removal or PCI fault
1157 */
1158 if (!irq_stat || (0xffffffffU == irq_stat)) {
1159 return IRQ_NONE;
1160 }
1161
1162 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1163 spin_lock(&host_set->lock);
1164
1165 for (hc = 0; hc < n_hcs; hc++) {
1166 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1167 if (relevant) {
1168 mv_host_intr(host_set, relevant, hc);
1169 handled++;
1170 }
1171 }
1172 if (PCI_ERR & irq_stat) {
1173 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1174 readl(mmio + PCI_IRQ_CAUSE_OFS));
1175
1176 DPRINTK("All regs @ PCI error\n");
1177 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1178
1179 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1180 handled++;
1181 }
1182 spin_unlock(&host_set->lock);
1183
1184 return IRQ_RETVAL(handled);
1185 }
1186
1187 /**
1188 * mv_check_err - Return the error shadow register to caller.
1189 * @ap: ATA channel to manipulate
1190 *
1191 * Marvell requires DMA to be stopped before accessing shadow
1192 * registers. So we do that, then return the needed register.
1193 *
1194 * LOCKING:
1195 * Inherited from caller. FIXME: protect mv_stop_dma with lock?
1196 */
1197 static u8 mv_check_err(struct ata_port *ap)
1198 {
1199 mv_stop_dma(ap); /* can't read shadow regs if DMA on */
1200 return readb((void __iomem *) ap->ioaddr.error_addr);
1201 }
1202
1203 /**
1204 * mv_phy_reset - Perform eDMA reset followed by COMRESET
1205 * @ap: ATA channel to manipulate
1206 *
1207 * Part of this is taken from __sata_phy_reset and modified to
1208 * not sleep since this routine gets called from interrupt level.
1209 *
1210 * LOCKING:
1211 * Inherited from caller. This is coded to safe to call at
1212 * interrupt level, i.e. it does not sleep.
1213 */
1214 static void mv_phy_reset(struct ata_port *ap)
1215 {
1216 void __iomem *port_mmio = mv_ap_base(ap);
1217 struct ata_taskfile tf;
1218 struct ata_device *dev = &ap->device[0];
1219 unsigned long timeout;
1220
1221 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1222
1223 mv_stop_dma(ap);
1224
1225 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1226 udelay(25); /* allow reset propagation */
1227
1228 /* Spec never mentions clearing the bit. Marvell's driver does
1229 * clear the bit, however.
1230 */
1231 writelfl(0, port_mmio + EDMA_CMD_OFS);
1232
1233 VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1234 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1235 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1236
1237 /* proceed to init communications via the scr_control reg */
1238 scr_write_flush(ap, SCR_CONTROL, 0x301);
1239 mdelay(1);
1240 scr_write_flush(ap, SCR_CONTROL, 0x300);
1241 timeout = jiffies + (HZ * 1);
1242 do {
1243 mdelay(10);
1244 if ((scr_read(ap, SCR_STATUS) & 0xf) != 1)
1245 break;
1246 } while (time_before(jiffies, timeout));
1247
1248 VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1249 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1250 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1251
1252 if (sata_dev_present(ap)) {
1253 ata_port_probe(ap);
1254 } else {
1255 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1256 ap->id, scr_read(ap, SCR_STATUS));
1257 ata_port_disable(ap);
1258 return;
1259 }
1260 ap->cbl = ATA_CBL_SATA;
1261
1262 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1263 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1264 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1265 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1266
1267 dev->class = ata_dev_classify(&tf);
1268 if (!ata_dev_present(dev)) {
1269 VPRINTK("Port disabled post-sig: No device present.\n");
1270 ata_port_disable(ap);
1271 }
1272 VPRINTK("EXIT\n");
1273 }
1274
1275 /**
1276 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1277 * @ap: ATA channel to manipulate
1278 *
1279 * Intent is to clear all pending error conditions, reset the
1280 * chip/bus, fail the command, and move on.
1281 *
1282 * LOCKING:
1283 * This routine holds the host_set lock while failing the command.
1284 */
1285 static void mv_eng_timeout(struct ata_port *ap)
1286 {
1287 struct ata_queued_cmd *qc;
1288 unsigned long flags;
1289
1290 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1291 DPRINTK("All regs @ start of eng_timeout\n");
1292 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1293 to_pci_dev(ap->host_set->dev));
1294
1295 qc = ata_qc_from_tag(ap, ap->active_tag);
1296 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1297 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1298 &qc->scsicmd->cmnd);
1299
1300 mv_err_intr(ap);
1301 mv_phy_reset(ap);
1302
1303 if (!qc) {
1304 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1305 ap->id);
1306 } else {
1307 /* hack alert! We cannot use the supplied completion
1308 * function from inside the ->eh_strategy_handler() thread.
1309 * libata is the only user of ->eh_strategy_handler() in
1310 * any kernel, so the default scsi_done() assumes it is
1311 * not being called from the SCSI EH.
1312 */
1313 spin_lock_irqsave(&ap->host_set->lock, flags);
1314 qc->scsidone = scsi_finish_command;
1315 ata_qc_complete(qc, ATA_ERR);
1316 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1317 }
1318 }
1319
1320 /**
1321 * mv_port_init - Perform some early initialization on a single port.
1322 * @port: libata data structure storing shadow register addresses
1323 * @port_mmio: base address of the port
1324 *
1325 * Initialize shadow register mmio addresses, clear outstanding
1326 * interrupts on the port, and unmask interrupts for the future
1327 * start of the port.
1328 *
1329 * LOCKING:
1330 * Inherited from caller.
1331 */
1332 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1333 {
1334 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1335 unsigned serr_ofs;
1336
1337 /* PIO related setup
1338 */
1339 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1340 port->error_addr =
1341 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1342 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1343 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1344 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1345 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1346 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1347 port->status_addr =
1348 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1349 /* special case: control/altstatus doesn't have ATA_REG_ address */
1350 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1351
1352 /* unused: */
1353 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1354
1355 /* Clear any currently outstanding port interrupt conditions */
1356 serr_ofs = mv_scr_offset(SCR_ERROR);
1357 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1358 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1359
1360 /* unmask all EDMA error interrupts */
1361 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1362
1363 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1364 readl(port_mmio + EDMA_CFG_OFS),
1365 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1366 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1367 }
1368
1369 /**
1370 * mv_host_init - Perform some early initialization of the host.
1371 * @probe_ent: early data struct representing the host
1372 *
1373 * If possible, do an early global reset of the host. Then do
1374 * our port init and clear/unmask all/relevant host interrupts.
1375 *
1376 * LOCKING:
1377 * Inherited from caller.
1378 */
1379 static int mv_host_init(struct ata_probe_ent *probe_ent)
1380 {
1381 int rc = 0, n_hc, port, hc;
1382 void __iomem *mmio = probe_ent->mmio_base;
1383 void __iomem *port_mmio;
1384
1385 if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) &&
1386 mv_global_soft_reset(probe_ent->mmio_base)) {
1387 rc = 1;
1388 goto done;
1389 }
1390
1391 n_hc = mv_get_hc_count(probe_ent->host_flags);
1392 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
1393
1394 for (port = 0; port < probe_ent->n_ports; port++) {
1395 port_mmio = mv_port_base(mmio, port);
1396 mv_port_init(&probe_ent->port[port], port_mmio);
1397 }
1398
1399 for (hc = 0; hc < n_hc; hc++) {
1400 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1401
1402 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
1403 "(before clear)=0x%08x\n", hc,
1404 readl(hc_mmio + HC_CFG_OFS),
1405 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
1406
1407 /* Clear any currently outstanding hc interrupt conditions */
1408 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
1409 }
1410
1411 /* Clear any currently outstanding host interrupt conditions */
1412 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1413
1414 /* and unmask interrupt generation for host regs */
1415 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
1416 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
1417
1418 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1419 "PCI int cause/mask=0x%08x/0x%08x\n",
1420 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
1421 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
1422 readl(mmio + PCI_IRQ_CAUSE_OFS),
1423 readl(mmio + PCI_IRQ_MASK_OFS));
1424 done:
1425 return rc;
1426 }
1427
1428 /**
1429 * mv_print_info - Dump key info to kernel log for perusal.
1430 * @probe_ent: early data struct representing the host
1431 *
1432 * FIXME: complete this.
1433 *
1434 * LOCKING:
1435 * Inherited from caller.
1436 */
1437 static void mv_print_info(struct ata_probe_ent *probe_ent)
1438 {
1439 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1440 struct mv_host_priv *hpriv = probe_ent->private_data;
1441 u8 rev_id, scc;
1442 const char *scc_s;
1443
1444 /* Use this to determine the HW stepping of the chip so we know
1445 * what errata to workaround
1446 */
1447 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1448
1449 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
1450 if (scc == 0)
1451 scc_s = "SCSI";
1452 else if (scc == 0x01)
1453 scc_s = "RAID";
1454 else
1455 scc_s = "unknown";
1456
1457 printk(KERN_INFO DRV_NAME
1458 "(%s) %u slots %u ports %s mode IRQ via %s\n",
1459 pci_name(pdev), (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
1460 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
1461 }
1462
1463 /**
1464 * mv_init_one - handle a positive probe of a Marvell host
1465 * @pdev: PCI device found
1466 * @ent: PCI device ID entry for the matched host
1467 *
1468 * LOCKING:
1469 * Inherited from caller.
1470 */
1471 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1472 {
1473 static int printed_version = 0;
1474 struct ata_probe_ent *probe_ent = NULL;
1475 struct mv_host_priv *hpriv;
1476 unsigned int board_idx = (unsigned int)ent->driver_data;
1477 void __iomem *mmio_base;
1478 int pci_dev_busy = 0, rc;
1479
1480 if (!printed_version++) {
1481 printk(KERN_INFO DRV_NAME " version " DRV_VERSION "\n");
1482 }
1483
1484 rc = pci_enable_device(pdev);
1485 if (rc) {
1486 return rc;
1487 }
1488
1489 rc = pci_request_regions(pdev, DRV_NAME);
1490 if (rc) {
1491 pci_dev_busy = 1;
1492 goto err_out;
1493 }
1494
1495 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1496 if (probe_ent == NULL) {
1497 rc = -ENOMEM;
1498 goto err_out_regions;
1499 }
1500
1501 memset(probe_ent, 0, sizeof(*probe_ent));
1502 probe_ent->dev = pci_dev_to_dev(pdev);
1503 INIT_LIST_HEAD(&probe_ent->node);
1504
1505 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
1506 if (mmio_base == NULL) {
1507 rc = -ENOMEM;
1508 goto err_out_free_ent;
1509 }
1510
1511 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1512 if (!hpriv) {
1513 rc = -ENOMEM;
1514 goto err_out_iounmap;
1515 }
1516 memset(hpriv, 0, sizeof(*hpriv));
1517
1518 probe_ent->sht = mv_port_info[board_idx].sht;
1519 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
1520 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
1521 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
1522 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
1523
1524 probe_ent->irq = pdev->irq;
1525 probe_ent->irq_flags = SA_SHIRQ;
1526 probe_ent->mmio_base = mmio_base;
1527 probe_ent->private_data = hpriv;
1528
1529 /* initialize adapter */
1530 rc = mv_host_init(probe_ent);
1531 if (rc) {
1532 goto err_out_hpriv;
1533 }
1534
1535 /* Enable interrupts */
1536 if (pci_enable_msi(pdev) == 0) {
1537 hpriv->hp_flags |= MV_HP_FLAG_MSI;
1538 } else {
1539 pci_intx(pdev, 1);
1540 }
1541
1542 mv_dump_pci_cfg(pdev, 0x68);
1543 mv_print_info(probe_ent);
1544
1545 if (ata_device_add(probe_ent) == 0) {
1546 rc = -ENODEV; /* No devices discovered */
1547 goto err_out_dev_add;
1548 }
1549
1550 kfree(probe_ent);
1551 return 0;
1552
1553 err_out_dev_add:
1554 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
1555 pci_disable_msi(pdev);
1556 } else {
1557 pci_intx(pdev, 0);
1558 }
1559 err_out_hpriv:
1560 kfree(hpriv);
1561 err_out_iounmap:
1562 pci_iounmap(pdev, mmio_base);
1563 err_out_free_ent:
1564 kfree(probe_ent);
1565 err_out_regions:
1566 pci_release_regions(pdev);
1567 err_out:
1568 if (!pci_dev_busy) {
1569 pci_disable_device(pdev);
1570 }
1571
1572 return rc;
1573 }
1574
1575 static int __init mv_init(void)
1576 {
1577 return pci_module_init(&mv_pci_driver);
1578 }
1579
1580 static void __exit mv_exit(void)
1581 {
1582 pci_unregister_driver(&mv_pci_driver);
1583 }
1584
1585 MODULE_AUTHOR("Brett Russ");
1586 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
1587 MODULE_LICENSE("GPL");
1588 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
1589 MODULE_VERSION(DRV_VERSION);
1590
1591 module_init(mv_init);
1592 module_exit(mv_exit);
x86 "subsystem" repository