2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
36 #define DBG(fmt...) printk(fmt)
41 unsigned long pci_probe_only
= 1;
42 int pci_assign_all_buses
= 0;
44 #ifdef CONFIG_PPC_MULTIPLATFORM
45 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
46 static void do_bus_setup(struct pci_bus
*bus
);
47 static void phbs_remap_io(void);
50 /* pci_io_base -- the base address from which io bars are offsets.
51 * This is the lowest I/O base address (so bar values are always positive),
52 * and it *must* be the start of ISA space if an ISA bus exists because
53 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
54 * page is mapped and isa_io_limit prevents access to it.
56 unsigned long isa_io_base
; /* NULL if no ISA bus */
57 EXPORT_SYMBOL(isa_io_base
);
58 unsigned long pci_io_base
;
59 EXPORT_SYMBOL(pci_io_base
);
61 void iSeries_pcibios_init(void);
65 struct dma_mapping_ops pci_dma_ops
;
66 EXPORT_SYMBOL(pci_dma_ops
);
68 int global_phb_number
; /* Global phb counter */
70 /* Cached ISA bridge dev. */
71 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
72 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev
);
74 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
76 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
77 dev
->vendor
= PCI_VENDOR_ID_AMD
;
78 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
81 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
83 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
86 unsigned long offset
= 0;
87 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
92 if (res
->flags
& IORESOURCE_IO
)
93 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
95 if (res
->flags
& IORESOURCE_MEM
)
96 offset
= hose
->pci_mem_offset
;
98 region
->start
= res
->start
- offset
;
99 region
->end
= res
->end
- offset
;
102 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
103 struct pci_bus_region
*region
)
105 unsigned long offset
= 0;
106 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
111 if (res
->flags
& IORESOURCE_IO
)
112 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
114 if (res
->flags
& IORESOURCE_MEM
)
115 offset
= hose
->pci_mem_offset
;
117 res
->start
= region
->start
+ offset
;
118 res
->end
= region
->end
+ offset
;
121 #ifdef CONFIG_HOTPLUG
122 EXPORT_SYMBOL(pcibios_resource_to_bus
);
123 EXPORT_SYMBOL(pcibios_bus_to_resource
);
127 * We need to avoid collisions with `mirrored' VGA ports
128 * and other strange ISA hardware, so we always want the
129 * addresses to be allocated in the 0x000-0x0ff region
132 * Why? Because some silly external IO cards only decode
133 * the low 10 bits of the IO address. The 0x00-0xff region
134 * is reserved for motherboard devices that decode all 16
135 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
136 * but we want to try to avoid allocating at 0x2900-0x2bff
137 * which might have be mirrored at 0x0100-0x03ff..
139 void pcibios_align_resource(void *data
, struct resource
*res
,
140 resource_size_t size
, resource_size_t align
)
142 struct pci_dev
*dev
= data
;
143 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
144 resource_size_t start
= res
->start
;
145 unsigned long alignto
;
147 if (res
->flags
& IORESOURCE_IO
) {
148 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
150 /* Make sure we start at our min on all hoses */
151 if (start
- offset
< PCIBIOS_MIN_IO
)
152 start
= PCIBIOS_MIN_IO
+ offset
;
155 * Put everything into 0x00-0xff region modulo 0x400
158 start
= (start
+ 0x3ff) & ~0x3ff;
160 } else if (res
->flags
& IORESOURCE_MEM
) {
161 /* Make sure we start at our min on all hoses */
162 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
163 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
165 /* Align to multiple of size of minimum base. */
166 alignto
= max(0x1000UL
, align
);
167 start
= ALIGN(start
, alignto
);
173 static DEFINE_SPINLOCK(hose_spinlock
);
176 * pci_controller(phb) initialized common variables.
178 static void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
180 memset(hose
, 0, sizeof(struct pci_controller
));
182 spin_lock(&hose_spinlock
);
183 hose
->global_number
= global_phb_number
++;
184 list_add_tail(&hose
->list_node
, &hose_list
);
185 spin_unlock(&hose_spinlock
);
188 struct pci_controller
* pcibios_alloc_controller(struct device_node
*dev
)
190 struct pci_controller
*phb
;
193 phb
= kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
195 phb
= alloc_bootmem(sizeof (struct pci_controller
));
198 pci_setup_pci_controller(phb
);
199 phb
->arch_data
= dev
;
200 phb
->is_dynamic
= mem_init_done
;
202 PHB_SET_NODE(phb
, of_node_to_nid(dev
));
206 void pcibios_free_controller(struct pci_controller
*phb
)
212 #ifndef CONFIG_PPC_ISERIES
213 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
216 struct pci_bus
*child_bus
;
218 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
221 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
222 struct resource
*r
= &dev
->resource
[i
];
224 if (r
->parent
|| !r
->start
|| !r
->flags
)
226 pci_claim_resource(dev
, i
);
230 list_for_each_entry(child_bus
, &b
->children
, node
)
231 pcibios_claim_one_bus(child_bus
);
233 #ifdef CONFIG_HOTPLUG
234 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
237 static void __init
pcibios_claim_of_setup(void)
241 list_for_each_entry(b
, &pci_root_buses
, node
)
242 pcibios_claim_one_bus(b
);
246 #ifdef CONFIG_PPC_MULTIPLATFORM
247 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
252 prop
= get_property(np
, name
, &len
);
253 if (prop
&& len
>= 4)
258 static unsigned int pci_parse_of_flags(u32 addr0
)
260 unsigned int flags
= 0;
262 if (addr0
& 0x02000000) {
263 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
264 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
265 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
266 if (addr0
& 0x40000000)
267 flags
|= IORESOURCE_PREFETCH
268 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
269 } else if (addr0
& 0x01000000)
270 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
274 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
276 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
280 struct resource
*res
;
285 addrs
= get_property(node
, "assigned-addresses", &proplen
);
288 DBG(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
289 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
290 flags
= pci_parse_of_flags(addrs
[0]);
293 base
= GET_64BIT(addrs
, 1);
294 size
= GET_64BIT(addrs
, 3);
298 DBG(" base: %llx, size: %llx, i: %x\n",
299 (unsigned long long)base
, (unsigned long long)size
, i
);
301 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
302 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
303 } else if (i
== dev
->rom_base_reg
) {
304 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
305 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
307 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
311 res
->end
= base
+ size
- 1;
313 res
->name
= pci_name(dev
);
314 fixup_resource(res
, dev
);
318 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
319 struct pci_bus
*bus
, int devfn
)
324 dev
= kmalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
327 type
= get_property(node
, "device_type", NULL
);
331 DBG(" create device, devfn: %x, type: %s\n", devfn
, type
);
333 memset(dev
, 0, sizeof(struct pci_dev
));
336 dev
->dev
.parent
= bus
->bridge
;
337 dev
->dev
.bus
= &pci_bus_type
;
339 dev
->multifunction
= 0; /* maybe a lie? */
341 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
342 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
343 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
344 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
346 dev
->cfg_size
= pci_cfg_space_size(dev
);
348 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
349 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
350 dev
->class = get_int_prop(node
, "class-code", 0);
352 DBG(" class: 0x%x\n", dev
->class);
354 dev
->current_state
= 4; /* unknown power state */
356 if (!strcmp(type
, "pci") || !strcmp(type
, "pciex")) {
357 /* a PCI-PCI bridge */
358 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
359 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
360 } else if (!strcmp(type
, "cardbus")) {
361 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
363 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
364 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
365 /* Maybe do a default OF mapping here */
369 pci_parse_of_addrs(node
, dev
);
371 DBG(" adding to system ...\n");
373 pci_device_add(dev
, bus
);
375 /* XXX pci_scan_msi_device(dev); */
379 EXPORT_SYMBOL(of_create_pci_dev
);
381 void __devinit
of_scan_bus(struct device_node
*node
,
384 struct device_node
*child
= NULL
;
389 DBG("of_scan_bus(%s) bus no %d... \n", node
->full_name
, bus
->number
);
391 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
392 DBG(" * %s\n", child
->full_name
);
393 reg
= get_property(child
, "reg", ®len
);
394 if (reg
== NULL
|| reglen
< 20)
396 devfn
= (reg
[0] >> 8) & 0xff;
398 /* create a new pci_dev for this device */
399 dev
= of_create_pci_dev(child
, bus
, devfn
);
402 DBG("dev header type: %x\n", dev
->hdr_type
);
404 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
405 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
406 of_scan_pci_bridge(child
, dev
);
411 EXPORT_SYMBOL(of_scan_bus
);
413 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
417 const u32
*busrange
, *ranges
;
419 struct resource
*res
;
423 DBG("of_scan_pci_bridge(%s)\n", node
->full_name
);
425 /* parse bus-range property */
426 busrange
= get_property(node
, "bus-range", &len
);
427 if (busrange
== NULL
|| len
!= 8) {
428 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
432 ranges
= get_property(node
, "ranges", &len
);
433 if (ranges
== NULL
) {
434 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
439 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
441 printk(KERN_ERR
"Failed to create pci bus for %s\n",
446 bus
->primary
= dev
->bus
->number
;
447 bus
->subordinate
= busrange
[1];
451 /* parse ranges property */
452 /* PCI #address-cells == 3 and #size-cells == 2 always */
453 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
454 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
456 bus
->resource
[i
] = res
;
460 for (; len
>= 32; len
-= 32, ranges
+= 8) {
461 flags
= pci_parse_of_flags(ranges
[0]);
462 size
= GET_64BIT(ranges
, 6);
463 if (flags
== 0 || size
== 0)
465 if (flags
& IORESOURCE_IO
) {
466 res
= bus
->resource
[0];
468 printk(KERN_ERR
"PCI: ignoring extra I/O range"
469 " for bridge %s\n", node
->full_name
);
473 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
474 printk(KERN_ERR
"PCI: too many memory ranges"
475 " for bridge %s\n", node
->full_name
);
478 res
= bus
->resource
[i
];
481 res
->start
= GET_64BIT(ranges
, 1);
482 res
->end
= res
->start
+ size
- 1;
484 fixup_resource(res
, dev
);
486 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
488 DBG(" bus name: %s\n", bus
->name
);
490 mode
= PCI_PROBE_NORMAL
;
491 if (ppc_md
.pci_probe_mode
)
492 mode
= ppc_md
.pci_probe_mode(bus
);
493 DBG(" probe mode: %d\n", mode
);
495 if (mode
== PCI_PROBE_DEVTREE
)
496 of_scan_bus(node
, bus
);
497 else if (mode
== PCI_PROBE_NORMAL
)
498 pci_scan_child_bus(bus
);
500 EXPORT_SYMBOL(of_scan_pci_bridge
);
501 #endif /* CONFIG_PPC_MULTIPLATFORM */
503 void __devinit
scan_phb(struct pci_controller
*hose
)
506 struct device_node
*node
= hose
->arch_data
;
508 struct resource
*res
;
510 DBG("Scanning PHB %s\n", node
? node
->full_name
: "<NO NAME>");
512 bus
= pci_create_bus(NULL
, hose
->first_busno
, hose
->ops
, node
);
514 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
515 hose
->global_number
);
518 bus
->secondary
= hose
->first_busno
;
521 bus
->resource
[0] = res
= &hose
->io_resource
;
522 if (res
->flags
&& request_resource(&ioport_resource
, res
))
523 printk(KERN_ERR
"Failed to request PCI IO region "
524 "on PCI domain %04x\n", hose
->global_number
);
526 for (i
= 0; i
< 3; ++i
) {
527 res
= &hose
->mem_resources
[i
];
528 bus
->resource
[i
+1] = res
;
529 if (res
->flags
&& request_resource(&iomem_resource
, res
))
530 printk(KERN_ERR
"Failed to request PCI memory region "
531 "on PCI domain %04x\n", hose
->global_number
);
534 mode
= PCI_PROBE_NORMAL
;
535 #ifdef CONFIG_PPC_MULTIPLATFORM
536 if (node
&& ppc_md
.pci_probe_mode
)
537 mode
= ppc_md
.pci_probe_mode(bus
);
538 DBG(" probe mode: %d\n", mode
);
539 if (mode
== PCI_PROBE_DEVTREE
) {
540 bus
->subordinate
= hose
->last_busno
;
541 of_scan_bus(node
, bus
);
543 #endif /* CONFIG_PPC_MULTIPLATFORM */
544 if (mode
== PCI_PROBE_NORMAL
)
545 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
548 static int __init
pcibios_init(void)
550 struct pci_controller
*hose
, *tmp
;
552 /* For now, override phys_mem_access_prot. If we need it,
553 * later, we may move that initialization to each ppc_md
555 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
557 #ifdef CONFIG_PPC_ISERIES
558 iSeries_pcibios_init();
561 printk(KERN_DEBUG
"PCI: Probing PCI hardware\n");
563 /* Scan all of the recorded PCI controllers. */
564 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
566 pci_bus_add_devices(hose
->bus
);
569 #ifndef CONFIG_PPC_ISERIES
571 pcibios_claim_of_setup();
573 /* FIXME: `else' will be removed when
574 pci_assign_unassigned_resources() is able to work
575 correctly with [partially] allocated PCI tree. */
576 pci_assign_unassigned_resources();
577 #endif /* !CONFIG_PPC_ISERIES */
579 /* Call machine dependent final fixup */
580 if (ppc_md
.pcibios_fixup
)
581 ppc_md
.pcibios_fixup();
583 /* Cache the location of the ISA bridge (if we have one) */
584 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
585 if (ppc64_isabridge_dev
!= NULL
)
586 printk(KERN_DEBUG
"ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
588 #ifdef CONFIG_PPC_MULTIPLATFORM
589 /* map in PCI I/O space */
593 printk(KERN_DEBUG
"PCI: Probing PCI hardware done\n");
598 subsys_initcall(pcibios_init
);
600 char __init
*pcibios_setup(char *str
)
605 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
610 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
613 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
614 struct resource
*res
= &dev
->resource
[i
];
616 /* Only set up the requested stuff */
617 if (!(mask
& (1<<i
)))
620 if (res
->flags
& IORESOURCE_IO
)
621 cmd
|= PCI_COMMAND_IO
;
622 if (res
->flags
& IORESOURCE_MEM
)
623 cmd
|= PCI_COMMAND_MEMORY
;
627 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
629 /* Enable the appropriate bits in the PCI command register. */
630 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
636 * Return the domain number for this bus.
638 int pci_domain_nr(struct pci_bus
*bus
)
640 #ifdef CONFIG_PPC_ISERIES
643 struct pci_controller
*hose
= pci_bus_to_host(bus
);
645 return hose
->global_number
;
649 EXPORT_SYMBOL(pci_domain_nr
);
651 /* Decide whether to display the domain number in /proc */
652 int pci_proc_domain(struct pci_bus
*bus
)
654 #ifdef CONFIG_PPC_ISERIES
657 struct pci_controller
*hose
= pci_bus_to_host(bus
);
663 * Platform support for /proc/bus/pci/X/Y mmap()s,
664 * modelled on the sparc64 implementation by Dave Miller.
669 * Adjust vm_pgoff of VMA such that it is the physical page offset
670 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
672 * Basically, the user finds the base address for his device which he wishes
673 * to mmap. They read the 32-bit value from the config space base register,
674 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
675 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
677 * Returns negative error code on failure, zero on success.
679 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
680 unsigned long *offset
,
681 enum pci_mmap_state mmap_state
)
683 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
684 unsigned long io_offset
= 0;
688 return NULL
; /* should never happen */
690 /* If memory, add on the PCI bridge address offset */
691 if (mmap_state
== pci_mmap_mem
) {
692 *offset
+= hose
->pci_mem_offset
;
693 res_bit
= IORESOURCE_MEM
;
695 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
696 *offset
+= io_offset
;
697 res_bit
= IORESOURCE_IO
;
701 * Check that the offset requested corresponds to one of the
702 * resources of the device.
704 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
705 struct resource
*rp
= &dev
->resource
[i
];
706 int flags
= rp
->flags
;
708 /* treat ROM as memory (should be already) */
709 if (i
== PCI_ROM_RESOURCE
)
710 flags
|= IORESOURCE_MEM
;
712 /* Active and same type? */
713 if ((flags
& res_bit
) == 0)
716 /* In the range of this resource? */
717 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
720 /* found it! construct the final physical address */
721 if (mmap_state
== pci_mmap_io
)
722 *offset
+= hose
->io_base_phys
- io_offset
;
730 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
733 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
735 enum pci_mmap_state mmap_state
,
738 unsigned long prot
= pgprot_val(protection
);
740 /* Write combine is always 0 on non-memory space mappings. On
741 * memory space, if the user didn't pass 1, we check for a
742 * "prefetchable" resource. This is a bit hackish, but we use
743 * this to workaround the inability of /sysfs to provide a write
746 if (mmap_state
!= pci_mmap_mem
)
748 else if (write_combine
== 0) {
749 if (rp
->flags
& IORESOURCE_PREFETCH
)
753 /* XXX would be nice to have a way to ask for write-through */
754 prot
|= _PAGE_NO_CACHE
;
756 prot
&= ~_PAGE_GUARDED
;
758 prot
|= _PAGE_GUARDED
;
760 printk(KERN_DEBUG
"PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
763 return __pgprot(prot
);
767 * This one is used by /dev/mem and fbdev who have no clue about the
768 * PCI device, it tries to find the PCI device first and calls the
771 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
776 struct pci_dev
*pdev
= NULL
;
777 struct resource
*found
= NULL
;
778 unsigned long prot
= pgprot_val(protection
);
779 unsigned long offset
= pfn
<< PAGE_SHIFT
;
782 if (page_is_ram(pfn
))
783 return __pgprot(prot
);
785 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
787 for_each_pci_dev(pdev
) {
788 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
789 struct resource
*rp
= &pdev
->resource
[i
];
790 int flags
= rp
->flags
;
792 /* Active and same type? */
793 if ((flags
& IORESOURCE_MEM
) == 0)
795 /* In the range of this resource? */
796 if (offset
< (rp
->start
& PAGE_MASK
) ||
806 if (found
->flags
& IORESOURCE_PREFETCH
)
807 prot
&= ~_PAGE_GUARDED
;
811 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
813 return __pgprot(prot
);
818 * Perform the actual remap of the pages for a PCI device mapping, as
819 * appropriate for this architecture. The region in the process to map
820 * is described by vm_start and vm_end members of VMA, the base physical
821 * address is found in vm_pgoff.
822 * The pci device structure is provided so that architectures may make mapping
823 * decisions on a per-device or per-bus basis.
825 * Returns a negative error code on failure, zero on success.
827 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
828 enum pci_mmap_state mmap_state
, int write_combine
)
830 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
834 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
838 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
839 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
841 mmap_state
, write_combine
);
843 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
844 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
849 static ssize_t
pci_show_devspec(struct device
*dev
,
850 struct device_attribute
*attr
, char *buf
)
852 struct pci_dev
*pdev
;
853 struct device_node
*np
;
855 pdev
= to_pci_dev (dev
);
856 np
= pci_device_to_OF_node(pdev
);
857 if (np
== NULL
|| np
->full_name
== NULL
)
859 return sprintf(buf
, "%s", np
->full_name
);
861 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
863 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
865 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
868 #ifdef CONFIG_PPC_MULTIPLATFORM
870 #define ISA_SPACE_MASK 0x1
871 #define ISA_SPACE_IO 0x1
873 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
874 unsigned long phb_io_base_phys
,
875 void __iomem
* phb_io_base_virt
)
877 /* Remove these asap */
891 struct isa_address isa_addr
;
892 struct pci_address pci_addr
;
896 const struct isa_range
*range
;
897 unsigned long pci_addr
;
898 unsigned int isa_addr
;
902 range
= get_property(isa_node
, "ranges", &rlen
);
903 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
904 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
906 __ioremap_explicit(phb_io_base_phys
,
907 (unsigned long)phb_io_base_virt
,
908 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
912 /* From "ISA Binding to 1275"
913 * The ranges property is laid out as an array of elements,
914 * each of which comprises:
915 * cells 0 - 1: an ISA address
916 * cells 2 - 4: a PCI address
917 * (size depending on dev->n_addr_cells)
918 * cell 5: the size of the range
920 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
921 isa_addr
= range
->isa_addr
.a_lo
;
922 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
923 range
->pci_addr
.a_lo
;
925 /* Assume these are both zero */
926 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
927 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
932 size
= PAGE_ALIGN(range
->size
);
934 __ioremap_explicit(phb_io_base_phys
,
935 (unsigned long) phb_io_base_virt
,
936 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
940 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
941 struct device_node
*dev
, int prim
)
943 const unsigned int *ranges
;
944 unsigned int pci_space
;
948 struct resource
*res
;
949 int np
, na
= prom_n_addr_cells(dev
);
950 unsigned long pci_addr
, cpu_phys_addr
;
954 /* From "PCI Binding to 1275"
955 * The ranges property is laid out as an array of elements,
956 * each of which comprises:
957 * cells 0 - 2: a PCI address
958 * cells 3 or 3+4: a CPU physical address
959 * (size depending on dev->n_addr_cells)
960 * cells 4+5 or 5+6: the size of the range
962 ranges
= get_property(dev
, "ranges", &rlen
);
965 hose
->io_base_phys
= 0;
966 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
968 pci_space
= ranges
[0];
969 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
971 cpu_phys_addr
= ranges
[3];
973 cpu_phys_addr
= (cpu_phys_addr
<< 32) | ranges
[4];
975 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
980 /* Now consume following elements while they are contiguous */
981 while (rlen
>= np
* sizeof(unsigned int)) {
982 unsigned long addr
, phys
;
984 if (ranges
[0] != pci_space
)
986 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
989 phys
= (phys
<< 32) | ranges
[4];
990 if (addr
!= pci_addr
+ size
||
991 phys
!= cpu_phys_addr
+ size
)
994 size
+= ((unsigned long)ranges
[na
+3] << 32)
997 rlen
-= np
* sizeof(unsigned int);
1000 switch ((pci_space
>> 24) & 0x3) {
1001 case 1: /* I/O space */
1002 hose
->io_base_phys
= cpu_phys_addr
;
1003 hose
->pci_io_size
= size
;
1005 res
= &hose
->io_resource
;
1006 res
->flags
= IORESOURCE_IO
;
1007 res
->start
= pci_addr
;
1008 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
1009 res
->start
, res
->start
+ size
- 1);
1011 case 2: /* memory space */
1013 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
1017 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
1019 res
= &hose
->mem_resources
[memno
];
1020 res
->flags
= IORESOURCE_MEM
;
1021 res
->start
= cpu_phys_addr
;
1022 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
1023 res
->start
, res
->start
+ size
- 1);
1028 res
->name
= dev
->full_name
;
1029 res
->end
= res
->start
+ size
- 1;
1031 res
->sibling
= NULL
;
1037 void __init
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
1039 unsigned long size
= hose
->pci_io_size
;
1040 unsigned long io_virt_offset
;
1041 struct resource
*res
;
1042 struct device_node
*isa_dn
;
1044 hose
->io_base_virt
= reserve_phb_iospace(size
);
1045 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1046 hose
->global_number
, hose
->io_base_phys
,
1047 (unsigned long) hose
->io_base_virt
);
1050 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1051 isa_dn
= of_find_node_by_type(NULL
, "isa");
1053 isa_io_base
= pci_io_base
;
1054 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
1055 hose
->io_base_virt
);
1056 of_node_put(isa_dn
);
1060 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1061 res
= &hose
->io_resource
;
1062 res
->start
+= io_virt_offset
;
1063 res
->end
+= io_virt_offset
;
1066 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
1069 unsigned long size
= hose
->pci_io_size
;
1070 unsigned long io_virt_offset
;
1071 struct resource
*res
;
1073 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
1074 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1075 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1076 hose
->global_number
, hose
->io_base_phys
,
1077 (unsigned long) hose
->io_base_virt
);
1080 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1082 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1083 res
= &hose
->io_resource
;
1084 res
->start
+= io_virt_offset
;
1085 res
->end
+= io_virt_offset
;
1089 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1090 unsigned long *start_virt
, unsigned long *size
)
1092 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1093 struct pci_bus_region region
;
1094 struct resource
*res
;
1097 res
= bus
->resource
[0];
1098 pcibios_resource_to_bus(bus
->self
, ®ion
, res
);
1099 *start_phys
= hose
->io_base_phys
+ region
.start
;
1100 *start_virt
= (unsigned long) hose
->io_base_virt
+
1102 if (region
.end
> region
.start
)
1103 *size
= region
.end
- region
.start
+ 1;
1105 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1106 __FUNCTION__
, region
.start
, region
.end
);
1112 res
= &hose
->io_resource
;
1113 *start_phys
= hose
->io_base_phys
;
1114 *start_virt
= (unsigned long) hose
->io_base_virt
;
1115 if (res
->end
> res
->start
)
1116 *size
= res
->end
- res
->start
+ 1;
1118 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1119 __FUNCTION__
, res
->start
, res
->end
);
1127 int unmap_bus_range(struct pci_bus
*bus
)
1129 unsigned long start_phys
;
1130 unsigned long start_virt
;
1134 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1138 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1140 if (iounmap_explicit((void __iomem
*) start_virt
, size
))
1145 EXPORT_SYMBOL(unmap_bus_range
);
1147 int remap_bus_range(struct pci_bus
*bus
)
1149 unsigned long start_phys
;
1150 unsigned long start_virt
;
1154 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1159 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1161 if (start_phys
== 0)
1163 printk(KERN_DEBUG
"mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1164 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1165 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1170 EXPORT_SYMBOL(remap_bus_range
);
1172 static void phbs_remap_io(void)
1174 struct pci_controller
*hose
, *tmp
;
1176 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1177 remap_bus_range(hose
->bus
);
1180 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1182 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1183 unsigned long offset
;
1185 if (res
->flags
& IORESOURCE_IO
) {
1186 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1188 res
->start
+= offset
;
1190 } else if (res
->flags
& IORESOURCE_MEM
) {
1191 res
->start
+= hose
->pci_mem_offset
;
1192 res
->end
+= hose
->pci_mem_offset
;
1196 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1197 struct pci_bus
*bus
)
1199 /* Update device resources. */
1202 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1203 if (dev
->resource
[i
].flags
)
1204 fixup_resource(&dev
->resource
[i
], dev
);
1206 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1209 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1211 struct pci_dev
*dev
;
1213 ppc_md
.iommu_bus_setup(bus
);
1215 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1216 ppc_md
.iommu_dev_setup(dev
);
1218 if (ppc_md
.irq_bus_setup
)
1219 ppc_md
.irq_bus_setup(bus
);
1222 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1224 struct pci_dev
*dev
= bus
->self
;
1226 if (dev
&& pci_probe_only
&&
1227 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1228 /* This is a subordinate bridge */
1230 pci_read_bridge_bases(bus
);
1231 pcibios_fixup_device_resources(dev
, bus
);
1236 if (!pci_probe_only
)
1239 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1240 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1241 pcibios_fixup_device_resources(dev
, bus
);
1243 EXPORT_SYMBOL(pcibios_fixup_bus
);
1246 * Reads the interrupt pin to determine if interrupt is use by card.
1247 * If the interrupt is used, then gets the interrupt line from the
1248 * openfirmware and sets it in the pci_dev and pci_config line.
1250 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1255 DBG("Try to map irq for %s...\n", pci_name(pci_dev
));
1258 memset(&oirq
, 0xff, sizeof(oirq
));
1260 /* Try to get a mapping from the device-tree */
1261 if (of_irq_map_pci(pci_dev
, &oirq
)) {
1264 /* If that fails, lets fallback to what is in the config
1265 * space and map that through the default controller. We
1266 * also set the type to level low since that's what PCI
1267 * interrupts are. If your platform does differently, then
1268 * either provide a proper interrupt tree or don't use this
1271 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
1275 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
1279 DBG(" -> no map ! Using irq line %d from PCI config\n", line
);
1281 virq
= irq_create_mapping(NULL
, line
);
1283 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
1285 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1286 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
1287 oirq
.controller
->full_name
);
1289 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
1292 if(virq
== NO_IRQ
) {
1293 DBG(" -> failed to map !\n");
1297 DBG(" -> mapped to linux irq %d\n", virq
);
1299 pci_dev
->irq
= virq
;
1300 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, virq
);
1304 EXPORT_SYMBOL(pci_read_irq_line
);
1306 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1307 const struct resource
*rsrc
,
1308 u64
*start
, u64
*end
)
1310 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1311 unsigned long offset
= 0;
1316 if (rsrc
->flags
& IORESOURCE_IO
)
1317 offset
= pci_io_base
- (unsigned long)hose
->io_base_virt
+
1320 *start
= rsrc
->start
+ offset
;
1321 *end
= rsrc
->end
+ offset
;
1324 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
1329 struct pci_controller
*hose
, *tmp
;
1330 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1331 if (hose
->arch_data
== node
)
1333 node
= node
->parent
;
1338 #endif /* CONFIG_PPC_MULTIPLATFORM */
1340 unsigned long pci_address_to_pio(phys_addr_t address
)
1342 struct pci_controller
*hose
, *tmp
;
1344 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1345 if (address
>= hose
->io_base_phys
&&
1346 address
< (hose
->io_base_phys
+ hose
->pci_io_size
)) {
1347 unsigned long base
=
1348 (unsigned long)hose
->io_base_virt
- pci_io_base
;
1349 return base
+ (address
- hose
->io_base_phys
);
1352 return (unsigned int)-1;
1354 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
1357 #define IOBASE_BRIDGE_NUMBER 0
1358 #define IOBASE_MEMORY 1
1360 #define IOBASE_ISA_IO 3
1361 #define IOBASE_ISA_MEM 4
1363 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1364 unsigned long in_devfn
)
1366 struct pci_controller
* hose
;
1367 struct list_head
*ln
;
1368 struct pci_bus
*bus
= NULL
;
1369 struct device_node
*hose_node
;
1371 /* Argh ! Please forgive me for that hack, but that's the
1372 * simplest way to get existing XFree to not lockup on some
1373 * G5 machines... So when something asks for bus 0 io base
1374 * (bus 0 is HT root), we return the AGP one instead.
1376 if (machine_is_compatible("MacRISC4"))
1380 /* That syscall isn't quite compatible with PCI domains, but it's
1381 * used on pre-domains setup. We return the first match
1384 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1385 bus
= pci_bus_b(ln
);
1386 if (in_bus
>= bus
->number
&& in_bus
< (bus
->number
+ bus
->subordinate
))
1390 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1393 hose_node
= (struct device_node
*)bus
->sysdata
;
1394 hose
= PCI_DN(hose_node
)->phb
;
1397 case IOBASE_BRIDGE_NUMBER
:
1398 return (long)hose
->first_busno
;
1400 return (long)hose
->pci_mem_offset
;
1402 return (long)hose
->io_base_phys
;
1404 return (long)isa_io_base
;
1405 case IOBASE_ISA_MEM
:
1413 int pcibus_to_node(struct pci_bus
*bus
)
1415 struct pci_controller
*phb
= pci_bus_to_host(bus
);
1418 EXPORT_SYMBOL(pcibus_to_node
);