2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
22 select HAVE_FUNCTION_GRAPH_TRACER
23 select HAVE_FUNCTION_TRACER
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
29 select ARCH_WANT_OPTIONAL_GPIOLIB
38 config GENERIC_FIND_NEXT_BIT
41 config GENERIC_HWEIGHT
44 config GENERIC_HARDIRQS
47 config GENERIC_IRQ_PROBE
53 config FORCE_MAX_ZONEORDER
57 config GENERIC_CALIBRATE_DELAY
60 config LOCKDEP_SUPPORT
63 config STACKTRACE_SUPPORT
66 config TRACE_IRQFLAGS_SUPPORT
71 source "kernel/Kconfig.preempt"
73 source "kernel/Kconfig.freezer"
75 menu "Blackfin Processor Options"
77 comment "Processor and Board Settings"
86 BF512 Processor Support.
91 BF514 Processor Support.
96 BF516 Processor Support.
101 BF518 Processor Support.
106 BF522 Processor Support.
111 BF523 Processor Support.
116 BF524 Processor Support.
121 BF525 Processor Support.
126 BF526 Processor Support.
131 BF527 Processor Support.
136 BF531 Processor Support.
141 BF532 Processor Support.
146 BF533 Processor Support.
151 BF534 Processor Support.
156 BF536 Processor Support.
161 BF537 Processor Support.
166 BF538 Processor Support.
171 BF539 Processor Support.
176 BF542 Processor Support.
181 BF542 Processor Support.
186 BF544 Processor Support.
191 BF544 Processor Support.
196 BF547 Processor Support.
201 BF547 Processor Support.
206 BF548 Processor Support.
211 BF548 Processor Support.
216 BF549 Processor Support.
221 BF549 Processor Support.
226 BF561 Processor Support.
233 bool "Symmetric multi-processing support"
235 This enables support for systems with more than one CPU,
236 like the dual core BF561. If you have a system with only one
237 CPU, say N. If you have a system with more than one CPU, say Y.
239 If you don't know what to do here, say N.
253 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
254 default 2 if (BF537 || BF536 || BF534)
255 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
256 default 4 if (BF538 || BF539)
260 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
261 default 3 if (BF537 || BF536 || BF534 || BF54xM)
262 default 5 if (BF561 || BF538 || BF539)
263 default 6 if (BF533 || BF532 || BF531)
267 default BF_REV_0_0 if (BF51x || BF52x)
268 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
269 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
273 depends on (BF51x || BF52x || (BF54x && !BF54xM))
277 depends on (BF51x || BF52x || (BF54x && !BF54xM))
281 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
285 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
289 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
293 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
297 depends on (BF533 || BF532 || BF531)
309 depends on (BF512 || BF514 || BF516 || BF518)
314 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
319 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
324 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
329 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
332 config MEM_GENERIC_BOARD
334 depends on GENERIC_BOARD
337 config MEM_MT48LC64M4A2FB_7E
339 depends on (BFIN533_STAMP)
342 config MEM_MT48LC16M16A2TG_75
344 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
345 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
346 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
349 config MEM_MT48LC32M8A2_75
351 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
354 config MEM_MT48LC8M32B2B5_7
356 depends on (BFIN561_BLUETECHNIX_CM)
359 config MEM_MT48LC32M16A2TG_75
361 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
364 config MEM_MT48LC32M8A2_75
366 depends on (BFIN518F_EZBRD)
369 config MEM_MT48H32M16LFCJ_75
371 depends on (BFIN526_EZBRD)
374 source "arch/blackfin/mach-bf518/Kconfig"
375 source "arch/blackfin/mach-bf527/Kconfig"
376 source "arch/blackfin/mach-bf533/Kconfig"
377 source "arch/blackfin/mach-bf561/Kconfig"
378 source "arch/blackfin/mach-bf537/Kconfig"
379 source "arch/blackfin/mach-bf538/Kconfig"
380 source "arch/blackfin/mach-bf548/Kconfig"
382 menu "Board customizations"
385 bool "Default bootloader kernel arguments"
388 string "Initial kernel command string"
389 depends on CMDLINE_BOOL
390 default "console=ttyBF0,57600"
392 If you don't have a boot loader capable of passing a command line string
393 to the kernel, you may specify one here. As a minimum, you should specify
394 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
397 hex "Kernel load address for booting"
399 range 0x1000 0x20000000
401 This option allows you to set the load address of the kernel.
402 This can be useful if you are on a board which has a small amount
403 of memory or you wish to reserve some memory at the beginning of
406 Note that you need to keep this value above 4k (0x1000) as this
407 memory region is used to capture NULL pointer references as well
408 as some core kernel functions.
411 hex "Kernel ROM Base"
414 range 0x20000000 0x20400000 if !(BF54x || BF561)
415 range 0x20000000 0x30000000 if (BF54x || BF561)
418 comment "Clock/PLL Setup"
421 int "Frequency of the crystal on the board in Hz"
422 default "10000000" if BFIN532_IP0X
423 default "11059200" if BFIN533_STAMP
424 default "24576000" if PNAV10
425 default "25000000" # most people use this
426 default "27000000" if BFIN533_EZKIT
427 default "30000000" if BFIN561_EZKIT
429 The frequency of CLKIN crystal oscillator on the board in Hz.
430 Warning: This value should match the crystal on the board. Otherwise,
431 peripherals won't work properly.
433 config BFIN_KERNEL_CLOCK
434 bool "Re-program Clocks while Kernel boots?"
437 This option decides if kernel clocks are re-programed from the
438 bootloader settings. If the clocks are not set, the SDRAM settings
439 are also not changed, and the Bootloader does 100% of the hardware
444 depends on BFIN_KERNEL_CLOCK
449 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
452 If this is set the clock will be divided by 2, before it goes to the PLL.
456 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
458 default "22" if BFIN533_EZKIT
459 default "45" if BFIN533_STAMP
460 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
461 default "22" if BFIN533_BLUETECHNIX_CM
462 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
463 default "20" if BFIN561_EZKIT
464 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
466 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
467 PLL Frequency = (Crystal Frequency) * (this setting)
470 prompt "Core Clock Divider"
471 depends on BFIN_KERNEL_CLOCK
474 This sets the frequency of the core. It can be 1, 2, 4 or 8
475 Core Frequency = (PLL frequency) / (this setting)
491 int "System Clock Divider"
492 depends on BFIN_KERNEL_CLOCK
496 This sets the frequency of the system clock (including SDRAM or DDR).
497 This can be between 1 and 15
498 System Clock = (PLL frequency) / (this setting)
501 prompt "DDR SDRAM Chip Type"
502 depends on BFIN_KERNEL_CLOCK
504 default MEM_MT46V32M16_5B
506 config MEM_MT46V32M16_6T
509 config MEM_MT46V32M16_5B
514 prompt "DDR/SDRAM Timing"
515 depends on BFIN_KERNEL_CLOCK
516 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
518 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
519 The calculated SDRAM timing parameters may not be 100%
520 accurate - This option is therefore marked experimental.
522 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
523 bool "Calculate Timings (EXPERIMENTAL)"
524 depends on EXPERIMENTAL
526 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
527 bool "Provide accurate Timings based on target SCLK"
529 Please consult the Blackfin Hardware Reference Manuals as well
530 as the memory device datasheet.
531 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
534 menu "Memory Init Control"
535 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
552 config MEM_EBIU_DDRQUE
569 # Max & Min Speeds for various Chips
573 default 400000000 if BF512
574 default 400000000 if BF514
575 default 400000000 if BF516
576 default 400000000 if BF518
577 default 600000000 if BF522
578 default 400000000 if BF523
579 default 400000000 if BF524
580 default 600000000 if BF525
581 default 400000000 if BF526
582 default 600000000 if BF527
583 default 400000000 if BF531
584 default 400000000 if BF532
585 default 750000000 if BF533
586 default 500000000 if BF534
587 default 400000000 if BF536
588 default 600000000 if BF537
589 default 533333333 if BF538
590 default 533333333 if BF539
591 default 600000000 if BF542
592 default 533333333 if BF544
593 default 600000000 if BF547
594 default 600000000 if BF548
595 default 533333333 if BF549
596 default 600000000 if BF561
610 comment "Kernel Timer/Scheduler"
612 source kernel/Kconfig.hz
618 config GENERIC_CLOCKEVENTS
619 bool "Generic clock events"
620 depends on GENERIC_TIME
624 prompt "Kernel Tick Source"
625 depends on GENERIC_CLOCKEVENTS
626 default TICKSOURCE_CORETMR
628 config TICKSOURCE_GPTMR0
629 bool "Gptimer0 (SCLK domain)"
632 config TICKSOURCE_CORETMR
633 bool "Core timer (CCLK domain)"
637 config CYCLES_CLOCKSOURCE
638 bool "Use 'CYCLES' as a clocksource"
639 depends on GENERIC_CLOCKEVENTS
640 depends on !BFIN_SCRATCH_REG_CYCLES
643 If you say Y here, you will enable support for using the 'cycles'
644 registers as a clock source. Doing so means you will be unable to
645 safely write to the 'cycles' register during runtime. You will
646 still be able to read it (such as for performance monitoring), but
647 writing the registers will most likely crash the kernel.
649 config GPTMR0_CLOCKSOURCE
650 bool "Use GPTimer0 as a clocksource (higher rating)"
651 depends on GENERIC_CLOCKEVENTS
652 depends on !TICKSOURCE_GPTMR0
654 source kernel/time/Kconfig
659 prompt "Blackfin Exception Scratch Register"
660 default BFIN_SCRATCH_REG_RETN
662 Select the resource to reserve for the Exception handler:
663 - RETN: Non-Maskable Interrupt (NMI)
664 - RETE: Exception Return (JTAG/ICE)
665 - CYCLES: Performance counter
667 If you are unsure, please select "RETN".
669 config BFIN_SCRATCH_REG_RETN
672 Use the RETN register in the Blackfin exception handler
673 as a stack scratch register. This means you cannot
674 safely use NMI on the Blackfin while running Linux, but
675 you can debug the system with a JTAG ICE and use the
676 CYCLES performance registers.
678 If you are unsure, please select "RETN".
680 config BFIN_SCRATCH_REG_RETE
683 Use the RETE register in the Blackfin exception handler
684 as a stack scratch register. This means you cannot
685 safely use a JTAG ICE while debugging a Blackfin board,
686 but you can safely use the CYCLES performance registers
689 If you are unsure, please select "RETN".
691 config BFIN_SCRATCH_REG_CYCLES
694 Use the CYCLES register in the Blackfin exception handler
695 as a stack scratch register. This means you cannot
696 safely use the CYCLES performance registers on a Blackfin
697 board at anytime, but you can debug the system with a JTAG
700 If you are unsure, please select "RETN".
707 menu "Blackfin Kernel Optimizations"
710 comment "Memory Optimizations"
713 bool "Locate interrupt entry code in L1 Memory"
716 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
717 into L1 instruction memory. (less latency)
719 config EXCPT_IRQ_SYSC_L1
720 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
723 If enabled, the entire ASM lowlevel exception and interrupt entry code
724 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
728 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
731 If enabled, the frequently called do_irq dispatcher function is linked
732 into L1 instruction memory. (less latency)
734 config CORE_TIMER_IRQ_L1
735 bool "Locate frequently called timer_interrupt() function in L1 Memory"
738 If enabled, the frequently called timer_interrupt() function is linked
739 into L1 instruction memory. (less latency)
742 bool "Locate frequently idle function in L1 Memory"
745 If enabled, the frequently called idle function is linked
746 into L1 instruction memory. (less latency)
749 bool "Locate kernel schedule function in L1 Memory"
752 If enabled, the frequently called kernel schedule is linked
753 into L1 instruction memory. (less latency)
755 config ARITHMETIC_OPS_L1
756 bool "Locate kernel owned arithmetic functions in L1 Memory"
759 If enabled, arithmetic functions are linked
760 into L1 instruction memory. (less latency)
763 bool "Locate access_ok function in L1 Memory"
766 If enabled, the access_ok function is linked
767 into L1 instruction memory. (less latency)
770 bool "Locate memset function in L1 Memory"
773 If enabled, the memset function is linked
774 into L1 instruction memory. (less latency)
777 bool "Locate memcpy function in L1 Memory"
780 If enabled, the memcpy function is linked
781 into L1 instruction memory. (less latency)
783 config SYS_BFIN_SPINLOCK_L1
784 bool "Locate sys_bfin_spinlock function in L1 Memory"
787 If enabled, sys_bfin_spinlock function is linked
788 into L1 instruction memory. (less latency)
790 config IP_CHECKSUM_L1
791 bool "Locate IP Checksum function in L1 Memory"
794 If enabled, the IP Checksum function is linked
795 into L1 instruction memory. (less latency)
797 config CACHELINE_ALIGNED_L1
798 bool "Locate cacheline_aligned data to L1 Data Memory"
803 If enabled, cacheline_aligned data is linked
804 into L1 data memory. (less latency)
806 config SYSCALL_TAB_L1
807 bool "Locate Syscall Table L1 Data Memory"
811 If enabled, the Syscall LUT is linked
812 into L1 data memory. (less latency)
814 config CPLB_SWITCH_TAB_L1
815 bool "Locate CPLB Switch Tables L1 Data Memory"
819 If enabled, the CPLB Switch Tables are linked
820 into L1 data memory. (less latency)
823 bool "Support locating application stack in L1 Scratch Memory"
826 If enabled the application stack can be located in L1
827 scratch memory (less latency).
829 Currently only works with FLAT binaries.
831 config EXCEPTION_L1_SCRATCH
832 bool "Locate exception stack in L1 Scratch Memory"
834 depends on !APP_STACK_L1
836 Whenever an exception occurs, use the L1 Scratch memory for
837 stack storage. You cannot place the stacks of FLAT binaries
838 in L1 when using this option.
840 If you don't use L1 Scratch, then you should say Y here.
842 comment "Speed Optimizations"
843 config BFIN_INS_LOWOVERHEAD
844 bool "ins[bwl] low overhead, higher interrupt latency"
847 Reads on the Blackfin are speculative. In Blackfin terms, this means
848 they can be interrupted at any time (even after they have been issued
849 on to the external bus), and re-issued after the interrupt occurs.
850 For memory - this is not a big deal, since memory does not change if
853 If a FIFO is sitting on the end of the read, it will see two reads,
854 when the core only sees one since the FIFO receives both the read
855 which is cancelled (and not delivered to the core) and the one which
856 is re-issued (which is delivered to the core).
858 To solve this, interrupts are turned off before reads occur to
859 I/O space. This option controls which the overhead/latency of
860 controlling interrupts during this time
861 "n" turns interrupts off every read
862 (higher overhead, but lower interrupt latency)
863 "y" turns interrupts off every loop
864 (low overhead, but longer interrupt latency)
866 default behavior is to leave this set to on (type "Y"). If you are experiencing
867 interrupt latency issues, it is safe and OK to turn this off.
872 prompt "Kernel executes from"
874 Choose the memory type that the kernel will be running in.
879 The kernel will be resident in RAM when running.
884 The kernel will be resident in FLASH/ROM when running.
891 tristate "Enable Blackfin General Purpose Timers API"
894 Enable support for the General Purpose Timers API. If you
897 To compile this driver as a module, choose M here: the module
898 will be called gptimers.
901 prompt "Uncached DMA region"
902 default DMA_UNCACHED_1M
903 config DMA_UNCACHED_4M
904 bool "Enable 4M DMA region"
905 config DMA_UNCACHED_2M
906 bool "Enable 2M DMA region"
907 config DMA_UNCACHED_1M
908 bool "Enable 1M DMA region"
909 config DMA_UNCACHED_NONE
910 bool "Disable DMA region"
914 comment "Cache Support"
919 config BFIN_ICACHE_LOCK
920 bool "Enable Instruction Cache Locking"
921 depends on BFIN_ICACHE
923 config BFIN_EXTMEM_ICACHEABLE
924 bool "Enable ICACHE for external memory"
925 depends on BFIN_ICACHE
927 config BFIN_L2_ICACHEABLE
928 bool "Enable ICACHE for L2 SRAM"
929 depends on BFIN_ICACHE
930 depends on BF54x || BF561
936 config BFIN_DCACHE_BANKA
937 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
938 depends on BFIN_DCACHE && !BF531
940 config BFIN_EXTMEM_DCACHEABLE
941 bool "Enable DCACHE for external memory"
942 depends on BFIN_DCACHE
945 prompt "External memory DCACHE policy"
946 depends on BFIN_EXTMEM_DCACHEABLE
947 default BFIN_EXTMEM_WRITEBACK if !SMP
948 default BFIN_EXTMEM_WRITETHROUGH if SMP
949 config BFIN_EXTMEM_WRITEBACK
954 Cached data will be written back to SDRAM only when needed.
955 This can give a nice increase in performance, but beware of
956 broken drivers that do not properly invalidate/flush their
959 Write Through Policy:
960 Cached data will always be written back to SDRAM when the
961 cache is updated. This is a completely safe setting, but
962 performance is worse than Write Back.
964 If you are unsure of the options and you want to be safe,
965 then go with Write Through.
967 config BFIN_EXTMEM_WRITETHROUGH
971 Cached data will be written back to SDRAM only when needed.
972 This can give a nice increase in performance, but beware of
973 broken drivers that do not properly invalidate/flush their
976 Write Through Policy:
977 Cached data will always be written back to SDRAM when the
978 cache is updated. This is a completely safe setting, but
979 performance is worse than Write Back.
981 If you are unsure of the options and you want to be safe,
982 then go with Write Through.
986 config BFIN_L2_DCACHEABLE
987 bool "Enable DCACHE for L2 SRAM"
988 depends on BFIN_DCACHE
989 depends on BF54x || BF561
992 prompt "L2 SRAM DCACHE policy"
993 depends on BFIN_L2_DCACHEABLE
994 default BFIN_L2_WRITEBACK
995 config BFIN_L2_WRITEBACK
999 config BFIN_L2_WRITETHROUGH
1000 bool "Write through"
1005 comment "Memory Protection Unit"
1007 bool "Enable the memory protection unit (EXPERIMENTAL)"
1010 Use the processor's MPU to protect applications from accessing
1011 memory they do not own. This comes at a performance penalty
1012 and is recommended only for debugging.
1014 comment "Asynchronous Memory Configuration"
1016 menu "EBIU_AMGCTL Global Control"
1018 bool "Enable CLKOUT"
1022 bool "DMA has priority over core for ext. accesses"
1027 bool "Bank 0 16 bit packing enable"
1032 bool "Bank 1 16 bit packing enable"
1037 bool "Bank 2 16 bit packing enable"
1042 bool "Bank 3 16 bit packing enable"
1046 prompt "Enable Asynchronous Memory Banks"
1050 bool "Disable All Banks"
1053 bool "Enable Bank 0"
1055 config C_AMBEN_B0_B1
1056 bool "Enable Bank 0 & 1"
1058 config C_AMBEN_B0_B1_B2
1059 bool "Enable Bank 0 & 1 & 2"
1062 bool "Enable All Banks"
1066 menu "EBIU_AMBCTL Control"
1068 hex "Bank 0 (AMBCTL0.L)"
1071 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1072 used to control the Asynchronous Memory Bank 0 settings.
1075 hex "Bank 1 (AMBCTL0.H)"
1077 default 0x5558 if BF54x
1079 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1080 used to control the Asynchronous Memory Bank 1 settings.
1083 hex "Bank 2 (AMBCTL1.L)"
1086 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1087 used to control the Asynchronous Memory Bank 2 settings.
1090 hex "Bank 3 (AMBCTL1.H)"
1093 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1094 used to control the Asynchronous Memory Bank 3 settings.
1098 config EBIU_MBSCTLVAL
1099 hex "EBIU Bank Select Control Register"
1104 hex "Flash Memory Mode Control Register"
1109 hex "Flash Memory Bank Control Register"
1114 #############################################################################
1115 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1121 Support for PCI bus.
1123 source "drivers/pci/Kconfig"
1126 bool "Support for hot-pluggable device"
1128 Say Y here if you want to plug devices into your computer while
1129 the system is running, and be able to use them quickly. In many
1130 cases, the devices can likewise be unplugged at any time too.
1132 One well known example of this is PCMCIA- or PC-cards, credit-card
1133 size devices such as network cards, modems or hard drives which are
1134 plugged into slots found on all modern laptop computers. Another
1135 example, used on modern desktops as well as laptops, is USB.
1137 Enable HOTPLUG and build a modular kernel. Get agent software
1138 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1139 Then your kernel will automatically call out to a user mode "policy
1140 agent" (/sbin/hotplug) to load modules and set up software needed
1141 to use devices as you hotplug them.
1143 source "drivers/pcmcia/Kconfig"
1145 source "drivers/pci/hotplug/Kconfig"
1149 menu "Executable file formats"
1151 source "fs/Kconfig.binfmt"
1155 menu "Power management options"
1156 source "kernel/power/Kconfig"
1158 config ARCH_SUSPEND_POSSIBLE
1163 prompt "Standby Power Saving Mode"
1165 default PM_BFIN_SLEEP_DEEPER
1166 config PM_BFIN_SLEEP_DEEPER
1169 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1170 power dissipation by disabling the clock to the processor core (CCLK).
1171 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1172 to 0.85 V to provide the greatest power savings, while preserving the
1174 The PLL and system clock (SCLK) continue to operate at a very low
1175 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1176 the SDRAM is put into Self Refresh Mode. Typically an external event
1177 such as GPIO interrupt or RTC activity wakes up the processor.
1178 Various Peripherals such as UART, SPORT, PPI may not function as
1179 normal during Sleep Deeper, due to the reduced SCLK frequency.
1180 When in the sleep mode, system DMA access to L1 memory is not supported.
1182 If unsure, select "Sleep Deeper".
1184 config PM_BFIN_SLEEP
1187 Sleep Mode (High Power Savings) - The sleep mode reduces power
1188 dissipation by disabling the clock to the processor core (CCLK).
1189 The PLL and system clock (SCLK), however, continue to operate in
1190 this mode. Typically an external event or RTC activity will wake
1191 up the processor. When in the sleep mode, system DMA access to L1
1192 memory is not supported.
1194 If unsure, select "Sleep Deeper".
1197 config PM_WAKEUP_BY_GPIO
1198 bool "Allow Wakeup from Standby by GPIO"
1199 depends on PM && !BF54x
1201 config PM_WAKEUP_GPIO_NUMBER
1204 depends on PM_WAKEUP_BY_GPIO
1208 prompt "GPIO Polarity"
1209 depends on PM_WAKEUP_BY_GPIO
1210 default PM_WAKEUP_GPIO_POLAR_H
1211 config PM_WAKEUP_GPIO_POLAR_H
1213 config PM_WAKEUP_GPIO_POLAR_L
1215 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1217 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1219 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1223 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1226 config PM_BFIN_WAKE_PH6
1227 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1228 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1231 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1233 config PM_BFIN_WAKE_GP
1234 bool "Allow Wake-Up from GPIOs"
1235 depends on PM && BF54x
1238 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1239 (all processors, except ADSP-BF549). This option sets
1240 the general-purpose wake-up enable (GPWE) control bit to enable
1241 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1242 On ADSP-BF549 this option enables the the same functionality on the
1243 /MRXON pin also PH7.
1247 menu "CPU Frequency scaling"
1249 source "drivers/cpufreq/Kconfig"
1251 config BFIN_CPU_FREQ
1254 select CPU_FREQ_TABLE
1258 bool "CPU Voltage scaling"
1259 depends on EXPERIMENTAL
1263 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1264 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1265 manuals. There is a theoretical risk that during VDDINT transitions
1270 source "net/Kconfig"
1272 source "drivers/Kconfig"
1276 source "arch/blackfin/Kconfig.debug"
1278 source "security/Kconfig"
1280 source "crypto/Kconfig"
1282 source "lib/Kconfig"