drivers/serial/sh-sci.h

   1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
   2  *
   3  *  linux/drivers/serial/sh-sci.h
   4  *
   5  *  SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   6  *  Copyright (C) 1999, 2000  Niibe Yutaka
   7  *  Copyright (C) 2000  Greg Banks
   8  *  Copyright (C) 2002, 2003  Paul Mundt
   9  *  Modified to support multiple serial ports. Stuart Menefy (May 2000).
  10  *  Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
  11  *  Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
  12  */
  13 #include <linux/config.h>
  14 #include <linux/serial_core.h>
  15 #include <asm/io.h>
  16
  17 #if defined(__H8300H__) || defined(__H8300S__)
  18 #include <asm/gpio.h>
  19 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  20 #include <asm/regs306x.h>
  21 #endif
  22 #if defined(CONFIG_H8S2678)
  23 #include <asm/regs267x.h>
  24 #endif
  25 #endif
  26
  27 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
  28 # define SCSPTR 0xffffff7c /* 8 bit */
  29 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  30 # define SCI_ONLY
  31 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  32       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
  33       defined(CONFIG_CPU_SUBTYPE_SH7706)
  34 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  35 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  36 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  37 # define SCI_AND_SCIF
  38 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  39 # define SCIF0          0xA4400000
  40 # define SCIF2          0xA4410000
  41 # define SCSMR_Ir       0xA44A0000
  42 # define IRDA_SCIF      SCIF0
  43 # define SCPCR 0xA4000116
  44 # define SCPDR 0xA4000136
  45
  46 /* Set the clock source,
  47  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  48  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  49  */
  50 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  51 # define SCIF_ONLY
  52 #elif defined(CONFIG_SH_RTS7751R2D)
  53 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  54 # define SCIF_ORER 0x0001   /* overrun error bit */
  55 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  56 # define SCIF_ONLY
  57 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
  58 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  59 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  60 # define SCIF_ORER 0x0001   /* overrun error bit */
  61 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  62         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  63         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  64 # define SCI_AND_SCIF
  65 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  66 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  67 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  68 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  69 # define SCIF_ORER 0x0001  /* overrun error bit */
  70 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  71 # define SCIF_ONLY
  72 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
  73 # define SCPCR  0xA4050116        /* 16 bit SCIF */
  74 # define SCPDR  0xA4050136        /* 16 bit SCIF */
  75 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  76 # define SCIF_ONLY
  77 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
  78 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  79 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  80 # define SCIF_ONLY
  81 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
  82 # define SCPDR  0xA4050138        /* 16 bit SCIF */
  83 # define SCSPTR2 SCPDR
  84 # define SCIF_ORER 0x0001   /* overrun error bit */
  85 # define SCSCR_INIT(port)  0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
  86 # define SCIF_ONLY
  87 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  88 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  89 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  90 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  91 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  92 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  93 # define SCIF_ONLY
  94 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
  95 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
  96 # define SCIF_ORER 0x0001   /* overrun error bit */
  97 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  98 # define SCIF_ONLY
  99 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 100 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
 101 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 102 # define SCIF_ORER 0x0001   /* overrun error bit */
 103 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 104 # define SCIF_ONLY
 105 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 106 # include <asm/hardware.h>
 107 # define SCIF_BASE_ADDR    0x01030000
 108 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 109 # define SCIF_PTR2_OFFS    0x0000020
 110 # define SCIF_LSR2_OFFS    0x0000024
 111 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 112 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 113 # define SCSCR_INIT(port)  0x38                           /* TIE=0,RIE=0,
 114                                                              TE=1,RE=1,REIE=1 */
 115 # define SCIF_ONLY
 116 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 117 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 118 # define SCI_ONLY
 119 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 120 #elif defined(CONFIG_H8S2678)
 121 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 122 # define SCI_ONLY
 123 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 124 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 125 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 126 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 127 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 128 # define SCIF_ORER 0x0001  /* overrun error bit */
 129 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 130 # define SCIF_ONLY
 131 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 132 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 133 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 134 # define SCIF_ORER      0x0001          /* Overrun error bit */
 135 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 136 # define SCIF_ONLY
 137 #else
 138 # error CPU subtype not defined
 139 #endif
 140
 141 /* SCSCR */
 142 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 143 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 144 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 145 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 146 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
 147 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 148 #else
 149 #define SCI_CTRL_FLAGS_REIE 0
 150 #endif
 151 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 152 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 153 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 154 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 155
 156 /* SCxSR SCI */
 157 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 158 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 159 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 160 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 161 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 162 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 163 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 164 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 165
 166 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 167
 168 /* SCxSR SCIF */
 169 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 170 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 171 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 172 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 173 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 174 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 175 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 176 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 177
 178 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 179 #define SCIF_ORER    0x0200
 180 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 181 #define SCIF_RFDC_MASK 0x007f
 182 #define SCIF_TXROOM_MAX 64
 183 #else
 184 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 185 #define SCIF_RFDC_MASK 0x001f
 186 #define SCIF_TXROOM_MAX 16
 187 #endif
 188
 189 #if defined(SCI_ONLY)
 190 # define SCxSR_TEND(port)               SCI_TEND
 191 # define SCxSR_ERRORS(port)             SCI_ERRORS
 192 # define SCxSR_RDxF(port)               SCI_RDRF
 193 # define SCxSR_TDxE(port)               SCI_TDRE
 194 # define SCxSR_ORER(port)               SCI_ORER
 195 # define SCxSR_FER(port)                SCI_FER
 196 # define SCxSR_PER(port)                SCI_PER
 197 # define SCxSR_BRK(port)                0x00
 198 # define SCxSR_RDxF_CLEAR(port)         0xbc
 199 # define SCxSR_ERROR_CLEAR(port)        0xc4
 200 # define SCxSR_TDxE_CLEAR(port)         0x78
 201 # define SCxSR_BREAK_CLEAR(port)        0xc4
 202 #elif defined(SCIF_ONLY)
 203 # define SCxSR_TEND(port)               SCIF_TEND
 204 # define SCxSR_ERRORS(port)             SCIF_ERRORS
 205 # define SCxSR_RDxF(port)               SCIF_RDF
 206 # define SCxSR_TDxE(port)               SCIF_TDFE
 207 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 208 # define SCxSR_ORER(port)               SCIF_ORER
 209 #else
 210 # define SCxSR_ORER(port)               0x0000
 211 #endif
 212 # define SCxSR_FER(port)                SCIF_FER
 213 # define SCxSR_PER(port)                SCIF_PER
 214 # define SCxSR_BRK(port)                SCIF_BRK
 215 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 216 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 217 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 218 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 219 # define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
 220 #else
 221 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
 222 # define SCxSR_RDxF_CLEAR(port)         0x00fc
 223 # define SCxSR_ERROR_CLEAR(port)        0x0073
 224 # define SCxSR_TDxE_CLEAR(port)         0x00df
 225 # define SCxSR_BREAK_CLEAR(port)        0x00e3
 226 #endif
 227 #else
 228 # define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 229 # define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 230 # define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 231 # define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 232 # define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
 233 # define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 234 # define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 235 # define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 236 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 237 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 238 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 239 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 240 #endif
 241
 242 /* SCFCR */
 243 #define SCFCR_RFRST 0x0002
 244 #define SCFCR_TFRST 0x0004
 245 #define SCFCR_TCRST 0x4000
 246 #define SCFCR_MCE   0x0008
 247
 248 #define SCI_MAJOR               204
 249 #define SCI_MINOR_START         8
 250
 251 /* Generic serial flags */
 252 #define SCI_RX_THROTTLE         0x0000001
 253
 254 #define SCI_MAGIC 0xbabeface
 255
 256 /*
 257  * Events are used to schedule things to happen at timer-interrupt
 258  * time, instead of at rs interrupt time.
 259  */
 260 #define SCI_EVENT_WRITE_WAKEUP  0
 261
 262 #define SCI_IN(size, offset)                                    \
 263   unsigned int addr = port->mapbase + (offset);                 \
 264   if ((size) == 8) {                                            \
 265     return ctrl_inb(addr);                                      \
 266   } else {                                                      \
 267     return ctrl_inw(addr);                                      \
 268   }
 269 #define SCI_OUT(size, offset, value)                            \
 270   unsigned int addr = port->mapbase + (offset);                 \
 271   if ((size) == 8) {                                            \
 272     ctrl_outb(value, addr);                                     \
 273   } else {                                                      \
 274     ctrl_outw(value, addr);                                     \
 275   }
 276
 277 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 278   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 279   {                                                                     \
 280     if (port->type == PORT_SCI) {                                       \
 281       SCI_IN(sci_size, sci_offset)                                      \
 282     } else {                                                            \
 283       SCI_IN(scif_size, scif_offset);                                   \
 284     }                                                                   \
 285   }                                                                     \
 286   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 287   {                                                                     \
 288     if (port->type == PORT_SCI) {                                       \
 289       SCI_OUT(sci_size, sci_offset, value)                              \
 290     } else {                                                            \
 291       SCI_OUT(scif_size, scif_offset, value);                           \
 292     }                                                                   \
 293   }
 294
 295 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 296   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 297   {                                                                     \
 298     SCI_IN(scif_size, scif_offset);                                     \
 299   }                                                                     \
 300   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 301   {                                                                     \
 302     SCI_OUT(scif_size, scif_offset, value);                             \
 303   }
 304
 305 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 306   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 307   {                                                                     \
 308     SCI_IN(sci_size, sci_offset);                                       \
 309   }                                                                     \
 310   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 311   {                                                                     \
 312     SCI_OUT(sci_size, sci_offset, value);                               \
 313   }
 314
 315 #ifdef CONFIG_CPU_SH3
 316 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 317     defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 318     defined(CONFIG_CPU_SUBTYPE_SH7710)
 319 #define SCIF_FNS(name, scif_offset, scif_size) \
 320   CPU_SCIF_FNS(name, scif_offset, scif_size)
 321 #else
 322 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 323                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 324                  h8_sci_offset, h8_sci_size) \
 325   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 326 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 327   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 328 #endif
 329 #elif defined(__H8300H__) || defined(__H8300S__)
 330 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 331                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 332                  h8_sci_offset, h8_sci_size) \
 333   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 334 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 335 #else
 336 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 337                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 338                  h8_sci_offset, h8_sci_size) \
 339   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 340 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 341   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 342 #endif
 343
 344 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 345     defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 346     defined(CONFIG_CPU_SUBTYPE_SH7710)
 347 SCIF_FNS(SCSMR,  0x00, 16)
 348 SCIF_FNS(SCBRR,  0x04,  8)
 349 SCIF_FNS(SCSCR,  0x08, 16)
 350 SCIF_FNS(SCTDSR, 0x0c,  8)
 351 SCIF_FNS(SCFER,  0x10, 16)
 352 SCIF_FNS(SCxSR,  0x14, 16)
 353 SCIF_FNS(SCFCR,  0x18, 16)
 354 SCIF_FNS(SCFDR,  0x1c, 16)
 355 SCIF_FNS(SCxTDR, 0x20,  8)
 356 SCIF_FNS(SCxRDR, 0x24,  8)
 357 SCIF_FNS(SCLSR,  0x24, 16)
 358 #else
 359 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 360 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 361 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 362 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 363 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 364 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 365 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 366 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 367 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 368 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
 369 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 370 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 371 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 372 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 373 #else
 374 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 375 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 376 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 377 #endif
 378 #endif
 379 #define sci_in(port, reg) sci_##reg##_in(port)
 380 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 381
 382 /* H8/300 series SCI pins assignment */
 383 #if defined(__H8300H__) || defined(__H8300S__)
 384 static const struct __attribute__((packed)) {
 385         int port;             /* GPIO port no */
 386         unsigned short rx,tx; /* GPIO bit no */
 387 } h8300_sci_pins[] = {
 388 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 389         {    /* SCI0 */
 390                 .port = H8300_GPIO_P9,
 391                 .rx   = H8300_GPIO_B2,
 392                 .tx   = H8300_GPIO_B0,
 393         },
 394         {    /* SCI1 */
 395                 .port = H8300_GPIO_P9,
 396                 .rx   = H8300_GPIO_B3,
 397                 .tx   = H8300_GPIO_B1,
 398         },
 399         {    /* SCI2 */
 400                 .port = H8300_GPIO_PB,
 401                 .rx   = H8300_GPIO_B7,
 402                 .tx   = H8300_GPIO_B6,
 403         }
 404 #elif defined(CONFIG_H8S2678)
 405         {    /* SCI0 */
 406                 .port = H8300_GPIO_P3,
 407                 .rx   = H8300_GPIO_B2,
 408                 .tx   = H8300_GPIO_B0,
 409         },
 410         {    /* SCI1 */
 411                 .port = H8300_GPIO_P3,
 412                 .rx   = H8300_GPIO_B3,
 413                 .tx   = H8300_GPIO_B1,
 414         },
 415         {    /* SCI2 */
 416                 .port = H8300_GPIO_P5,
 417                 .rx   = H8300_GPIO_B1,
 418                 .tx   = H8300_GPIO_B0,
 419         }
 420 #endif
 421 };
 422 #endif
 423
 424 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
 425 static inline int sci_rxd_in(struct uart_port *port)
 426 {
 427         if (port->mapbase == 0xfffffe80)
 428                 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
 429         return 1;
 430 }
 431 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 432       defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 433       defined(CONFIG_CPU_SUBTYPE_SH7706)
 434 static inline int sci_rxd_in(struct uart_port *port)
 435 {
 436         if (port->mapbase == 0xfffffe80)
 437                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 438         if (port->mapbase == 0xa4000150)
 439                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 440         if (port->mapbase == 0xa4000140)
 441                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 442         return 1;
 443 }
 444 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 445 static inline int sci_rxd_in(struct uart_port *port)
 446 {
 447         if (port->mapbase == SCIF0)
 448                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 449         if (port->mapbase == SCIF2)
 450                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 451         return 1;
 452 }
 453 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
 454 static inline int sci_rxd_in(struct uart_port *port)
 455 {
 456         if (port->mapbase == SCSPTR0)
 457                 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0;
 458         return 1;
 459 }
 460 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 461       defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 462       defined(CONFIG_CPU_SUBTYPE_SH4_202)
 463 static inline int sci_rxd_in(struct uart_port *port)
 464 {
 465 #ifndef SCIF_ONLY
 466         if (port->mapbase == 0xffe00000)
 467                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 468 #endif
 469 #ifndef SCI_ONLY
 470         if (port->mapbase == 0xffe80000)
 471                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 472 #endif
 473         return 1;
 474 }
 475 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 476 static inline int sci_rxd_in(struct uart_port *port)
 477 {
 478         if (port->mapbase == 0xfe600000)
 479                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 480         if (port->mapbase == 0xfe610000)
 481                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 482         if (port->mapbase == 0xfe620000)
 483                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 484 }
 485 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
 486 static inline int sci_rxd_in(struct uart_port *port)
 487 {
 488         if (port->mapbase == 0xa4430000)
 489                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 490         return 1;
 491 }
 492 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
 493 static inline int sci_rxd_in(struct uart_port *port)
 494 {
 495         return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 496 }
 497 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 498 static inline int sci_rxd_in(struct uart_port *port)
 499 {
 500         if (port->mapbase == 0xffe00000)
 501                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 502         if (port->mapbase == 0xffe10000)
 503                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 504         if (port->mapbase == 0xffe20000)
 505                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 506         if (port->mapbase == 0xffe30000)
 507                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 508         return 1;
 509 }
 510 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 511 static inline int sci_rxd_in(struct uart_port *port)
 512 {
 513         if (port->mapbase == 0xffe00000)
 514                 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
 515         else
 516                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 517
 518 }
 519 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 520 static inline int sci_rxd_in(struct uart_port *port)
 521 {
 522          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 523 }
 524 #elif defined(__H8300H__) || defined(__H8300S__)
 525 static inline int sci_rxd_in(struct uart_port *port)
 526 {
 527         int ch = (port->mapbase - SMR0) >> 3;
 528         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 529 }
 530 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 531 static inline int sci_rxd_in(struct uart_port *port)
 532 {
 533         if (port->mapbase == 0xff923000)
 534                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 535         if (port->mapbase == 0xff924000)
 536                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 537         if (port->mapbase == 0xff925000)
 538                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 539 }
 540 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 541 static inline int sci_rxd_in(struct uart_port *port)
 542 {
 543         if (port->mapbase == 0xffe00000)
 544                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 545         if (port->mapbase == 0xffe10000)
 546                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 547 }
 548 #endif
 549
 550 /*
 551  * Values for the BitRate Register (SCBRR)
 552  *
 553  * The values are actually divisors for a frequency which can
 554  * be internal to the SH3 (14.7456MHz) or derived from an external
 555  * clock source.  This driver assumes the internal clock is used;
 556  * to support using an external clock source, config options or
 557  * possibly command-line options would need to be added.
 558  *
 559  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 560  * the SCSMR register would also need to be set to non-zero values.
 561  *
 562  * -- Greg Banks 27Feb2000
 563  *
 564  * Answer: The SCBRR register is only eight bits, and the value in
 565  * it gets larger with lower baud rates. At around 2400 (depending on
 566  * the peripherial module clock) you run out of bits. However the
 567  * lower two bits of SCSMR allow the module clock to be divided down,
 568  * scaling the value which is needed in SCBRR.
 569  *
 570  * -- Stuart Menefy - 23 May 2000
 571  *
 572  * I meant, why would anyone bother with bitrates below 2400.
 573  *
 574  * -- Greg Banks - 7Jul2000
 575  *
 576  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 577  * tape reader as a console!
 578  *
 579  * -- Mitch Davis - 15 Jul 2000
 580  */
 581
 582 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
 583 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 584 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 585 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 586 #elif defined(__H8300H__) || defined(__H8300S__)
 587 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
 588 #elif defined(CONFIG_SUPERH64)
 589 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
 590 #else /* Generic SH */
 591 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 592 #endif