2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/string.h>
20 #include <linux/log2.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
24 unsigned int pci_pm_d3_delay
= 10;
26 #ifdef CONFIG_PCI_DOMAINS
27 int pci_domains_supported
= 1;
30 #define DEFAULT_CARDBUS_IO_SIZE (256)
31 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
33 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
34 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
43 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
45 struct list_head
*tmp
;
48 max
= bus
->subordinate
;
49 list_for_each(tmp
, &bus
->children
) {
50 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
56 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
60 * pci_max_busnr - returns maximum PCI bus number
62 * Returns the highest PCI bus number present in the system global list of
65 unsigned char __devinit
68 struct pci_bus
*bus
= NULL
;
72 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
73 n
= pci_bus_max_busnr(bus
);
82 #define PCI_FIND_CAP_TTL 48
84 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
85 u8 pos
, int cap
, int *ttl
)
90 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
94 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
100 pos
+= PCI_CAP_LIST_NEXT
;
105 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
108 int ttl
= PCI_FIND_CAP_TTL
;
110 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
113 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
115 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
116 pos
+ PCI_CAP_LIST_NEXT
, cap
);
118 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
120 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
121 unsigned int devfn
, u8 hdr_type
)
125 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
126 if (!(status
& PCI_STATUS_CAP_LIST
))
130 case PCI_HEADER_TYPE_NORMAL
:
131 case PCI_HEADER_TYPE_BRIDGE
:
132 return PCI_CAPABILITY_LIST
;
133 case PCI_HEADER_TYPE_CARDBUS
:
134 return PCI_CB_CAPABILITY_LIST
;
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
161 int pci_find_capability(struct pci_dev
*dev
, int cap
)
165 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
167 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
173 * pci_bus_find_capability - query for devices' capabilities
174 * @bus: the PCI bus to query
175 * @devfn: PCI device to query
176 * @cap: capability code
178 * Like pci_find_capability() but works for pci devices that do not have a
179 * pci_dev structure set up yet.
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
185 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
190 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
192 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
194 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
200 * pci_find_ext_capability - Find an extended capability
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Returns the address of the requested extended capability structure
205 * within the device's PCI configuration space or 0 if the device does
206 * not support it. Possible values for @cap:
208 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
209 * %PCI_EXT_CAP_ID_VC Virtual Channel
210 * %PCI_EXT_CAP_ID_DSN Device Serial Number
211 * %PCI_EXT_CAP_ID_PWR Power Budgeting
213 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
216 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
219 if (dev
->cfg_size
<= 256)
222 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
226 * If we have no capabilities, this is indicated by cap ID,
227 * cap version and next pointer all being 0.
233 if (PCI_EXT_CAP_ID(header
) == cap
)
236 pos
= PCI_EXT_CAP_NEXT(header
);
240 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
246 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
248 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
250 int rc
, ttl
= PCI_FIND_CAP_TTL
;
253 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
254 mask
= HT_3BIT_CAP_MASK
;
256 mask
= HT_5BIT_CAP_MASK
;
258 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
259 PCI_CAP_ID_HT
, &ttl
);
261 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
262 if (rc
!= PCIBIOS_SUCCESSFUL
)
265 if ((cap
& mask
) == ht_cap
)
268 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
269 pos
+ PCI_CAP_LIST_NEXT
,
270 PCI_CAP_ID_HT
, &ttl
);
276 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
277 * @dev: PCI device to query
278 * @pos: Position from which to continue searching
279 * @ht_cap: Hypertransport capability code
281 * To be used in conjunction with pci_find_ht_capability() to search for
282 * all capabilities matching @ht_cap. @pos should always be a value returned
283 * from pci_find_ht_capability().
285 * NB. To be 100% safe against broken PCI devices, the caller should take
286 * steps to avoid an infinite loop.
288 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
290 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
292 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
295 * pci_find_ht_capability - query a device's Hypertransport capabilities
296 * @dev: PCI device to query
297 * @ht_cap: Hypertransport capability code
299 * Tell if a device supports a given Hypertransport capability.
300 * Returns an address within the device's PCI configuration space
301 * or 0 in case the device does not support the request capability.
302 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
303 * which has a Hypertransport capability matching @ht_cap.
305 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
309 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
311 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
315 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
317 void pcie_wait_pending_transaction(struct pci_dev
*dev
)
322 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
326 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, ®16
);
327 if (!(reg16
& PCI_EXP_DEVSTA_TRPND
))
333 EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction
);
336 * pci_find_parent_resource - return resource region of parent bus of given region
337 * @dev: PCI device structure contains resources to be searched
338 * @res: child resource record for which parent is sought
340 * For given resource region of given device, return the resource
341 * region of parent bus the given region is contained in or where
342 * it should be allocated from.
345 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
347 const struct pci_bus
*bus
= dev
->bus
;
349 struct resource
*best
= NULL
;
351 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
352 struct resource
*r
= bus
->resource
[i
];
355 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
356 continue; /* Not contained */
357 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
358 continue; /* Wrong type */
359 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
360 return r
; /* Exact match */
361 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
362 best
= r
; /* Approximating prefetchable by non-prefetchable */
368 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
369 * @dev: PCI device to have its BARs restored
371 * Restore the BAR values for a given device, so as to make it
372 * accessible by its driver.
375 pci_restore_bars(struct pci_dev
*dev
)
379 switch (dev
->hdr_type
) {
380 case PCI_HEADER_TYPE_NORMAL
:
383 case PCI_HEADER_TYPE_BRIDGE
:
386 case PCI_HEADER_TYPE_CARDBUS
:
390 /* Should never get here, but just in case... */
394 for (i
= 0; i
< numres
; i
++)
395 pci_update_resource(dev
, &dev
->resource
[i
], i
);
398 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
401 * pci_set_power_state - Set the power state of a PCI device
402 * @dev: PCI device to be suspended
403 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
405 * Transition a device to a new power state, using the Power Management
406 * Capabilities in the device's config space.
409 * -EINVAL if trying to enter a lower state than we're already in.
410 * 0 if we're already in the requested state.
411 * -EIO if device does not support PCI PM.
412 * 0 if we can successfully change the power state.
415 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
417 int pm
, need_restore
= 0;
420 /* bound the state we're entering */
421 if (state
> PCI_D3hot
)
425 * If the device or the parent bridge can't support PCI PM, ignore
426 * the request if we're doing anything besides putting it into D0
427 * (which would only happen on boot).
429 if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
432 /* find PCI PM capability in list */
433 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
435 /* abort if the device doesn't support PM capabilities */
439 /* Validate current state:
440 * Can enter D0 from any state, but if we can only go deeper
441 * to sleep if we're already in a low power state
443 if (state
!= PCI_D0
&& dev
->current_state
> state
) {
444 printk(KERN_ERR
"%s(): %s: state=%d, current state=%d\n",
445 __FUNCTION__
, pci_name(dev
), state
, dev
->current_state
);
447 } else if (dev
->current_state
== state
)
448 return 0; /* we're already there */
451 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
452 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
454 "PCI: %s has unsupported PM cap regs version (%u)\n",
455 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
459 /* check if this device supports the desired state */
460 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
462 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
465 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
467 /* If we're (effectively) in D3, force entire word to 0.
468 * This doesn't affect PME_Status, disables PME_En, and
469 * sets PowerState to 0.
471 switch (dev
->current_state
) {
475 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
478 case PCI_UNKNOWN
: /* Boot-up */
479 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
480 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
482 /* Fall-through: force to D0 */
488 /* enter specified state */
489 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
491 /* Mandatory power management transition delays */
492 /* see PCI PM 1.1 5.6.1 table 18 */
493 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
494 msleep(pci_pm_d3_delay
);
495 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
499 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
500 * Firmware method after native method ?
502 if (platform_pci_set_power_state
)
503 platform_pci_set_power_state(dev
, state
);
505 dev
->current_state
= state
;
507 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
508 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
509 * from D3hot to D0 _may_ perform an internal reset, thereby
510 * going to "D0 Uninitialized" rather than "D0 Initialized".
511 * For example, at least some versions of the 3c905B and the
512 * 3c556B exhibit this behaviour.
514 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
515 * devices in a D3hot state at boot. Consequently, we need to
516 * restore at least the BARs so that the device will be
517 * accessible to its driver.
520 pci_restore_bars(dev
);
525 pci_power_t (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
528 * pci_choose_state - Choose the power state of a PCI device
529 * @dev: PCI device to be suspended
530 * @state: target sleep state for the whole system. This is the value
531 * that is passed to suspend() function.
533 * Returns PCI power state suitable for given device and given system
537 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
541 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
544 if (platform_pci_choose_state
) {
545 ret
= platform_pci_choose_state(dev
, state
);
546 if (ret
!= PCI_POWER_ERROR
)
550 switch (state
.event
) {
553 case PM_EVENT_FREEZE
:
554 case PM_EVENT_PRETHAW
:
555 /* REVISIT both freeze and pre-thaw "should" use D0 */
556 case PM_EVENT_SUSPEND
:
559 printk("Unrecognized suspend event %d\n", state
.event
);
565 EXPORT_SYMBOL(pci_choose_state
);
567 static int pci_save_pcie_state(struct pci_dev
*dev
)
570 struct pci_cap_saved_state
*save_state
;
573 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
577 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
579 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
) * 4, GFP_KERNEL
);
581 dev_err(&dev
->dev
, "Out of memory in pci_save_pcie_state\n");
584 cap
= (u16
*)&save_state
->data
[0];
586 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
587 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
588 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
589 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
590 save_state
->cap_nr
= PCI_CAP_ID_EXP
;
591 pci_add_saved_cap(dev
, save_state
);
595 static void pci_restore_pcie_state(struct pci_dev
*dev
)
598 struct pci_cap_saved_state
*save_state
;
601 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
602 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
603 if (!save_state
|| pos
<= 0)
605 cap
= (u16
*)&save_state
->data
[0];
607 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
608 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
609 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
610 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
614 static int pci_save_pcix_state(struct pci_dev
*dev
)
617 struct pci_cap_saved_state
*save_state
;
620 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
624 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
626 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
), GFP_KERNEL
);
628 dev_err(&dev
->dev
, "Out of memory in pci_save_pcie_state\n");
631 cap
= (u16
*)&save_state
->data
[0];
633 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, &cap
[i
++]);
634 save_state
->cap_nr
= PCI_CAP_ID_PCIX
;
635 pci_add_saved_cap(dev
, save_state
);
639 static void pci_restore_pcix_state(struct pci_dev
*dev
)
642 struct pci_cap_saved_state
*save_state
;
645 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
646 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
647 if (!save_state
|| pos
<= 0)
649 cap
= (u16
*)&save_state
->data
[0];
651 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
656 * pci_save_state - save the PCI configuration space of a device before suspending
657 * @dev: - PCI device that we're dealing with
660 pci_save_state(struct pci_dev
*dev
)
663 /* XXX: 100% dword access ok here? */
664 for (i
= 0; i
< 16; i
++)
665 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
666 if ((i
= pci_save_pcie_state(dev
)) != 0)
668 if ((i
= pci_save_pcix_state(dev
)) != 0)
674 * pci_restore_state - Restore the saved state of a PCI device
675 * @dev: - PCI device that we're dealing with
678 pci_restore_state(struct pci_dev
*dev
)
683 /* PCI Express register must be restored first */
684 pci_restore_pcie_state(dev
);
687 * The Base Address register should be programmed before the command
690 for (i
= 15; i
>= 0; i
--) {
691 pci_read_config_dword(dev
, i
* 4, &val
);
692 if (val
!= dev
->saved_config_space
[i
]) {
693 printk(KERN_DEBUG
"PM: Writing back config space on "
694 "device %s at offset %x (was %x, writing %x)\n",
696 val
, (int)dev
->saved_config_space
[i
]);
697 pci_write_config_dword(dev
,i
* 4,
698 dev
->saved_config_space
[i
]);
701 pci_restore_pcix_state(dev
);
702 pci_restore_msi_state(dev
);
707 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
711 err
= pci_set_power_state(dev
, PCI_D0
);
712 if (err
< 0 && err
!= -EIO
)
714 err
= pcibios_enable_device(dev
, bars
);
717 pci_fixup_device(pci_fixup_enable
, dev
);
723 * pci_reenable_device - Resume abandoned device
724 * @dev: PCI device to be resumed
726 * Note this function is a backend of pci_default_resume and is not supposed
727 * to be called by normal code, write proper resume handler and use it instead.
729 int pci_reenable_device(struct pci_dev
*dev
)
731 if (atomic_read(&dev
->enable_cnt
))
732 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
737 * pci_enable_device_bars - Initialize some of a device for use
738 * @dev: PCI device to be initialized
739 * @bars: bitmask of BAR's that must be configured
741 * Initialize device before it's used by a driver. Ask low-level code
742 * to enable selected I/O and memory resources. Wake up the device if it
743 * was suspended. Beware, this function can fail.
746 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
750 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
751 return 0; /* already enabled */
753 err
= do_pci_enable_device(dev
, bars
);
755 atomic_dec(&dev
->enable_cnt
);
760 * pci_enable_device - Initialize device before it's used by a driver.
761 * @dev: PCI device to be initialized
763 * Initialize device before it's used by a driver. Ask low-level code
764 * to enable I/O and memory. Wake up the device if it was suspended.
765 * Beware, this function can fail.
767 * Note we don't actually enable the device many times if we call
768 * this function repeatedly (we just increment the count).
770 int pci_enable_device(struct pci_dev
*dev
)
772 return pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
776 * Managed PCI resources. This manages device on/off, intx/msi/msix
777 * on/off and BAR regions. pci_dev itself records msi/msix status, so
778 * there's no need to track it separately. pci_devres is initialized
779 * when a device is enabled using managed PCI device enable interface.
782 unsigned int enabled
:1;
783 unsigned int pinned
:1;
784 unsigned int orig_intx
:1;
785 unsigned int restore_intx
:1;
789 static void pcim_release(struct device
*gendev
, void *res
)
791 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
792 struct pci_devres
*this = res
;
795 if (dev
->msi_enabled
)
796 pci_disable_msi(dev
);
797 if (dev
->msix_enabled
)
798 pci_disable_msix(dev
);
800 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
801 if (this->region_mask
& (1 << i
))
802 pci_release_region(dev
, i
);
804 if (this->restore_intx
)
805 pci_intx(dev
, this->orig_intx
);
807 if (this->enabled
&& !this->pinned
)
808 pci_disable_device(dev
);
811 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
813 struct pci_devres
*dr
, *new_dr
;
815 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
819 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
822 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
825 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
827 if (pci_is_managed(pdev
))
828 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
833 * pcim_enable_device - Managed pci_enable_device()
834 * @pdev: PCI device to be initialized
836 * Managed pci_enable_device().
838 int pcim_enable_device(struct pci_dev
*pdev
)
840 struct pci_devres
*dr
;
843 dr
= get_pci_dr(pdev
);
846 WARN_ON(!!dr
->enabled
);
848 rc
= pci_enable_device(pdev
);
850 pdev
->is_managed
= 1;
857 * pcim_pin_device - Pin managed PCI device
858 * @pdev: PCI device to pin
860 * Pin managed PCI device @pdev. Pinned device won't be disabled on
861 * driver detach. @pdev must have been enabled with
862 * pcim_enable_device().
864 void pcim_pin_device(struct pci_dev
*pdev
)
866 struct pci_devres
*dr
;
868 dr
= find_pci_dr(pdev
);
869 WARN_ON(!dr
|| !dr
->enabled
);
875 * pcibios_disable_device - disable arch specific PCI resources for device dev
876 * @dev: the PCI device to disable
878 * Disables architecture specific PCI resources for the device. This
879 * is the default implementation. Architecture implementations can
882 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
885 * pci_disable_device - Disable PCI device after use
886 * @dev: PCI device to be disabled
888 * Signal to the system that the PCI device is not in use by the system
889 * anymore. This only involves disabling PCI bus-mastering, if active.
891 * Note we don't actually disable the device until all callers of
892 * pci_device_enable() have called pci_device_disable().
895 pci_disable_device(struct pci_dev
*dev
)
897 struct pci_devres
*dr
;
900 dr
= find_pci_dr(dev
);
904 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
907 /* Wait for all transactions are finished before disabling the device */
908 pcie_wait_pending_transaction(dev
);
910 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
911 if (pci_command
& PCI_COMMAND_MASTER
) {
912 pci_command
&= ~PCI_COMMAND_MASTER
;
913 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
915 dev
->is_busmaster
= 0;
917 pcibios_disable_device(dev
);
921 * pcibios_set_pcie_reset_state - set reset state for device dev
922 * @dev: the PCI-E device reset
923 * @state: Reset state to enter into
926 * Sets the PCI-E reset state for the device. This is the default
927 * implementation. Architecture implementations can override this.
929 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
930 enum pcie_reset_state state
)
936 * pci_set_pcie_reset_state - set reset state for device dev
937 * @dev: the PCI-E device reset
938 * @state: Reset state to enter into
941 * Sets the PCI reset state for the device.
943 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
945 return pcibios_set_pcie_reset_state(dev
, state
);
949 * pci_enable_wake - enable PCI device as wakeup event source
950 * @dev: PCI device affected
951 * @state: PCI state from which device will issue wakeup events
952 * @enable: True to enable event generation; false to disable
954 * This enables the device as a wakeup event source, or disables it.
955 * When such events involves platform-specific hooks, those hooks are
956 * called automatically by this routine.
958 * Devices with legacy power management (no standard PCI PM capabilities)
959 * always require such platform hooks. Depending on the platform, devices
960 * supporting the standard PCI PME# signal may require such platform hooks;
961 * they always update bits in config space to allow PME# generation.
963 * -EIO is returned if the device can't ever be a wakeup event source.
964 * -EINVAL is returned if the device can't generate wakeup events from
965 * the specified PCI state. Returns zero if the operation is successful.
967 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
973 /* Note that drivers should verify device_may_wakeup(&dev->dev)
974 * before calling this function. Platform code should report
975 * errors when drivers try to enable wakeup on devices that
976 * can't issue wakeups, or on which wakeups were disabled by
977 * userspace updating the /sys/devices.../power/wakeup file.
980 status
= call_platform_enable_wakeup(&dev
->dev
, enable
);
982 /* find PCI PM capability in list */
983 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
985 /* If device doesn't support PM Capabilities, but caller wants to
986 * disable wake events, it's a NOP. Otherwise fail unless the
987 * platform hooks handled this legacy device already.
990 return enable
? status
: 0;
992 /* Check device's ability to generate PME# */
993 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
995 value
&= PCI_PM_CAP_PME_MASK
;
996 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
998 /* Check if it can generate PME# from requested state. */
999 if (!value
|| !(value
& (1 << state
))) {
1000 /* if it can't, revert what the platform hook changed,
1001 * always reporting the base "EINVAL, can't PME#" error
1004 call_platform_enable_wakeup(&dev
->dev
, 0);
1005 return enable
? -EINVAL
: 0;
1008 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
1010 /* Clear PME_Status by writing 1 to it and enable PME# */
1011 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1014 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
1016 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
1022 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1030 while (dev
->bus
->self
) {
1031 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
1032 dev
= dev
->bus
->self
;
1039 * pci_release_region - Release a PCI bar
1040 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1041 * @bar: BAR to release
1043 * Releases the PCI I/O and memory resources previously reserved by a
1044 * successful call to pci_request_region. Call this function only
1045 * after all use of the PCI regions has ceased.
1047 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1049 struct pci_devres
*dr
;
1051 if (pci_resource_len(pdev
, bar
) == 0)
1053 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1054 release_region(pci_resource_start(pdev
, bar
),
1055 pci_resource_len(pdev
, bar
));
1056 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1057 release_mem_region(pci_resource_start(pdev
, bar
),
1058 pci_resource_len(pdev
, bar
));
1060 dr
= find_pci_dr(pdev
);
1062 dr
->region_mask
&= ~(1 << bar
);
1066 * pci_request_region - Reserved PCI I/O and memory resource
1067 * @pdev: PCI device whose resources are to be reserved
1068 * @bar: BAR to be reserved
1069 * @res_name: Name to be associated with resource.
1071 * Mark the PCI region associated with PCI device @pdev BR @bar as
1072 * being reserved by owner @res_name. Do not access any
1073 * address inside the PCI regions unless this call returns
1076 * Returns 0 on success, or %EBUSY on error. A warning
1077 * message is also printed on failure.
1079 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1081 struct pci_devres
*dr
;
1083 if (pci_resource_len(pdev
, bar
) == 0)
1086 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1087 if (!request_region(pci_resource_start(pdev
, bar
),
1088 pci_resource_len(pdev
, bar
), res_name
))
1091 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1092 if (!request_mem_region(pci_resource_start(pdev
, bar
),
1093 pci_resource_len(pdev
, bar
), res_name
))
1097 dr
= find_pci_dr(pdev
);
1099 dr
->region_mask
|= 1 << bar
;
1104 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%llx@%llx "
1106 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1107 bar
+ 1, /* PCI BAR # */
1108 (unsigned long long)pci_resource_len(pdev
, bar
),
1109 (unsigned long long)pci_resource_start(pdev
, bar
),
1115 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1116 * @pdev: PCI device whose resources were previously reserved
1117 * @bars: Bitmask of BARs to be released
1119 * Release selected PCI I/O and memory resources previously reserved.
1120 * Call this function only after all use of the PCI regions has ceased.
1122 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1126 for (i
= 0; i
< 6; i
++)
1127 if (bars
& (1 << i
))
1128 pci_release_region(pdev
, i
);
1132 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1133 * @pdev: PCI device whose resources are to be reserved
1134 * @bars: Bitmask of BARs to be requested
1135 * @res_name: Name to be associated with resource
1137 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1138 const char *res_name
)
1142 for (i
= 0; i
< 6; i
++)
1143 if (bars
& (1 << i
))
1144 if(pci_request_region(pdev
, i
, res_name
))
1150 if (bars
& (1 << i
))
1151 pci_release_region(pdev
, i
);
1157 * pci_release_regions - Release reserved PCI I/O and memory resources
1158 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1160 * Releases all PCI I/O and memory resources previously reserved by a
1161 * successful call to pci_request_regions. Call this function only
1162 * after all use of the PCI regions has ceased.
1165 void pci_release_regions(struct pci_dev
*pdev
)
1167 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1171 * pci_request_regions - Reserved PCI I/O and memory resources
1172 * @pdev: PCI device whose resources are to be reserved
1173 * @res_name: Name to be associated with resource.
1175 * Mark all PCI regions associated with PCI device @pdev as
1176 * being reserved by owner @res_name. Do not access any
1177 * address inside the PCI regions unless this call returns
1180 * Returns 0 on success, or %EBUSY on error. A warning
1181 * message is also printed on failure.
1183 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1185 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1189 * pci_set_master - enables bus-mastering for device dev
1190 * @dev: the PCI device to enable
1192 * Enables bus-mastering on the device and calls pcibios_set_master()
1193 * to do the needed arch specific settings.
1196 pci_set_master(struct pci_dev
*dev
)
1200 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1201 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1202 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
1203 cmd
|= PCI_COMMAND_MASTER
;
1204 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1206 dev
->is_busmaster
= 1;
1207 pcibios_set_master(dev
);
1210 #ifdef PCI_DISABLE_MWI
1211 int pci_set_mwi(struct pci_dev
*dev
)
1216 int pci_try_set_mwi(struct pci_dev
*dev
)
1221 void pci_clear_mwi(struct pci_dev
*dev
)
1227 #ifndef PCI_CACHE_LINE_BYTES
1228 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1231 /* This can be overridden by arch code. */
1232 /* Don't forget this is measured in 32-bit words, not bytes */
1233 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1236 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1237 * @dev: the PCI device for which MWI is to be enabled
1239 * Helper function for pci_set_mwi.
1240 * Originally copied from drivers/net/acenic.c.
1241 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1243 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1246 pci_set_cacheline_size(struct pci_dev
*dev
)
1250 if (!pci_cache_line_size
)
1251 return -EINVAL
; /* The system doesn't support MWI. */
1253 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1254 equal to or multiple of the right value. */
1255 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1256 if (cacheline_size
>= pci_cache_line_size
&&
1257 (cacheline_size
% pci_cache_line_size
) == 0)
1260 /* Write the correct value. */
1261 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1263 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1264 if (cacheline_size
== pci_cache_line_size
)
1267 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
1268 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
1274 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1275 * @dev: the PCI device for which MWI is enabled
1277 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1279 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1282 pci_set_mwi(struct pci_dev
*dev
)
1287 rc
= pci_set_cacheline_size(dev
);
1291 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1292 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1293 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1295 cmd
|= PCI_COMMAND_INVALIDATE
;
1296 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1303 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1304 * @dev: the PCI device for which MWI is enabled
1306 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1307 * Callers are not required to check the return value.
1309 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1311 int pci_try_set_mwi(struct pci_dev
*dev
)
1313 int rc
= pci_set_mwi(dev
);
1318 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1319 * @dev: the PCI device to disable
1321 * Disables PCI Memory-Write-Invalidate transaction on the device
1324 pci_clear_mwi(struct pci_dev
*dev
)
1328 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1329 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1330 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1331 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1334 #endif /* ! PCI_DISABLE_MWI */
1337 * pci_intx - enables/disables PCI INTx for device dev
1338 * @pdev: the PCI device to operate on
1339 * @enable: boolean: whether to enable or disable PCI INTx
1341 * Enables/disables PCI INTx for device dev
1344 pci_intx(struct pci_dev
*pdev
, int enable
)
1346 u16 pci_command
, new;
1348 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1351 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1353 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1356 if (new != pci_command
) {
1357 struct pci_devres
*dr
;
1359 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1361 dr
= find_pci_dr(pdev
);
1362 if (dr
&& !dr
->restore_intx
) {
1363 dr
->restore_intx
= 1;
1364 dr
->orig_intx
= !enable
;
1370 * pci_msi_off - disables any msi or msix capabilities
1371 * @dev: the PCI device to operate on
1373 * If you want to use msi see pci_enable_msi and friends.
1374 * This is a lower level primitive that allows us to disable
1375 * msi operation at the device level.
1377 void pci_msi_off(struct pci_dev
*dev
)
1382 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1384 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1385 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1386 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1388 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1390 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1391 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1392 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1396 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1398 * These can be overridden by arch-specific implementations
1401 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1403 if (!pci_dma_supported(dev
, mask
))
1406 dev
->dma_mask
= mask
;
1412 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1414 if (!pci_dma_supported(dev
, mask
))
1417 dev
->dev
.coherent_dma_mask
= mask
;
1424 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1425 * @dev: PCI device to query
1427 * Returns mmrbc: maximum designed memory read count in bytes
1428 * or appropriate error value.
1430 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
1435 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1439 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1443 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
1445 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
1448 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1449 * @dev: PCI device to query
1451 * Returns mmrbc: maximum memory read count in bytes
1452 * or appropriate error value.
1454 int pcix_get_mmrbc(struct pci_dev
*dev
)
1459 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1463 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1465 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
1469 EXPORT_SYMBOL(pcix_get_mmrbc
);
1472 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1473 * @dev: PCI device to query
1474 * @mmrbc: maximum memory read count in bytes
1475 * valid values are 512, 1024, 2048, 4096
1477 * If possible sets maximum memory read byte count, some bridges have erratas
1478 * that prevent this.
1480 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
1482 int cap
, err
= -EINVAL
;
1483 u32 stat
, cmd
, v
, o
;
1485 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
1488 v
= ffs(mmrbc
) - 10;
1490 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1494 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1498 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
1501 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1505 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
1507 if (v
> o
&& dev
->bus
&&
1508 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
1511 cmd
&= ~PCI_X_CMD_MAX_READ
;
1513 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
1518 EXPORT_SYMBOL(pcix_set_mmrbc
);
1521 * pcie_get_readrq - get PCI Express read request size
1522 * @dev: PCI device to query
1524 * Returns maximum memory read request in bytes
1525 * or appropriate error value.
1527 int pcie_get_readrq(struct pci_dev
*dev
)
1532 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1536 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1538 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
1542 EXPORT_SYMBOL(pcie_get_readrq
);
1545 * pcie_set_readrq - set PCI Express maximum memory read request
1546 * @dev: PCI device to query
1547 * @rq: maximum memory read count in bytes
1548 * valid values are 128, 256, 512, 1024, 2048, 4096
1550 * If possible sets maximum read byte count
1552 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
1554 int cap
, err
= -EINVAL
;
1557 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
1560 v
= (ffs(rq
) - 8) << 12;
1562 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1566 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1570 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
1571 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
1573 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
1579 EXPORT_SYMBOL(pcie_set_readrq
);
1582 * pci_select_bars - Make BAR mask from the type of resource
1583 * @dev: the PCI device for which BAR mask is made
1584 * @flags: resource type mask to be selected
1586 * This helper routine makes bar mask from the type of resource.
1588 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
1591 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1592 if (pci_resource_flags(dev
, i
) & flags
)
1597 static void __devinit
pci_no_domains(void)
1599 #ifdef CONFIG_PCI_DOMAINS
1600 pci_domains_supported
= 0;
1604 static int __devinit
pci_init(void)
1606 struct pci_dev
*dev
= NULL
;
1608 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1609 pci_fixup_device(pci_fixup_final
, dev
);
1614 static int __devinit
pci_setup(char *str
)
1617 char *k
= strchr(str
, ',');
1620 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
1621 if (!strcmp(str
, "nomsi")) {
1623 } else if (!strcmp(str
, "noaer")) {
1625 } else if (!strcmp(str
, "nodomains")) {
1627 } else if (!strncmp(str
, "cbiosize=", 9)) {
1628 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
1629 } else if (!strncmp(str
, "cbmemsize=", 10)) {
1630 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
1632 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
1640 early_param("pci", pci_setup
);
1642 device_initcall(pci_init
);
1644 EXPORT_SYMBOL(pci_reenable_device
);
1645 EXPORT_SYMBOL(pci_enable_device_bars
);
1646 EXPORT_SYMBOL(pci_enable_device
);
1647 EXPORT_SYMBOL(pcim_enable_device
);
1648 EXPORT_SYMBOL(pcim_pin_device
);
1649 EXPORT_SYMBOL(pci_disable_device
);
1650 EXPORT_SYMBOL(pci_find_capability
);
1651 EXPORT_SYMBOL(pci_bus_find_capability
);
1652 EXPORT_SYMBOL(pci_release_regions
);
1653 EXPORT_SYMBOL(pci_request_regions
);
1654 EXPORT_SYMBOL(pci_release_region
);
1655 EXPORT_SYMBOL(pci_request_region
);
1656 EXPORT_SYMBOL(pci_release_selected_regions
);
1657 EXPORT_SYMBOL(pci_request_selected_regions
);
1658 EXPORT_SYMBOL(pci_set_master
);
1659 EXPORT_SYMBOL(pci_set_mwi
);
1660 EXPORT_SYMBOL(pci_try_set_mwi
);
1661 EXPORT_SYMBOL(pci_clear_mwi
);
1662 EXPORT_SYMBOL_GPL(pci_intx
);
1663 EXPORT_SYMBOL(pci_set_dma_mask
);
1664 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
1665 EXPORT_SYMBOL(pci_assign_resource
);
1666 EXPORT_SYMBOL(pci_find_parent_resource
);
1667 EXPORT_SYMBOL(pci_select_bars
);
1669 EXPORT_SYMBOL(pci_set_power_state
);
1670 EXPORT_SYMBOL(pci_save_state
);
1671 EXPORT_SYMBOL(pci_restore_state
);
1672 EXPORT_SYMBOL(pci_enable_wake
);
1673 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);