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regulator: documentation - regulator driver
[linux-2.6/x86.git] / drivers / spi / spi_mpc83xx.c
blob070c6219e2d605a617c55547984cc61548a27bf3
1 /*
2 * MPC83xx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/completion.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/irq.h>
21 #include <linux/device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
24 #include <linux/platform_device.h>
25 #include <linux/fsl_devices.h>
26
27 #include <asm/irq.h>
28 #include <asm/io.h>
29
30 /* SPI Controller registers */
31 struct mpc83xx_spi_reg {
32 u8 res1[0x20];
33 __be32 mode;
34 __be32 event;
35 __be32 mask;
36 __be32 command;
37 __be32 transmit;
38 __be32 receive;
39 };
40
41 /* SPI Controller mode register definitions */
42 #define SPMODE_LOOP (1 << 30)
43 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
44 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
45 #define SPMODE_DIV16 (1 << 27)
46 #define SPMODE_REV (1 << 26)
47 #define SPMODE_MS (1 << 25)
48 #define SPMODE_ENABLE (1 << 24)
49 #define SPMODE_LEN(x) ((x) << 20)
50 #define SPMODE_PM(x) ((x) << 16)
51 #define SPMODE_OP (1 << 14)
52 #define SPMODE_CG(x) ((x) << 7)
53
54 /*
55 * Default for SPI Mode:
56 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
57 */
58 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
59 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
60
61 /* SPIE register values */
62 #define SPIE_NE 0x00000200 /* Not empty */
63 #define SPIE_NF 0x00000100 /* Not full */
64
65 /* SPIM register values */
66 #define SPIM_NE 0x00000200 /* Not empty */
67 #define SPIM_NF 0x00000100 /* Not full */
68
69 /* SPI Controller driver's private data. */
70 struct mpc83xx_spi {
71 struct mpc83xx_spi_reg __iomem *base;
72
73 /* rx & tx bufs from the spi_transfer */
74 const void *tx;
75 void *rx;
76
77 /* functions to deal with different sized buffers */
78 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
79 u32(*get_tx) (struct mpc83xx_spi *);
80
81 unsigned int count;
82 int irq;
83
84 unsigned nsecs; /* (clock cycle time)/2 */
85
86 u32 spibrg; /* SPIBRG input clock */
87 u32 rx_shift; /* RX data reg shift when in qe mode */
88 u32 tx_shift; /* TX data reg shift when in qe mode */
89
90 bool qe_mode;
91
92 void (*activate_cs) (u8 cs, u8 polarity);
93 void (*deactivate_cs) (u8 cs, u8 polarity);
94
95 u8 busy;
96
97 struct workqueue_struct *workqueue;
98 struct work_struct work;
99
100 struct list_head queue;
101 spinlock_t lock;
102
103 struct completion done;
104 };
105
106 struct spi_mpc83xx_cs {
107 /* functions to deal with different sized buffers */
108 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
109 u32 (*get_tx) (struct mpc83xx_spi *);
110 u32 rx_shift; /* RX data reg shift when in qe mode */
111 u32 tx_shift; /* TX data reg shift when in qe mode */
112 u32 hw_mode; /* Holds HW mode register settings */
113 };
114
115 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
116 {
117 out_be32(reg, val);
118 }
119
120 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
121 {
122 return in_be32(reg);
123 }
124
125 #define MPC83XX_SPI_RX_BUF(type) \
126 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
127 { \
128 type * rx = mpc83xx_spi->rx; \
129 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
130 mpc83xx_spi->rx = rx; \
131 }
132
133 #define MPC83XX_SPI_TX_BUF(type) \
134 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
135 { \
136 u32 data; \
137 const type * tx = mpc83xx_spi->tx; \
138 if (!tx) \
139 return 0; \
140 data = *tx++ << mpc83xx_spi->tx_shift; \
141 mpc83xx_spi->tx = tx; \
142 return data; \
143 }
144
145 MPC83XX_SPI_RX_BUF(u8)
146 MPC83XX_SPI_RX_BUF(u16)
147 MPC83XX_SPI_RX_BUF(u32)
148 MPC83XX_SPI_TX_BUF(u8)
149 MPC83XX_SPI_TX_BUF(u16)
150 MPC83XX_SPI_TX_BUF(u32)
151
152 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
153 {
154 struct mpc83xx_spi *mpc83xx_spi;
155 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
156 struct spi_mpc83xx_cs *cs = spi->controller_state;
157
158 mpc83xx_spi = spi_master_get_devdata(spi->master);
159
160 if (value == BITBANG_CS_INACTIVE) {
161 if (mpc83xx_spi->deactivate_cs)
162 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
163 }
164
165 if (value == BITBANG_CS_ACTIVE) {
166 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
167
168 mpc83xx_spi->rx_shift = cs->rx_shift;
169 mpc83xx_spi->tx_shift = cs->tx_shift;
170 mpc83xx_spi->get_rx = cs->get_rx;
171 mpc83xx_spi->get_tx = cs->get_tx;
172
173 if (cs->hw_mode != regval) {
174 unsigned long flags;
175 void *tmp_ptr = &mpc83xx_spi->base->mode;
176
177 regval = cs->hw_mode;
178 /* Turn off IRQs locally to minimize time that
179 * SPI is disabled
180 */
181 local_irq_save(flags);
182 /* Turn off SPI unit prior changing mode */
183 mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
184 mpc83xx_spi_write_reg(tmp_ptr, regval);
185 local_irq_restore(flags);
186 }
187 if (mpc83xx_spi->activate_cs)
188 mpc83xx_spi->activate_cs(spi->chip_select, pol);
189 }
190 }
191
192 static
193 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
194 {
195 struct mpc83xx_spi *mpc83xx_spi;
196 u32 regval;
197 u8 bits_per_word, pm;
198 u32 hz;
199 struct spi_mpc83xx_cs *cs = spi->controller_state;
200
201 mpc83xx_spi = spi_master_get_devdata(spi->master);
202
203 if (t) {
204 bits_per_word = t->bits_per_word;
205 hz = t->speed_hz;
206 } else {
207 bits_per_word = 0;
208 hz = 0;
209 }
210
211 /* spi_transfer level calls that work per-word */
212 if (!bits_per_word)
213 bits_per_word = spi->bits_per_word;
214
215 /* Make sure its a bit width we support [4..16, 32] */
216 if ((bits_per_word < 4)
217 || ((bits_per_word > 16) && (bits_per_word != 32)))
218 return -EINVAL;
219
220 if (!hz)
221 hz = spi->max_speed_hz;
222
223 cs->rx_shift = 0;
224 cs->tx_shift = 0;
225 if (bits_per_word <= 8) {
226 cs->get_rx = mpc83xx_spi_rx_buf_u8;
227 cs->get_tx = mpc83xx_spi_tx_buf_u8;
228 if (mpc83xx_spi->qe_mode) {
229 cs->rx_shift = 16;
230 cs->tx_shift = 24;
231 }
232 } else if (bits_per_word <= 16) {
233 cs->get_rx = mpc83xx_spi_rx_buf_u16;
234 cs->get_tx = mpc83xx_spi_tx_buf_u16;
235 if (mpc83xx_spi->qe_mode) {
236 cs->rx_shift = 16;
237 cs->tx_shift = 16;
238 }
239 } else if (bits_per_word <= 32) {
240 cs->get_rx = mpc83xx_spi_rx_buf_u32;
241 cs->get_tx = mpc83xx_spi_tx_buf_u32;
242 } else
243 return -EINVAL;
244
245 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
246 cs->tx_shift = 0;
247 if (bits_per_word <= 8)
248 cs->rx_shift = 8;
249 else
250 cs->rx_shift = 0;
251 }
252
253 mpc83xx_spi->rx_shift = cs->rx_shift;
254 mpc83xx_spi->tx_shift = cs->tx_shift;
255 mpc83xx_spi->get_rx = cs->get_rx;
256 mpc83xx_spi->get_tx = cs->get_tx;
257
258 if (bits_per_word == 32)
259 bits_per_word = 0;
260 else
261 bits_per_word = bits_per_word - 1;
262
263 /* mask out bits we are going to set */
264 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
265 | SPMODE_PM(0xF));
266
267 cs->hw_mode |= SPMODE_LEN(bits_per_word);
268
269 if ((mpc83xx_spi->spibrg / hz) > 64) {
270 pm = mpc83xx_spi->spibrg / (hz * 64);
271 if (pm > 16) {
272 cs->hw_mode |= SPMODE_DIV16;
273 pm /= 16;
274 if (pm > 16) {
275 dev_err(&spi->dev, "Requested speed is too "
276 "low: %d Hz. Will use %d Hz instead.\n",
277 hz, mpc83xx_spi->spibrg / 1024);
278 pm = 16;
279 }
280 }
281 } else
282 pm = mpc83xx_spi->spibrg / (hz * 4);
283 if (pm)
284 pm--;
285
286 cs->hw_mode |= SPMODE_PM(pm);
287 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
288 if (cs->hw_mode != regval) {
289 unsigned long flags;
290 void *tmp_ptr = &mpc83xx_spi->base->mode;
291
292 regval = cs->hw_mode;
293 /* Turn off IRQs locally to minimize time
294 * that SPI is disabled
295 */
296 local_irq_save(flags);
297 /* Turn off SPI unit prior changing mode */
298 mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
299 mpc83xx_spi_write_reg(tmp_ptr, regval);
300 local_irq_restore(flags);
301 }
302 return 0;
303 }
304
305 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
306 {
307 struct mpc83xx_spi *mpc83xx_spi;
308 u32 word, len, bits_per_word;
309
310 mpc83xx_spi = spi_master_get_devdata(spi->master);
311
312 mpc83xx_spi->tx = t->tx_buf;
313 mpc83xx_spi->rx = t->rx_buf;
314 bits_per_word = spi->bits_per_word;
315 if (t->bits_per_word)
316 bits_per_word = t->bits_per_word;
317 len = t->len;
318 if (bits_per_word > 8)
319 len /= 2;
320 if (bits_per_word > 16)
321 len /= 2;
322 mpc83xx_spi->count = len;
323 INIT_COMPLETION(mpc83xx_spi->done);
324
325 /* enable rx ints */
326 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
327
328 /* transmit word */
329 word = mpc83xx_spi->get_tx(mpc83xx_spi);
330 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
331
332 wait_for_completion(&mpc83xx_spi->done);
333
334 /* disable rx ints */
335 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
336
337 return mpc83xx_spi->count;
338 }
339
340 static void mpc83xx_spi_work(struct work_struct *work)
341 {
342 struct mpc83xx_spi *mpc83xx_spi =
343 container_of(work, struct mpc83xx_spi, work);
344
345 spin_lock_irq(&mpc83xx_spi->lock);
346 mpc83xx_spi->busy = 1;
347 while (!list_empty(&mpc83xx_spi->queue)) {
348 struct spi_message *m;
349 struct spi_device *spi;
350 struct spi_transfer *t = NULL;
351 unsigned cs_change;
352 int status, nsecs = 50;
353
354 m = container_of(mpc83xx_spi->queue.next,
355 struct spi_message, queue);
356 list_del_init(&m->queue);
357 spin_unlock_irq(&mpc83xx_spi->lock);
358
359 spi = m->spi;
360 cs_change = 1;
361 status = 0;
362 list_for_each_entry(t, &m->transfers, transfer_list) {
363 if (t->bits_per_word || t->speed_hz) {
364 /* Don't allow changes if CS is active */
365 status = -EINVAL;
366
367 if (cs_change)
368 status = mpc83xx_spi_setup_transfer(spi, t);
369 if (status < 0)
370 break;
371 }
372
373 if (cs_change)
374 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
375 cs_change = t->cs_change;
376 if (t->len)
377 status = mpc83xx_spi_bufs(spi, t);
378 if (status) {
379 status = -EMSGSIZE;
380 break;
381 }
382 m->actual_length += t->len;
383
384 if (t->delay_usecs)
385 udelay(t->delay_usecs);
386
387 if (cs_change) {
388 ndelay(nsecs);
389 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
390 ndelay(nsecs);
391 }
392 }
393
394 m->status = status;
395 m->complete(m->context);
396
397 if (status || !cs_change) {
398 ndelay(nsecs);
399 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
400 }
401
402 mpc83xx_spi_setup_transfer(spi, NULL);
403
404 spin_lock_irq(&mpc83xx_spi->lock);
405 }
406 mpc83xx_spi->busy = 0;
407 spin_unlock_irq(&mpc83xx_spi->lock);
408 }
409
410 /* the spi->mode bits understood by this driver: */
411 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
412 | SPI_LSB_FIRST | SPI_LOOP)
413
414 static int mpc83xx_spi_setup(struct spi_device *spi)
415 {
416 struct mpc83xx_spi *mpc83xx_spi;
417 int retval;
418 u32 hw_mode;
419 struct spi_mpc83xx_cs *cs = spi->controller_state;
420
421 if (spi->mode & ~MODEBITS) {
422 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
423 spi->mode & ~MODEBITS);
424 return -EINVAL;
425 }
426
427 if (!spi->max_speed_hz)
428 return -EINVAL;
429
430 if (!cs) {
431 cs = kzalloc(sizeof *cs, GFP_KERNEL);
432 if (!cs)
433 return -ENOMEM;
434 spi->controller_state = cs;
435 }
436 mpc83xx_spi = spi_master_get_devdata(spi->master);
437
438 if (!spi->bits_per_word)
439 spi->bits_per_word = 8;
440
441 hw_mode = cs->hw_mode; /* Save orginal settings */
442 cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
443 /* mask out bits we are going to set */
444 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
445 | SPMODE_REV | SPMODE_LOOP);
446
447 if (spi->mode & SPI_CPHA)
448 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
449 if (spi->mode & SPI_CPOL)
450 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
451 if (!(spi->mode & SPI_LSB_FIRST))
452 cs->hw_mode |= SPMODE_REV;
453 if (spi->mode & SPI_LOOP)
454 cs->hw_mode |= SPMODE_LOOP;
455
456 retval = mpc83xx_spi_setup_transfer(spi, NULL);
457 if (retval < 0) {
458 cs->hw_mode = hw_mode; /* Restore settings */
459 return retval;
460 }
461
462 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
463 __func__, spi->mode & (SPI_CPOL | SPI_CPHA),
464 spi->bits_per_word, spi->max_speed_hz);
465 #if 0 /* Don't think this is needed */
466 /* NOTE we _need_ to call chipselect() early, ideally with adapter
467 * setup, unless the hardware defaults cooperate to avoid confusion
468 * between normal (active low) and inverted chipselects.
469 */
470
471 /* deselect chip (low or high) */
472 spin_lock(&mpc83xx_spi->lock);
473 if (!mpc83xx_spi->busy)
474 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
475 spin_unlock(&mpc83xx_spi->lock);
476 #endif
477 return 0;
478 }
479
480 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
481 {
482 struct mpc83xx_spi *mpc83xx_spi = context_data;
483 u32 event;
484 irqreturn_t ret = IRQ_NONE;
485
486 /* Get interrupt events(tx/rx) */
487 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
488
489 /* We need handle RX first */
490 if (event & SPIE_NE) {
491 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
492
493 if (mpc83xx_spi->rx)
494 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
495
496 ret = IRQ_HANDLED;
497 }
498
499 if ((event & SPIE_NF) == 0)
500 /* spin until TX is done */
501 while (((event =
502 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
503 SPIE_NF) == 0)
504 cpu_relax();
505
506 mpc83xx_spi->count -= 1;
507 if (mpc83xx_spi->count) {
508 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
509 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
510 } else {
511 complete(&mpc83xx_spi->done);
512 }
513
514 /* Clear the events */
515 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
516
517 return ret;
518 }
519 static int mpc83xx_spi_transfer(struct spi_device *spi,
520 struct spi_message *m)
521 {
522 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
523 unsigned long flags;
524
525 m->actual_length = 0;
526 m->status = -EINPROGRESS;
527
528 spin_lock_irqsave(&mpc83xx_spi->lock, flags);
529 list_add_tail(&m->queue, &mpc83xx_spi->queue);
530 queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
531 spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
532
533 return 0;
534 }
535
536
537 static void mpc83xx_spi_cleanup(struct spi_device *spi)
538 {
539 kfree(spi->controller_state);
540 }
541
542 static int __init mpc83xx_spi_probe(struct platform_device *dev)
543 {
544 struct spi_master *master;
545 struct mpc83xx_spi *mpc83xx_spi;
546 struct fsl_spi_platform_data *pdata;
547 struct resource *r;
548 u32 regval;
549 int ret = 0;
550
551 /* Get resources(memory, IRQ) associated with the device */
552 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
553
554 if (master == NULL) {
555 ret = -ENOMEM;
556 goto err;
557 }
558
559 platform_set_drvdata(dev, master);
560 pdata = dev->dev.platform_data;
561
562 if (pdata == NULL) {
563 ret = -ENODEV;
564 goto free_master;
565 }
566
567 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
568 if (r == NULL) {
569 ret = -ENODEV;
570 goto free_master;
571 }
572 master->setup = mpc83xx_spi_setup;
573 master->transfer = mpc83xx_spi_transfer;
574 master->cleanup = mpc83xx_spi_cleanup;
575
576 mpc83xx_spi = spi_master_get_devdata(master);
577 mpc83xx_spi->activate_cs = pdata->activate_cs;
578 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
579 mpc83xx_spi->qe_mode = pdata->qe_mode;
580 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
581 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
582 mpc83xx_spi->spibrg = pdata->sysclk;
583
584 mpc83xx_spi->rx_shift = 0;
585 mpc83xx_spi->tx_shift = 0;
586 if (mpc83xx_spi->qe_mode) {
587 mpc83xx_spi->rx_shift = 16;
588 mpc83xx_spi->tx_shift = 24;
589 }
590
591 init_completion(&mpc83xx_spi->done);
592
593 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
594 if (mpc83xx_spi->base == NULL) {
595 ret = -ENOMEM;
596 goto put_master;
597 }
598
599 mpc83xx_spi->irq = platform_get_irq(dev, 0);
600
601 if (mpc83xx_spi->irq < 0) {
602 ret = -ENXIO;
603 goto unmap_io;
604 }
605
606 /* Register for SPI Interrupt */
607 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
608 0, "mpc83xx_spi", mpc83xx_spi);
609
610 if (ret != 0)
611 goto unmap_io;
612
613 master->bus_num = pdata->bus_num;
614 master->num_chipselect = pdata->max_chipselect;
615
616 /* SPI controller initializations */
617 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
618 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
619 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
620 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
621
622 /* Enable SPI interface */
623 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
624 if (pdata->qe_mode)
625 regval |= SPMODE_OP;
626
627 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
628 spin_lock_init(&mpc83xx_spi->lock);
629 init_completion(&mpc83xx_spi->done);
630 INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
631 INIT_LIST_HEAD(&mpc83xx_spi->queue);
632
633 mpc83xx_spi->workqueue = create_singlethread_workqueue(
634 master->dev.parent->bus_id);
635 if (mpc83xx_spi->workqueue == NULL) {
636 ret = -EBUSY;
637 goto free_irq;
638 }
639
640 ret = spi_register_master(master);
641 if (ret < 0)
642 goto unreg_master;
643
644 printk(KERN_INFO
645 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
646 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
647
648 return ret;
649
650 unreg_master:
651 destroy_workqueue(mpc83xx_spi->workqueue);
652 free_irq:
653 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
654 unmap_io:
655 iounmap(mpc83xx_spi->base);
656 put_master:
657 spi_master_put(master);
658 free_master:
659 kfree(master);
660 err:
661 return ret;
662 }
663
664 static int __exit mpc83xx_spi_remove(struct platform_device *dev)
665 {
666 struct mpc83xx_spi *mpc83xx_spi;
667 struct spi_master *master;
668
669 master = platform_get_drvdata(dev);
670 mpc83xx_spi = spi_master_get_devdata(master);
671
672 flush_workqueue(mpc83xx_spi->workqueue);
673 destroy_workqueue(mpc83xx_spi->workqueue);
674 spi_unregister_master(master);
675
676 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
677 iounmap(mpc83xx_spi->base);
678
679 return 0;
680 }
681
682 MODULE_ALIAS("platform:mpc83xx_spi");
683 static struct platform_driver mpc83xx_spi_driver = {
684 .remove = __exit_p(mpc83xx_spi_remove),
685 .driver = {
686 .name = "mpc83xx_spi",
687 .owner = THIS_MODULE,
688 },
689 };
690
691 static int __init mpc83xx_spi_init(void)
692 {
693 return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
694 }
695
696 static void __exit mpc83xx_spi_exit(void)
697 {
698 platform_driver_unregister(&mpc83xx_spi_driver);
699 }
700
701 module_init(mpc83xx_spi_init);
702 module_exit(mpc83xx_spi_exit);
703
704 MODULE_AUTHOR("Kumar Gala");
705 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
706 MODULE_LICENSE("GPL");
x86 "subsystem" repository