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ahci: workarounds for mcp65
[linux-2.6/x86.git] / drivers / ata / ahci.c
blob1c62b8e396451d6f6373f54127956a7ace8fffad
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92 board_ahci_mcp65 = 6,
93
94 /* global controller registers */
95 HOST_CAP = 0x00, /* host capabilities */
96 HOST_CTL = 0x04, /* global host control */
97 HOST_IRQ_STAT = 0x08, /* interrupt status */
98 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
99 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
100
101 /* HOST_CTL bits */
102 HOST_RESET = (1 << 0), /* reset controller; self-clear */
103 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
104 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
105
106 /* HOST_CAP bits */
107 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
108 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
109 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
110 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
111 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
112 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
113 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
114 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
115
116 /* registers for each SATA port */
117 PORT_LST_ADDR = 0x00, /* command list DMA addr */
118 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
119 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
120 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
121 PORT_IRQ_STAT = 0x10, /* interrupt status */
122 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
123 PORT_CMD = 0x18, /* port command */
124 PORT_TFDATA = 0x20, /* taskfile data */
125 PORT_SIG = 0x24, /* device TF signature */
126 PORT_CMD_ISSUE = 0x38, /* command issue */
127 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
128 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
129 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
130 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
131 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
132
133 /* PORT_IRQ_{STAT,MASK} bits */
134 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
135 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
136 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
137 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
138 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
139 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
140 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
141 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
142
143 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
144 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
145 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
146 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
147 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
148 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
149 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
150 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
151 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
152
153 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
154 PORT_IRQ_IF_ERR |
155 PORT_IRQ_CONNECT |
156 PORT_IRQ_PHYRDY |
157 PORT_IRQ_UNK_FIS |
158 PORT_IRQ_BAD_PMP,
159 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
160 PORT_IRQ_TF_ERR |
161 PORT_IRQ_HBUS_DATA_ERR,
162 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
163 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
164 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
165
166 /* PORT_CMD bits */
167 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
168 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
169 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
170 PORT_CMD_PMP = (1 << 17), /* PMP attached */
171 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
172 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
173 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
174 PORT_CMD_CLO = (1 << 3), /* Command list override */
175 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
176 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
177 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
178
179 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
180 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
181 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
182 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
183
184 /* hpriv->flags bits */
185 AHCI_HFLAG_NO_NCQ = (1 << 0),
186 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
187 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
188 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
189 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
190 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
191 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
192 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
193 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
194 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
195
196 /* ap->flags bits */
197
198 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
199 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
200 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
201 ATA_FLAG_IPM,
202
203 ICH_MAP = 0x90, /* ICH MAP register */
204 };
205
206 struct ahci_cmd_hdr {
207 __le32 opts;
208 __le32 status;
209 __le32 tbl_addr;
210 __le32 tbl_addr_hi;
211 __le32 reserved[4];
212 };
213
214 struct ahci_sg {
215 __le32 addr;
216 __le32 addr_hi;
217 __le32 reserved;
218 __le32 flags_size;
219 };
220
221 struct ahci_host_priv {
222 unsigned int flags; /* AHCI_HFLAG_* */
223 u32 cap; /* cap to use */
224 u32 port_map; /* port map to use */
225 u32 saved_cap; /* saved initial cap */
226 u32 saved_port_map; /* saved initial port_map */
227 };
228
229 struct ahci_port_priv {
230 struct ata_link *active_link;
231 struct ahci_cmd_hdr *cmd_slot;
232 dma_addr_t cmd_slot_dma;
233 void *cmd_tbl;
234 dma_addr_t cmd_tbl_dma;
235 void *rx_fis;
236 dma_addr_t rx_fis_dma;
237 /* for NCQ spurious interrupt analysis */
238 unsigned int ncq_saw_d2h:1;
239 unsigned int ncq_saw_dmas:1;
240 unsigned int ncq_saw_sdb:1;
241 u32 intr_mask; /* interrupts to enable */
242 };
243
244 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
245 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
246 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
247 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
248 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
249 static int ahci_port_start(struct ata_port *ap);
250 static void ahci_port_stop(struct ata_port *ap);
251 static void ahci_qc_prep(struct ata_queued_cmd *qc);
252 static void ahci_freeze(struct ata_port *ap);
253 static void ahci_thaw(struct ata_port *ap);
254 static void ahci_pmp_attach(struct ata_port *ap);
255 static void ahci_pmp_detach(struct ata_port *ap);
256 static int ahci_softreset(struct ata_link *link, unsigned int *class,
257 unsigned long deadline);
258 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
259 unsigned long deadline);
260 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
261 unsigned long deadline);
262 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
263 unsigned long deadline);
264 static void ahci_postreset(struct ata_link *link, unsigned int *class);
265 static void ahci_error_handler(struct ata_port *ap);
266 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
267 static int ahci_port_resume(struct ata_port *ap);
268 static void ahci_dev_config(struct ata_device *dev);
269 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
270 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
271 u32 opts);
272 #ifdef CONFIG_PM
273 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
274 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
275 static int ahci_pci_device_resume(struct pci_dev *pdev);
276 #endif
277
278 static struct device_attribute *ahci_shost_attrs[] = {
279 &dev_attr_link_power_management_policy,
280 NULL
281 };
282
283 static struct scsi_host_template ahci_sht = {
284 ATA_NCQ_SHT(DRV_NAME),
285 .can_queue = AHCI_MAX_CMDS - 1,
286 .sg_tablesize = AHCI_MAX_SG,
287 .dma_boundary = AHCI_DMA_BOUNDARY,
288 .shost_attrs = ahci_shost_attrs,
289 };
290
291 static struct ata_port_operations ahci_ops = {
292 .inherits = &sata_pmp_port_ops,
293
294 .qc_defer = sata_pmp_qc_defer_cmd_switch,
295 .qc_prep = ahci_qc_prep,
296 .qc_issue = ahci_qc_issue,
297 .qc_fill_rtf = ahci_qc_fill_rtf,
298
299 .freeze = ahci_freeze,
300 .thaw = ahci_thaw,
301 .softreset = ahci_softreset,
302 .hardreset = ahci_hardreset,
303 .postreset = ahci_postreset,
304 .pmp_softreset = ahci_softreset,
305 .error_handler = ahci_error_handler,
306 .post_internal_cmd = ahci_post_internal_cmd,
307 .dev_config = ahci_dev_config,
308
309 .scr_read = ahci_scr_read,
310 .scr_write = ahci_scr_write,
311 .pmp_attach = ahci_pmp_attach,
312 .pmp_detach = ahci_pmp_detach,
313
314 .enable_pm = ahci_enable_alpm,
315 .disable_pm = ahci_disable_alpm,
316 #ifdef CONFIG_PM
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
319 #endif
320 .port_start = ahci_port_start,
321 .port_stop = ahci_port_stop,
322 };
323
324 static struct ata_port_operations ahci_vt8251_ops = {
325 .inherits = &ahci_ops,
326 .hardreset = ahci_vt8251_hardreset,
327 };
328
329 static struct ata_port_operations ahci_p5wdh_ops = {
330 .inherits = &ahci_ops,
331 .hardreset = ahci_p5wdh_hardreset,
332 };
333
334 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
335
336 static const struct ata_port_info ahci_port_info[] = {
337 /* board_ahci */
338 {
339 .flags = AHCI_FLAG_COMMON,
340 .pio_mask = 0x1f, /* pio0-4 */
341 .udma_mask = ATA_UDMA6,
342 .port_ops = &ahci_ops,
343 },
344 /* board_ahci_vt8251 */
345 {
346 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
347 .flags = AHCI_FLAG_COMMON,
348 .pio_mask = 0x1f, /* pio0-4 */
349 .udma_mask = ATA_UDMA6,
350 .port_ops = &ahci_vt8251_ops,
351 },
352 /* board_ahci_ign_iferr */
353 {
354 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
355 .flags = AHCI_FLAG_COMMON,
356 .pio_mask = 0x1f, /* pio0-4 */
357 .udma_mask = ATA_UDMA6,
358 .port_ops = &ahci_ops,
359 },
360 /* board_ahci_sb600 */
361 {
362 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
363 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
364 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
365 .flags = AHCI_FLAG_COMMON,
366 .pio_mask = 0x1f, /* pio0-4 */
367 .udma_mask = ATA_UDMA6,
368 .port_ops = &ahci_ops,
369 },
370 /* board_ahci_mv */
371 {
372 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
373 AHCI_HFLAG_MV_PATA),
374 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
375 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
376 .pio_mask = 0x1f, /* pio0-4 */
377 .udma_mask = ATA_UDMA6,
378 .port_ops = &ahci_ops,
379 },
380 /* board_ahci_sb700 */
381 {
382 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
383 AHCI_HFLAG_NO_PMP),
384 .flags = AHCI_FLAG_COMMON,
385 .pio_mask = 0x1f, /* pio0-4 */
386 .udma_mask = ATA_UDMA6,
387 .port_ops = &ahci_ops,
388 },
389 /* board_ahci_mcp65 */
390 {
391 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
392 .flags = AHCI_FLAG_COMMON,
393 .pio_mask = 0x1f, /* pio0-4 */
394 .udma_mask = ATA_UDMA6,
395 .port_ops = &ahci_ops,
396 },
397 };
398
399 static const struct pci_device_id ahci_pci_tbl[] = {
400 /* Intel */
401 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
402 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
403 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
404 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
405 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
406 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
407 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
408 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
409 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
410 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
411 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
412 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
413 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
414 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
415 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
416 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
417 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
418 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
419 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
420 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
421 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
422 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
423 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
424 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
425 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
426 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
427 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
428 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
429 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
430 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
431 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
432
433 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
434 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
435 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
436
437 /* ATI */
438 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
439 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
440 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
441 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
442 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
443 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
444 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
445
446 /* VIA */
447 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
448 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
449
450 /* NVIDIA */
451 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
458 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
482 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
493 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
494 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
502 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
504 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
505 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
506 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
507 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
508 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
509 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
510 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
511 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
512 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
513 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
514 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
515 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
516 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
517 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
518 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
519
520 /* SiS */
521 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
522 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
523 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
524
525 /* Marvell */
526 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
527 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
528
529 /* Generic, PCI class code for AHCI */
530 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
531 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
532
533 { } /* terminate list */
534 };
535
536
537 static struct pci_driver ahci_pci_driver = {
538 .name = DRV_NAME,
539 .id_table = ahci_pci_tbl,
540 .probe = ahci_init_one,
541 .remove = ata_pci_remove_one,
542 #ifdef CONFIG_PM
543 .suspend = ahci_pci_device_suspend,
544 .resume = ahci_pci_device_resume,
545 #endif
546 };
547
548
549 static inline int ahci_nr_ports(u32 cap)
550 {
551 return (cap & 0x1f) + 1;
552 }
553
554 static inline void __iomem *__ahci_port_base(struct ata_host *host,
555 unsigned int port_no)
556 {
557 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
558
559 return mmio + 0x100 + (port_no * 0x80);
560 }
561
562 static inline void __iomem *ahci_port_base(struct ata_port *ap)
563 {
564 return __ahci_port_base(ap->host, ap->port_no);
565 }
566
567 static void ahci_enable_ahci(void __iomem *mmio)
568 {
569 int i;
570 u32 tmp;
571
572 /* turn on AHCI_EN */
573 tmp = readl(mmio + HOST_CTL);
574 if (tmp & HOST_AHCI_EN)
575 return;
576
577 /* Some controllers need AHCI_EN to be written multiple times.
578 * Try a few times before giving up.
579 */
580 for (i = 0; i < 5; i++) {
581 tmp |= HOST_AHCI_EN;
582 writel(tmp, mmio + HOST_CTL);
583 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
584 if (tmp & HOST_AHCI_EN)
585 return;
586 msleep(10);
587 }
588
589 WARN_ON(1);
590 }
591
592 /**
593 * ahci_save_initial_config - Save and fixup initial config values
594 * @pdev: target PCI device
595 * @hpriv: host private area to store config values
596 *
597 * Some registers containing configuration info might be setup by
598 * BIOS and might be cleared on reset. This function saves the
599 * initial values of those registers into @hpriv such that they
600 * can be restored after controller reset.
601 *
602 * If inconsistent, config values are fixed up by this function.
603 *
604 * LOCKING:
605 * None.
606 */
607 static void ahci_save_initial_config(struct pci_dev *pdev,
608 struct ahci_host_priv *hpriv)
609 {
610 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
611 u32 cap, port_map;
612 int i;
613 int mv;
614
615 /* make sure AHCI mode is enabled before accessing CAP */
616 ahci_enable_ahci(mmio);
617
618 /* Values prefixed with saved_ are written back to host after
619 * reset. Values without are used for driver operation.
620 */
621 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
622 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
623
624 /* some chips have errata preventing 64bit use */
625 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
626 dev_printk(KERN_INFO, &pdev->dev,
627 "controller can't do 64bit DMA, forcing 32bit\n");
628 cap &= ~HOST_CAP_64;
629 }
630
631 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
632 dev_printk(KERN_INFO, &pdev->dev,
633 "controller can't do NCQ, turning off CAP_NCQ\n");
634 cap &= ~HOST_CAP_NCQ;
635 }
636
637 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
638 dev_printk(KERN_INFO, &pdev->dev,
639 "controller can do NCQ, turning on CAP_NCQ\n");
640 cap |= HOST_CAP_NCQ;
641 }
642
643 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
644 dev_printk(KERN_INFO, &pdev->dev,
645 "controller can't do PMP, turning off CAP_PMP\n");
646 cap &= ~HOST_CAP_PMP;
647 }
648
649 /*
650 * Temporary Marvell 6145 hack: PATA port presence
651 * is asserted through the standard AHCI port
652 * presence register, as bit 4 (counting from 0)
653 */
654 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
655 if (pdev->device == 0x6121)
656 mv = 0x3;
657 else
658 mv = 0xf;
659 dev_printk(KERN_ERR, &pdev->dev,
660 "MV_AHCI HACK: port_map %x -> %x\n",
661 port_map,
662 port_map & mv);
663
664 port_map &= mv;
665 }
666
667 /* cross check port_map and cap.n_ports */
668 if (port_map) {
669 int map_ports = 0;
670
671 for (i = 0; i < AHCI_MAX_PORTS; i++)
672 if (port_map & (1 << i))
673 map_ports++;
674
675 /* If PI has more ports than n_ports, whine, clear
676 * port_map and let it be generated from n_ports.
677 */
678 if (map_ports > ahci_nr_ports(cap)) {
679 dev_printk(KERN_WARNING, &pdev->dev,
680 "implemented port map (0x%x) contains more "
681 "ports than nr_ports (%u), using nr_ports\n",
682 port_map, ahci_nr_ports(cap));
683 port_map = 0;
684 }
685 }
686
687 /* fabricate port_map from cap.nr_ports */
688 if (!port_map) {
689 port_map = (1 << ahci_nr_ports(cap)) - 1;
690 dev_printk(KERN_WARNING, &pdev->dev,
691 "forcing PORTS_IMPL to 0x%x\n", port_map);
692
693 /* write the fixed up value to the PI register */
694 hpriv->saved_port_map = port_map;
695 }
696
697 /* record values to use during operation */
698 hpriv->cap = cap;
699 hpriv->port_map = port_map;
700 }
701
702 /**
703 * ahci_restore_initial_config - Restore initial config
704 * @host: target ATA host
705 *
706 * Restore initial config stored by ahci_save_initial_config().
707 *
708 * LOCKING:
709 * None.
710 */
711 static void ahci_restore_initial_config(struct ata_host *host)
712 {
713 struct ahci_host_priv *hpriv = host->private_data;
714 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
715
716 writel(hpriv->saved_cap, mmio + HOST_CAP);
717 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
718 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
719 }
720
721 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
722 {
723 static const int offset[] = {
724 [SCR_STATUS] = PORT_SCR_STAT,
725 [SCR_CONTROL] = PORT_SCR_CTL,
726 [SCR_ERROR] = PORT_SCR_ERR,
727 [SCR_ACTIVE] = PORT_SCR_ACT,
728 [SCR_NOTIFICATION] = PORT_SCR_NTF,
729 };
730 struct ahci_host_priv *hpriv = ap->host->private_data;
731
732 if (sc_reg < ARRAY_SIZE(offset) &&
733 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
734 return offset[sc_reg];
735 return 0;
736 }
737
738 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
739 {
740 void __iomem *port_mmio = ahci_port_base(ap);
741 int offset = ahci_scr_offset(ap, sc_reg);
742
743 if (offset) {
744 *val = readl(port_mmio + offset);
745 return 0;
746 }
747 return -EINVAL;
748 }
749
750 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
751 {
752 void __iomem *port_mmio = ahci_port_base(ap);
753 int offset = ahci_scr_offset(ap, sc_reg);
754
755 if (offset) {
756 writel(val, port_mmio + offset);
757 return 0;
758 }
759 return -EINVAL;
760 }
761
762 static void ahci_start_engine(struct ata_port *ap)
763 {
764 void __iomem *port_mmio = ahci_port_base(ap);
765 u32 tmp;
766
767 /* start DMA */
768 tmp = readl(port_mmio + PORT_CMD);
769 tmp |= PORT_CMD_START;
770 writel(tmp, port_mmio + PORT_CMD);
771 readl(port_mmio + PORT_CMD); /* flush */
772 }
773
774 static int ahci_stop_engine(struct ata_port *ap)
775 {
776 void __iomem *port_mmio = ahci_port_base(ap);
777 u32 tmp;
778
779 tmp = readl(port_mmio + PORT_CMD);
780
781 /* check if the HBA is idle */
782 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
783 return 0;
784
785 /* setting HBA to idle */
786 tmp &= ~PORT_CMD_START;
787 writel(tmp, port_mmio + PORT_CMD);
788
789 /* wait for engine to stop. This could be as long as 500 msec */
790 tmp = ata_wait_register(port_mmio + PORT_CMD,
791 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
792 if (tmp & PORT_CMD_LIST_ON)
793 return -EIO;
794
795 return 0;
796 }
797
798 static void ahci_start_fis_rx(struct ata_port *ap)
799 {
800 void __iomem *port_mmio = ahci_port_base(ap);
801 struct ahci_host_priv *hpriv = ap->host->private_data;
802 struct ahci_port_priv *pp = ap->private_data;
803 u32 tmp;
804
805 /* set FIS registers */
806 if (hpriv->cap & HOST_CAP_64)
807 writel((pp->cmd_slot_dma >> 16) >> 16,
808 port_mmio + PORT_LST_ADDR_HI);
809 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
810
811 if (hpriv->cap & HOST_CAP_64)
812 writel((pp->rx_fis_dma >> 16) >> 16,
813 port_mmio + PORT_FIS_ADDR_HI);
814 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
815
816 /* enable FIS reception */
817 tmp = readl(port_mmio + PORT_CMD);
818 tmp |= PORT_CMD_FIS_RX;
819 writel(tmp, port_mmio + PORT_CMD);
820
821 /* flush */
822 readl(port_mmio + PORT_CMD);
823 }
824
825 static int ahci_stop_fis_rx(struct ata_port *ap)
826 {
827 void __iomem *port_mmio = ahci_port_base(ap);
828 u32 tmp;
829
830 /* disable FIS reception */
831 tmp = readl(port_mmio + PORT_CMD);
832 tmp &= ~PORT_CMD_FIS_RX;
833 writel(tmp, port_mmio + PORT_CMD);
834
835 /* wait for completion, spec says 500ms, give it 1000 */
836 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
837 PORT_CMD_FIS_ON, 10, 1000);
838 if (tmp & PORT_CMD_FIS_ON)
839 return -EBUSY;
840
841 return 0;
842 }
843
844 static void ahci_power_up(struct ata_port *ap)
845 {
846 struct ahci_host_priv *hpriv = ap->host->private_data;
847 void __iomem *port_mmio = ahci_port_base(ap);
848 u32 cmd;
849
850 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
851
852 /* spin up device */
853 if (hpriv->cap & HOST_CAP_SSS) {
854 cmd |= PORT_CMD_SPIN_UP;
855 writel(cmd, port_mmio + PORT_CMD);
856 }
857
858 /* wake up link */
859 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
860 }
861
862 static void ahci_disable_alpm(struct ata_port *ap)
863 {
864 struct ahci_host_priv *hpriv = ap->host->private_data;
865 void __iomem *port_mmio = ahci_port_base(ap);
866 u32 cmd;
867 struct ahci_port_priv *pp = ap->private_data;
868
869 /* IPM bits should be disabled by libata-core */
870 /* get the existing command bits */
871 cmd = readl(port_mmio + PORT_CMD);
872
873 /* disable ALPM and ASP */
874 cmd &= ~PORT_CMD_ASP;
875 cmd &= ~PORT_CMD_ALPE;
876
877 /* force the interface back to active */
878 cmd |= PORT_CMD_ICC_ACTIVE;
879
880 /* write out new cmd value */
881 writel(cmd, port_mmio + PORT_CMD);
882 cmd = readl(port_mmio + PORT_CMD);
883
884 /* wait 10ms to be sure we've come out of any low power state */
885 msleep(10);
886
887 /* clear out any PhyRdy stuff from interrupt status */
888 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
889
890 /* go ahead and clean out PhyRdy Change from Serror too */
891 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
892
893 /*
894 * Clear flag to indicate that we should ignore all PhyRdy
895 * state changes
896 */
897 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
898
899 /*
900 * Enable interrupts on Phy Ready.
901 */
902 pp->intr_mask |= PORT_IRQ_PHYRDY;
903 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
904
905 /*
906 * don't change the link pm policy - we can be called
907 * just to turn of link pm temporarily
908 */
909 }
910
911 static int ahci_enable_alpm(struct ata_port *ap,
912 enum link_pm policy)
913 {
914 struct ahci_host_priv *hpriv = ap->host->private_data;
915 void __iomem *port_mmio = ahci_port_base(ap);
916 u32 cmd;
917 struct ahci_port_priv *pp = ap->private_data;
918 u32 asp;
919
920 /* Make sure the host is capable of link power management */
921 if (!(hpriv->cap & HOST_CAP_ALPM))
922 return -EINVAL;
923
924 switch (policy) {
925 case MAX_PERFORMANCE:
926 case NOT_AVAILABLE:
927 /*
928 * if we came here with NOT_AVAILABLE,
929 * it just means this is the first time we
930 * have tried to enable - default to max performance,
931 * and let the user go to lower power modes on request.
932 */
933 ahci_disable_alpm(ap);
934 return 0;
935 case MIN_POWER:
936 /* configure HBA to enter SLUMBER */
937 asp = PORT_CMD_ASP;
938 break;
939 case MEDIUM_POWER:
940 /* configure HBA to enter PARTIAL */
941 asp = 0;
942 break;
943 default:
944 return -EINVAL;
945 }
946
947 /*
948 * Disable interrupts on Phy Ready. This keeps us from
949 * getting woken up due to spurious phy ready interrupts
950 * TBD - Hot plug should be done via polling now, is
951 * that even supported?
952 */
953 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
954 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
955
956 /*
957 * Set a flag to indicate that we should ignore all PhyRdy
958 * state changes since these can happen now whenever we
959 * change link state
960 */
961 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
962
963 /* get the existing command bits */
964 cmd = readl(port_mmio + PORT_CMD);
965
966 /*
967 * Set ASP based on Policy
968 */
969 cmd |= asp;
970
971 /*
972 * Setting this bit will instruct the HBA to aggressively
973 * enter a lower power link state when it's appropriate and
974 * based on the value set above for ASP
975 */
976 cmd |= PORT_CMD_ALPE;
977
978 /* write out new cmd value */
979 writel(cmd, port_mmio + PORT_CMD);
980 cmd = readl(port_mmio + PORT_CMD);
981
982 /* IPM bits should be set by libata-core */
983 return 0;
984 }
985
986 #ifdef CONFIG_PM
987 static void ahci_power_down(struct ata_port *ap)
988 {
989 struct ahci_host_priv *hpriv = ap->host->private_data;
990 void __iomem *port_mmio = ahci_port_base(ap);
991 u32 cmd, scontrol;
992
993 if (!(hpriv->cap & HOST_CAP_SSS))
994 return;
995
996 /* put device into listen mode, first set PxSCTL.DET to 0 */
997 scontrol = readl(port_mmio + PORT_SCR_CTL);
998 scontrol &= ~0xf;
999 writel(scontrol, port_mmio + PORT_SCR_CTL);
1000
1001 /* then set PxCMD.SUD to 0 */
1002 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1003 cmd &= ~PORT_CMD_SPIN_UP;
1004 writel(cmd, port_mmio + PORT_CMD);
1005 }
1006 #endif
1007
1008 static void ahci_start_port(struct ata_port *ap)
1009 {
1010 /* enable FIS reception */
1011 ahci_start_fis_rx(ap);
1012
1013 /* enable DMA */
1014 ahci_start_engine(ap);
1015 }
1016
1017 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1018 {
1019 int rc;
1020
1021 /* disable DMA */
1022 rc = ahci_stop_engine(ap);
1023 if (rc) {
1024 *emsg = "failed to stop engine";
1025 return rc;
1026 }
1027
1028 /* disable FIS reception */
1029 rc = ahci_stop_fis_rx(ap);
1030 if (rc) {
1031 *emsg = "failed stop FIS RX";
1032 return rc;
1033 }
1034
1035 return 0;
1036 }
1037
1038 static int ahci_reset_controller(struct ata_host *host)
1039 {
1040 struct pci_dev *pdev = to_pci_dev(host->dev);
1041 struct ahci_host_priv *hpriv = host->private_data;
1042 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1043 u32 tmp;
1044
1045 /* we must be in AHCI mode, before using anything
1046 * AHCI-specific, such as HOST_RESET.
1047 */
1048 ahci_enable_ahci(mmio);
1049
1050 /* global controller reset */
1051 if (!ahci_skip_host_reset) {
1052 tmp = readl(mmio + HOST_CTL);
1053 if ((tmp & HOST_RESET) == 0) {
1054 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1055 readl(mmio + HOST_CTL); /* flush */
1056 }
1057
1058 /* reset must complete within 1 second, or
1059 * the hardware should be considered fried.
1060 */
1061 ssleep(1);
1062
1063 tmp = readl(mmio + HOST_CTL);
1064 if (tmp & HOST_RESET) {
1065 dev_printk(KERN_ERR, host->dev,
1066 "controller reset failed (0x%x)\n", tmp);
1067 return -EIO;
1068 }
1069
1070 /* turn on AHCI mode */
1071 ahci_enable_ahci(mmio);
1072
1073 /* Some registers might be cleared on reset. Restore
1074 * initial values.
1075 */
1076 ahci_restore_initial_config(host);
1077 } else
1078 dev_printk(KERN_INFO, host->dev,
1079 "skipping global host reset\n");
1080
1081 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1082 u16 tmp16;
1083
1084 /* configure PCS */
1085 pci_read_config_word(pdev, 0x92, &tmp16);
1086 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1087 tmp16 |= hpriv->port_map;
1088 pci_write_config_word(pdev, 0x92, tmp16);
1089 }
1090 }
1091
1092 return 0;
1093 }
1094
1095 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1096 int port_no, void __iomem *mmio,
1097 void __iomem *port_mmio)
1098 {
1099 const char *emsg = NULL;
1100 int rc;
1101 u32 tmp;
1102
1103 /* make sure port is not active */
1104 rc = ahci_deinit_port(ap, &emsg);
1105 if (rc)
1106 dev_printk(KERN_WARNING, &pdev->dev,
1107 "%s (%d)\n", emsg, rc);
1108
1109 /* clear SError */
1110 tmp = readl(port_mmio + PORT_SCR_ERR);
1111 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1112 writel(tmp, port_mmio + PORT_SCR_ERR);
1113
1114 /* clear port IRQ */
1115 tmp = readl(port_mmio + PORT_IRQ_STAT);
1116 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1117 if (tmp)
1118 writel(tmp, port_mmio + PORT_IRQ_STAT);
1119
1120 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1121 }
1122
1123 static void ahci_init_controller(struct ata_host *host)
1124 {
1125 struct ahci_host_priv *hpriv = host->private_data;
1126 struct pci_dev *pdev = to_pci_dev(host->dev);
1127 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1128 int i;
1129 void __iomem *port_mmio;
1130 u32 tmp;
1131 int mv;
1132
1133 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1134 if (pdev->device == 0x6121)
1135 mv = 2;
1136 else
1137 mv = 4;
1138 port_mmio = __ahci_port_base(host, mv);
1139
1140 writel(0, port_mmio + PORT_IRQ_MASK);
1141
1142 /* clear port IRQ */
1143 tmp = readl(port_mmio + PORT_IRQ_STAT);
1144 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1145 if (tmp)
1146 writel(tmp, port_mmio + PORT_IRQ_STAT);
1147 }
1148
1149 for (i = 0; i < host->n_ports; i++) {
1150 struct ata_port *ap = host->ports[i];
1151
1152 port_mmio = ahci_port_base(ap);
1153 if (ata_port_is_dummy(ap))
1154 continue;
1155
1156 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1157 }
1158
1159 tmp = readl(mmio + HOST_CTL);
1160 VPRINTK("HOST_CTL 0x%x\n", tmp);
1161 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1162 tmp = readl(mmio + HOST_CTL);
1163 VPRINTK("HOST_CTL 0x%x\n", tmp);
1164 }
1165
1166 static void ahci_dev_config(struct ata_device *dev)
1167 {
1168 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1169
1170 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1171 dev->max_sectors = 255;
1172 ata_dev_printk(dev, KERN_INFO,
1173 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1174 }
1175 }
1176
1177 static unsigned int ahci_dev_classify(struct ata_port *ap)
1178 {
1179 void __iomem *port_mmio = ahci_port_base(ap);
1180 struct ata_taskfile tf;
1181 u32 tmp;
1182
1183 tmp = readl(port_mmio + PORT_SIG);
1184 tf.lbah = (tmp >> 24) & 0xff;
1185 tf.lbam = (tmp >> 16) & 0xff;
1186 tf.lbal = (tmp >> 8) & 0xff;
1187 tf.nsect = (tmp) & 0xff;
1188
1189 return ata_dev_classify(&tf);
1190 }
1191
1192 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1193 u32 opts)
1194 {
1195 dma_addr_t cmd_tbl_dma;
1196
1197 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1198
1199 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1200 pp->cmd_slot[tag].status = 0;
1201 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1202 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1203 }
1204
1205 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1206 {
1207 void __iomem *port_mmio = ahci_port_base(ap);
1208 struct ahci_host_priv *hpriv = ap->host->private_data;
1209 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1210 u32 tmp;
1211 int busy, rc;
1212
1213 /* do we need to kick the port? */
1214 busy = status & (ATA_BUSY | ATA_DRQ);
1215 if (!busy && !force_restart)
1216 return 0;
1217
1218 /* stop engine */
1219 rc = ahci_stop_engine(ap);
1220 if (rc)
1221 goto out_restart;
1222
1223 /* need to do CLO? */
1224 if (!busy) {
1225 rc = 0;
1226 goto out_restart;
1227 }
1228
1229 if (!(hpriv->cap & HOST_CAP_CLO)) {
1230 rc = -EOPNOTSUPP;
1231 goto out_restart;
1232 }
1233
1234 /* perform CLO */
1235 tmp = readl(port_mmio + PORT_CMD);
1236 tmp |= PORT_CMD_CLO;
1237 writel(tmp, port_mmio + PORT_CMD);
1238
1239 rc = 0;
1240 tmp = ata_wait_register(port_mmio + PORT_CMD,
1241 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1242 if (tmp & PORT_CMD_CLO)
1243 rc = -EIO;
1244
1245 /* restart engine */
1246 out_restart:
1247 ahci_start_engine(ap);
1248 return rc;
1249 }
1250
1251 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1252 struct ata_taskfile *tf, int is_cmd, u16 flags,
1253 unsigned long timeout_msec)
1254 {
1255 const u32 cmd_fis_len = 5; /* five dwords */
1256 struct ahci_port_priv *pp = ap->private_data;
1257 void __iomem *port_mmio = ahci_port_base(ap);
1258 u8 *fis = pp->cmd_tbl;
1259 u32 tmp;
1260
1261 /* prep the command */
1262 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1263 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1264
1265 /* issue & wait */
1266 writel(1, port_mmio + PORT_CMD_ISSUE);
1267
1268 if (timeout_msec) {
1269 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1270 1, timeout_msec);
1271 if (tmp & 0x1) {
1272 ahci_kick_engine(ap, 1);
1273 return -EBUSY;
1274 }
1275 } else
1276 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1277
1278 return 0;
1279 }
1280
1281 static int ahci_check_ready(struct ata_link *link)
1282 {
1283 void __iomem *port_mmio = ahci_port_base(link->ap);
1284 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1285
1286 return ata_check_ready(status);
1287 }
1288
1289 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1290 unsigned long deadline)
1291 {
1292 struct ata_port *ap = link->ap;
1293 int pmp = sata_srst_pmp(link);
1294 const char *reason = NULL;
1295 unsigned long now, msecs;
1296 struct ata_taskfile tf;
1297 int rc;
1298
1299 DPRINTK("ENTER\n");
1300
1301 /* prepare for SRST (AHCI-1.1 10.4.1) */
1302 rc = ahci_kick_engine(ap, 1);
1303 if (rc && rc != -EOPNOTSUPP)
1304 ata_link_printk(link, KERN_WARNING,
1305 "failed to reset engine (errno=%d)\n", rc);
1306
1307 ata_tf_init(link->device, &tf);
1308
1309 /* issue the first D2H Register FIS */
1310 msecs = 0;
1311 now = jiffies;
1312 if (time_after(now, deadline))
1313 msecs = jiffies_to_msecs(deadline - now);
1314
1315 tf.ctl |= ATA_SRST;
1316 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1317 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1318 rc = -EIO;
1319 reason = "1st FIS failed";
1320 goto fail;
1321 }
1322
1323 /* spec says at least 5us, but be generous and sleep for 1ms */
1324 msleep(1);
1325
1326 /* issue the second D2H Register FIS */
1327 tf.ctl &= ~ATA_SRST;
1328 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1329
1330 /* wait for link to become ready */
1331 rc = ata_wait_after_reset(link, deadline, ahci_check_ready);
1332 /* link occupied, -ENODEV too is an error */
1333 if (rc) {
1334 reason = "device not ready";
1335 goto fail;
1336 }
1337 *class = ahci_dev_classify(ap);
1338
1339 DPRINTK("EXIT, class=%u\n", *class);
1340 return 0;
1341
1342 fail:
1343 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1344 return rc;
1345 }
1346
1347 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1348 unsigned long deadline)
1349 {
1350 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1351 struct ata_port *ap = link->ap;
1352 struct ahci_port_priv *pp = ap->private_data;
1353 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1354 struct ata_taskfile tf;
1355 bool online;
1356 int rc;
1357
1358 DPRINTK("ENTER\n");
1359
1360 ahci_stop_engine(ap);
1361
1362 /* clear D2H reception area to properly wait for D2H FIS */
1363 ata_tf_init(link->device, &tf);
1364 tf.command = 0x80;
1365 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1366
1367 rc = sata_link_hardreset(link, timing, deadline, &online,
1368 ahci_check_ready);
1369
1370 ahci_start_engine(ap);
1371
1372 if (online)
1373 *class = ahci_dev_classify(ap);
1374
1375 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1376 return rc;
1377 }
1378
1379 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1380 unsigned long deadline)
1381 {
1382 struct ata_port *ap = link->ap;
1383 bool online;
1384 int rc;
1385
1386 DPRINTK("ENTER\n");
1387
1388 ahci_stop_engine(ap);
1389
1390 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1391 deadline, &online, NULL);
1392
1393 ahci_start_engine(ap);
1394
1395 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1396
1397 /* vt8251 doesn't clear BSY on signature FIS reception,
1398 * request follow-up softreset.
1399 */
1400 return online ? -EAGAIN : rc;
1401 }
1402
1403 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1404 unsigned long deadline)
1405 {
1406 struct ata_port *ap = link->ap;
1407 struct ahci_port_priv *pp = ap->private_data;
1408 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1409 struct ata_taskfile tf;
1410 bool online;
1411 int rc;
1412
1413 ahci_stop_engine(ap);
1414
1415 /* clear D2H reception area to properly wait for D2H FIS */
1416 ata_tf_init(link->device, &tf);
1417 tf.command = 0x80;
1418 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1419
1420 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1421 deadline, &online, NULL);
1422
1423 ahci_start_engine(ap);
1424
1425 /* The pseudo configuration device on SIMG4726 attached to
1426 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1427 * hardreset if no device is attached to the first downstream
1428 * port && the pseudo device locks up on SRST w/ PMP==0. To
1429 * work around this, wait for !BSY only briefly. If BSY isn't
1430 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1431 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1432 *
1433 * Wait for two seconds. Devices attached to downstream port
1434 * which can't process the following IDENTIFY after this will
1435 * have to be reset again. For most cases, this should
1436 * suffice while making probing snappish enough.
1437 */
1438 if (online) {
1439 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1440 ahci_check_ready);
1441 if (rc)
1442 ahci_kick_engine(ap, 0);
1443 }
1444 return rc;
1445 }
1446
1447 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1448 {
1449 struct ata_port *ap = link->ap;
1450 void __iomem *port_mmio = ahci_port_base(ap);
1451 u32 new_tmp, tmp;
1452
1453 ata_std_postreset(link, class);
1454
1455 /* Make sure port's ATAPI bit is set appropriately */
1456 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1457 if (*class == ATA_DEV_ATAPI)
1458 new_tmp |= PORT_CMD_ATAPI;
1459 else
1460 new_tmp &= ~PORT_CMD_ATAPI;
1461 if (new_tmp != tmp) {
1462 writel(new_tmp, port_mmio + PORT_CMD);
1463 readl(port_mmio + PORT_CMD); /* flush */
1464 }
1465 }
1466
1467 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1468 {
1469 struct scatterlist *sg;
1470 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1471 unsigned int si;
1472
1473 VPRINTK("ENTER\n");
1474
1475 /*
1476 * Next, the S/G list.
1477 */
1478 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1479 dma_addr_t addr = sg_dma_address(sg);
1480 u32 sg_len = sg_dma_len(sg);
1481
1482 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1483 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1484 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1485 }
1486
1487 return si;
1488 }
1489
1490 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1491 {
1492 struct ata_port *ap = qc->ap;
1493 struct ahci_port_priv *pp = ap->private_data;
1494 int is_atapi = ata_is_atapi(qc->tf.protocol);
1495 void *cmd_tbl;
1496 u32 opts;
1497 const u32 cmd_fis_len = 5; /* five dwords */
1498 unsigned int n_elem;
1499
1500 /*
1501 * Fill in command table information. First, the header,
1502 * a SATA Register - Host to Device command FIS.
1503 */
1504 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1505
1506 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1507 if (is_atapi) {
1508 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1509 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1510 }
1511
1512 n_elem = 0;
1513 if (qc->flags & ATA_QCFLAG_DMAMAP)
1514 n_elem = ahci_fill_sg(qc, cmd_tbl);
1515
1516 /*
1517 * Fill in command slot information.
1518 */
1519 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1520 if (qc->tf.flags & ATA_TFLAG_WRITE)
1521 opts |= AHCI_CMD_WRITE;
1522 if (is_atapi)
1523 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1524
1525 ahci_fill_cmd_slot(pp, qc->tag, opts);
1526 }
1527
1528 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1529 {
1530 struct ahci_host_priv *hpriv = ap->host->private_data;
1531 struct ahci_port_priv *pp = ap->private_data;
1532 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1533 struct ata_link *link = NULL;
1534 struct ata_queued_cmd *active_qc;
1535 struct ata_eh_info *active_ehi;
1536 u32 serror;
1537
1538 /* determine active link */
1539 ata_port_for_each_link(link, ap)
1540 if (ata_link_active(link))
1541 break;
1542 if (!link)
1543 link = &ap->link;
1544
1545 active_qc = ata_qc_from_tag(ap, link->active_tag);
1546 active_ehi = &link->eh_info;
1547
1548 /* record irq stat */
1549 ata_ehi_clear_desc(host_ehi);
1550 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1551
1552 /* AHCI needs SError cleared; otherwise, it might lock up */
1553 ahci_scr_read(ap, SCR_ERROR, &serror);
1554 ahci_scr_write(ap, SCR_ERROR, serror);
1555 host_ehi->serror |= serror;
1556
1557 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1558 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1559 irq_stat &= ~PORT_IRQ_IF_ERR;
1560
1561 if (irq_stat & PORT_IRQ_TF_ERR) {
1562 /* If qc is active, charge it; otherwise, the active
1563 * link. There's no active qc on NCQ errors. It will
1564 * be determined by EH by reading log page 10h.
1565 */
1566 if (active_qc)
1567 active_qc->err_mask |= AC_ERR_DEV;
1568 else
1569 active_ehi->err_mask |= AC_ERR_DEV;
1570
1571 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1572 host_ehi->serror &= ~SERR_INTERNAL;
1573 }
1574
1575 if (irq_stat & PORT_IRQ_UNK_FIS) {
1576 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1577
1578 active_ehi->err_mask |= AC_ERR_HSM;
1579 active_ehi->action |= ATA_EH_RESET;
1580 ata_ehi_push_desc(active_ehi,
1581 "unknown FIS %08x %08x %08x %08x" ,
1582 unk[0], unk[1], unk[2], unk[3]);
1583 }
1584
1585 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1586 active_ehi->err_mask |= AC_ERR_HSM;
1587 active_ehi->action |= ATA_EH_RESET;
1588 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1589 }
1590
1591 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1592 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1593 host_ehi->action |= ATA_EH_RESET;
1594 ata_ehi_push_desc(host_ehi, "host bus error");
1595 }
1596
1597 if (irq_stat & PORT_IRQ_IF_ERR) {
1598 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1599 host_ehi->action |= ATA_EH_RESET;
1600 ata_ehi_push_desc(host_ehi, "interface fatal error");
1601 }
1602
1603 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1604 ata_ehi_hotplugged(host_ehi);
1605 ata_ehi_push_desc(host_ehi, "%s",
1606 irq_stat & PORT_IRQ_CONNECT ?
1607 "connection status changed" : "PHY RDY changed");
1608 }
1609
1610 /* okay, let's hand over to EH */
1611
1612 if (irq_stat & PORT_IRQ_FREEZE)
1613 ata_port_freeze(ap);
1614 else
1615 ata_port_abort(ap);
1616 }
1617
1618 static void ahci_port_intr(struct ata_port *ap)
1619 {
1620 void __iomem *port_mmio = ahci_port_base(ap);
1621 struct ata_eh_info *ehi = &ap->link.eh_info;
1622 struct ahci_port_priv *pp = ap->private_data;
1623 struct ahci_host_priv *hpriv = ap->host->private_data;
1624 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1625 u32 status, qc_active;
1626 int rc;
1627
1628 status = readl(port_mmio + PORT_IRQ_STAT);
1629 writel(status, port_mmio + PORT_IRQ_STAT);
1630
1631 /* ignore BAD_PMP while resetting */
1632 if (unlikely(resetting))
1633 status &= ~PORT_IRQ_BAD_PMP;
1634
1635 /* If we are getting PhyRdy, this is
1636 * just a power state change, we should
1637 * clear out this, plus the PhyRdy/Comm
1638 * Wake bits from Serror
1639 */
1640 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1641 (status & PORT_IRQ_PHYRDY)) {
1642 status &= ~PORT_IRQ_PHYRDY;
1643 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1644 }
1645
1646 if (unlikely(status & PORT_IRQ_ERROR)) {
1647 ahci_error_intr(ap, status);
1648 return;
1649 }
1650
1651 if (status & PORT_IRQ_SDB_FIS) {
1652 /* If SNotification is available, leave notification
1653 * handling to sata_async_notification(). If not,
1654 * emulate it by snooping SDB FIS RX area.
1655 *
1656 * Snooping FIS RX area is probably cheaper than
1657 * poking SNotification but some constrollers which
1658 * implement SNotification, ICH9 for example, don't
1659 * store AN SDB FIS into receive area.
1660 */
1661 if (hpriv->cap & HOST_CAP_SNTF)
1662 sata_async_notification(ap);
1663 else {
1664 /* If the 'N' bit in word 0 of the FIS is set,
1665 * we just received asynchronous notification.
1666 * Tell libata about it.
1667 */
1668 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1669 u32 f0 = le32_to_cpu(f[0]);
1670
1671 if (f0 & (1 << 15))
1672 sata_async_notification(ap);
1673 }
1674 }
1675
1676 /* pp->active_link is valid iff any command is in flight */
1677 if (ap->qc_active && pp->active_link->sactive)
1678 qc_active = readl(port_mmio + PORT_SCR_ACT);
1679 else
1680 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1681
1682 rc = ata_qc_complete_multiple(ap, qc_active);
1683
1684 /* while resetting, invalid completions are expected */
1685 if (unlikely(rc < 0 && !resetting)) {
1686 ehi->err_mask |= AC_ERR_HSM;
1687 ehi->action |= ATA_EH_RESET;
1688 ata_port_freeze(ap);
1689 }
1690 }
1691
1692 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1693 {
1694 struct ata_host *host = dev_instance;
1695 struct ahci_host_priv *hpriv;
1696 unsigned int i, handled = 0;
1697 void __iomem *mmio;
1698 u32 irq_stat, irq_ack = 0;
1699
1700 VPRINTK("ENTER\n");
1701
1702 hpriv = host->private_data;
1703 mmio = host->iomap[AHCI_PCI_BAR];
1704
1705 /* sigh. 0xffffffff is a valid return from h/w */
1706 irq_stat = readl(mmio + HOST_IRQ_STAT);
1707 irq_stat &= hpriv->port_map;
1708 if (!irq_stat)
1709 return IRQ_NONE;
1710
1711 spin_lock(&host->lock);
1712
1713 for (i = 0; i < host->n_ports; i++) {
1714 struct ata_port *ap;
1715
1716 if (!(irq_stat & (1 << i)))
1717 continue;
1718
1719 ap = host->ports[i];
1720 if (ap) {
1721 ahci_port_intr(ap);
1722 VPRINTK("port %u\n", i);
1723 } else {
1724 VPRINTK("port %u (no irq)\n", i);
1725 if (ata_ratelimit())
1726 dev_printk(KERN_WARNING, host->dev,
1727 "interrupt on disabled port %u\n", i);
1728 }
1729
1730 irq_ack |= (1 << i);
1731 }
1732
1733 if (irq_ack) {
1734 writel(irq_ack, mmio + HOST_IRQ_STAT);
1735 handled = 1;
1736 }
1737
1738 spin_unlock(&host->lock);
1739
1740 VPRINTK("EXIT\n");
1741
1742 return IRQ_RETVAL(handled);
1743 }
1744
1745 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1746 {
1747 struct ata_port *ap = qc->ap;
1748 void __iomem *port_mmio = ahci_port_base(ap);
1749 struct ahci_port_priv *pp = ap->private_data;
1750
1751 /* Keep track of the currently active link. It will be used
1752 * in completion path to determine whether NCQ phase is in
1753 * progress.
1754 */
1755 pp->active_link = qc->dev->link;
1756
1757 if (qc->tf.protocol == ATA_PROT_NCQ)
1758 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1759 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1760 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1761
1762 return 0;
1763 }
1764
1765 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1766 {
1767 struct ahci_port_priv *pp = qc->ap->private_data;
1768 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1769
1770 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1771 return true;
1772 }
1773
1774 static void ahci_freeze(struct ata_port *ap)
1775 {
1776 void __iomem *port_mmio = ahci_port_base(ap);
1777
1778 /* turn IRQ off */
1779 writel(0, port_mmio + PORT_IRQ_MASK);
1780 }
1781
1782 static void ahci_thaw(struct ata_port *ap)
1783 {
1784 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1785 void __iomem *port_mmio = ahci_port_base(ap);
1786 u32 tmp;
1787 struct ahci_port_priv *pp = ap->private_data;
1788
1789 /* clear IRQ */
1790 tmp = readl(port_mmio + PORT_IRQ_STAT);
1791 writel(tmp, port_mmio + PORT_IRQ_STAT);
1792 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1793
1794 /* turn IRQ back on */
1795 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1796 }
1797
1798 static void ahci_error_handler(struct ata_port *ap)
1799 {
1800 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1801 /* restart engine */
1802 ahci_stop_engine(ap);
1803 ahci_start_engine(ap);
1804 }
1805
1806 sata_pmp_error_handler(ap);
1807 }
1808
1809 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1810 {
1811 struct ata_port *ap = qc->ap;
1812
1813 /* make DMA engine forget about the failed command */
1814 if (qc->flags & ATA_QCFLAG_FAILED)
1815 ahci_kick_engine(ap, 1);
1816 }
1817
1818 static void ahci_pmp_attach(struct ata_port *ap)
1819 {
1820 void __iomem *port_mmio = ahci_port_base(ap);
1821 struct ahci_port_priv *pp = ap->private_data;
1822 u32 cmd;
1823
1824 cmd = readl(port_mmio + PORT_CMD);
1825 cmd |= PORT_CMD_PMP;
1826 writel(cmd, port_mmio + PORT_CMD);
1827
1828 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1829 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1830 }
1831
1832 static void ahci_pmp_detach(struct ata_port *ap)
1833 {
1834 void __iomem *port_mmio = ahci_port_base(ap);
1835 struct ahci_port_priv *pp = ap->private_data;
1836 u32 cmd;
1837
1838 cmd = readl(port_mmio + PORT_CMD);
1839 cmd &= ~PORT_CMD_PMP;
1840 writel(cmd, port_mmio + PORT_CMD);
1841
1842 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1843 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1844 }
1845
1846 static int ahci_port_resume(struct ata_port *ap)
1847 {
1848 ahci_power_up(ap);
1849 ahci_start_port(ap);
1850
1851 if (sata_pmp_attached(ap))
1852 ahci_pmp_attach(ap);
1853 else
1854 ahci_pmp_detach(ap);
1855
1856 return 0;
1857 }
1858
1859 #ifdef CONFIG_PM
1860 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1861 {
1862 const char *emsg = NULL;
1863 int rc;
1864
1865 rc = ahci_deinit_port(ap, &emsg);
1866 if (rc == 0)
1867 ahci_power_down(ap);
1868 else {
1869 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1870 ahci_start_port(ap);
1871 }
1872
1873 return rc;
1874 }
1875
1876 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1877 {
1878 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1879 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1880 u32 ctl;
1881
1882 if (mesg.event & PM_EVENT_SLEEP) {
1883 /* AHCI spec rev1.1 section 8.3.3:
1884 * Software must disable interrupts prior to requesting a
1885 * transition of the HBA to D3 state.
1886 */
1887 ctl = readl(mmio + HOST_CTL);
1888 ctl &= ~HOST_IRQ_EN;
1889 writel(ctl, mmio + HOST_CTL);
1890 readl(mmio + HOST_CTL); /* flush */
1891 }
1892
1893 return ata_pci_device_suspend(pdev, mesg);
1894 }
1895
1896 static int ahci_pci_device_resume(struct pci_dev *pdev)
1897 {
1898 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1899 int rc;
1900
1901 rc = ata_pci_device_do_resume(pdev);
1902 if (rc)
1903 return rc;
1904
1905 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1906 rc = ahci_reset_controller(host);
1907 if (rc)
1908 return rc;
1909
1910 ahci_init_controller(host);
1911 }
1912
1913 ata_host_resume(host);
1914
1915 return 0;
1916 }
1917 #endif
1918
1919 static int ahci_port_start(struct ata_port *ap)
1920 {
1921 struct device *dev = ap->host->dev;
1922 struct ahci_port_priv *pp;
1923 void *mem;
1924 dma_addr_t mem_dma;
1925
1926 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1927 if (!pp)
1928 return -ENOMEM;
1929
1930 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1931 GFP_KERNEL);
1932 if (!mem)
1933 return -ENOMEM;
1934 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1935
1936 /*
1937 * First item in chunk of DMA memory: 32-slot command table,
1938 * 32 bytes each in size
1939 */
1940 pp->cmd_slot = mem;
1941 pp->cmd_slot_dma = mem_dma;
1942
1943 mem += AHCI_CMD_SLOT_SZ;
1944 mem_dma += AHCI_CMD_SLOT_SZ;
1945
1946 /*
1947 * Second item: Received-FIS area
1948 */
1949 pp->rx_fis = mem;
1950 pp->rx_fis_dma = mem_dma;
1951
1952 mem += AHCI_RX_FIS_SZ;
1953 mem_dma += AHCI_RX_FIS_SZ;
1954
1955 /*
1956 * Third item: data area for storing a single command
1957 * and its scatter-gather table
1958 */
1959 pp->cmd_tbl = mem;
1960 pp->cmd_tbl_dma = mem_dma;
1961
1962 /*
1963 * Save off initial list of interrupts to be enabled.
1964 * This could be changed later
1965 */
1966 pp->intr_mask = DEF_PORT_IRQ;
1967
1968 ap->private_data = pp;
1969
1970 /* engage engines, captain */
1971 return ahci_port_resume(ap);
1972 }
1973
1974 static void ahci_port_stop(struct ata_port *ap)
1975 {
1976 const char *emsg = NULL;
1977 int rc;
1978
1979 /* de-initialize port */
1980 rc = ahci_deinit_port(ap, &emsg);
1981 if (rc)
1982 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1983 }
1984
1985 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1986 {
1987 int rc;
1988
1989 if (using_dac &&
1990 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1991 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1992 if (rc) {
1993 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1994 if (rc) {
1995 dev_printk(KERN_ERR, &pdev->dev,
1996 "64-bit DMA enable failed\n");
1997 return rc;
1998 }
1999 }
2000 } else {
2001 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2002 if (rc) {
2003 dev_printk(KERN_ERR, &pdev->dev,
2004 "32-bit DMA enable failed\n");
2005 return rc;
2006 }
2007 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2008 if (rc) {
2009 dev_printk(KERN_ERR, &pdev->dev,
2010 "32-bit consistent DMA enable failed\n");
2011 return rc;
2012 }
2013 }
2014 return 0;
2015 }
2016
2017 static void ahci_print_info(struct ata_host *host)
2018 {
2019 struct ahci_host_priv *hpriv = host->private_data;
2020 struct pci_dev *pdev = to_pci_dev(host->dev);
2021 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2022 u32 vers, cap, impl, speed;
2023 const char *speed_s;
2024 u16 cc;
2025 const char *scc_s;
2026
2027 vers = readl(mmio + HOST_VERSION);
2028 cap = hpriv->cap;
2029 impl = hpriv->port_map;
2030
2031 speed = (cap >> 20) & 0xf;
2032 if (speed == 1)
2033 speed_s = "1.5";
2034 else if (speed == 2)
2035 speed_s = "3";
2036 else
2037 speed_s = "?";
2038
2039 pci_read_config_word(pdev, 0x0a, &cc);
2040 if (cc == PCI_CLASS_STORAGE_IDE)
2041 scc_s = "IDE";
2042 else if (cc == PCI_CLASS_STORAGE_SATA)
2043 scc_s = "SATA";
2044 else if (cc == PCI_CLASS_STORAGE_RAID)
2045 scc_s = "RAID";
2046 else
2047 scc_s = "unknown";
2048
2049 dev_printk(KERN_INFO, &pdev->dev,
2050 "AHCI %02x%02x.%02x%02x "
2051 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2052 ,
2053
2054 (vers >> 24) & 0xff,
2055 (vers >> 16) & 0xff,
2056 (vers >> 8) & 0xff,
2057 vers & 0xff,
2058
2059 ((cap >> 8) & 0x1f) + 1,
2060 (cap & 0x1f) + 1,
2061 speed_s,
2062 impl,
2063 scc_s);
2064
2065 dev_printk(KERN_INFO, &pdev->dev,
2066 "flags: "
2067 "%s%s%s%s%s%s%s"
2068 "%s%s%s%s%s%s%s\n"
2069 ,
2070
2071 cap & (1 << 31) ? "64bit " : "",
2072 cap & (1 << 30) ? "ncq " : "",
2073 cap & (1 << 29) ? "sntf " : "",
2074 cap & (1 << 28) ? "ilck " : "",
2075 cap & (1 << 27) ? "stag " : "",
2076 cap & (1 << 26) ? "pm " : "",
2077 cap & (1 << 25) ? "led " : "",
2078
2079 cap & (1 << 24) ? "clo " : "",
2080 cap & (1 << 19) ? "nz " : "",
2081 cap & (1 << 18) ? "only " : "",
2082 cap & (1 << 17) ? "pmp " : "",
2083 cap & (1 << 15) ? "pio " : "",
2084 cap & (1 << 14) ? "slum " : "",
2085 cap & (1 << 13) ? "part " : ""
2086 );
2087 }
2088
2089 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2090 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2091 * support PMP and the 4726 either directly exports the device
2092 * attached to the first downstream port or acts as a hardware storage
2093 * controller and emulate a single ATA device (can be RAID 0/1 or some
2094 * other configuration).
2095 *
2096 * When there's no device attached to the first downstream port of the
2097 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2098 * configure the 4726. However, ATA emulation of the device is very
2099 * lame. It doesn't send signature D2H Reg FIS after the initial
2100 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2101 *
2102 * The following function works around the problem by always using
2103 * hardreset on the port and not depending on receiving signature FIS
2104 * afterward. If signature FIS isn't received soon, ATA class is
2105 * assumed without follow-up softreset.
2106 */
2107 static void ahci_p5wdh_workaround(struct ata_host *host)
2108 {
2109 static struct dmi_system_id sysids[] = {
2110 {
2111 .ident = "P5W DH Deluxe",
2112 .matches = {
2113 DMI_MATCH(DMI_SYS_VENDOR,
2114 "ASUSTEK COMPUTER INC"),
2115 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2116 },
2117 },
2118 { }
2119 };
2120 struct pci_dev *pdev = to_pci_dev(host->dev);
2121
2122 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2123 dmi_check_system(sysids)) {
2124 struct ata_port *ap = host->ports[1];
2125
2126 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2127 "Deluxe on-board SIMG4726 workaround\n");
2128
2129 ap->ops = &ahci_p5wdh_ops;
2130 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2131 }
2132 }
2133
2134 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2135 {
2136 static int printed_version;
2137 unsigned int board_id = ent->driver_data;
2138 struct ata_port_info pi = ahci_port_info[board_id];
2139 const struct ata_port_info *ppi[] = { &pi, NULL };
2140 struct device *dev = &pdev->dev;
2141 struct ahci_host_priv *hpriv;
2142 struct ata_host *host;
2143 int n_ports, i, rc;
2144
2145 VPRINTK("ENTER\n");
2146
2147 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2148
2149 if (!printed_version++)
2150 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2151
2152 /* acquire resources */
2153 rc = pcim_enable_device(pdev);
2154 if (rc)
2155 return rc;
2156
2157 /* AHCI controllers often implement SFF compatible interface.
2158 * Grab all PCI BARs just in case.
2159 */
2160 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2161 if (rc == -EBUSY)
2162 pcim_pin_device(pdev);
2163 if (rc)
2164 return rc;
2165
2166 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2167 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2168 u8 map;
2169
2170 /* ICH6s share the same PCI ID for both piix and ahci
2171 * modes. Enabling ahci mode while MAP indicates
2172 * combined mode is a bad idea. Yield to ata_piix.
2173 */
2174 pci_read_config_byte(pdev, ICH_MAP, &map);
2175 if (map & 0x3) {
2176 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2177 "combined mode, can't enable AHCI mode\n");
2178 return -ENODEV;
2179 }
2180 }
2181
2182 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2183 if (!hpriv)
2184 return -ENOMEM;
2185 hpriv->flags |= (unsigned long)pi.private_data;
2186
2187 /* MCP65 revision A1 and A2 can't do MSI */
2188 if (board_id == board_ahci_mcp65 &&
2189 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2190 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2191
2192 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2193 pci_intx(pdev, 1);
2194
2195 /* save initial config */
2196 ahci_save_initial_config(pdev, hpriv);
2197
2198 /* prepare host */
2199 if (hpriv->cap & HOST_CAP_NCQ)
2200 pi.flags |= ATA_FLAG_NCQ;
2201
2202 if (hpriv->cap & HOST_CAP_PMP)
2203 pi.flags |= ATA_FLAG_PMP;
2204
2205 /* CAP.NP sometimes indicate the index of the last enabled
2206 * port, at other times, that of the last possible port, so
2207 * determining the maximum port number requires looking at
2208 * both CAP.NP and port_map.
2209 */
2210 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2211
2212 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2213 if (!host)
2214 return -ENOMEM;
2215 host->iomap = pcim_iomap_table(pdev);
2216 host->private_data = hpriv;
2217
2218 for (i = 0; i < host->n_ports; i++) {
2219 struct ata_port *ap = host->ports[i];
2220
2221 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2222 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2223 0x100 + ap->port_no * 0x80, "port");
2224
2225 /* set initial link pm policy */
2226 ap->pm_policy = NOT_AVAILABLE;
2227
2228 /* disabled/not-implemented port */
2229 if (!(hpriv->port_map & (1 << i)))
2230 ap->ops = &ata_dummy_port_ops;
2231 }
2232
2233 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2234 ahci_p5wdh_workaround(host);
2235
2236 /* initialize adapter */
2237 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2238 if (rc)
2239 return rc;
2240
2241 rc = ahci_reset_controller(host);
2242 if (rc)
2243 return rc;
2244
2245 ahci_init_controller(host);
2246 ahci_print_info(host);
2247
2248 pci_set_master(pdev);
2249 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2250 &ahci_sht);
2251 }
2252
2253 static int __init ahci_init(void)
2254 {
2255 return pci_register_driver(&ahci_pci_driver);
2256 }
2257
2258 static void __exit ahci_exit(void)
2259 {
2260 pci_unregister_driver(&ahci_pci_driver);
2261 }
2262
2263
2264 MODULE_AUTHOR("Jeff Garzik");
2265 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2266 MODULE_LICENSE("GPL");
2267 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2268 MODULE_VERSION(DRV_VERSION);
2269
2270 module_init(ahci_init);
2271 module_exit(ahci_exit);
x86 "subsystem" repository