2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
31 #include <linux/smp.h>
34 #include <asm/processor.h>
41 /* Handle unconfigured int18 (should never happen) */
42 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
44 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
48 /* Call the installed machine check handler for this CPU setup. */
49 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
50 unexpected_machine_check
;
54 #ifdef CONFIG_X86_NEW_MCE
56 #define MISC_MCELOG_MINOR 227
60 DEFINE_PER_CPU(unsigned, mce_exception_count
);
64 * 0: always panic on uncorrected errors, log corrected errors
65 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
66 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
67 * 3: never panic or SIGBUS, log all errors (for testing only)
69 static int tolerant
= 1;
72 static unsigned long notify_user
;
74 static int mce_bootlog
= -1;
76 static char trigger
[128];
77 static char *trigger_argv
[2] = { trigger
, NULL
};
79 static unsigned long dont_init_banks
;
81 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
83 /* MCA banks polled by the period polling timer for corrected events */
84 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
85 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
88 static inline int skip_bank_init(int i
)
90 return i
< BITS_PER_LONG
&& test_bit(i
, &dont_init_banks
);
93 /* Do initial initialization of a struct mce */
94 void mce_setup(struct mce
*m
)
96 memset(m
, 0, sizeof(struct mce
));
97 m
->cpu
= m
->extcpu
= smp_processor_id();
99 /* We hope get_seconds stays lockless */
100 m
->time
= get_seconds();
101 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
102 m
->cpuid
= cpuid_eax(1);
104 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
106 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
107 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
110 DEFINE_PER_CPU(struct mce
, injectm
);
111 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
114 * Lockless MCE logging infrastructure.
115 * This avoids deadlocks on printk locks without having to break locks. Also
116 * separate MCEs from kernel messages to avoid bogus bug reports.
119 static struct mce_log mcelog
= {
120 .signature
= MCE_LOG_SIGNATURE
,
122 .recordlen
= sizeof(struct mce
),
125 void mce_log(struct mce
*mce
)
127 unsigned next
, entry
;
132 entry
= rcu_dereference(mcelog
.next
);
135 * When the buffer fills up discard new entries.
136 * Assume that the earlier errors are the more
139 if (entry
>= MCE_LOG_LEN
) {
140 set_bit(MCE_OVERFLOW
,
141 (unsigned long *)&mcelog
.flags
);
144 /* Old left over entry. Skip: */
145 if (mcelog
.entry
[entry
].finished
) {
153 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
156 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
158 mcelog
.entry
[entry
].finished
= 1;
161 set_bit(0, ¬ify_user
);
164 static void print_mce(struct mce
*m
)
166 printk(KERN_EMERG
"\n"
167 KERN_EMERG
"HARDWARE ERROR\n"
169 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
170 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
172 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
173 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
175 if (m
->cs
== __KERNEL_CS
)
176 print_symbol("{%s}", m
->ip
);
179 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
181 printk("ADDR %llx ", m
->addr
);
183 printk("MISC %llx ", m
->misc
);
185 printk(KERN_EMERG
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
186 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
,
188 printk(KERN_EMERG
"This is not a software problem!\n");
189 printk(KERN_EMERG
"Run through mcelog --ascii to decode "
190 "and contact your hardware vendor\n");
193 static void mce_panic(char *msg
, struct mce
*backup
, u64 start
)
199 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
200 u64 tsc
= mcelog
.entry
[i
].tsc
;
202 if ((s64
)(tsc
- start
) < 0)
204 print_mce(&mcelog
.entry
[i
]);
205 if (backup
&& mcelog
.entry
[i
].tsc
== backup
->tsc
)
213 /* Support code for software error injection */
215 static int msr_to_offset(u32 msr
)
217 unsigned bank
= __get_cpu_var(injectm
.bank
);
219 return offsetof(struct mce
, ip
);
220 if (msr
== MSR_IA32_MC0_STATUS
+ bank
*4)
221 return offsetof(struct mce
, status
);
222 if (msr
== MSR_IA32_MC0_ADDR
+ bank
*4)
223 return offsetof(struct mce
, addr
);
224 if (msr
== MSR_IA32_MC0_MISC
+ bank
*4)
225 return offsetof(struct mce
, misc
);
226 if (msr
== MSR_IA32_MCG_STATUS
)
227 return offsetof(struct mce
, mcgstatus
);
231 /* MSR access wrappers used for error injection */
232 static u64
mce_rdmsrl(u32 msr
)
235 if (__get_cpu_var(injectm
).finished
) {
236 int offset
= msr_to_offset(msr
);
239 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
245 static void mce_wrmsrl(u32 msr
, u64 v
)
247 if (__get_cpu_var(injectm
).finished
) {
248 int offset
= msr_to_offset(msr
);
250 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
256 int mce_available(struct cpuinfo_x86
*c
)
260 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
263 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
265 if (regs
&& (m
->mcgstatus
& MCG_STATUS_RIPV
)) {
273 /* Assume the RIP in the MSR is exact. Is this true? */
274 m
->mcgstatus
|= MCG_STATUS_EIPV
;
275 m
->ip
= mce_rdmsrl(rip_msr
);
280 DEFINE_PER_CPU(unsigned, mce_poll_count
);
283 * Poll for corrected events or events that happened before reset.
284 * Those are just logged through /dev/mcelog.
286 * This is executed in standard interrupt context.
288 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
293 __get_cpu_var(mce_poll_count
)++;
297 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
298 for (i
= 0; i
< banks
; i
++) {
299 if (!bank
[i
] || !test_bit(i
, *b
))
308 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
309 if (!(m
.status
& MCI_STATUS_VAL
))
313 * Uncorrected events are handled by the exception handler
314 * when it is enabled. But when the exception is disabled log
317 * TBD do the same check for MCI_STATUS_EN here?
319 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
322 if (m
.status
& MCI_STATUS_MISCV
)
323 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
324 if (m
.status
& MCI_STATUS_ADDRV
)
325 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
327 if (!(flags
& MCP_TIMESTAMP
))
330 * Don't get the IP here because it's unlikely to
331 * have anything to do with the actual error location.
333 if (!(flags
& MCP_DONTLOG
)) {
335 add_taint(TAINT_MACHINE_CHECK
);
339 * Clear state for this bank.
341 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
345 * Don't clear MCG_STATUS here because it's only defined for
351 EXPORT_SYMBOL_GPL(machine_check_poll
);
354 * The actual machine check handler. This only handles real
355 * exceptions when something got corrupted coming in through int 18.
357 * This is executed in NMI context not subject to normal locking rules. This
358 * implies that most kernel services cannot be safely used. Don't even
359 * think about putting a printk in there!
361 void do_machine_check(struct pt_regs
*regs
, long error_code
)
363 struct mce m
, panicm
;
364 int panicm_found
= 0;
368 * If no_way_out gets set, there is no safe way to recover from this
369 * MCE. If tolerant is cranked up, we'll try anyway.
373 * If kill_it gets set, there might be a way to recover from this
377 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
379 atomic_inc(&mce_entry
);
381 __get_cpu_var(mce_exception_count
)++;
383 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
384 18, SIGKILL
) == NOTIFY_STOP
)
391 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
393 /* if the restart IP is not valid, we're done for */
394 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
400 for (i
= 0; i
< banks
; i
++) {
401 __clear_bit(i
, toclear
);
409 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
410 if ((m
.status
& MCI_STATUS_VAL
) == 0)
414 * Non uncorrected errors are handled by machine_check_poll
415 * Leave them alone, unless this panics.
417 if ((m
.status
& MCI_STATUS_UC
) == 0 && !no_way_out
)
421 * Set taint even when machine check was not enabled.
423 add_taint(TAINT_MACHINE_CHECK
);
425 __set_bit(i
, toclear
);
427 if (m
.status
& MCI_STATUS_EN
) {
428 /* if PCC was set, there's no way out */
429 no_way_out
|= !!(m
.status
& MCI_STATUS_PCC
);
431 * If this error was uncorrectable and there was
432 * an overflow, we're in trouble. If no overflow,
433 * we might get away with just killing a task.
435 if (m
.status
& MCI_STATUS_UC
) {
436 if (tolerant
< 1 || m
.status
& MCI_STATUS_OVER
)
442 * Machine check event was not enabled. Clear, but
448 if (m
.status
& MCI_STATUS_MISCV
)
449 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
450 if (m
.status
& MCI_STATUS_ADDRV
)
451 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
453 mce_get_rip(&m
, regs
);
457 * Did this bank cause the exception?
459 * Assume that the bank with uncorrectable errors did it,
460 * and that there is only a single one:
462 if ((m
.status
& MCI_STATUS_UC
) &&
463 (m
.status
& MCI_STATUS_EN
)) {
470 * If we didn't find an uncorrectable error, pick
471 * the last one (shouldn't happen, just being safe).
477 * If we have decided that we just CAN'T continue, and the user
478 * has not set tolerant to an insane level, give up and die.
480 if (no_way_out
&& tolerant
< 3)
481 mce_panic("Machine check", &panicm
, mcestart
);
484 * If the error seems to be unrecoverable, something should be
485 * done. Try to kill as little as possible. If we can kill just
486 * one task, do that. If the user has set the tolerance very
487 * high, don't try to do anything at all.
489 if (kill_it
&& tolerant
< 3) {
493 * If the EIPV bit is set, it means the saved IP is the
494 * instruction which caused the MCE.
496 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
497 user_space
= panicm
.ip
&& (panicm
.cs
& 3);
500 * If we know that the error was in user space, send a
501 * SIGBUS. Otherwise, panic if tolerance is low.
503 * force_sig() takes an awful lot of locks and has a slight
504 * risk of deadlocking.
507 force_sig(SIGBUS
, current
);
508 } else if (panic_on_oops
|| tolerant
< 2) {
509 mce_panic("Uncorrected machine check",
514 /* notify userspace ASAP */
515 set_thread_flag(TIF_MCE_NOTIFY
);
517 /* the last thing we do is clear state */
518 for (i
= 0; i
< banks
; i
++) {
519 if (test_bit(i
, toclear
))
520 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
522 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
524 atomic_dec(&mce_entry
);
527 EXPORT_SYMBOL_GPL(do_machine_check
);
529 #ifdef CONFIG_X86_MCE_INTEL
531 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
532 * @cpu: The CPU on which the event occurred.
533 * @status: Event status information
535 * This function should be called by the thermal interrupt after the
536 * event has been processed and the decision was made to log the event
539 * The status parameter will be saved to the 'status' field of 'struct mce'
540 * and historically has been the register value of the
541 * MSR_IA32_THERMAL_STATUS (Intel) msr.
543 void mce_log_therm_throt_event(__u64 status
)
548 m
.bank
= MCE_THERMAL_BANK
;
552 #endif /* CONFIG_X86_MCE_INTEL */
555 * Periodic polling timer for "silent" machine check errors. If the
556 * poller finds an MCE, poll 2x faster. When the poller finds no more
557 * errors, poll 2x slower (up to check_interval seconds).
559 static int check_interval
= 5 * 60; /* 5 minutes */
561 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
562 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
564 static void mcheck_timer(unsigned long data
)
566 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
569 WARN_ON(smp_processor_id() != data
);
571 if (mce_available(¤t_cpu_data
)) {
572 machine_check_poll(MCP_TIMESTAMP
,
573 &__get_cpu_var(mce_poll_banks
));
577 * Alert userspace if needed. If we logged an MCE, reduce the
578 * polling interval, otherwise increase the polling interval.
580 n
= &__get_cpu_var(next_interval
);
581 if (mce_notify_user())
582 *n
= max(*n
/2, HZ
/100);
584 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
586 t
->expires
= jiffies
+ *n
;
590 static void mce_do_trigger(struct work_struct
*work
)
592 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
595 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
598 * Notify the user(s) about new machine check events.
599 * Can be called from interrupt context, but not from machine check/NMI
602 int mce_notify_user(void)
604 /* Not more than two messages every minute */
605 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
607 clear_thread_flag(TIF_MCE_NOTIFY
);
609 if (test_and_clear_bit(0, ¬ify_user
)) {
610 wake_up_interruptible(&mce_wait
);
613 * There is no risk of missing notifications because
614 * work_pending is always cleared before the function is
617 if (trigger
[0] && !work_pending(&mce_trigger_work
))
618 schedule_work(&mce_trigger_work
);
620 if (__ratelimit(&ratelimit
))
621 printk(KERN_INFO
"Machine check events logged\n");
627 EXPORT_SYMBOL_GPL(mce_notify_user
);
630 * Initialize Machine Checks for a CPU.
632 static int mce_cap_init(void)
637 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
639 b
= cap
& MCG_BANKCNT_MASK
;
640 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
642 if (b
> MAX_NR_BANKS
) {
644 "MCE: Using only %u machine check banks out of %u\n",
649 /* Don't support asymmetric configurations today */
650 WARN_ON(banks
!= 0 && b
!= banks
);
653 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
656 memset(bank
, 0xff, banks
* sizeof(u64
));
659 /* Use accurate RIP reporting if available. */
660 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
661 rip_msr
= MSR_IA32_MCG_EIP
;
666 static void mce_init(void)
668 mce_banks_t all_banks
;
673 * Log the machine checks left over from the previous reset.
675 bitmap_fill(all_banks
, MAX_NR_BANKS
);
676 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
678 set_in_cr4(X86_CR4_MCE
);
680 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
682 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
684 for (i
= 0; i
< banks
; i
++) {
685 if (skip_bank_init(i
))
687 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
688 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
692 /* Add per CPU specific workarounds here */
693 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
695 /* This should be disabled by the BIOS, but isn't always */
696 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
697 if (c
->x86
== 15 && banks
> 4) {
699 * disable GART TBL walk error reporting, which
700 * trips off incorrectly with the IOMMU & 3ware
703 clear_bit(10, (unsigned long *)&bank
[4]);
705 if (c
->x86
<= 17 && mce_bootlog
< 0) {
707 * Lots of broken BIOS around that don't clear them
708 * by default and leave crap in there. Don't log:
713 * Various K7s with broken bank 0 around. Always disable
720 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
722 * SDM documents that on family 6 bank 0 should not be written
723 * because it aliases to another special BIOS controlled
725 * But it's not aliased anymore on model 0x1a+
726 * Don't ignore bank 0 completely because there could be a
727 * valid event later, merely don't write CTL0.
730 if (c
->x86
== 6 && c
->x86_model
< 0x1A)
731 __set_bit(0, &dont_init_banks
);
735 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
739 switch (c
->x86_vendor
) {
740 case X86_VENDOR_INTEL
:
741 if (mce_p5_enabled())
742 intel_p5_mcheck_init(c
);
744 case X86_VENDOR_CENTAUR
:
745 winchip_mcheck_init(c
);
750 static void mce_cpu_features(struct cpuinfo_x86
*c
)
752 switch (c
->x86_vendor
) {
753 case X86_VENDOR_INTEL
:
754 mce_intel_feature_init(c
);
757 mce_amd_feature_init(c
);
764 static void mce_init_timer(void)
766 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
767 int *n
= &__get_cpu_var(next_interval
);
769 *n
= check_interval
* HZ
;
772 setup_timer(t
, mcheck_timer
, smp_processor_id());
773 t
->expires
= round_jiffies(jiffies
+ *n
);
778 * Called for each booted CPU to set up machine checks.
779 * Must be called with preempt off:
781 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
788 if (!mce_available(c
))
791 if (mce_cap_init() < 0) {
797 machine_check_vector
= do_machine_check
;
805 * Character device to read and clear the MCE log.
808 static DEFINE_SPINLOCK(mce_state_lock
);
809 static int open_count
; /* #times opened */
810 static int open_exclu
; /* already open exclusive? */
812 static int mce_open(struct inode
*inode
, struct file
*file
)
814 spin_lock(&mce_state_lock
);
816 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
817 spin_unlock(&mce_state_lock
);
822 if (file
->f_flags
& O_EXCL
)
826 spin_unlock(&mce_state_lock
);
828 return nonseekable_open(inode
, file
);
831 static int mce_release(struct inode
*inode
, struct file
*file
)
833 spin_lock(&mce_state_lock
);
838 spin_unlock(&mce_state_lock
);
843 static void collect_tscs(void *data
)
845 unsigned long *cpu_tsc
= (unsigned long *)data
;
847 rdtscll(cpu_tsc
[smp_processor_id()]);
850 static DEFINE_MUTEX(mce_read_mutex
);
852 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
855 char __user
*buf
= ubuf
;
856 unsigned long *cpu_tsc
;
860 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
864 mutex_lock(&mce_read_mutex
);
865 next
= rcu_dereference(mcelog
.next
);
867 /* Only supports full reads right now */
868 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
869 mutex_unlock(&mce_read_mutex
);
878 for (i
= prev
; i
< next
; i
++) {
879 unsigned long start
= jiffies
;
881 while (!mcelog
.entry
[i
].finished
) {
882 if (time_after_eq(jiffies
, start
+ 2)) {
883 memset(mcelog
.entry
+ i
, 0,
890 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
892 buf
+= sizeof(struct mce
);
897 memset(mcelog
.entry
+ prev
, 0,
898 (next
- prev
) * sizeof(struct mce
));
900 next
= cmpxchg(&mcelog
.next
, prev
, 0);
901 } while (next
!= prev
);
906 * Collect entries that were still getting written before the
909 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
911 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
912 if (mcelog
.entry
[i
].finished
&&
913 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
914 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
917 buf
+= sizeof(struct mce
);
918 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
921 mutex_unlock(&mce_read_mutex
);
924 return err
? -EFAULT
: buf
- ubuf
;
927 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
929 poll_wait(file
, &mce_wait
, wait
);
930 if (rcu_dereference(mcelog
.next
))
931 return POLLIN
| POLLRDNORM
;
935 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
937 int __user
*p
= (int __user
*)arg
;
939 if (!capable(CAP_SYS_ADMIN
))
943 case MCE_GET_RECORD_LEN
:
944 return put_user(sizeof(struct mce
), p
);
945 case MCE_GET_LOG_LEN
:
946 return put_user(MCE_LOG_LEN
, p
);
947 case MCE_GETCLEAR_FLAGS
: {
951 flags
= mcelog
.flags
;
952 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
954 return put_user(flags
, p
);
961 /* Modified in mce-inject.c, so not static or const */
962 struct file_operations mce_chrdev_ops
= {
964 .release
= mce_release
,
967 .unlocked_ioctl
= mce_ioctl
,
969 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
971 static struct miscdevice mce_log_device
= {
978 * mce=off disables machine check
979 * mce=TOLERANCELEVEL (number, see above)
980 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
981 * mce=nobootlog Don't log MCEs from before booting.
983 static int __init
mcheck_enable(char *str
)
989 if (!strcmp(str
, "off"))
991 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
992 mce_bootlog
= (str
[0] == 'b');
993 else if (isdigit(str
[0]))
994 get_option(&str
, &tolerant
);
996 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1002 __setup("mce", mcheck_enable
);
1009 * Disable machine checks on suspend and shutdown. We can't really handle
1012 static int mce_disable(void)
1016 for (i
= 0; i
< banks
; i
++) {
1017 if (!skip_bank_init(i
))
1018 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1023 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1025 return mce_disable();
1028 static int mce_shutdown(struct sys_device
*dev
)
1030 return mce_disable();
1034 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1035 * Only one CPU is active at this time, the others get re-added later using
1038 static int mce_resume(struct sys_device
*dev
)
1041 mce_cpu_features(¤t_cpu_data
);
1046 static void mce_cpu_restart(void *data
)
1048 del_timer_sync(&__get_cpu_var(mce_timer
));
1049 if (mce_available(¤t_cpu_data
))
1054 /* Reinit MCEs after user configuration changes */
1055 static void mce_restart(void)
1057 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1060 static struct sysdev_class mce_sysclass
= {
1061 .suspend
= mce_suspend
,
1062 .shutdown
= mce_shutdown
,
1063 .resume
= mce_resume
,
1064 .name
= "machinecheck",
1067 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1070 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1072 static struct sysdev_attribute
*bank_attrs
;
1074 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1077 u64 b
= bank
[attr
- bank_attrs
];
1079 return sprintf(buf
, "%llx\n", b
);
1082 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1083 const char *buf
, size_t size
)
1087 if (strict_strtoull(buf
, 0, &new) < 0)
1090 bank
[attr
- bank_attrs
] = new;
1097 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1099 strcpy(buf
, trigger
);
1101 return strlen(trigger
) + 1;
1104 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1105 const char *buf
, size_t siz
)
1110 strncpy(trigger
, buf
, sizeof(trigger
));
1111 trigger
[sizeof(trigger
)-1] = 0;
1112 len
= strlen(trigger
);
1113 p
= strchr(trigger
, '\n');
1121 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1122 struct sysdev_attribute
*attr
,
1123 const char *buf
, size_t size
)
1125 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1130 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1131 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1133 static struct sysdev_ext_attribute attr_check_interval
= {
1134 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1135 store_int_with_restart
),
1139 static struct sysdev_attribute
*mce_attrs
[] = {
1140 &attr_tolerant
.attr
, &attr_check_interval
.attr
, &attr_trigger
,
1144 static cpumask_var_t mce_dev_initialized
;
1146 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1147 static __cpuinit
int mce_create_device(unsigned int cpu
)
1152 if (!mce_available(&boot_cpu_data
))
1155 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1156 per_cpu(mce_dev
, cpu
).id
= cpu
;
1157 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1159 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1163 for (i
= 0; mce_attrs
[i
]; i
++) {
1164 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1168 for (i
= 0; i
< banks
; i
++) {
1169 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1174 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1179 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1182 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1184 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1189 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1193 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1196 for (i
= 0; mce_attrs
[i
]; i
++)
1197 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1199 for (i
= 0; i
< banks
; i
++)
1200 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1202 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1203 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1206 /* Make sure there are no machine checks on offlined CPUs. */
1207 static void mce_disable_cpu(void *h
)
1209 unsigned long action
= *(unsigned long *)h
;
1212 if (!mce_available(¤t_cpu_data
))
1214 if (!(action
& CPU_TASKS_FROZEN
))
1216 for (i
= 0; i
< banks
; i
++) {
1217 if (!skip_bank_init(i
))
1218 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1222 static void mce_reenable_cpu(void *h
)
1224 unsigned long action
= *(unsigned long *)h
;
1227 if (!mce_available(¤t_cpu_data
))
1230 if (!(action
& CPU_TASKS_FROZEN
))
1232 for (i
= 0; i
< banks
; i
++) {
1233 if (!skip_bank_init(i
))
1234 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1238 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1239 static int __cpuinit
1240 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1242 unsigned int cpu
= (unsigned long)hcpu
;
1243 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1247 case CPU_ONLINE_FROZEN
:
1248 mce_create_device(cpu
);
1249 if (threshold_cpu_callback
)
1250 threshold_cpu_callback(action
, cpu
);
1253 case CPU_DEAD_FROZEN
:
1254 if (threshold_cpu_callback
)
1255 threshold_cpu_callback(action
, cpu
);
1256 mce_remove_device(cpu
);
1258 case CPU_DOWN_PREPARE
:
1259 case CPU_DOWN_PREPARE_FROZEN
:
1261 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1263 case CPU_DOWN_FAILED
:
1264 case CPU_DOWN_FAILED_FROZEN
:
1265 t
->expires
= round_jiffies(jiffies
+
1266 __get_cpu_var(next_interval
));
1267 add_timer_on(t
, cpu
);
1268 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1271 /* intentionally ignoring frozen here */
1272 cmci_rediscover(cpu
);
1278 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1279 .notifier_call
= mce_cpu_callback
,
1282 static __init
int mce_init_banks(void)
1286 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1291 for (i
= 0; i
< banks
; i
++) {
1292 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1294 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1298 a
->attr
.mode
= 0644;
1299 a
->show
= show_bank
;
1300 a
->store
= set_bank
;
1306 kfree(bank_attrs
[i
].attr
.name
);
1313 static __init
int mce_init_device(void)
1318 if (!mce_available(&boot_cpu_data
))
1321 alloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1323 err
= mce_init_banks();
1327 err
= sysdev_class_register(&mce_sysclass
);
1331 for_each_online_cpu(i
) {
1332 err
= mce_create_device(i
);
1337 register_hotcpu_notifier(&mce_cpu_notifier
);
1338 misc_register(&mce_log_device
);
1343 device_initcall(mce_init_device
);
1345 #else /* CONFIG_X86_OLD_MCE: */
1348 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1350 /* This has to be run for each processor */
1351 void mcheck_init(struct cpuinfo_x86
*c
)
1353 if (mce_disabled
== 1)
1356 switch (c
->x86_vendor
) {
1357 case X86_VENDOR_AMD
:
1361 case X86_VENDOR_INTEL
:
1363 intel_p5_mcheck_init(c
);
1365 intel_p6_mcheck_init(c
);
1367 intel_p4_mcheck_init(c
);
1370 case X86_VENDOR_CENTAUR
:
1372 winchip_mcheck_init(c
);
1378 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", nr_mce_banks
);
1381 static int __init
mcheck_enable(char *str
)
1387 __setup("mce", mcheck_enable
);
1389 #endif /* CONFIG_X86_OLD_MCE */
1392 * Old style boot options parsing. Only for compatibility.
1394 static int __init
mcheck_disable(char *str
)
1399 __setup("nomce", mcheck_disable
);