2 * intel_idle.c - native hardware idle loop for modern Intel processors
4 * Copyright (c) 2010, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
31 * All CPUs have same idle states as boot CPU
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
53 /* un-comment DEBUG to enable pr_debug() statements */
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/clockchips.h>
59 #include <linux/hrtimer.h> /* ktime_get_real() */
60 #include <trace/events/power.h>
61 #include <linux/sched.h>
63 #define INTEL_IDLE_VERSION "0.4"
64 #define PREFIX "intel_idle: "
66 #define MWAIT_SUBSTATE_MASK (0xf)
67 #define MWAIT_CSTATE_MASK (0xf)
68 #define MWAIT_SUBSTATE_SIZE (4)
69 #define MWAIT_MAX_NUM_CSTATES 8
70 #define CPUID_MWAIT_LEAF (5)
71 #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
72 #define CPUID5_ECX_INTERRUPT_BREAK (0x2)
74 static struct cpuidle_driver intel_idle_driver
= {
78 /* intel_idle.max_cstate=0 disables driver */
79 static int max_cstate
= MWAIT_MAX_NUM_CSTATES
- 1;
81 static unsigned int mwait_substates
;
83 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
84 static unsigned int lapic_timer_reliable_states
;
86 static struct cpuidle_device __percpu
*intel_idle_cpuidle_devices
;
87 static int intel_idle(struct cpuidle_device
*dev
, struct cpuidle_state
*state
);
89 static struct cpuidle_state
*cpuidle_state_table
;
92 * States are indexed by the cstate number,
93 * which is also the index into the MWAIT hint array.
96 static struct cpuidle_state nehalem_cstates
[MWAIT_MAX_NUM_CSTATES
] = {
100 .desc
= "MWAIT 0x00",
101 .driver_data
= (void *) 0x00,
102 .flags
= CPUIDLE_FLAG_TIME_VALID
,
105 .target_residency
= 6,
106 .enter
= &intel_idle
},
109 .desc
= "MWAIT 0x10",
110 .driver_data
= (void *) 0x10,
111 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
114 .target_residency
= 80,
115 .enter
= &intel_idle
},
118 .desc
= "MWAIT 0x20",
119 .driver_data
= (void *) 0x20,
120 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
123 .target_residency
= 800,
124 .enter
= &intel_idle
},
127 static struct cpuidle_state atom_cstates
[MWAIT_MAX_NUM_CSTATES
] = {
131 .desc
= "MWAIT 0x00",
132 .driver_data
= (void *) 0x00,
133 .flags
= CPUIDLE_FLAG_TIME_VALID
,
136 .target_residency
= 4,
137 .enter
= &intel_idle
},
140 .desc
= "MWAIT 0x10",
141 .driver_data
= (void *) 0x10,
142 .flags
= CPUIDLE_FLAG_TIME_VALID
,
145 .target_residency
= 80,
146 .enter
= &intel_idle
},
150 .desc
= "MWAIT 0x30",
151 .driver_data
= (void *) 0x30,
152 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
155 .target_residency
= 400,
156 .enter
= &intel_idle
},
160 .desc
= "MWAIT 0x40",
161 .driver_data
= (void *) 0x40,
162 .flags
= CPUIDLE_FLAG_TIME_VALID
| CPUIDLE_FLAG_TLB_FLUSHED
,
165 .target_residency
= 800,
166 .enter
= NULL
}, /* disabled */
171 * @dev: cpuidle_device
172 * @state: cpuidle state
175 static int intel_idle(struct cpuidle_device
*dev
, struct cpuidle_state
*state
)
177 unsigned long ecx
= 1; /* break on interrupt flag */
178 unsigned long eax
= (unsigned long)cpuidle_get_statedata(state
);
180 ktime_t kt_before
, kt_after
;
182 int cpu
= smp_processor_id();
184 cstate
= (((eax
) >> MWAIT_SUBSTATE_SIZE
) & MWAIT_CSTATE_MASK
) + 1;
189 * If the state flag indicates that the TLB will be flushed or if this
190 * is the deepest c-state supported, do a voluntary leave mm to avoid
191 * costly and mostly unnecessary wakeups for flushing the user TLB's
192 * associated with the active mm.
194 if (state
->flags
& CPUIDLE_FLAG_TLB_FLUSHED
||
195 (&dev
->states
[dev
->state_count
- 1] == state
))
198 if (!(lapic_timer_reliable_states
& (1 << (cstate
))))
199 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
201 kt_before
= ktime_get_real();
203 stop_critical_timings();
205 trace_power_start(POWER_CSTATE
, (eax
>> 4) + 1, cpu
);
207 if (!need_resched()) {
209 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
215 start_critical_timings();
217 kt_after
= ktime_get_real();
218 usec_delta
= ktime_to_us(ktime_sub(kt_after
, kt_before
));
222 if (!(lapic_timer_reliable_states
& (1 << (cstate
))))
223 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
231 static int intel_idle_probe(void)
233 unsigned int eax
, ebx
, ecx
;
235 if (max_cstate
== 0) {
236 pr_debug(PREFIX
"disabled\n");
240 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
243 if (!boot_cpu_has(X86_FEATURE_MWAIT
))
246 if (boot_cpu_data
.cpuid_level
< CPUID_MWAIT_LEAF
)
249 cpuid(CPUID_MWAIT_LEAF
, &eax
, &ebx
, &ecx
, &mwait_substates
);
251 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
) ||
252 !(ecx
& CPUID5_ECX_INTERRUPT_BREAK
))
255 pr_debug(PREFIX
"MWAIT substates: 0x%x\n", mwait_substates
);
257 if (boot_cpu_has(X86_FEATURE_ARAT
)) /* Always Reliable APIC Timer */
258 lapic_timer_reliable_states
= 0xFFFFFFFF;
260 if (boot_cpu_data
.x86
!= 6) /* family 6 */
263 switch (boot_cpu_data
.x86_model
) {
265 case 0x1A: /* Core i7, Xeon 5500 series */
266 case 0x1E: /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
267 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
268 case 0x2E: /* Nehalem-EX Xeon */
269 case 0x2F: /* Westmere-EX Xeon */
270 lapic_timer_reliable_states
= (1 << 1); /* C1 */
272 case 0x25: /* Westmere */
273 case 0x2C: /* Westmere */
274 cpuidle_state_table
= nehalem_cstates
;
277 case 0x1C: /* 28 - Atom Processor */
278 case 0x26: /* 38 - Lincroft Atom Processor */
279 lapic_timer_reliable_states
= (1 << 2) | (1 << 1); /* C2, C1 */
280 cpuidle_state_table
= atom_cstates
;
283 case 0x17: /* 23 - Core 2 Duo */
284 lapic_timer_reliable_states
= (1 << 2) | (1 << 1); /* C2, C1 */
288 pr_debug(PREFIX
"does not run on family %d model %d\n",
289 boot_cpu_data
.x86
, boot_cpu_data
.x86_model
);
293 pr_debug(PREFIX
"v" INTEL_IDLE_VERSION
294 " model 0x%X\n", boot_cpu_data
.x86_model
);
296 pr_debug(PREFIX
"lapic_timer_reliable_states 0x%x\n",
297 lapic_timer_reliable_states
);
302 * intel_idle_cpuidle_devices_uninit()
303 * unregister, free cpuidle_devices
305 static void intel_idle_cpuidle_devices_uninit(void)
308 struct cpuidle_device
*dev
;
310 for_each_online_cpu(i
) {
311 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, i
);
312 cpuidle_unregister_device(dev
);
315 free_percpu(intel_idle_cpuidle_devices
);
319 * intel_idle_cpuidle_devices_init()
320 * allocate, initialize, register cpuidle_devices
322 static int intel_idle_cpuidle_devices_init(void)
325 struct cpuidle_device
*dev
;
327 intel_idle_cpuidle_devices
= alloc_percpu(struct cpuidle_device
);
328 if (intel_idle_cpuidle_devices
== NULL
)
331 for_each_online_cpu(i
) {
332 dev
= per_cpu_ptr(intel_idle_cpuidle_devices
, i
);
334 dev
->state_count
= 1;
336 for (cstate
= 1; cstate
< MWAIT_MAX_NUM_CSTATES
; ++cstate
) {
339 if (cstate
> max_cstate
) {
340 printk(PREFIX
"max_cstate %d reached\n",
345 /* does the state exist in CPUID.MWAIT? */
346 num_substates
= (mwait_substates
>> ((cstate
) * 4))
347 & MWAIT_SUBSTATE_MASK
;
348 if (num_substates
== 0)
350 /* is the state not enabled? */
351 if (cpuidle_state_table
[cstate
].enter
== NULL
) {
352 /* does the driver not know about the state? */
353 if (*cpuidle_state_table
[cstate
].name
== '\0')
354 pr_debug(PREFIX
"unaware of model 0x%x"
356 " contact lenb@kernel.org",
357 boot_cpu_data
.x86_model
, cstate
);
362 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
363 mark_tsc_unstable("TSC halts in idle"
364 " states deeper than C2");
366 dev
->states
[dev
->state_count
] = /* structure copy */
367 cpuidle_state_table
[cstate
];
369 dev
->state_count
+= 1;
373 if (cpuidle_register_device(dev
)) {
374 pr_debug(PREFIX
"cpuidle_register_device %d failed!\n",
376 intel_idle_cpuidle_devices_uninit();
385 static int __init
intel_idle_init(void)
389 retval
= intel_idle_probe();
393 retval
= cpuidle_register_driver(&intel_idle_driver
);
395 printk(KERN_DEBUG PREFIX
"intel_idle yielding to %s",
396 cpuidle_get_driver()->name
);
400 retval
= intel_idle_cpuidle_devices_init();
402 cpuidle_unregister_driver(&intel_idle_driver
);
409 static void __exit
intel_idle_exit(void)
411 intel_idle_cpuidle_devices_uninit();
412 cpuidle_unregister_driver(&intel_idle_driver
);
417 module_init(intel_idle_init
);
418 module_exit(intel_idle_exit
);
420 module_param(max_cstate
, int, 0444);
422 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
423 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION
);
424 MODULE_LICENSE("GPL");