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[PATCH] uml: tls support: hack to make it compile on any host
[linux-2.6/x86.git] / drivers / scsi / sata_promise.c
blobcc928c68a4790e26621214919d0b9db4f1e11918
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.04"
50
51
52 enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
63
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10),
66
67 board_2037x = 0, /* FastTrak S150 TX2plus */
68 board_20319 = 1, /* FastTrak S150 TX4 */
69 board_20619 = 2, /* FastTrak TX4000 */
70 board_20771 = 3, /* FastTrak TX2300 */
71 board_2057x = 4, /* SATAII150 Tx2plus */
72 board_40518 = 5, /* SATAII150 Tx4 */
73
74 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
75
76 PDC_RESET = (1 << 11), /* HDMA reset */
77
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI,
80 };
81
82
83 struct pdc_port_priv {
84 u8 *pkt;
85 dma_addr_t pkt_dma;
86 };
87
88 struct pdc_host_priv {
89 int hotplug_offset;
90 };
91
92 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
93 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
94 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
95 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
96 static void pdc_eng_timeout(struct ata_port *ap);
97 static int pdc_port_start(struct ata_port *ap);
98 static void pdc_port_stop(struct ata_port *ap);
99 static void pdc_pata_phy_reset(struct ata_port *ap);
100 static void pdc_sata_phy_reset(struct ata_port *ap);
101 static void pdc_qc_prep(struct ata_queued_cmd *qc);
102 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
103 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
104 static void pdc_irq_clear(struct ata_port *ap);
105 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
106 static void pdc_host_stop(struct ata_host_set *host_set);
107
108
109 static struct scsi_host_template pdc_ata_sht = {
110 .module = THIS_MODULE,
111 .name = DRV_NAME,
112 .ioctl = ata_scsi_ioctl,
113 .queuecommand = ata_scsi_queuecmd,
114 .eh_strategy_handler = ata_scsi_error,
115 .can_queue = ATA_DEF_QUEUE,
116 .this_id = ATA_SHT_THIS_ID,
117 .sg_tablesize = LIBATA_MAX_PRD,
118 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
119 .emulated = ATA_SHT_EMULATED,
120 .use_clustering = ATA_SHT_USE_CLUSTERING,
121 .proc_name = DRV_NAME,
122 .dma_boundary = ATA_DMA_BOUNDARY,
123 .slave_configure = ata_scsi_slave_config,
124 .bios_param = ata_std_bios_param,
125 };
126
127 static const struct ata_port_operations pdc_sata_ops = {
128 .port_disable = ata_port_disable,
129 .tf_load = pdc_tf_load_mmio,
130 .tf_read = ata_tf_read,
131 .check_status = ata_check_status,
132 .exec_command = pdc_exec_command_mmio,
133 .dev_select = ata_std_dev_select,
134
135 .phy_reset = pdc_sata_phy_reset,
136
137 .qc_prep = pdc_qc_prep,
138 .qc_issue = pdc_qc_issue_prot,
139 .eng_timeout = pdc_eng_timeout,
140 .irq_handler = pdc_interrupt,
141 .irq_clear = pdc_irq_clear,
142
143 .scr_read = pdc_sata_scr_read,
144 .scr_write = pdc_sata_scr_write,
145 .port_start = pdc_port_start,
146 .port_stop = pdc_port_stop,
147 .host_stop = pdc_host_stop,
148 };
149
150 static const struct ata_port_operations pdc_pata_ops = {
151 .port_disable = ata_port_disable,
152 .tf_load = pdc_tf_load_mmio,
153 .tf_read = ata_tf_read,
154 .check_status = ata_check_status,
155 .exec_command = pdc_exec_command_mmio,
156 .dev_select = ata_std_dev_select,
157
158 .phy_reset = pdc_pata_phy_reset,
159
160 .qc_prep = pdc_qc_prep,
161 .qc_issue = pdc_qc_issue_prot,
162 .eng_timeout = pdc_eng_timeout,
163 .irq_handler = pdc_interrupt,
164 .irq_clear = pdc_irq_clear,
165
166 .port_start = pdc_port_start,
167 .port_stop = pdc_port_stop,
168 .host_stop = pdc_host_stop,
169 };
170
171 static const struct ata_port_info pdc_port_info[] = {
172 /* board_2037x */
173 {
174 .sht = &pdc_ata_sht,
175 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
176 .pio_mask = 0x1f, /* pio0-4 */
177 .mwdma_mask = 0x07, /* mwdma0-2 */
178 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
179 .port_ops = &pdc_sata_ops,
180 },
181
182 /* board_20319 */
183 {
184 .sht = &pdc_ata_sht,
185 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
186 .pio_mask = 0x1f, /* pio0-4 */
187 .mwdma_mask = 0x07, /* mwdma0-2 */
188 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
189 .port_ops = &pdc_sata_ops,
190 },
191
192 /* board_20619 */
193 {
194 .sht = &pdc_ata_sht,
195 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
196 .pio_mask = 0x1f, /* pio0-4 */
197 .mwdma_mask = 0x07, /* mwdma0-2 */
198 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
199 .port_ops = &pdc_pata_ops,
200 },
201
202 /* board_20771 */
203 {
204 .sht = &pdc_ata_sht,
205 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
206 .pio_mask = 0x1f, /* pio0-4 */
207 .mwdma_mask = 0x07, /* mwdma0-2 */
208 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
209 .port_ops = &pdc_sata_ops,
210 },
211
212 /* board_2057x */
213 {
214 .sht = &pdc_ata_sht,
215 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
216 .pio_mask = 0x1f, /* pio0-4 */
217 .mwdma_mask = 0x07, /* mwdma0-2 */
218 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
219 .port_ops = &pdc_sata_ops,
220 },
221
222 /* board_40518 */
223 {
224 .sht = &pdc_ata_sht,
225 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
226 .pio_mask = 0x1f, /* pio0-4 */
227 .mwdma_mask = 0x07, /* mwdma0-2 */
228 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
229 .port_ops = &pdc_sata_ops,
230 },
231 };
232
233 static const struct pci_device_id pdc_ata_pci_tbl[] = {
234 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
235 board_2037x },
236 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
237 board_2037x },
238 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
239 board_2037x },
240 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
241 board_2037x },
242 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
243 board_2037x },
244 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
245 board_2037x },
246 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
247 board_2057x },
248 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
249 board_2057x },
250 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
251 board_2037x },
252
253 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
254 board_20319 },
255 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
256 board_20319 },
257 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
258 board_20319 },
259 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_20319 },
261 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_20319 },
263 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_40518 },
265
266 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_20619 },
268
269 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_20771 },
271 { } /* terminate list */
272 };
273
274
275 static struct pci_driver pdc_ata_pci_driver = {
276 .name = DRV_NAME,
277 .id_table = pdc_ata_pci_tbl,
278 .probe = pdc_ata_init_one,
279 .remove = ata_pci_remove_one,
280 };
281
282
283 static int pdc_port_start(struct ata_port *ap)
284 {
285 struct device *dev = ap->host_set->dev;
286 struct pdc_port_priv *pp;
287 int rc;
288
289 rc = ata_port_start(ap);
290 if (rc)
291 return rc;
292
293 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
294 if (!pp) {
295 rc = -ENOMEM;
296 goto err_out;
297 }
298
299 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
300 if (!pp->pkt) {
301 rc = -ENOMEM;
302 goto err_out_kfree;
303 }
304
305 ap->private_data = pp;
306
307 return 0;
308
309 err_out_kfree:
310 kfree(pp);
311 err_out:
312 ata_port_stop(ap);
313 return rc;
314 }
315
316
317 static void pdc_port_stop(struct ata_port *ap)
318 {
319 struct device *dev = ap->host_set->dev;
320 struct pdc_port_priv *pp = ap->private_data;
321
322 ap->private_data = NULL;
323 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
324 kfree(pp);
325 ata_port_stop(ap);
326 }
327
328
329 static void pdc_host_stop(struct ata_host_set *host_set)
330 {
331 struct pdc_host_priv *hp = host_set->private_data;
332
333 ata_pci_host_stop(host_set);
334
335 kfree(hp);
336 }
337
338
339 static void pdc_reset_port(struct ata_port *ap)
340 {
341 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
342 unsigned int i;
343 u32 tmp;
344
345 for (i = 11; i > 0; i--) {
346 tmp = readl(mmio);
347 if (tmp & PDC_RESET)
348 break;
349
350 udelay(100);
351
352 tmp |= PDC_RESET;
353 writel(tmp, mmio);
354 }
355
356 tmp &= ~PDC_RESET;
357 writel(tmp, mmio);
358 readl(mmio); /* flush */
359 }
360
361 static void pdc_sata_phy_reset(struct ata_port *ap)
362 {
363 pdc_reset_port(ap);
364 sata_phy_reset(ap);
365 }
366
367 static void pdc_pata_phy_reset(struct ata_port *ap)
368 {
369 /* FIXME: add cable detect. Don't assume 40-pin cable */
370 ap->cbl = ATA_CBL_PATA40;
371 ap->udma_mask &= ATA_UDMA_MASK_40C;
372
373 pdc_reset_port(ap);
374 ata_port_probe(ap);
375 ata_bus_reset(ap);
376 }
377
378 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
379 {
380 if (sc_reg > SCR_CONTROL)
381 return 0xffffffffU;
382 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
383 }
384
385
386 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
387 u32 val)
388 {
389 if (sc_reg > SCR_CONTROL)
390 return;
391 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
392 }
393
394 static void pdc_qc_prep(struct ata_queued_cmd *qc)
395 {
396 struct pdc_port_priv *pp = qc->ap->private_data;
397 unsigned int i;
398
399 VPRINTK("ENTER\n");
400
401 switch (qc->tf.protocol) {
402 case ATA_PROT_DMA:
403 ata_qc_prep(qc);
404 /* fall through */
405
406 case ATA_PROT_NODATA:
407 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
408 qc->dev->devno, pp->pkt);
409
410 if (qc->tf.flags & ATA_TFLAG_LBA48)
411 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
412 else
413 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
414
415 pdc_pkt_footer(&qc->tf, pp->pkt, i);
416 break;
417
418 default:
419 break;
420 }
421 }
422
423 static void pdc_eng_timeout(struct ata_port *ap)
424 {
425 struct ata_host_set *host_set = ap->host_set;
426 u8 drv_stat;
427 struct ata_queued_cmd *qc;
428 unsigned long flags;
429
430 DPRINTK("ENTER\n");
431
432 spin_lock_irqsave(&host_set->lock, flags);
433
434 qc = ata_qc_from_tag(ap, ap->active_tag);
435
436 switch (qc->tf.protocol) {
437 case ATA_PROT_DMA:
438 case ATA_PROT_NODATA:
439 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
440 drv_stat = ata_wait_idle(ap);
441 qc->err_mask |= __ac_err_mask(drv_stat);
442 break;
443
444 default:
445 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
446
447 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
448 ap->id, qc->tf.command, drv_stat);
449
450 qc->err_mask |= ac_err_mask(drv_stat);
451 break;
452 }
453
454 spin_unlock_irqrestore(&host_set->lock, flags);
455 ata_eh_qc_complete(qc);
456 DPRINTK("EXIT\n");
457 }
458
459 static inline unsigned int pdc_host_intr( struct ata_port *ap,
460 struct ata_queued_cmd *qc)
461 {
462 unsigned int handled = 0;
463 u32 tmp;
464 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
465
466 tmp = readl(mmio);
467 if (tmp & PDC_ERR_MASK) {
468 qc->err_mask |= AC_ERR_DEV;
469 pdc_reset_port(ap);
470 }
471
472 switch (qc->tf.protocol) {
473 case ATA_PROT_DMA:
474 case ATA_PROT_NODATA:
475 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
476 ata_qc_complete(qc);
477 handled = 1;
478 break;
479
480 default:
481 ap->stats.idle_irq++;
482 break;
483 }
484
485 return handled;
486 }
487
488 static void pdc_irq_clear(struct ata_port *ap)
489 {
490 struct ata_host_set *host_set = ap->host_set;
491 void __iomem *mmio = host_set->mmio_base;
492
493 readl(mmio + PDC_INT_SEQMASK);
494 }
495
496 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
497 {
498 struct ata_host_set *host_set = dev_instance;
499 struct ata_port *ap;
500 u32 mask = 0;
501 unsigned int i, tmp;
502 unsigned int handled = 0;
503 void __iomem *mmio_base;
504
505 VPRINTK("ENTER\n");
506
507 if (!host_set || !host_set->mmio_base) {
508 VPRINTK("QUICK EXIT\n");
509 return IRQ_NONE;
510 }
511
512 mmio_base = host_set->mmio_base;
513
514 /* reading should also clear interrupts */
515 mask = readl(mmio_base + PDC_INT_SEQMASK);
516
517 if (mask == 0xffffffff) {
518 VPRINTK("QUICK EXIT 2\n");
519 return IRQ_NONE;
520 }
521
522 spin_lock(&host_set->lock);
523
524 mask &= 0xffff; /* only 16 tags possible */
525 if (!mask) {
526 VPRINTK("QUICK EXIT 3\n");
527 goto done_irq;
528 }
529
530 writel(mask, mmio_base + PDC_INT_SEQMASK);
531
532 for (i = 0; i < host_set->n_ports; i++) {
533 VPRINTK("port %u\n", i);
534 ap = host_set->ports[i];
535 tmp = mask & (1 << (i + 1));
536 if (tmp && ap &&
537 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
538 struct ata_queued_cmd *qc;
539
540 qc = ata_qc_from_tag(ap, ap->active_tag);
541 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
542 handled += pdc_host_intr(ap, qc);
543 }
544 }
545
546 VPRINTK("EXIT\n");
547
548 done_irq:
549 spin_unlock(&host_set->lock);
550 return IRQ_RETVAL(handled);
551 }
552
553 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
554 {
555 struct ata_port *ap = qc->ap;
556 struct pdc_port_priv *pp = ap->private_data;
557 unsigned int port_no = ap->port_no;
558 u8 seq = (u8) (port_no + 1);
559
560 VPRINTK("ENTER, ap %p\n", ap);
561
562 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
563 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
564
565 pp->pkt[2] = seq;
566 wmb(); /* flush PRD, pkt writes */
567 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
568 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
569 }
570
571 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
572 {
573 switch (qc->tf.protocol) {
574 case ATA_PROT_DMA:
575 case ATA_PROT_NODATA:
576 pdc_packet_start(qc);
577 return 0;
578
579 case ATA_PROT_ATAPI_DMA:
580 BUG();
581 break;
582
583 default:
584 break;
585 }
586
587 return ata_qc_issue_prot(qc);
588 }
589
590 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
591 {
592 WARN_ON (tf->protocol == ATA_PROT_DMA ||
593 tf->protocol == ATA_PROT_NODATA);
594 ata_tf_load(ap, tf);
595 }
596
597
598 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
599 {
600 WARN_ON (tf->protocol == ATA_PROT_DMA ||
601 tf->protocol == ATA_PROT_NODATA);
602 ata_exec_command(ap, tf);
603 }
604
605
606 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
607 {
608 port->cmd_addr = base;
609 port->data_addr = base;
610 port->feature_addr =
611 port->error_addr = base + 0x4;
612 port->nsect_addr = base + 0x8;
613 port->lbal_addr = base + 0xc;
614 port->lbam_addr = base + 0x10;
615 port->lbah_addr = base + 0x14;
616 port->device_addr = base + 0x18;
617 port->command_addr =
618 port->status_addr = base + 0x1c;
619 port->altstatus_addr =
620 port->ctl_addr = base + 0x38;
621 }
622
623
624 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
625 {
626 void __iomem *mmio = pe->mmio_base;
627 struct pdc_host_priv *hp = pe->private_data;
628 int hotplug_offset = hp->hotplug_offset;
629 u32 tmp;
630
631 /*
632 * Except for the hotplug stuff, this is voodoo from the
633 * Promise driver. Label this entire section
634 * "TODO: figure out why we do this"
635 */
636
637 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
638 tmp = readl(mmio + PDC_FLASH_CTL);
639 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
640 writel(tmp, mmio + PDC_FLASH_CTL);
641
642 /* clear plug/unplug flags for all ports */
643 tmp = readl(mmio + hotplug_offset);
644 writel(tmp | 0xff, mmio + hotplug_offset);
645
646 /* mask plug/unplug ints */
647 tmp = readl(mmio + hotplug_offset);
648 writel(tmp | 0xff0000, mmio + hotplug_offset);
649
650 /* reduce TBG clock to 133 Mhz. */
651 tmp = readl(mmio + PDC_TBG_MODE);
652 tmp &= ~0x30000; /* clear bit 17, 16*/
653 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
654 writel(tmp, mmio + PDC_TBG_MODE);
655
656 readl(mmio + PDC_TBG_MODE); /* flush */
657 msleep(10);
658
659 /* adjust slew rate control register. */
660 tmp = readl(mmio + PDC_SLEW_CTL);
661 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
662 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
663 writel(tmp, mmio + PDC_SLEW_CTL);
664 }
665
666 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
667 {
668 static int printed_version;
669 struct ata_probe_ent *probe_ent = NULL;
670 struct pdc_host_priv *hp;
671 unsigned long base;
672 void __iomem *mmio_base;
673 unsigned int board_idx = (unsigned int) ent->driver_data;
674 int pci_dev_busy = 0;
675 int rc;
676
677 if (!printed_version++)
678 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
679
680 /*
681 * If this driver happens to only be useful on Apple's K2, then
682 * we should check that here as it has a normal Serverworks ID
683 */
684 rc = pci_enable_device(pdev);
685 if (rc)
686 return rc;
687
688 rc = pci_request_regions(pdev, DRV_NAME);
689 if (rc) {
690 pci_dev_busy = 1;
691 goto err_out;
692 }
693
694 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
695 if (rc)
696 goto err_out_regions;
697 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
698 if (rc)
699 goto err_out_regions;
700
701 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
702 if (probe_ent == NULL) {
703 rc = -ENOMEM;
704 goto err_out_regions;
705 }
706
707 probe_ent->dev = pci_dev_to_dev(pdev);
708 INIT_LIST_HEAD(&probe_ent->node);
709
710 mmio_base = pci_iomap(pdev, 3, 0);
711 if (mmio_base == NULL) {
712 rc = -ENOMEM;
713 goto err_out_free_ent;
714 }
715 base = (unsigned long) mmio_base;
716
717 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
718 if (hp == NULL) {
719 rc = -ENOMEM;
720 goto err_out_free_ent;
721 }
722
723 /* Set default hotplug offset */
724 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
725 probe_ent->private_data = hp;
726
727 probe_ent->sht = pdc_port_info[board_idx].sht;
728 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
729 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
730 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
731 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
732 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
733
734 probe_ent->irq = pdev->irq;
735 probe_ent->irq_flags = SA_SHIRQ;
736 probe_ent->mmio_base = mmio_base;
737
738 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
739 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
740
741 probe_ent->port[0].scr_addr = base + 0x400;
742 probe_ent->port[1].scr_addr = base + 0x500;
743
744 /* notice 4-port boards */
745 switch (board_idx) {
746 case board_40518:
747 /* Override hotplug offset for SATAII150 */
748 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
749 /* Fall through */
750 case board_20319:
751 probe_ent->n_ports = 4;
752
753 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
754 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
755
756 probe_ent->port[2].scr_addr = base + 0x600;
757 probe_ent->port[3].scr_addr = base + 0x700;
758 break;
759 case board_2057x:
760 /* Override hotplug offset for SATAII150 */
761 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
762 /* Fall through */
763 case board_2037x:
764 probe_ent->n_ports = 2;
765 break;
766 case board_20771:
767 probe_ent->n_ports = 2;
768 break;
769 case board_20619:
770 probe_ent->n_ports = 4;
771
772 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
773 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
774
775 probe_ent->port[2].scr_addr = base + 0x600;
776 probe_ent->port[3].scr_addr = base + 0x700;
777 break;
778 default:
779 BUG();
780 break;
781 }
782
783 pci_set_master(pdev);
784
785 /* initialize adapter */
786 pdc_host_init(board_idx, probe_ent);
787
788 /* FIXME: Need any other frees than hp? */
789 if (!ata_device_add(probe_ent))
790 kfree(hp);
791
792 kfree(probe_ent);
793
794 return 0;
795
796 err_out_free_ent:
797 kfree(probe_ent);
798 err_out_regions:
799 pci_release_regions(pdev);
800 err_out:
801 if (!pci_dev_busy)
802 pci_disable_device(pdev);
803 return rc;
804 }
805
806
807 static int __init pdc_ata_init(void)
808 {
809 return pci_module_init(&pdc_ata_pci_driver);
810 }
811
812
813 static void __exit pdc_ata_exit(void)
814 {
815 pci_unregister_driver(&pdc_ata_pci_driver);
816 }
817
818
819 MODULE_AUTHOR("Jeff Garzik");
820 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
821 MODULE_LICENSE("GPL");
822 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
823 MODULE_VERSION(DRV_VERSION);
824
825 module_init(pdc_ata_init);
826 module_exit(pdc_ata_exit);
x86 "subsystem" repository