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Merge branch 'core-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6/x86.git] / drivers / staging / rt3070 / rt_ate.c
blob9238d960121ceea2b3fcf5babc6b178f37c4fb3e
1 /*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26 */
27
28 #include "rt_config.h"
29
30 #ifdef UCOS
31 INT IoctlResponse(PUCHAR payload, PUCHAR msg, INT len);
32 #endif // UCOS //
33
34 #define ATE_BBP_REG_NUM 168
35 UCHAR restore_BBP[ATE_BBP_REG_NUM]={0};
36
37 #ifdef RALINK_ATE
38 UCHAR TemplateFrame[24] = {0x08/* Data type */,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xAA,0xBB,0x12,0x34,0x56,0x00,0x11,0x22,0xAA,0xBB,0xCC,0x00,0x00}; // 802.11 MAC Header, Type:Data, Length:24bytes
39 extern RTMP_RF_REGS RF2850RegTable[];
40 extern UCHAR NUM_OF_2850_CHNL;
41
42 #ifdef RT2870
43 extern UCHAR EpToQueue[];
44 extern VOID RTUSBRejectPendingPackets( IN PRTMP_ADAPTER pAd);
45 #endif // RT2870 //
46
47 #ifdef RT30xx
48 //2008/07/10:KH adds to support 3070 ATE<--
49 extern FREQUENCY_ITEM FreqItems3020[];
50 extern UCHAR NUM_OF_3020_CHNL;
51 //2008/07/10:KH adds to support 3070 ATE-->
52 #endif // RT30xx //
53
54 #ifdef UCOS
55 extern INT ConsoleResponse(IN PUCHAR buff);
56 extern int (*remote_display)(char *);
57 #endif // UCOS //
58
59 static CHAR CCKRateTable[] = {0, 1, 2, 3, 8, 9, 10, 11, -1}; /* CCK Mode. */
60 static CHAR OFDMRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, -1}; /* OFDM Mode. */
61 static CHAR HTMIXRateTable[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}; /* HT Mix Mode. */
62
63 static INT TxDmaBusy(
64 IN PRTMP_ADAPTER pAd);
65
66 static INT RxDmaBusy(
67 IN PRTMP_ADAPTER pAd);
68
69 static VOID RtmpDmaEnable(
70 IN PRTMP_ADAPTER pAd,
71 IN INT Enable);
72
73 static VOID BbpSoftReset(
74 IN PRTMP_ADAPTER pAd);
75
76 static VOID RtmpRfIoWrite(
77 IN PRTMP_ADAPTER pAd);
78
79 static INT ATESetUpFrame(
80 IN PRTMP_ADAPTER pAd,
81 IN UINT32 TxIdx);
82
83 static INT ATETxPwrHandler(
84 IN PRTMP_ADAPTER pAd,
85 IN char index);
86
87 static INT ATECmdHandler(
88 IN PRTMP_ADAPTER pAd,
89 IN PUCHAR arg);
90
91 static int CheckMCSValid(
92 IN UCHAR Mode,
93 IN UCHAR Mcs);
94
95
96 #ifdef RT2870
97 static VOID ATEWriteTxInfo(
98 IN PRTMP_ADAPTER pAd,
99 IN PTXINFO_STRUC pTxInfo,
100 IN USHORT USBDMApktLen,
101 IN BOOLEAN bWiv,
102 IN UCHAR QueueSel,
103 IN UCHAR NextValid,
104 IN UCHAR TxBurst);
105
106 static VOID ATEWriteTxWI(
107 IN PRTMP_ADAPTER pAd,
108 IN PTXWI_STRUC pTxWI,
109 IN BOOLEAN FRAG,
110 IN BOOLEAN InsTimestamp,
111 IN BOOLEAN AMPDU,
112 IN BOOLEAN Ack,
113 IN BOOLEAN NSeq, // HW new a sequence.
114 IN UCHAR BASize,
115 IN UCHAR WCID,
116 IN ULONG Length,
117 IN UCHAR PID,
118 IN UCHAR MIMOps,
119 IN UCHAR Txopmode,
120 IN BOOLEAN CfAck,
121 IN HTTRANSMIT_SETTING Transmit);
122
123 #endif // RT2870 //
124
125 static VOID SetJapanFilter(
126 IN PRTMP_ADAPTER pAd);
127
128 /*=========================end of prototype=========================*/
129
130
131 #ifdef RT2870
132 static INT TxDmaBusy(
133 IN PRTMP_ADAPTER pAd)
134 {
135 INT result;
136 USB_DMA_CFG_STRUC UsbCfg;
137
138 RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); // disable DMA
139 if (UsbCfg.field.TxBusy)
140 result = 1;
141 else
142 result = 0;
143
144 return result;
145 }
146
147 static INT RxDmaBusy(
148 IN PRTMP_ADAPTER pAd)
149 {
150 INT result;
151 USB_DMA_CFG_STRUC UsbCfg;
152
153 RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); // disable DMA
154 if (UsbCfg.field.RxBusy)
155 result = 1;
156 else
157 result = 0;
158
159 return result;
160 }
161
162 static VOID RtmpDmaEnable(
163 IN PRTMP_ADAPTER pAd,
164 IN INT Enable)
165 {
166 BOOLEAN value;
167 ULONG WaitCnt;
168 USB_DMA_CFG_STRUC UsbCfg;
169
170 value = Enable > 0 ? 1 : 0;
171
172 // check DMA is in busy mode.
173 WaitCnt = 0;
174 while (TxDmaBusy(pAd) || RxDmaBusy(pAd))
175 {
176 RTMPusecDelay(10);
177 if (WaitCnt++ > 100)
178 break;
179 }
180
181 //Why not to clear USB DMA TX path first ???
182 RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); // disable DMA
183 UsbCfg.field.TxBulkEn = value;
184 UsbCfg.field.RxBulkEn = value;
185 RTMP_IO_WRITE32(pAd, USB_DMA_CFG, UsbCfg.word); // abort all TX rings
186 RTMPusecDelay(5000);
187
188 return;
189 }
190 #endif // RT2870 //
191
192 static VOID BbpSoftReset(
193 IN PRTMP_ADAPTER pAd)
194 {
195 UCHAR BbpData = 0;
196
197 // Soft reset, set BBP R21 bit0=1->0
198 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData);
199 BbpData |= 0x00000001; //set bit0=1
200 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData);
201
202 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R21, &BbpData);
203 BbpData &= ~(0x00000001); //set bit0=0
204 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R21, BbpData);
205
206 return;
207 }
208
209 static VOID RtmpRfIoWrite(
210 IN PRTMP_ADAPTER pAd)
211 {
212 // Set RF value 1's set R3[bit2] = [0]
213 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
214 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
215 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
216 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
217
218 RTMPusecDelay(200);
219
220 // Set RF value 2's set R3[bit2] = [1]
221 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
222 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
223 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 | 0x04));
224 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
225
226 RTMPusecDelay(200);
227
228 // Set RF value 3's set R3[bit2] = [0]
229 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
230 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
231 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
232 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
233
234 return;
235 }
236
237 static int CheckMCSValid(
238 UCHAR Mode,
239 UCHAR Mcs)
240 {
241 int i;
242 PCHAR pRateTab;
243
244 switch(Mode)
245 {
246 case 0:
247 pRateTab = CCKRateTable;
248 break;
249 case 1:
250 pRateTab = OFDMRateTable;
251 break;
252 case 2:
253 case 3:
254 pRateTab = HTMIXRateTable;
255 break;
256 default:
257 ATEDBGPRINT(RT_DEBUG_ERROR, ("unrecognizable Tx Mode %d\n", Mode));
258 return -1;
259 break;
260 }
261
262 i = 0;
263 while(pRateTab[i] != -1)
264 {
265 if (pRateTab[i] == Mcs)
266 return 0;
267 i++;
268 }
269
270 return -1;
271 }
272
273 #if 1
274 static INT ATETxPwrHandler(
275 IN PRTMP_ADAPTER pAd,
276 IN char index)
277 {
278 ULONG R;
279 CHAR TxPower;
280 UCHAR Bbp94 = 0;
281 BOOLEAN bPowerReduce = FALSE;
282 #ifdef RT30xx
283 UCHAR RFValue;
284 #endif // RT30xx //
285 #ifdef RALINK_28xx_QA
286 if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
287 {
288 /* When QA is used for Tx, pAd->ate.TxPower0/1 and real tx power
289 ** are not synchronized.
290 */
291 /*
292 pAd->ate.TxPower0 = pAd->LatchRfRegs.xxx;
293 pAd->ate.TxPower1 = pAd->LatchRfRegs.xxx;
294 */
295 return 0;
296 }
297 else
298 #endif // RALINK_28xx_QA //
299 {
300 TxPower = index == 0 ? pAd->ate.TxPower0 : pAd->ate.TxPower1;
301
302 if (pAd->ate.Channel <= 14)
303 {
304 if (TxPower > 31)
305 {
306 //
307 // R3, R4 can't large than 31 (0x24), 31 ~ 36 used by BBP 94
308 //
309 R = 31;
310 if (TxPower <= 36)
311 Bbp94 = BBPR94_DEFAULT + (UCHAR)(TxPower - 31);
312 }
313 else if (TxPower < 0)
314 {
315 //
316 // R3, R4 can't less than 0, -1 ~ -6 used by BBP 94
317 //
318 R = 0;
319 if (TxPower >= -6)
320 Bbp94 = BBPR94_DEFAULT + TxPower;
321 }
322 else
323 {
324 // 0 ~ 31
325 R = (ULONG) TxPower;
326 Bbp94 = BBPR94_DEFAULT;
327 }
328
329 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%ld, BBP_R94=%d)\n", __FUNCTION__, TxPower, R, Bbp94));
330 }
331 else// 5.5 GHz
332 {
333 if (TxPower > 15)
334 {
335 //
336 // R3, R4 can't large than 15 (0x0F)
337 //
338 R = 15;
339 }
340 else if (TxPower < 0)
341 {
342 //
343 // R3, R4 can't less than 0
344 //
345 // -1 ~ -7
346 ASSERT((TxPower >= -7));
347 R = (ULONG)(TxPower + 7);
348 bPowerReduce = TRUE;
349 }
350 else
351 {
352 // 0 ~ 15
353 R = (ULONG) TxPower;
354 }
355
356 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R=%lu)\n", __FUNCTION__, TxPower, R));
357 }
358 //2008/09/10:KH adds to support 3070 ATE TX Power tunning real time<--
359 #ifdef RT30xx
360 if(IS_RT30xx(pAd))
361 {
362 // Set Tx Power
363
364 RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue);
365 RFValue = (RFValue & 0xE0) | TxPower;
366 RT30xxWriteRFRegister(pAd, RF_R12, (UCHAR)RFValue);
367 ATEDBGPRINT(RT_DEBUG_TRACE, ("3070 or 2070:%s (TxPower=%d, RFValue=%x)\n", __FUNCTION__, TxPower, RFValue));
368
369 }
370 else
371 #endif // RT30xx //
372 {
373 if (pAd->ate.Channel <= 14)
374 {
375 if (index == 0)
376 {
377 R = R << 9; // shift TX power control to correct RF(R3) register bit position
378 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
379 pAd->LatchRfRegs.R3 = R;
380 }
381 else
382 {
383 R = R << 6; // shift TX power control to correct RF(R4) register bit position
384 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
385 pAd->LatchRfRegs.R4 = R;
386 }
387 }
388 else// 5.5GHz
389 {
390 if (bPowerReduce == FALSE)
391 {
392 if (index == 0)
393 {
394 R = (R << 10) | (1 << 9); // shift TX power control to correct RF(R3) register bit position
395 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
396 pAd->LatchRfRegs.R3 = R;
397 }
398 else
399 {
400 R = (R << 7) | (1 << 6); // shift TX power control to correct RF(R4) register bit position
401 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
402 pAd->LatchRfRegs.R4 = R;
403 }
404 }
405 else
406 {
407 if (index == 0)
408 {
409 R = (R << 10); // shift TX power control to correct RF(R3) register bit position
410 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
411
412 /* Clear bit 9 of R3 to reduce 7dB. */
413 pAd->LatchRfRegs.R3 = (R & (~(1 << 9)));
414 }
415 else
416 {
417 R = (R << 7); // shift TX power control to correct RF(R4) register bit position
418 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
419
420 /* Clear bit 6 of R4 to reduce 7dB. */
421 pAd->LatchRfRegs.R4 = (R & (~(1 << 6)));
422 }
423 }
424 }
425 RtmpRfIoWrite(pAd);
426 }
427 //2008/09/10:KH adds to support 3070 ATE TX Power tunning real time-->
428
429 return 0;
430 }
431 }
432 #else// 1 //
433 static INT ATETxPwrHandler(
434 IN PRTMP_ADAPTER pAd,
435 IN char index)
436 {
437 ULONG R;
438 CHAR TxPower;
439 UCHAR Bbp94 = 0;
440
441 #ifdef RALINK_28xx_QA
442 if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
443 {
444 // TODO: how to get current TxPower0/1 from pAd->LatchRfRegs ?
445 /* When QA is used for Tx, pAd->ate.TxPower0/1 and real tx power
446 ** are not synchronized.
447 */
448 /*
449 pAd->ate.TxPower0 = pAd->LatchRfRegs.xxx;
450 pAd->ate.TxPower1 = pAd->LatchRfRegs.xxx;
451 */
452 return 0;
453 }
454 else
455 #endif // RALINK_28xx_QA //
456 {
457 TxPower = index == 0 ? pAd->ate.TxPower0 : pAd->ate.TxPower1;
458
459 if (TxPower > 31)
460 {
461 //
462 // R3, R4 can't large than 36 (0x24), 31 ~ 36 used by BBP 94
463 //
464 R = 31;
465 if (TxPower <= 36)
466 Bbp94 = BBPR94_DEFAULT + (UCHAR)(TxPower - 31);
467 }
468 else if (TxPower < 0)
469 {
470 //
471 // R3, R4 can't less than 0, -1 ~ -6 used by BBP 94
472 //
473 R = 0;
474 if (TxPower >= -6)
475 Bbp94 = BBPR94_DEFAULT + TxPower;
476 }
477 else
478 {
479 // 0 ~ 31
480 R = (ULONG) TxPower;
481 Bbp94 = BBPR94_DEFAULT;
482 }
483
484 ATEDBGPRINT(RT_DEBUG_TRACE, ("%s (TxPower=%d, R3=%ld, BBP_R94=%d)\n", __FUNCTION__, TxPower, R, Bbp94));
485
486 if (pAd->ate.Channel <= 14)
487 {
488 if (index == 0)
489 {
490 R = R << 9; // shift TX power control to correct RF(R3) register bit position
491 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
492 pAd->LatchRfRegs.R3 = R;
493 }
494 else
495 {
496 R = R << 6; // shift TX power control to correct RF(R4) register bit position
497 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
498 pAd->LatchRfRegs.R4 = R;
499 }
500 }
501 else
502 {
503 if (index == 0)
504 {
505 R = (R << 10) | (1 << 9); // shift TX power control to correct RF(R3) register bit position
506 R |= (pAd->LatchRfRegs.R3 & 0xffffc1ff);
507 pAd->LatchRfRegs.R3 = R;
508 }
509 else
510 {
511 R = (R << 7) | (1 << 6); // shift TX power control to correct RF(R4) register bit position
512 R |= (pAd->LatchRfRegs.R4 & 0xfffff83f);
513 pAd->LatchRfRegs.R4 = R;
514 }
515 }
516
517 RtmpRfIoWrite(pAd);
518
519 return 0;
520 }
521 }
522 #endif // 1 //
523 /*
524 ==========================================================================
525 Description:
526 Set ATE operation mode to
527 0. ATESTART = Start ATE Mode
528 1. ATESTOP = Stop ATE Mode
529 2. TXCONT = Continuous Transmit
530 3. TXCARR = Transmit Carrier
531 4. TXFRAME = Transmit Frames
532 5. RXFRAME = Receive Frames
533 #ifdef RALINK_28xx_QA
534 6. TXSTOP = Stop Any Type of Transmition
535 7. RXSTOP = Stop Receiving Frames
536 #endif // RALINK_28xx_QA //
537 Return:
538 TRUE if all parameters are OK, FALSE otherwise
539 ==========================================================================
540 */
541 /* */
542 /* */
543 /*=======================End of RT2860=======================*/
544
545
546 /*======================Start of RT2870======================*/
547 /* */
548 /* */
549
550 #ifdef RT2870
551 static INT ATECmdHandler(
552 IN PRTMP_ADAPTER pAd,
553 IN PUCHAR arg)
554 {
555 UINT32 Value;
556 UCHAR BbpData;
557 UINT32 MacData;
558 UINT i=0, atemode;
559 //NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
560 //PUCHAR pDest;
561 UINT32 temp;
562 ULONG IrqFlags;
563
564 ATEDBGPRINT(RT_DEBUG_TRACE, ("===> ATECmdHandler()\n"));
565 ATEAsicSwitchChannel(pAd);
566 /* AsicLockChannel() is empty function so far in fact */
567 AsicLockChannel(pAd, pAd->ate.Channel);
568
569 RTMPusecDelay(5000);
570
571 // Default value in BBP R22 is 0x0.
572 BbpData = 0;
573
574 /* Enter ATE mode and set Tx/Rx Idle */
575 if (!strcmp(arg, "ATESTART"))
576 {
577 #ifdef CONFIG_STA_SUPPORT
578 BOOLEAN Cancelled;
579 #endif // CONFIG_STA_SUPPORT //
580 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: ATESTART\n"));
581
582 netif_stop_queue(pAd->net_dev);
583
584 atemode = pAd->ate.Mode;
585 pAd->ate.Mode = ATE_START;
586 // pAd->ate.TxDoneCount = pAd->ate.TxCount;
587 // Disable Rx
588 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
589 Value &= ~(1 << 3);
590 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
591
592 // Disable auto responder
593 RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &temp);
594 temp = temp & 0xFFFFFFFE;
595 RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, temp);
596
597 // read MAC_SYS_CTRL and backup MAC_SYS_CTRL value.
598 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
599 // clean bit4 to stop continuous Tx production test.
600 MacData &= 0xFFFFFFEF;
601 // Stop continuous TX production test.
602 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);//disable or cancel pending irp first ???
603
604 if (atemode & ATE_TXCARR
605 #ifdef RT30xx
606 || atemode & ATE_TXCONT
607 #endif // RT30xx //
608 )
609 {
610 #ifdef RT30xx
611 //Hardware Reset BBP
612 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &temp);
613 temp = temp |0x00000002;
614 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, temp);
615 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &temp);
616 temp = temp & ~(0x00000002);
617 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, temp);
618 //Restore All BBP Value
619 for(i=0;i<ATE_BBP_REG_NUM;i++)
620 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd,i,restore_BBP[i]);
621 #endif // RT30xx //
622
623 // No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0
624 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
625 BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
626 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
627 }
628 else if (atemode & ATE_TXCARRSUPP)
629 {
630 #ifdef RT30xx
631 //Hardware Reset BBP
632 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &temp);
633 temp = temp |0x00000002;
634 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, temp);
635 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &temp);
636 temp = temp & ~(0x00000002);
637 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, temp);
638 //Restore All BBP Value
639 for(i=0;i<ATE_BBP_REG_NUM;i++)
640 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd,i,restore_BBP[i]);
641 #endif // RT30xx //
642
643 // No Cont. TX set BBP R22 bit7=0
644 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
645 BbpData &= ~(1 << 7); //set bit7=0
646 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
647
648 // No Carrier Suppression set BBP R24 bit0=0
649 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R24, &BbpData);
650 BbpData &= 0xFFFFFFFE; //clear bit0
651 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, BbpData);
652 }
653 // We should free some resource which allocate when ATE_TXFRAME , ATE_STOP, and ATE_TXCONT.
654 // TODO:Should we free some resource which was allocated when LoopBack and ATE_STOP ?
655 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
656 {
657 if (atemode & ATE_TXCONT)
658 {
659 // Not Cont. TX anymore, so set BBP R22 bit7=0
660 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
661 BbpData &= ~(1 << 7); //set bit7=0
662 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
663 }
664 // Abort Tx, Rx DMA.
665 RtmpDmaEnable(pAd, 0);
666
667 {
668 // It seems nothing to free,
669 // because we didn't allocate any resource when we entered ATE_TXFRAME mode latestly.
670 }
671
672 // Start Tx, RX DMA
673 RtmpDmaEnable(pAd, 1);
674 }
675
676 RTUSBRejectPendingPackets(pAd);
677 RTUSBCleanUpDataBulkOutQueue(pAd);
678
679 #ifdef CONFIG_STA_SUPPORT
680 //
681 // It will be called in MlmeSuspend().
682 //
683 // Cancel pending timers
684 RTMPCancelTimer(&pAd->MlmeAux.AssocTimer, &Cancelled);
685 RTMPCancelTimer(&pAd->MlmeAux.ReassocTimer, &Cancelled);
686 RTMPCancelTimer(&pAd->MlmeAux.DisassocTimer, &Cancelled);
687 RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled);
688 RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled);
689 RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled);
690 #endif // CONFIG_STA_SUPPORT //
691
692 //RTUSBCleanUpMLMEWaitQueue(pAd); /* not used in RT28xx */
693 RTUSBCleanUpMLMEBulkOutQueue(pAd);
694
695 // Sometimes kernel will hang on, so we avoid calling MlmeSuspend().
696 // MlmeSuspend(pAd, TRUE);
697 //RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled);
698
699 // Disable Rx
700 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
701 Value &= ~(1 << 3);
702 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
703
704 // Abort Tx, RX DMA.
705 RtmpDmaEnable(pAd, 0);
706
707 // Disable Tx
708 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
709 Value &= ~(1 << 2);
710 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
711
712 // Make sure there are no pending bulk in/out IRPs before we go on.
713 /*=========================================================================*/
714 /* pAd->PendingRx is not of type atomic_t anymore in 28xx */
715 // while ((atomic_read(&pAd->PendingRx) > 0)) //pAd->BulkFlags != 0 wait bulk out finish
716 while ((pAd->PendingRx > 0)) //pAd->BulkFlags != 0 wait bulk out finish
717 {
718 #if 1
719 ATE_RTUSBCancelPendingBulkInIRP(pAd);
720 #else
721 NdisInterlockedDecrement(&pAd->PendingRx);
722 #endif
723 /* delay 0.5 seconds */
724 RTMPusecDelay(500000);
725 pAd->PendingRx = 0;
726 }
727 /* peter : why don't we have to get BulkOutLock first ? */
728 while (((pAd->BulkOutPending[0] == TRUE) ||
729 (pAd->BulkOutPending[1] == TRUE) ||
730 (pAd->BulkOutPending[2] == TRUE) ||
731 (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) //pAd->BulkFlags != 0 wait bulk out finish
732 {
733 do
734 {
735 /* pAd->BulkOutPending[y] will be set to FALSE in RTUSBCancelPendingBulkOutIRP(pAd) */
736 RTUSBCancelPendingBulkOutIRP(pAd);
737 } while (FALSE);
738
739 /* we have enough time delay in RTUSBCancelPendingBulkOutIRP(pAd)
740 ** so this is not necessary
741 */
742 // RTMPusecDelay(500000);
743 }
744
745 /* pAd->PendingRx is not of type atomic_t anymore in 28xx */
746 // ASSERT(atomic_read(&pAd->PendingRx) == 0);
747 ASSERT(pAd->PendingRx == 0);
748 /*=========================================================================*/
749
750 // reset Rx statistics.
751 pAd->ate.LastSNR0 = 0;
752 pAd->ate.LastSNR1 = 0;
753 pAd->ate.LastRssi0 = 0;
754 pAd->ate.LastRssi1 = 0;
755 pAd->ate.LastRssi2 = 0;
756 pAd->ate.AvgRssi0 = 0;
757 pAd->ate.AvgRssi1 = 0;
758 pAd->ate.AvgRssi2 = 0;
759 pAd->ate.AvgRssi0X8 = 0;
760 pAd->ate.AvgRssi1X8 = 0;
761 pAd->ate.AvgRssi2X8 = 0;
762 pAd->ate.NumOfAvgRssiSample = 0;
763
764 #ifdef RALINK_28xx_QA
765 // Tx frame
766 pAd->ate.bQATxStart = FALSE;
767 pAd->ate.bQARxStart = FALSE;
768 pAd->ate.seq = 0;
769
770 // counters
771 pAd->ate.U2M = 0;
772 pAd->ate.OtherData = 0;
773 pAd->ate.Beacon = 0;
774 pAd->ate.OtherCount = 0;
775 pAd->ate.TxAc0 = 0;
776 pAd->ate.TxAc1 = 0;
777 pAd->ate.TxAc2 = 0;
778 pAd->ate.TxAc3 = 0;
779 pAd->ate.TxHCCA = 0;
780 pAd->ate.TxMgmt = 0;
781 pAd->ate.RSSI0 = 0;
782 pAd->ate.RSSI1 = 0;
783 pAd->ate.RSSI2 = 0;
784 pAd->ate.SNR0 = 0;
785 pAd->ate.SNR1 = 0;
786
787 // control
788 pAd->ate.TxDoneCount = 0;
789 pAd->ate.TxStatus = 0; // task Tx status // 0 --> task is idle, 1 --> task is running
790 #endif // RALINK_28xx_QA //
791
792 // Soft reset BBP.
793 BbpSoftReset(pAd);
794
795
796 #ifdef CONFIG_STA_SUPPORT
797 AsicDisableSync(pAd);
798
799 /*
800 ** If we skip "LinkDown()", we should disable protection
801 ** to prevent from sending out RTS or CTS-to-self.
802 */
803 ATEDisableAsicProtect(pAd);
804 RTMPStationStop(pAd);
805 #endif // CONFIG_STA_SUPPORT //
806
807 // Default value in BBP R22 is 0x0.
808 BbpData = 0;
809 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
810
811 // Clean bit4 to stop continuous Tx production test.
812 MacData &= 0xFFFFFFEF;
813 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
814 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
815 //Clean ATE Bulk in/out counter and continue setup
816 InterlockedExchange(&pAd->BulkOutRemained, 0);
817
818 /* NdisAcquireSpinLock()/NdisReleaseSpinLock() need only one argument in RT28xx */
819 NdisAcquireSpinLock(&pAd->GenericLock);
820 pAd->ContinBulkOut = FALSE;
821 pAd->ContinBulkIn = FALSE;
822 NdisReleaseSpinLock(&pAd->GenericLock);
823
824 RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE);
825 }
826 else if (!strcmp(arg, "ATESTOP"))
827 {
828 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE : ATESTOP ===>\n"));
829
830 // Default value in BBP R22 is 0x0.
831 BbpData = 0;
832 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);//0820
833 // Clean bit4 to stop continuous Tx production test.
834 MacData &= 0xFFFFFFEF;
835 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
836 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData); // recover the MAC_SYS_CTRL register back.
837
838 // Disable Rx
839 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
840 Value &= ~(1 << 3);
841 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
842
843 /*
844 ** Abort Tx, RX DMA.
845 ** Q : How to do the following I/O if Tx, Rx DMA is aborted ?
846 ** Ans : Bulk endpoints are aborted, while the control endpoint is not.
847 */
848 RtmpDmaEnable(pAd, 0);
849
850 // Disable Tx
851 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
852 Value &= ~(1 << 2);
853 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
854
855 /* Make sure there are no pending bulk in/out IRPs before we go on. */
856 /*=========================================================================*/
857 // while ((atomic_read(&pAd->PendingRx) > 0)) //pAd->BulkFlags != 0 wait bulk out finish
858 while (pAd->PendingRx > 0)
859 {
860 #if 1
861 ATE_RTUSBCancelPendingBulkInIRP(pAd);
862 #else
863 // NdisInterlockedDecrement(&pAd->PendingRx);
864 pAd->PendingRx--;
865 #endif
866 RTMPusecDelay(500000);
867 }
868
869 while (((pAd->BulkOutPending[0] == TRUE) ||
870 (pAd->BulkOutPending[1] == TRUE) ||
871 (pAd->BulkOutPending[2] == TRUE) ||
872 (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) //pAd->BulkFlags != 0 wait bulk out finish
873 {
874 do
875 {
876 RTUSBCancelPendingBulkOutIRP(pAd);
877 } while (FALSE);
878
879 RTMPusecDelay(500000);
880 }
881
882 // ASSERT(atomic_read(&pAd->PendingRx) == 0);
883 ASSERT(pAd->PendingRx == 0);
884 /*=========================================================================*/
885 /* Reset Rx RING */
886 /*=========================================================================*/
887 // InterlockedExchange(&pAd->PendingRx, 0);
888 pAd->PendingRx = 0;
889 pAd->NextRxBulkInReadIndex = 0; // Next Rx Read index
890 pAd->NextRxBulkInIndex = RX_RING_SIZE - 1; // Rx Bulk pointer
891 pAd->NextRxBulkInPosition = 0;
892 for (i = 0; i < (RX_RING_SIZE); i++)
893 {
894 PRX_CONTEXT pRxContext = &(pAd->RxContext[i]);
895 NdisZeroMemory(pRxContext->TransferBuffer, MAX_RXBULK_SIZE);
896 /* peter : why don't we have to get BulkInLock first ? */
897 pRxContext->pAd = pAd;
898 pRxContext->pIrp = NULL;
899 /* peter debug ++ */
900 pRxContext->BulkInOffset = 0;
901 pRxContext->bRxHandling = FALSE;
902 /* peter debug -- */
903 pRxContext->InUse = FALSE;
904 pRxContext->IRPPending = FALSE;
905 pRxContext->Readable = FALSE;
906 // pRxContext->ReorderInUse = FALSE;
907 // pRxContext->ReadPosOffset = 0;
908 }
909
910 /*=========================================================================*/
911 /* Reset Tx RING */
912 /*=========================================================================*/
913 do
914 {
915 RTUSBCancelPendingBulkOutIRP(pAd);
916 } while (FALSE);
917
918 /*=========================================================================*/
919 // Enable auto responder.
920 RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &temp);
921 temp = temp | (0x01);
922 RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, temp);
923
924 /*================================================*/
925 AsicEnableBssSync(pAd);
926
927 /* Soft reset BBP.*/
928 /* In 2870 chipset, ATE_BBP_IO_READ8_BY_REG_ID() == RTMP_BBP_IO_READ8_BY_REG_ID() */
929 /* Both rt2870ap and rt2870sta use BbpSoftReset(pAd) to do BBP soft reset */
930 BbpSoftReset(pAd);
931 /*================================================*/
932 {
933 #ifdef CONFIG_STA_SUPPORT
934 // Set all state machines back IDLE
935 pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
936 pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
937 pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
938 pAd->Mlme.AuthRspMachine.CurrState = AUTH_RSP_IDLE;
939 pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
940 pAd->Mlme.ActMachine.CurrState = ACT_IDLE;
941 #endif // CONFIG_STA_SUPPORT //
942
943 //
944 // ===> refer to MlmeRestartStateMachine().
945 // When we entered ATE_START mode, PeriodicTimer was not cancelled.
946 // So we don't have to set it here.
947 //
948 //RTMPSetTimer(pAd, &pAd->Mlme.PeriodicTimer, MLME_TASK_EXEC_INTV);
949
950 ASSERT(pAd->CommonCfg.Channel != 0);
951
952 AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
953 AsicLockChannel(pAd, pAd->CommonCfg.Channel);
954
955
956 #ifdef CONFIG_STA_SUPPORT
957 RTMPStationStart(pAd);
958 #endif // CONFIG_STA_SUPPORT //
959 }
960 //
961 // These two steps have been done when entering ATE_STOP mode.
962 //
963 // Clean ATE Bulk in/out counter and continue setup.
964 InterlockedExchange(&pAd->BulkOutRemained, 0);
965 NdisAcquireSpinLock(&pAd->GenericLock);
966 pAd->ContinBulkOut = FALSE;
967 pAd->ContinBulkIn = FALSE;
968 NdisReleaseSpinLock(&pAd->GenericLock);
969
970 /* Wait 50ms to prevent next URB to bulkout during HW reset. */
971 /* todo : remove this if not necessary */
972 NdisMSleep(50000);
973
974 pAd->ate.Mode = ATE_STOP;
975
976 // Enable Tx
977 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
978 Value |= (1 << 2);
979 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
980
981 /*=========================================================================*/
982 /* restore RX_FILTR_CFG */
983 #ifdef CONFIG_STA_SUPPORT
984 /* restore RX_FILTR_CFG in order that QA maybe set it to 0x3 */
985 RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, STANORMAL);
986 #endif // CONFIG_STA_SUPPORT //
987 /*=========================================================================*/
988
989 // Enable Tx, RX DMA.
990 RtmpDmaEnable(pAd, 1);
991
992 // Enable Rx
993 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
994 Value |= (1 << 3);
995 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
996
997 // Wait 10ms to wait all of the bulk-in URBs to complete.
998 /* todo : remove this if not necessary */
999 NdisMSleep(10000);
1000
1001 // Everything is ready to start normal Tx/Rx.
1002 RTUSBBulkReceive(pAd);
1003 netif_start_queue(pAd->net_dev);
1004
1005 ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== ATE : ATESTOP \n"));
1006 }
1007 else if (!strcmp(arg, "TXCARR")) // Tx Carrier
1008 {
1009 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXCARR\n"));
1010 pAd->ate.Mode |= ATE_TXCARR;
1011
1012 #ifdef RT30xx
1013 for(i=0;i<ATE_BBP_REG_NUM;i++)
1014 restore_BBP[i]=0;
1015 //Record All BBP Value
1016 for(i=0;i<ATE_BBP_REG_NUM;i++)
1017 ATE_BBP_IO_READ8_BY_REG_ID(pAd,i,&restore_BBP[i]);
1018 #endif // RT30xx //
1019
1020 // Disable Rx
1021 // May be we need not to do this, because these have been done in ATE_START mode ???
1022 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1023 Value &= ~(1 << 3);
1024 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1025
1026 // QA has done the following steps if it is used.
1027 if (pAd->ate.bQATxStart == FALSE)
1028 {
1029 // Soft reset BBP.
1030 BbpSoftReset(pAd);
1031
1032 // Carrier Test set BBP R22 bit7=1, bit6=1, bit[5~0]=0x01
1033 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1034 BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
1035 BbpData |= 0x000000C1; //set bit7=1, bit6=1, bit[5~0]=0x01
1036 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1037
1038 // set MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 1
1039 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1040 Value = Value | 0x00000010;
1041 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1042 }
1043 }
1044 else if (!strcmp(arg, "TXCONT")) // Tx Continue
1045 {
1046 if (pAd->ate.bQATxStart == TRUE)
1047 {
1048 /* set MAC_SYS_CTRL(0x1004) bit4(Continuous Tx Production Test)
1049 and bit2(MAC TX enable) back to zero. */
1050 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1051 MacData &= 0xFFFFFFEB;
1052 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1053
1054 // set BBP R22 bit7=0
1055 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1056 BbpData &= 0xFFFFFF7F; //set bit7=0
1057 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1058 }
1059
1060 /* for TxCont mode.
1061 ** Step 1: Send 50 packets first then wait for a moment.
1062 ** Step 2: Send more 50 packet then start continue mode.
1063 */
1064 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXCONT\n"));
1065
1066 #ifdef RT30xx
1067 for(i=0;i<ATE_BBP_REG_NUM;i++)
1068 restore_BBP[i]=0;
1069 //Record All BBP Value
1070 for(i=0;i<ATE_BBP_REG_NUM;i++)
1071 ATE_BBP_IO_READ8_BY_REG_ID(pAd,i,&restore_BBP[i]);
1072 #endif // RT30xx //
1073
1074 // Step 1: send 50 packets first.
1075 pAd->ate.Mode |= ATE_TXCONT;
1076 pAd->ate.TxCount = 50;
1077 pAd->ate.TxDoneCount = 0;
1078
1079 // Soft reset BBP.
1080 BbpSoftReset(pAd);
1081
1082 // Abort Tx, RX DMA.
1083 RtmpDmaEnable(pAd, 0);
1084
1085
1086 /* Only needed if we have to send some normal frames. */
1087 SetJapanFilter(pAd);
1088
1089 // Setup frame format.
1090 ATESetUpFrame(pAd, 0);
1091
1092 // Enable Tx
1093 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1094 Value |= (1 << 2);
1095 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1096
1097 // Disable Rx
1098 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1099 Value &= ~(1 << 3);
1100 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1101
1102 // Start Tx, RX DMA.
1103 RtmpDmaEnable(pAd, 1);
1104
1105 InterlockedExchange(&pAd->BulkOutRemained, pAd->ate.TxCount);
1106
1107 #ifdef RALINK_28xx_QA
1108 if (pAd->ate.bQATxStart == TRUE)
1109 {
1110 pAd->ate.TxStatus = 1;
1111 //pAd->ate.Repeat = 0;
1112 }
1113 #endif // RALINK_28xx_QA //
1114
1115 NdisAcquireSpinLock(&pAd->GenericLock);//0820
1116 pAd->ContinBulkOut = FALSE;
1117 NdisReleaseSpinLock(&pAd->GenericLock);
1118
1119 RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE);
1120
1121 // Kick bulk out
1122 RTUSBKickBulkOut(pAd);
1123
1124 /* To make sure all the 50 frames have been bulk out before executing step 2 */
1125 while (atomic_read(&pAd->BulkOutRemained) > 0)
1126 {
1127 RTMPusecDelay(5000);
1128 }
1129
1130 // Step 2: send more 50 packets then start continue mode.
1131 // Abort Tx, RX DMA.
1132 RtmpDmaEnable(pAd, 0);
1133
1134 // Cont. TX set BBP R22 bit7=1
1135 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1136 BbpData |= 0x00000080; //set bit7=1
1137 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1138
1139 pAd->ate.TxCount = 50;
1140 pAd->ate.TxDoneCount = 0;
1141
1142 SetJapanFilter(pAd);
1143
1144 // Setup frame format.
1145 ATESetUpFrame(pAd, 0);
1146
1147 // Enable Tx
1148 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1149 Value |= (1 << 2);
1150 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1151
1152 // Disable Rx
1153 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1154 Value &= ~(1 << 3);
1155
1156 // Start Tx, RX DMA.
1157 RtmpDmaEnable(pAd, 1);
1158
1159 InterlockedExchange(&pAd->BulkOutRemained, pAd->ate.TxCount);
1160
1161 #ifdef RALINK_28xx_QA
1162 if (pAd->ate.bQATxStart == TRUE)
1163 {
1164 pAd->ate.TxStatus = 1;
1165 //pAd->ate.Repeat = 0;
1166 }
1167 #endif // RALINK_28xx_QA //
1168
1169 NdisAcquireSpinLock(&pAd->GenericLock);//0820
1170 pAd->ContinBulkOut = FALSE;
1171 NdisReleaseSpinLock(&pAd->GenericLock);
1172
1173 RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE);
1174 // Kick bulk out
1175 RTUSBKickBulkOut(pAd);
1176
1177 #if 1
1178 RTMPusecDelay(500);
1179 #else
1180 while (atomic_read(&pAd->BulkOutRemained) > 0)
1181 {
1182 RTMPusecDelay(5000);
1183 }
1184 #endif // 1 //
1185
1186 // Set MAC_SYS_CTRL(0x1004) Continuous Tx Production Test (bit4) = 1.
1187 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1188 MacData |= 0x00000010;
1189 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1190 }
1191 else if (!strcmp(arg, "TXFRAME")) // Tx Frames
1192 {
1193 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXFRAME(Count=0x%08x)\n", pAd->ate.TxCount));
1194 pAd->ate.Mode |= ATE_TXFRAME;
1195
1196 // Soft reset BBP.
1197 BbpSoftReset(pAd);
1198
1199 // Default value in BBP R22 is 0x0.
1200 BbpData = 0;
1201
1202 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1203
1204 // Clean bit4 to stop continuous Tx production test.
1205 MacData &= 0xFFFFFFEF;
1206
1207 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1208 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1209
1210 #ifdef RALINK_28xx_QA
1211 // add this for LoopBack mode
1212 if (pAd->ate.bQARxStart == FALSE)
1213 {
1214 // Disable Rx
1215 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1216 Value &= ~(1 << 3);
1217 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1218 }
1219
1220 if (pAd->ate.bQATxStart == TRUE)
1221 {
1222 pAd->ate.TxStatus = 1;
1223 //pAd->ate.Repeat = 0;
1224 }
1225 #else
1226 // Disable Rx
1227 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1228 Value &= ~(1 << 3);
1229 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1230 #endif // RALINK_28xx_QA //
1231
1232 // Enable Tx
1233 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1234 Value |= (1 << 2);
1235 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1236
1237 SetJapanFilter(pAd);
1238
1239 // Abort Tx, RX DMA.
1240 RtmpDmaEnable(pAd, 0);
1241
1242 pAd->ate.TxDoneCount = 0;
1243
1244 // Setup frame format
1245 ATESetUpFrame(pAd, 0);
1246
1247 // Start Tx, RX DMA.
1248 RtmpDmaEnable(pAd, 1);
1249
1250 // Check count is continuous or not yet.
1251 //
1252 // Due to the type mismatch between "pAd->BulkOutRemained"(atomic_t) and "pAd->ate.TxCount"(UINT32)
1253 //
1254 if (pAd->ate.TxCount == 0)
1255 {
1256 InterlockedExchange(&pAd->BulkOutRemained, 0);
1257 }
1258 else
1259 {
1260 InterlockedExchange(&pAd->BulkOutRemained, pAd->ate.TxCount);
1261 }
1262 ATEDBGPRINT(RT_DEBUG_TRACE, ("bulk out count = %d\n", atomic_read(&pAd->BulkOutRemained)));
1263 ASSERT((atomic_read(&pAd->BulkOutRemained) >= 0));
1264
1265 if (atomic_read(&pAd->BulkOutRemained) == 0)
1266 {
1267 ATEDBGPRINT(RT_DEBUG_TRACE, ("Send packet countinuously\n"));
1268
1269 /* In 28xx, NdisAcquireSpinLock() == spin_lock_bh() */
1270 /* NdisAcquireSpinLock only need one argument in 28xx. */
1271 NdisAcquireSpinLock(&pAd->GenericLock);
1272 pAd->ContinBulkOut = TRUE;
1273 NdisReleaseSpinLock(&pAd->GenericLock);
1274
1275 /* In 28xx, BULK_OUT_LOCK() == spin_lock_irqsave() */
1276 BULK_OUT_LOCK(&pAd->BulkOutLock[0], IrqFlags);// peter : NdisAcquireSpinLock ==> BULK_OUT_LOCK
1277 pAd->BulkOutPending[0] = FALSE;
1278 BULK_OUT_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);// peter : NdisAcquireSpinLock ==> BULK_OUT_LOCK
1279 }
1280 else
1281 {
1282 ATEDBGPRINT(RT_DEBUG_TRACE, ("Send packets depend on counter\n"));
1283
1284 NdisAcquireSpinLock(&pAd->GenericLock);
1285 pAd->ContinBulkOut = FALSE;
1286 NdisReleaseSpinLock(&pAd->GenericLock);
1287
1288 BULK_OUT_LOCK(&pAd->BulkOutLock[0], IrqFlags);
1289 pAd->BulkOutPending[0] = FALSE;
1290 BULK_OUT_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
1291 }
1292
1293 RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE);
1294
1295 // Kick bulk out
1296 RTUSBKickBulkOut(pAd);
1297 }
1298 #ifdef RALINK_28xx_QA
1299 else if (!strcmp(arg, "TXSTOP")) //Enter ATE mode and set Tx/Rx Idle
1300 {
1301 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: TXSTOP\n"));
1302
1303 atemode = pAd->ate.Mode;
1304 pAd->ate.Mode &= ATE_TXSTOP;
1305 pAd->ate.bQATxStart = FALSE;
1306 // pAd->ate.TxDoneCount = pAd->ate.TxCount;
1307
1308 /*=========================================================================*/
1309 if (atemode & ATE_TXCARR)
1310 {
1311 // No Carrier Test set BBP R22 bit7=0, bit6=0, bit[5~0]=0x0
1312 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1313 BbpData &= 0xFFFFFF00; //clear bit7, bit6, bit[5~0]
1314 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1315 }
1316 else if (atemode & ATE_TXCARRSUPP)
1317 {
1318 // No Cont. TX set BBP R22 bit7=0
1319 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1320 BbpData &= ~(1 << 7); //set bit7=0
1321 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1322
1323 // No Carrier Suppression set BBP R24 bit0=0
1324 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R24, &BbpData);
1325 BbpData &= 0xFFFFFFFE; //clear bit0
1326 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, BbpData);
1327 }
1328 else if ((atemode & ATE_TXFRAME) || (atemode == ATE_STOP))
1329 {
1330 if (atemode & ATE_TXCONT)
1331 {
1332 // No Cont. TX set BBP R22 bit7=0
1333 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R22, &BbpData);
1334 BbpData &= ~(1 << 7); //set bit7=0
1335 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1336 }
1337 }
1338
1339 /*=========================================================================*/
1340 RTUSBRejectPendingPackets(pAd);
1341 RTUSBCleanUpDataBulkOutQueue(pAd);
1342
1343 /* not used in RT28xx */
1344 //RTUSBCleanUpMLMEWaitQueue(pAd);
1345 /* empty function so far */
1346 RTUSBCleanUpMLMEBulkOutQueue(pAd);
1347 /*=========================================================================*/
1348 // Abort Tx, RX DMA.
1349 RtmpDmaEnable(pAd, 0);
1350 /*=========================================================================*/
1351
1352 /* In 28xx, pAd->PendingRx is not of type atomic_t anymore */
1353 // while ((atomic_read(&pAd->PendingRx) > 0)) //pAd->BulkFlags != 0 wait bulk out finish
1354 /* peter todo : BulkInLock */
1355 while (pAd->PendingRx > 0)
1356 {
1357 #if 1
1358 ATE_RTUSBCancelPendingBulkInIRP(pAd);
1359 #else
1360 // NdisInterlockedDecrement(&pAd->PendingRx);
1361 pAd->PendingRx--;
1362 #endif
1363 RTMPusecDelay(500000);
1364 }
1365
1366 while (((pAd->BulkOutPending[0] == TRUE) ||
1367 (pAd->BulkOutPending[1] == TRUE) ||
1368 (pAd->BulkOutPending[2] == TRUE) ||
1369 (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) //pAd->BulkFlags != 0 wait bulk out finish
1370 {
1371 do
1372 {
1373 RTUSBCancelPendingBulkOutIRP(pAd);
1374 } while (FALSE);
1375
1376 RTMPusecDelay(500000);
1377 }
1378
1379 ASSERT(pAd->PendingRx == 0);
1380 /*=========================================================================*/
1381 // Enable Tx, Rx DMA.
1382 RtmpDmaEnable(pAd, 1);
1383
1384 /* task Tx status : 0 --> task is idle, 1 --> task is running */
1385 pAd->ate.TxStatus = 0;
1386
1387 // Soft reset BBP.
1388 BbpSoftReset(pAd);
1389
1390 // Disable Tx
1391 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1392 MacData &= (0xfffffffb);
1393 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1394
1395 //Clean ATE Bulk in/out counter and continue setup
1396 InterlockedExchange(&pAd->BulkOutRemained, 0);
1397
1398 pAd->ContinBulkOut = FALSE;
1399 }
1400 else if (!strcmp(arg, "RXSTOP"))
1401 {
1402 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: RXSTOP\n"));
1403 atemode = pAd->ate.Mode;
1404
1405 // Disable Rx
1406 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1407 Value &= ~(1 << 3);
1408 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1409
1410 pAd->ate.Mode &= ATE_RXSTOP;
1411 pAd->ate.bQARxStart = FALSE;
1412 // pAd->ate.TxDoneCount = pAd->ate.TxCount;
1413
1414 /*=========================================================================*/
1415 RTUSBRejectPendingPackets(pAd);
1416 RTUSBCleanUpDataBulkOutQueue(pAd);
1417
1418 /* not used in RT28xx */
1419 //RTUSBCleanUpMLMEWaitQueue(pAd);
1420 RTUSBCleanUpMLMEBulkOutQueue(pAd);
1421 /*=========================================================================*/
1422
1423 // Abort Tx, RX DMA.
1424 RtmpDmaEnable(pAd, 0);
1425 /*=========================================================================*/
1426 // while ((atomic_read(&pAd->PendingRx) > 0))
1427 while (pAd->PendingRx > 0)
1428 {
1429 #if 1
1430 ATE_RTUSBCancelPendingBulkInIRP(pAd);
1431 #else
1432 // NdisInterlockedDecrement(&pAd->PendingRx);
1433 pAd->PendingRx--;
1434 #endif
1435 RTMPusecDelay(500000);
1436 }
1437
1438 while (((pAd->BulkOutPending[0] == TRUE) ||
1439 (pAd->BulkOutPending[1] == TRUE) ||
1440 (pAd->BulkOutPending[2] == TRUE) ||
1441 (pAd->BulkOutPending[3] == TRUE)) && (pAd->BulkFlags != 0)) //pAd->BulkFlags != 0 wait bulk out finish
1442 {
1443 do
1444 {
1445 RTUSBCancelPendingBulkOutIRP(pAd);
1446 } while (FALSE);
1447
1448 RTMPusecDelay(500000);
1449 }
1450
1451 ASSERT(pAd->PendingRx == 0);
1452 /*=========================================================================*/
1453
1454 // Soft reset BBP.
1455 BbpSoftReset(pAd);
1456 pAd->ContinBulkIn = FALSE;
1457 }
1458 #endif // RALINK_28xx_QA //
1459 else if (!strcmp(arg, "RXFRAME")) // Rx Frames
1460 {
1461 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: RXFRAME\n"));
1462
1463 // Disable Rx of MAC block
1464 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1465 Value &= ~(1 << 3);
1466 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1467
1468 // Default value in BBP R22 is 0x0.
1469 BbpData = 0;
1470
1471 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &MacData);
1472 // Clean bit4 to stop continuous Tx production test.
1473 MacData &= 0xFFFFFFEF;
1474
1475 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R22, BbpData);
1476 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, MacData);
1477
1478 pAd->ate.Mode |= ATE_RXFRAME;
1479
1480 // Abort Tx, RX DMA.
1481 RtmpDmaEnable(pAd, 0);
1482
1483 // Disable TX of MAC block
1484 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1485 Value &= ~(1 << 2);
1486 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1487
1488 // Reset Rx RING.
1489 for ( i = 0; i < (RX_RING_SIZE); i++)
1490 {
1491 PRX_CONTEXT pRxContext = &(pAd->RxContext[i]);
1492
1493 pRxContext->InUse = FALSE;
1494 pRxContext->IRPPending = FALSE;
1495 pRxContext->Readable = FALSE;
1496
1497 //
1498 // Get the urb from kernel back to driver.
1499 //
1500 RTUSB_UNLINK_URB(pRxContext->pUrb);
1501
1502 /* Sleep 200 microsecs to give cancellation time to work. */
1503 NdisMSleep(200);
1504 pAd->BulkInReq = 0;
1505
1506 // InterlockedExchange(&pAd->PendingRx, 0);
1507 pAd->PendingRx = 0;
1508 pAd->NextRxBulkInReadIndex = 0; // Next Rx Read index
1509 pAd->NextRxBulkInIndex = RX_RING_SIZE - 1; // Rx Bulk pointer
1510 pAd->NextRxBulkInPosition = 0;
1511 }
1512
1513 // read to clear counters
1514 RTUSBReadMACRegister(pAd, RX_STA_CNT0, &temp); //RX PHY & RX CRC count
1515 RTUSBReadMACRegister(pAd, RX_STA_CNT1, &temp); //RX PLCP error count & CCA false alarm count
1516 RTUSBReadMACRegister(pAd, RX_STA_CNT2, &temp); //RX FIFO overflow frame count & RX duplicated filtered frame count
1517
1518 pAd->ContinBulkIn = TRUE;
1519
1520 // Enable Tx, RX DMA.
1521 RtmpDmaEnable(pAd, 1);
1522
1523 // Enable RX of MAC block
1524 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
1525 Value |= (1 << 3);
1526 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
1527
1528 // Kick bulk in
1529 RTUSBBulkReceive(pAd);
1530 }
1531 else
1532 {
1533 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATE: Invalid arg!\n"));
1534 return FALSE;
1535 }
1536 RTMPusecDelay(5000);
1537
1538 ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== ATECmdHandler()\n"));
1539
1540 return TRUE;
1541 }
1542 #endif // RT2870 //
1543
1544 INT Set_ATE_Proc(
1545 IN PRTMP_ADAPTER pAd,
1546 IN PUCHAR arg)
1547 {
1548 if (ATECmdHandler(pAd, arg))
1549 {
1550 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_Proc Success\n"));
1551
1552
1553 return TRUE;
1554 }
1555 else
1556 {
1557 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_Proc Failed\n"));
1558 return FALSE;
1559 }
1560 }
1561
1562 /*
1563 ==========================================================================
1564 Description:
1565 Set ATE ADDR1=DA for TxFrame(AP : To DS = 0 ; From DS = 1)
1566 or
1567 Set ATE ADDR3=DA for TxFrame(STA : To DS = 1 ; From DS = 0)
1568
1569 Return:
1570 TRUE if all parameters are OK, FALSE otherwise
1571 ==========================================================================
1572 */
1573 INT Set_ATE_DA_Proc(
1574 IN PRTMP_ADAPTER pAd,
1575 IN PUCHAR arg)
1576 {
1577 CHAR *value;
1578 INT i;
1579
1580 if(strlen(arg) != 17) //Mac address acceptable format 01:02:03:04:05:06 length 17
1581 return FALSE;
1582
1583 for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1584 {
1585 if((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))) )
1586 return FALSE; //Invalid
1587
1588
1589 #ifdef CONFIG_STA_SUPPORT
1590 AtoH(value, &pAd->ate.Addr3[i++], 1);
1591 #endif // CONFIG_STA_SUPPORT //
1592 }
1593
1594 if(i != 6)
1595 return FALSE; //Invalid
1596
1597
1598 #ifdef CONFIG_STA_SUPPORT
1599 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_DA_Proc (DA = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr3[0],
1600 pAd->ate.Addr3[1], pAd->ate.Addr3[2], pAd->ate.Addr3[3], pAd->ate.Addr3[4], pAd->ate.Addr3[5]));
1601 #endif // CONFIG_STA_SUPPORT //
1602
1603 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_DA_Proc Success\n"));
1604
1605 return TRUE;
1606 }
1607
1608 /*
1609 ==========================================================================
1610 Description:
1611 Set ATE ADDR3=SA for TxFrame(AP : To DS = 0 ; From DS = 1)
1612 or
1613 Set ATE ADDR2=SA for TxFrame(STA : To DS = 1 ; From DS = 0)
1614
1615 Return:
1616 TRUE if all parameters are OK, FALSE otherwise
1617 ==========================================================================
1618 */
1619 INT Set_ATE_SA_Proc(
1620 IN PRTMP_ADAPTER pAd,
1621 IN PUCHAR arg)
1622 {
1623 CHAR *value;
1624 INT i;
1625
1626 if(strlen(arg) != 17) //Mac address acceptable format 01:02:03:04:05:06 length 17
1627 return FALSE;
1628
1629 for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1630 {
1631 if((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))) )
1632 return FALSE; //Invalid
1633
1634
1635 #ifdef CONFIG_STA_SUPPORT
1636 AtoH(value, &pAd->ate.Addr2[i++], 1);
1637 #endif // CONFIG_STA_SUPPORT //
1638 }
1639
1640 if(i != 6)
1641 return FALSE; //Invalid
1642
1643
1644 #ifdef CONFIG_STA_SUPPORT
1645 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_SA_Proc (SA = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr2[0],
1646 pAd->ate.Addr2[1], pAd->ate.Addr2[2], pAd->ate.Addr2[3], pAd->ate.Addr2[4], pAd->ate.Addr2[5]));
1647 #endif // CONFIG_STA_SUPPORT //
1648
1649 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_SA_Proc Success\n"));
1650
1651 return TRUE;
1652 }
1653
1654 /*
1655 ==========================================================================
1656 Description:
1657 Set ATE ADDR2=BSSID for TxFrame(AP : To DS = 0 ; From DS = 1)
1658 or
1659 Set ATE ADDR1=BSSID for TxFrame(STA : To DS = 1 ; From DS = 0)
1660
1661 Return:
1662 TRUE if all parameters are OK, FALSE otherwise
1663 ==========================================================================
1664 */
1665 INT Set_ATE_BSSID_Proc(
1666 IN PRTMP_ADAPTER pAd,
1667 IN PUCHAR arg)
1668 {
1669 CHAR *value;
1670 INT i;
1671
1672 if(strlen(arg) != 17) //Mac address acceptable format 01:02:03:04:05:06 length 17
1673 return FALSE;
1674
1675 for (i=0, value = rstrtok(arg, ":"); value; value = rstrtok(NULL, ":"))
1676 {
1677 if((strlen(value) != 2) || (!isxdigit(*value)) || (!isxdigit(*(value+1))) )
1678 return FALSE; //Invalid
1679
1680
1681 #ifdef CONFIG_STA_SUPPORT
1682 AtoH(value, &pAd->ate.Addr1[i++], 1);
1683 #endif // CONFIG_STA_SUPPORT //
1684 }
1685
1686 if(i != 6)
1687 return FALSE; //Invalid
1688
1689
1690 #ifdef CONFIG_STA_SUPPORT
1691 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_BSSID_Proc (BSSID = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAd->ate.Addr1[0],
1692 pAd->ate.Addr1[1], pAd->ate.Addr1[2], pAd->ate.Addr1[3], pAd->ate.Addr1[4], pAd->ate.Addr1[5]));
1693 #endif // CONFIG_STA_SUPPORT //
1694
1695 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_BSSID_Proc Success\n"));
1696
1697 return TRUE;
1698 }
1699
1700 /*
1701 ==========================================================================
1702 Description:
1703 Set ATE Tx Channel
1704
1705 Return:
1706 TRUE if all parameters are OK, FALSE otherwise
1707 ==========================================================================
1708 */
1709 INT Set_ATE_CHANNEL_Proc(
1710 IN PRTMP_ADAPTER pAd,
1711 IN PUCHAR arg)
1712 {
1713 UCHAR channel;
1714
1715 channel = simple_strtol(arg, 0, 10);
1716
1717 if ((channel < 1) || (channel > 216))// to allow A band channel : ((channel < 1) || (channel > 14))
1718 {
1719 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_CHANNEL_Proc::Out of range, it should be in range of 1~14.\n"));
1720 return FALSE;
1721 }
1722 pAd->ate.Channel = channel;
1723
1724 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_CHANNEL_Proc (ATE Channel = %d)\n", pAd->ate.Channel));
1725 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_CHANNEL_Proc Success\n"));
1726
1727
1728 return TRUE;
1729 }
1730
1731 /*
1732 ==========================================================================
1733 Description:
1734 Set ATE Tx Power0
1735
1736 Return:
1737 TRUE if all parameters are OK, FALSE otherwise
1738 ==========================================================================
1739 */
1740 INT Set_ATE_TX_POWER0_Proc(
1741 IN PRTMP_ADAPTER pAd,
1742 IN PUCHAR arg)
1743 {
1744 CHAR TxPower;
1745
1746 TxPower = simple_strtol(arg, 0, 10);
1747
1748 if (pAd->ate.Channel <= 14)
1749 {
1750 if ((TxPower > 31) || (TxPower < 0))
1751 {
1752 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER0_Proc::Out of range (Value=%d)\n", TxPower));
1753 return FALSE;
1754 }
1755 }
1756 else// 5.5GHz
1757 {
1758 if ((TxPower > 15) || (TxPower < -7))
1759 {
1760 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER0_Proc::Out of range (Value=%d)\n", TxPower));
1761 return FALSE;
1762 }
1763 }
1764
1765 pAd->ate.TxPower0 = TxPower;
1766 ATETxPwrHandler(pAd, 0);
1767 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_POWER0_Proc Success\n"));
1768
1769
1770 return TRUE;
1771 }
1772
1773 /*
1774 ==========================================================================
1775 Description:
1776 Set ATE Tx Power1
1777
1778 Return:
1779 TRUE if all parameters are OK, FALSE otherwise
1780 ==========================================================================
1781 */
1782 INT Set_ATE_TX_POWER1_Proc(
1783 IN PRTMP_ADAPTER pAd,
1784 IN PUCHAR arg)
1785 {
1786 CHAR TxPower;
1787
1788 TxPower = simple_strtol(arg, 0, 10);
1789
1790 if (pAd->ate.Channel <= 14)
1791 {
1792 if ((TxPower > 31) || (TxPower < 0))
1793 {
1794 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER1_Proc::Out of range (Value=%d)\n", TxPower));
1795 return FALSE;
1796 }
1797 }
1798 else
1799 {
1800 if ((TxPower > 15) || (TxPower < -7))
1801 {
1802 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_POWER1_Proc::Out of range (Value=%d)\n", TxPower));
1803 return FALSE;
1804 }
1805 }
1806
1807 pAd->ate.TxPower1 = TxPower;
1808 ATETxPwrHandler(pAd, 1);
1809 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_POWER1_Proc Success\n"));
1810
1811
1812 return TRUE;
1813 }
1814
1815 /*
1816 ==========================================================================
1817 Description:
1818 Set ATE Tx Antenna
1819
1820 Return:
1821 TRUE if all parameters are OK, FALSE otherwise
1822 ==========================================================================
1823 */
1824 INT Set_ATE_TX_Antenna_Proc(
1825 IN PRTMP_ADAPTER pAd,
1826 IN PUCHAR arg)
1827 {
1828 CHAR value;
1829
1830 value = simple_strtol(arg, 0, 10);
1831
1832 if ((value > 2) || (value < 0))
1833 {
1834 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_Antenna_Proc::Out of range (Value=%d)\n", value));
1835 return FALSE;
1836 }
1837
1838 pAd->ate.TxAntennaSel = value;
1839
1840 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_Antenna_Proc (Antenna = %d)\n", pAd->ate.TxAntennaSel));
1841 ATEDBGPRINT(RT_DEBUG_TRACE,("Ralink: Set_ATE_TX_Antenna_Proc Success\n"));
1842
1843
1844 return TRUE;
1845 }
1846
1847 /*
1848 ==========================================================================
1849 Description:
1850 Set ATE Rx Antenna
1851
1852 Return:
1853 TRUE if all parameters are OK, FALSE otherwise
1854 ==========================================================================
1855 */
1856 INT Set_ATE_RX_Antenna_Proc(
1857 IN PRTMP_ADAPTER pAd,
1858 IN PUCHAR arg)
1859 {
1860 CHAR value;
1861
1862 value = simple_strtol(arg, 0, 10);
1863
1864 if ((value > 3) || (value < 0))
1865 {
1866 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_RX_Antenna_Proc::Out of range (Value=%d)\n", value));
1867 return FALSE;
1868 }
1869
1870 pAd->ate.RxAntennaSel = value;
1871
1872 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_Antenna_Proc (Antenna = %d)\n", pAd->ate.RxAntennaSel));
1873 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_Antenna_Proc Success\n"));
1874
1875
1876 return TRUE;
1877 }
1878
1879 /*
1880 ==========================================================================
1881 Description:
1882 Set ATE RF frequence offset
1883
1884 Return:
1885 TRUE if all parameters are OK, FALSE otherwise
1886 ==========================================================================
1887 */
1888 INT Set_ATE_TX_FREQOFFSET_Proc(
1889 IN PRTMP_ADAPTER pAd,
1890 IN PUCHAR arg)
1891 {
1892 UCHAR RFFreqOffset;
1893 ULONG R4;
1894
1895 RFFreqOffset = simple_strtol(arg, 0, 10);
1896 #ifndef RT30xx
1897 if(RFFreqOffset >= 64)
1898 #endif // RT30xx //
1899 #ifdef RT30xx
1900 //2008/08/06: KH modified the limit of offset value from 65 to 95(0x5F)
1901 if(RFFreqOffset >= 95)
1902 #endif // RT30xx //
1903 {
1904 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_FREQOFFSET_Proc::Out of range, it should be in range of 0~63.\n"));
1905 return FALSE;
1906 }
1907
1908 pAd->ate.RFFreqOffset = RFFreqOffset;
1909 #ifdef RT30xx
1910 if(IS_RT30xx(pAd))
1911 {
1912 // Set RF offset
1913 UCHAR RFValue;
1914 RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue);
1915 //2008/08/06: KH modified "pAd->RFFreqOffset" to "pAd->ate.RFFreqOffset"
1916 RFValue = (RFValue & 0x80) | pAd->ate.RFFreqOffset;
1917 RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue);
1918 }
1919 else
1920 #endif // RT30xx //
1921 {
1922
1923 R4 = pAd->ate.RFFreqOffset << 15; // shift TX power control to correct RF register bit position
1924 R4 |= (pAd->LatchRfRegs.R4 & ((~0x001f8000)));
1925 pAd->LatchRfRegs.R4 = R4;
1926
1927 RtmpRfIoWrite(pAd);
1928 }
1929 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_FREQOFFSET_Proc (RFFreqOffset = %d)\n", pAd->ate.RFFreqOffset));
1930 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_FREQOFFSET_Proc Success\n"));
1931
1932
1933 return TRUE;
1934 }
1935
1936 /*
1937 ==========================================================================
1938 Description:
1939 Set ATE RF BW
1940
1941 Return:
1942 TRUE if all parameters are OK, FALSE otherwise
1943 ==========================================================================
1944 */
1945 INT Set_ATE_TX_BW_Proc(
1946 IN PRTMP_ADAPTER pAd,
1947 IN PUCHAR arg)
1948 {
1949 int i;
1950 UCHAR value = 0;
1951 UCHAR BBPCurrentBW;
1952
1953 BBPCurrentBW = simple_strtol(arg, 0, 10);
1954
1955 if(BBPCurrentBW == 0)
1956 pAd->ate.TxWI.BW = BW_20;
1957 else
1958 pAd->ate.TxWI.BW = BW_40;
1959
1960 if(pAd->ate.TxWI.BW == BW_20)
1961 {
1962 if(pAd->ate.Channel <= 14)
1963 {
1964 for (i=0; i<5; i++)
1965 {
1966 if (pAd->Tx20MPwrCfgGBand[i] != 0xffffffff)
1967 {
1968 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx20MPwrCfgGBand[i]);
1969 RTMPusecDelay(5000);
1970 }
1971 }
1972 }
1973 else
1974 {
1975 for (i=0; i<5; i++)
1976 {
1977 if (pAd->Tx20MPwrCfgABand[i] != 0xffffffff)
1978 {
1979 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx20MPwrCfgABand[i]);
1980 RTMPusecDelay(5000);
1981 }
1982 }
1983 }
1984
1985 //Set BBP R4 bit[4:3]=0:0
1986 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
1987 value &= (~0x18);
1988 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
1989
1990 //Set BBP R66=0x3C
1991 value = 0x3C;
1992 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
1993 //Set BBP R68=0x0B
1994 //to improve Rx sensitivity.
1995 value = 0x0B;
1996 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
1997 //Set BBP R69=0x16
1998 value = 0x16;
1999 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
2000 //Set BBP R70=0x08
2001 value = 0x08;
2002 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
2003 //Set BBP R73=0x11
2004 value = 0x11;
2005 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
2006
2007 // If Channel=14, Bandwidth=20M and Mode=CCK, Set BBP R4 bit5=1
2008 // (Japan filter coefficients)
2009 // This segment of code will only works when ATETXMODE and ATECHANNEL
2010 // were set to MODE_CCK and 14 respectively before ATETXBW is set to 0.
2011 //=====================================================================
2012 if (pAd->ate.Channel == 14)
2013 {
2014 int TxMode = pAd->ate.TxWI.PHYMODE;
2015 if (TxMode == MODE_CCK)
2016 {
2017 // when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1
2018 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
2019 value |= 0x20; //set bit5=1
2020 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
2021 }
2022 }
2023
2024 //=====================================================================
2025 // If bandwidth != 40M, RF Reg4 bit 21 = 0.
2026 #ifdef RT30xx
2027 // Set BW
2028 if(IS_RT30xx(pAd))
2029 RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR) pAd->Mlme.CaliBW20RfR24);
2030 else
2031 #endif // RT30xx //
2032 {
2033 pAd->LatchRfRegs.R4 &= ~0x00200000;
2034 RtmpRfIoWrite(pAd);
2035 }
2036
2037 }
2038 else if(pAd->ate.TxWI.BW == BW_40)
2039 {
2040 if(pAd->ate.Channel <= 14)
2041 {
2042 for (i=0; i<5; i++)
2043 {
2044 if (pAd->Tx40MPwrCfgGBand[i] != 0xffffffff)
2045 {
2046 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx40MPwrCfgGBand[i]);
2047 RTMPusecDelay(5000);
2048 }
2049 }
2050 }
2051 else
2052 {
2053 for (i=0; i<5; i++)
2054 {
2055 if (pAd->Tx40MPwrCfgABand[i] != 0xffffffff)
2056 {
2057 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, pAd->Tx40MPwrCfgABand[i]);
2058 RTMPusecDelay(5000);
2059 }
2060 }
2061 #ifdef DOT11_N_SUPPORT
2062 if ((pAd->ate.TxWI.PHYMODE >= MODE_HTMIX) && (pAd->ate.TxWI.MCS == 7))
2063 {
2064 value = 0x28;
2065 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R67, value);
2066 }
2067 #endif // DOT11_N_SUPPORT //
2068 }
2069
2070 //Set BBP R4 bit[4:3]=1:0
2071 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &value);
2072 value &= (~0x18);
2073 value |= 0x10;
2074 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, value);
2075
2076 //Set BBP R66=0x3C
2077 value = 0x3C;
2078 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, value);
2079 //Set BBP R68=0x0C
2080 //to improve Rx sensitivity.
2081 value = 0x0C;
2082 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R68, value);
2083 //Set BBP R69=0x1A
2084 value = 0x1A;
2085 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, value);
2086 //Set BBP R70=0x0A
2087 value = 0x0A;
2088 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, value);
2089 //Set BBP R73=0x16
2090 value = 0x16;
2091 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, value);
2092
2093 // If bandwidth = 40M, set RF Reg4 bit 21 = 1.
2094 #ifdef RT30xx
2095 // Set BW
2096 if(IS_RT30xx(pAd))
2097 RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR) pAd->Mlme.CaliBW40RfR24);
2098 else
2099 #endif // RT30xx //
2100 {
2101 pAd->LatchRfRegs.R4 |= 0x00200000;
2102 RtmpRfIoWrite(pAd);
2103 }
2104 }
2105
2106 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_BW_Proc (BBPCurrentBW = %d)\n", pAd->ate.TxWI.BW));
2107 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_BW_Proc Success\n"));
2108
2109
2110 return TRUE;
2111 }
2112
2113 /*
2114 ==========================================================================
2115 Description:
2116 Set ATE Tx frame length
2117
2118 Return:
2119 TRUE if all parameters are OK, FALSE otherwise
2120 ==========================================================================
2121 */
2122 INT Set_ATE_TX_LENGTH_Proc(
2123 IN PRTMP_ADAPTER pAd,
2124 IN PUCHAR arg)
2125 {
2126 pAd->ate.TxLength = simple_strtol(arg, 0, 10);
2127
2128 if((pAd->ate.TxLength < 24) || (pAd->ate.TxLength > (MAX_FRAME_SIZE - 34/* == 2312 */)))
2129 {
2130 pAd->ate.TxLength = (MAX_FRAME_SIZE - 34/* == 2312 */);
2131 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_LENGTH_Proc::Out of range, it should be in range of 24~%d.\n", (MAX_FRAME_SIZE - 34/* == 2312 */)));
2132 return FALSE;
2133 }
2134
2135 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_LENGTH_Proc (TxLength = %d)\n", pAd->ate.TxLength));
2136 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_LENGTH_Proc Success\n"));
2137
2138
2139 return TRUE;
2140 }
2141
2142 /*
2143 ==========================================================================
2144 Description:
2145 Set ATE Tx frame count
2146
2147 Return:
2148 TRUE if all parameters are OK, FALSE otherwise
2149 ==========================================================================
2150 */
2151 INT Set_ATE_TX_COUNT_Proc(
2152 IN PRTMP_ADAPTER pAd,
2153 IN PUCHAR arg)
2154 {
2155 pAd->ate.TxCount = simple_strtol(arg, 0, 10);
2156
2157 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_COUNT_Proc (TxCount = %d)\n", pAd->ate.TxCount));
2158 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_COUNT_Proc Success\n"));
2159
2160
2161 return TRUE;
2162 }
2163
2164 /*
2165 ==========================================================================
2166 Description:
2167 Set ATE Tx frame MCS
2168
2169 Return:
2170 TRUE if all parameters are OK, FALSE otherwise
2171 ==========================================================================
2172 */
2173 INT Set_ATE_TX_MCS_Proc(
2174 IN PRTMP_ADAPTER pAd,
2175 IN PUCHAR arg)
2176 {
2177 UCHAR MCS;
2178 int result;
2179
2180 MCS = simple_strtol(arg, 0, 10);
2181 result = CheckMCSValid(pAd->ate.TxWI.PHYMODE, MCS);
2182
2183 if (result != -1)
2184 {
2185 pAd->ate.TxWI.MCS = (UCHAR)MCS;
2186 }
2187 else
2188 {
2189 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_MCS_Proc::Out of range, refer to rate table.\n"));
2190 return FALSE;
2191 }
2192
2193 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MCS_Proc (MCS = %d)\n", pAd->ate.TxWI.MCS));
2194 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MCS_Proc Success\n"));
2195
2196
2197 return TRUE;
2198 }
2199
2200 /*
2201 ==========================================================================
2202 Description:
2203 Set ATE Tx frame Mode
2204 0: MODE_CCK
2205 1: MODE_OFDM
2206 2: MODE_HTMIX
2207 3: MODE_HTGREENFIELD
2208
2209 Return:
2210 TRUE if all parameters are OK, FALSE otherwise
2211 ==========================================================================
2212 */
2213 INT Set_ATE_TX_MODE_Proc(
2214 IN PRTMP_ADAPTER pAd,
2215 IN PUCHAR arg)
2216 {
2217 pAd->ate.TxWI.PHYMODE = simple_strtol(arg, 0, 10);
2218
2219 if(pAd->ate.TxWI.PHYMODE > 3)
2220 {
2221 pAd->ate.TxWI.PHYMODE = 0;
2222 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_MODE_Proc::Out of range. it should be in range of 0~3\n"));
2223 ATEDBGPRINT(RT_DEBUG_ERROR, ("0: CCK, 1: OFDM, 2: HT_MIX, 3: HT_GREEN_FIELD.\n"));
2224 return FALSE;
2225 }
2226
2227 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_MODE_Proc (TxMode = %d)\n", pAd->ate.TxWI.PHYMODE));
2228 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_MODE_Proc Success\n"));
2229
2230
2231 return TRUE;
2232 }
2233
2234 /*
2235 ==========================================================================
2236 Description:
2237 Set ATE Tx frame GI
2238
2239 Return:
2240 TRUE if all parameters are OK, FALSE otherwise
2241 ==========================================================================
2242 */
2243 INT Set_ATE_TX_GI_Proc(
2244 IN PRTMP_ADAPTER pAd,
2245 IN PUCHAR arg)
2246 {
2247 pAd->ate.TxWI.ShortGI = simple_strtol(arg, 0, 10);
2248
2249 if(pAd->ate.TxWI.ShortGI > 1)
2250 {
2251 pAd->ate.TxWI.ShortGI = 0;
2252 ATEDBGPRINT(RT_DEBUG_ERROR, ("Set_ATE_TX_GI_Proc::Out of range\n"));
2253 return FALSE;
2254 }
2255
2256 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_TX_GI_Proc (GI = %d)\n", pAd->ate.TxWI.ShortGI));
2257 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_TX_GI_Proc Success\n"));
2258
2259
2260 return TRUE;
2261 }
2262
2263 /*
2264 ==========================================================================
2265 Description:
2266 ==========================================================================
2267 */
2268 INT Set_ATE_RX_FER_Proc(
2269 IN PRTMP_ADAPTER pAd,
2270 IN PUCHAR arg)
2271 {
2272 pAd->ate.bRxFer = simple_strtol(arg, 0, 10);
2273
2274 if (pAd->ate.bRxFer == 1)
2275 {
2276 pAd->ate.RxCntPerSec = 0;
2277 pAd->ate.RxTotalCnt = 0;
2278 }
2279
2280 ATEDBGPRINT(RT_DEBUG_TRACE, ("Set_ATE_RX_FER_Proc (bRxFer = %d)\n", pAd->ate.bRxFer));
2281 ATEDBGPRINT(RT_DEBUG_TRACE, ("Ralink: Set_ATE_RX_FER_Proc Success\n"));
2282
2283
2284 return TRUE;
2285 }
2286
2287 INT Set_ATE_Read_RF_Proc(
2288 IN PRTMP_ADAPTER pAd,
2289 IN PUCHAR arg)
2290 {
2291 #ifdef RT30xx
2292 //2008/07/10:KH add to support RT30xx ATE<--
2293 if(IS_RT30xx(pAd))
2294 {
2295 /* modify by WY for Read RF Reg. error */
2296 UCHAR RFValue;
2297 INT index=0;
2298 for (index = 0; index < 32; index++)
2299 {
2300 RT30xxReadRFRegister(pAd, index, (PUCHAR)&RFValue);
2301 printk("R%d=%d\n",index,RFValue);
2302 }
2303 }
2304 else
2305 //2008/07/10:KH add to support RT30xx ATE-->
2306 #endif // RT30xx //
2307 {
2308 ate_print(KERN_EMERG "R1 = %lx\n", pAd->LatchRfRegs.R1);
2309 ate_print(KERN_EMERG "R2 = %lx\n", pAd->LatchRfRegs.R2);
2310 ate_print(KERN_EMERG "R3 = %lx\n", pAd->LatchRfRegs.R3);
2311 ate_print(KERN_EMERG "R4 = %lx\n", pAd->LatchRfRegs.R4);
2312 }
2313 return TRUE;
2314 }
2315
2316 INT Set_ATE_Write_RF1_Proc(
2317 IN PRTMP_ADAPTER pAd,
2318 IN PUCHAR arg)
2319 {
2320 #ifdef RT30xx
2321 //2008/07/10:KH add to support 3070 ATE<--
2322 if(IS_RT30xx(pAd))
2323 {
2324 printk("Warning!! RT30xx Don't Support\n");
2325 return FALSE;
2326
2327 }
2328 else
2329 //2008/07/10:KH add to support 3070 ATE-->
2330 #endif // RT30xx //
2331 {
2332 UINT32 value = simple_strtol(arg, 0, 16);
2333
2334 pAd->LatchRfRegs.R1 = value;
2335 RtmpRfIoWrite(pAd);
2336 }
2337 return TRUE;
2338
2339 }
2340
2341 INT Set_ATE_Write_RF2_Proc(
2342 IN PRTMP_ADAPTER pAd,
2343 IN PUCHAR arg)
2344 {
2345 #ifdef RT30xx
2346 //2008/07/10:KH add to support 3070 ATE<--
2347 if(IS_RT30xx(pAd))
2348 {
2349 printk("Warning!! RT30xx Don't Support\n");
2350 return FALSE;
2351
2352 }
2353 else
2354 //2008/07/10:KH add to support 3070 ATE-->
2355 #endif // RT30xx //
2356 {
2357 UINT32 value = simple_strtol(arg, 0, 16);
2358
2359 pAd->LatchRfRegs.R2 = value;
2360 RtmpRfIoWrite(pAd);
2361 }
2362 return TRUE;
2363 }
2364
2365 INT Set_ATE_Write_RF3_Proc(
2366 IN PRTMP_ADAPTER pAd,
2367 IN PUCHAR arg)
2368 {
2369 #ifdef RT30xx
2370 //2008/07/10:KH add to support 3070 ATE<--
2371 if(IS_RT30xx(pAd))
2372 {
2373 printk("Warning!! RT30xx Don't Support\n");
2374 return FALSE;
2375
2376 }
2377 else
2378 //2008/07/10:KH add to support 3070 ATE-->
2379 #endif // RT30xx //
2380 {
2381 UINT32 value = simple_strtol(arg, 0, 16);
2382
2383 pAd->LatchRfRegs.R3 = value;
2384 RtmpRfIoWrite(pAd);
2385 }
2386 return TRUE;
2387 }
2388
2389 INT Set_ATE_Write_RF4_Proc(
2390 IN PRTMP_ADAPTER pAd,
2391 IN PUCHAR arg)
2392 {
2393 #ifdef RT30xx
2394 //2008/07/10:KH add to support 3070 ATE<--
2395 if(IS_RT30xx(pAd))
2396 {
2397 printk("Warning!! RT30xx Don't Support\n");
2398 return FALSE;
2399
2400 }
2401 else
2402 //2008/07/10:KH add to support 3070 ATE-->
2403 #endif // RT30xx //
2404 {
2405 UINT32 value = simple_strtol(arg, 0, 16);
2406
2407 pAd->LatchRfRegs.R4 = value;
2408 RtmpRfIoWrite(pAd);
2409 }
2410 return TRUE;
2411 }
2412 #ifdef RT30xx
2413 //2008/07/10:KH add to support 3070 ATE<--
2414 INT SET_ATE_3070RF_Proc(
2415 IN PRTMP_ADAPTER pAd,
2416 IN PUCHAR arg)
2417 {
2418 CHAR *this_char;
2419 CHAR *value;
2420 UINT32 Reg,RFValue;
2421 if(IS_RT30xx(pAd))
2422 {
2423 printk("SET_ATE_3070RF_Proc=%s\n",arg);
2424 this_char =arg;
2425 if ((value = strchr(this_char, ':')) != NULL)
2426 *value++ = 0;
2427 Reg= simple_strtol(this_char, 0, 16);
2428 RFValue= simple_strtol(value, 0, 16);
2429 printk("RF Reg[%d]=%d\n",Reg,RFValue);
2430 RT30xxWriteRFRegister(pAd, Reg,RFValue);
2431 }
2432 else
2433 printk("Warning!! Only 3070 Support\n");
2434 return TRUE;
2435 }
2436 //2008/07/10:KH add to support 3070 ATE-->
2437 #endif // RT30xx //
2438 /*
2439 ==========================================================================
2440 Description:
2441 Load and Write EEPROM from a binary file prepared in advance.
2442
2443 Return:
2444 TRUE if all parameters are OK, FALSE otherwise
2445 ==========================================================================
2446 */
2447 #ifndef UCOS
2448 INT Set_ATE_Load_E2P_Proc(
2449 IN PRTMP_ADAPTER pAd,
2450 IN PUCHAR arg)
2451 {
2452 BOOLEAN ret = FALSE;
2453 PUCHAR src = EEPROM_BIN_FILE_NAME;
2454 struct file *srcf;
2455 INT32 retval, orgfsuid, orgfsgid;
2456 mm_segment_t orgfs;
2457 USHORT WriteEEPROM[(EEPROM_SIZE/2)];
2458 UINT32 FileLength = 0;
2459 UINT32 value = simple_strtol(arg, 0, 10);
2460
2461 ATEDBGPRINT(RT_DEBUG_ERROR, ("===> %s (value=%d)\n\n", __FUNCTION__, value));
2462
2463 if (value > 0)
2464 {
2465 /* zero the e2p buffer */
2466 NdisZeroMemory((PUCHAR)WriteEEPROM, EEPROM_SIZE);
2467
2468 /* save uid and gid used for filesystem access.
2469 ** set user and group to 0 (root)
2470 */
2471 orgfsuid = current->fsuid;
2472 orgfsgid = current->fsgid;
2473 /* as root */
2474 current->fsuid = current->fsgid = 0;
2475 orgfs = get_fs();
2476 set_fs(KERNEL_DS);
2477
2478 do
2479 {
2480 /* open the bin file */
2481 srcf = filp_open(src, O_RDONLY, 0);
2482
2483 if (IS_ERR(srcf))
2484 {
2485 ate_print("%s - Error %ld opening %s\n", __FUNCTION__, -PTR_ERR(srcf), src);
2486 break;
2487 }
2488
2489 /* the object must have a read method */
2490 if ((srcf->f_op == NULL) || (srcf->f_op->read == NULL))
2491 {
2492 ate_print("%s - %s does not have a read method\n", __FUNCTION__, src);
2493 break;
2494 }
2495
2496 /* read the firmware from the file *.bin */
2497 FileLength = srcf->f_op->read(srcf,
2498 (PUCHAR)WriteEEPROM,
2499 EEPROM_SIZE,
2500 &srcf->f_pos);
2501
2502 if (FileLength != EEPROM_SIZE)
2503 {
2504 ate_print("%s: error file length (=%d) in e2p.bin\n",
2505 __FUNCTION__, FileLength);
2506 break;
2507 }
2508 else
2509 {
2510 /* write the content of .bin file to EEPROM */
2511 rt_ee_write_all(pAd, WriteEEPROM);
2512 ret = TRUE;
2513 }
2514 break;
2515 } while(TRUE);
2516
2517 /* close firmware file */
2518 if (IS_ERR(srcf))
2519 {
2520 ;
2521 }
2522 else
2523 {
2524 retval = filp_close(srcf, NULL);
2525 if (retval)
2526 {
2527 ATEDBGPRINT(RT_DEBUG_ERROR, ("--> Error %d closing %s\n", -retval, src));
2528
2529 }
2530 }
2531
2532 /* restore */
2533 set_fs(orgfs);
2534 current->fsuid = orgfsuid;
2535 current->fsgid = orgfsgid;
2536 }
2537 ATEDBGPRINT(RT_DEBUG_ERROR, ("<=== %s (ret=%d)\n", __FUNCTION__, ret));
2538
2539 return ret;
2540
2541 }
2542 #else
2543 INT Set_ATE_Load_E2P_Proc(
2544 IN PRTMP_ADAPTER pAd,
2545 IN PUCHAR arg)
2546 {
2547 USHORT WriteEEPROM[(EEPROM_SIZE/2)];
2548 struct iwreq *wrq = (struct iwreq *)arg;
2549
2550 ATEDBGPRINT(RT_DEBUG_TRACE, ("===> %s (wrq->u.data.length = %d)\n\n", __FUNCTION__, wrq->u.data.length));
2551
2552 if (wrq->u.data.length != EEPROM_SIZE)
2553 {
2554 ate_print("%s: error length (=%d) from host\n",
2555 __FUNCTION__, wrq->u.data.length);
2556 return FALSE;
2557 }
2558 else/* (wrq->u.data.length == EEPROM_SIZE) */
2559 {
2560 /* zero the e2p buffer */
2561 NdisZeroMemory((PUCHAR)WriteEEPROM, EEPROM_SIZE);
2562
2563 /* fill the local buffer */
2564 NdisMoveMemory((PUCHAR)WriteEEPROM, wrq->u.data.pointer, wrq->u.data.length);
2565
2566 do
2567 {
2568 /* write the content of .bin file to EEPROM */
2569 rt_ee_write_all(pAd, WriteEEPROM);
2570
2571 } while(FALSE);
2572 }
2573
2574 ATEDBGPRINT(RT_DEBUG_TRACE, ("<=== %s\n", __FUNCTION__));
2575
2576 return TRUE;
2577
2578 }
2579 #endif // !UCOS //
2580
2581 INT Set_ATE_Read_E2P_Proc(
2582 IN PRTMP_ADAPTER pAd,
2583 IN PUCHAR arg)
2584 {
2585 USHORT buffer[EEPROM_SIZE/2];
2586 USHORT *p;
2587 int i;
2588
2589 rt_ee_read_all(pAd, (USHORT *)buffer);
2590 p = buffer;
2591 for (i = 0; i < (EEPROM_SIZE/2); i++)
2592 {
2593 ate_print("%4.4x ", *p);
2594 if (((i+1) % 16) == 0)
2595 ate_print("\n");
2596 p++;
2597 }
2598 return TRUE;
2599 }
2600
2601 INT Set_ATE_Show_Proc(
2602 IN PRTMP_ADAPTER pAd,
2603 IN PUCHAR arg)
2604 {
2605 ate_print("Mode=%d\n", pAd->ate.Mode);
2606 ate_print("TxPower0=%d\n", pAd->ate.TxPower0);
2607 ate_print("TxPower1=%d\n", pAd->ate.TxPower1);
2608 ate_print("TxAntennaSel=%d\n", pAd->ate.TxAntennaSel);
2609 ate_print("RxAntennaSel=%d\n", pAd->ate.RxAntennaSel);
2610 ate_print("BBPCurrentBW=%d\n", pAd->ate.TxWI.BW);
2611 ate_print("GI=%d\n", pAd->ate.TxWI.ShortGI);
2612 ate_print("MCS=%d\n", pAd->ate.TxWI.MCS);
2613 ate_print("TxMode=%d\n", pAd->ate.TxWI.PHYMODE);
2614 ate_print("Addr1=%02x:%02x:%02x:%02x:%02x:%02x\n",
2615 pAd->ate.Addr1[0], pAd->ate.Addr1[1], pAd->ate.Addr1[2], pAd->ate.Addr1[3], pAd->ate.Addr1[4], pAd->ate.Addr1[5]);
2616 ate_print("Addr2=%02x:%02x:%02x:%02x:%02x:%02x\n",
2617 pAd->ate.Addr2[0], pAd->ate.Addr2[1], pAd->ate.Addr2[2], pAd->ate.Addr2[3], pAd->ate.Addr2[4], pAd->ate.Addr2[5]);
2618 ate_print("Addr3=%02x:%02x:%02x:%02x:%02x:%02x\n",
2619 pAd->ate.Addr3[0], pAd->ate.Addr3[1], pAd->ate.Addr3[2], pAd->ate.Addr3[3], pAd->ate.Addr3[4], pAd->ate.Addr3[5]);
2620 ate_print("Channel=%d\n", pAd->ate.Channel);
2621 ate_print("TxLength=%d\n", pAd->ate.TxLength);
2622 ate_print("TxCount=%u\n", pAd->ate.TxCount);
2623 ate_print("RFFreqOffset=%d\n", pAd->ate.RFFreqOffset);
2624 ate_print(KERN_EMERG "Set_ATE_Show_Proc Success\n");
2625 return TRUE;
2626 }
2627
2628 INT Set_ATE_Help_Proc(
2629 IN PRTMP_ADAPTER pAd,
2630 IN PUCHAR arg)
2631 {
2632 ate_print("ATE=ATESTART, ATESTOP, TXCONT, TXCARR, TXFRAME, RXFRAME\n");
2633 ate_print("ATEDA\n");
2634 ate_print("ATESA\n");
2635 ate_print("ATEBSSID\n");
2636 ate_print("ATECHANNEL, range:0~14(unless A band !)\n");
2637 ate_print("ATETXPOW0, set power level of antenna 1.\n");
2638 ate_print("ATETXPOW1, set power level of antenna 2.\n");
2639 ate_print("ATETXANT, set TX antenna. 0:all, 1:antenna one, 2:antenna two.\n");
2640 ate_print("ATERXANT, set RX antenna.0:all, 1:antenna one, 2:antenna two, 3:antenna three.\n");
2641 ate_print("ATETXFREQOFFSET, set frequency offset, range 0~63\n");
2642 ate_print("ATETXBW, set BandWidth, 0:20MHz, 1:40MHz.\n");
2643 ate_print("ATETXLEN, set Frame length, range 24~%d\n", (MAX_FRAME_SIZE - 34/* == 2312 */));
2644 ate_print("ATETXCNT, set how many frame going to transmit.\n");
2645 ate_print("ATETXMCS, set MCS, reference to rate table.\n");
2646 ate_print("ATETXMODE, set Mode 0:CCK, 1:OFDM, 2:HT-Mix, 3:GreenField, reference to rate table.\n");
2647 ate_print("ATETXGI, set GI interval, 0:Long, 1:Short\n");
2648 ate_print("ATERXFER, 0:disable Rx Frame error rate. 1:enable Rx Frame error rate.\n");
2649 ate_print("ATERRF, show all RF registers.\n");
2650 ate_print("ATEWRF1, set RF1 register.\n");
2651 ate_print("ATEWRF2, set RF2 register.\n");
2652 ate_print("ATEWRF3, set RF3 register.\n");
2653 ate_print("ATEWRF4, set RF4 register.\n");
2654 ate_print("ATELDE2P, load EEPROM from .bin file.\n");
2655 ate_print("ATERE2P, display all EEPROM content.\n");
2656 ate_print("ATESHOW, display all parameters of ATE.\n");
2657 ate_print("ATEHELP, online help.\n");
2658
2659 return TRUE;
2660 }
2661
2662 /*
2663 ==========================================================================
2664 Description:
2665
2666 AsicSwitchChannel() dedicated for ATE.
2667
2668 ==========================================================================
2669 */
2670 VOID ATEAsicSwitchChannel(
2671 IN PRTMP_ADAPTER pAd)
2672 {
2673 UINT32 R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0, Value = 0;
2674 CHAR TxPwer = 0, TxPwer2 = 0;
2675 UCHAR index, BbpValue = 0, R66 = 0x30;
2676 RTMP_RF_REGS *RFRegTable;
2677 UCHAR Channel;
2678
2679 #ifdef RALINK_28xx_QA
2680 if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
2681 {
2682 if (pAd->ate.Channel != pAd->LatchRfRegs.Channel)
2683 {
2684 pAd->ate.Channel = pAd->LatchRfRegs.Channel;
2685 }
2686 return;
2687 }
2688 else
2689 #endif // RALINK_28xx_QA //
2690 Channel = pAd->ate.Channel;
2691
2692 // Select antenna
2693 AsicAntennaSelect(pAd, Channel);
2694
2695 // fill Tx power value
2696 TxPwer = pAd->ate.TxPower0;
2697 TxPwer2 = pAd->ate.TxPower1;
2698 #ifdef RT30xx
2699 //2008/07/10:KH add to support 3070 ATE<--
2700
2701 // The RF programming sequence is difference between 3xxx and 2xxx
2702 // The 3070 is 1T1R. Therefore, we don't need to set the number of Tx/Rx path and the only job is to set the parameters of channels.
2703 if (IS_RT30xx(pAd) && ((pAd->RfIcType == RFIC_3020) ||
2704 (pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) ||
2705 (pAd->RfIcType == RFIC_2020)))
2706 {
2707 /* modify by WY for Read RF Reg. error */
2708 UCHAR RFValue;
2709
2710 for (index = 0; index < NUM_OF_3020_CHNL; index++)
2711 {
2712 if (Channel == FreqItems3020[index].Channel)
2713 {
2714 // Programming channel parameters
2715 RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N);
2716 RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3020[index].K);
2717
2718 RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RFValue);
2719 RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
2720 RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RFValue);
2721
2722 // Set Tx Power
2723 RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue);
2724 RFValue = (RFValue & 0xE0) | TxPwer;
2725 RT30xxWriteRFRegister(pAd, RF_R12, (UCHAR)RFValue);
2726
2727 // Set RF offset
2728 RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue);
2729 //2008/08/06: KH modified "pAd->RFFreqOffset" to "pAd->ate.RFFreqOffset"
2730 RFValue = (RFValue & 0x80) | pAd->ate.RFFreqOffset;
2731 RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue);
2732
2733 // Set BW
2734 if (pAd->ate.TxWI.BW == BW_40)
2735 {
2736 RFValue = pAd->Mlme.CaliBW40RfR24;
2737 //DISABLE_11N_CHECK(pAd);
2738 }
2739 else
2740 {
2741 RFValue = pAd->Mlme.CaliBW20RfR24;
2742 }
2743 RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR)RFValue);
2744
2745 // Enable RF tuning
2746 RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue);
2747 RFValue = RFValue | 0x1;
2748 RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue);
2749
2750 // latch channel for future usage.
2751 pAd->LatchRfRegs.Channel = Channel;
2752
2753 break;
2754 }
2755 }
2756
2757 DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
2758 Channel,
2759 pAd->RfIcType,
2760 TxPwer,
2761 TxPwer2,
2762 pAd->Antenna.field.TxPath,
2763 FreqItems3020[index].N,
2764 FreqItems3020[index].K,
2765 FreqItems3020[index].R));
2766 }
2767 else
2768 //2008/07/10:KH add to support 3070 ATE-->
2769 #endif // RT30xx //
2770 {
2771 RFRegTable = RF2850RegTable;
2772
2773 switch (pAd->RfIcType)
2774 {
2775 /* But only 2850 and 2750 support 5.5GHz band... */
2776 case RFIC_2820:
2777 case RFIC_2850:
2778 case RFIC_2720:
2779 case RFIC_2750:
2780
2781 for (index = 0; index < NUM_OF_2850_CHNL; index++)
2782 {
2783 if (Channel == RFRegTable[index].Channel)
2784 {
2785 R2 = RFRegTable[index].R2;
2786 if (pAd->Antenna.field.TxPath == 1)
2787 {
2788 R2 |= 0x4000; // If TXpath is 1, bit 14 = 1;
2789 }
2790
2791 if (pAd->Antenna.field.RxPath == 2)
2792 {
2793 switch (pAd->ate.RxAntennaSel)
2794 {
2795 case 1:
2796 R2 |= 0x20040;
2797 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2798 BbpValue &= 0xE4;
2799 BbpValue |= 0x00;
2800 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2801 break;
2802 case 2:
2803 R2 |= 0x10040;
2804 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2805 BbpValue &= 0xE4;
2806 BbpValue |= 0x01;
2807 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2808 break;
2809 default:
2810 R2 |= 0x40;
2811 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2812 BbpValue &= 0xE4;
2813 /* Only enable two Antenna to receive. */
2814 BbpValue |= 0x08;
2815 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2816 break;
2817 }
2818 }
2819 else if (pAd->Antenna.field.RxPath == 1)
2820 {
2821 R2 |= 0x20040; // write 1 to off RxPath
2822 }
2823
2824 if (pAd->Antenna.field.TxPath == 2)
2825 {
2826 if (pAd->ate.TxAntennaSel == 1)
2827 {
2828 R2 |= 0x4000; // If TX Antenna select is 1 , bit 14 = 1; Disable Ant 2
2829 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2830 BbpValue &= 0xE7; //11100111B
2831 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2832 }
2833 else if (pAd->ate.TxAntennaSel == 2)
2834 {
2835 R2 |= 0x8000; // If TX Antenna select is 2 , bit 15 = 1; Disable Ant 1
2836 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2837 BbpValue &= 0xE7;
2838 BbpValue |= 0x08;
2839 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2840 }
2841 else
2842 {
2843 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
2844 BbpValue &= 0xE7;
2845 BbpValue |= 0x10;
2846 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
2847 }
2848 }
2849 if (pAd->Antenna.field.RxPath == 3)
2850 {
2851 switch (pAd->ate.RxAntennaSel)
2852 {
2853 case 1:
2854 R2 |= 0x20040;
2855 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2856 BbpValue &= 0xE4;
2857 BbpValue |= 0x00;
2858 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2859 break;
2860 case 2:
2861 R2 |= 0x10040;
2862 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2863 BbpValue &= 0xE4;
2864 BbpValue |= 0x01;
2865 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2866 break;
2867 case 3:
2868 R2 |= 0x30000;
2869 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2870 BbpValue &= 0xE4;
2871 BbpValue |= 0x02;
2872 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2873 break;
2874 default:
2875 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
2876 BbpValue &= 0xE4;
2877 BbpValue |= 0x10;
2878 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
2879 break;
2880 }
2881 }
2882
2883 if (Channel > 14)
2884 {
2885 // initialize R3, R4
2886 R3 = (RFRegTable[index].R3 & 0xffffc1ff);
2887 R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->ate.RFFreqOffset << 15);
2888
2889 // According the Rory's suggestion to solve the middle range issue.
2890 // 5.5G band power range: 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0" means the TX power reduce 7dB
2891 // R3
2892 if ((TxPwer >= -7) && (TxPwer < 0))
2893 {
2894 TxPwer = (7+TxPwer);
2895 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
2896 R3 |= (TxPwer << 10);
2897 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer=%d \n", TxPwer));
2898 }
2899 else
2900 {
2901 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
2902 R3 |= (TxPwer << 10) | (1 << 9);
2903 }
2904
2905 // R4
2906 if ((TxPwer2 >= -7) && (TxPwer2 < 0))
2907 {
2908 TxPwer2 = (7+TxPwer2);
2909 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
2910 R4 |= (TxPwer2 << 7);
2911 ATEDBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
2912 }
2913 else
2914 {
2915 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
2916 R4 |= (TxPwer2 << 7) | (1 << 6);
2917 }
2918 }
2919 else
2920 {
2921 R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9); // set TX power0
2922 R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->ate.RFFreqOffset << 15) | (TxPwer2 <<6);// Set freq offset & TxPwr1
2923 }
2924
2925 // Based on BBP current mode before changing RF channel.
2926 if (pAd->ate.TxWI.BW == BW_40)
2927 {
2928 R4 |=0x200000;
2929 }
2930
2931 // Update variables
2932 pAd->LatchRfRegs.Channel = Channel;
2933 pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
2934 pAd->LatchRfRegs.R2 = R2;
2935 pAd->LatchRfRegs.R3 = R3;
2936 pAd->LatchRfRegs.R4 = R4;
2937
2938 RtmpRfIoWrite(pAd);
2939
2940 break;
2941 }
2942 }
2943 break;
2944
2945 default:
2946 break;
2947 }
2948 }
2949 // Change BBP setting during switch from a->g, g->a
2950 if (Channel <= 14)
2951 {
2952 ULONG TxPinCfg = 0x00050F0A;// 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A
2953
2954 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
2955 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
2956 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
2957
2958 /* For 1T/2R chip only... */
2959 if (pAd->NicConfig2.field.ExternalLNAForG)
2960 {
2961 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
2962 }
2963 else
2964 {
2965 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
2966 }
2967
2968 // According the Rory's suggestion to solve the middle range issue.
2969 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R86, &BbpValue);
2970 ASSERT((BbpValue == 0x00));
2971 if ((BbpValue != 0x00))
2972 {
2973 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x00);
2974 }
2975
2976 // 5.5GHz band selection PIN, bit1 and bit2 are complement
2977 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
2978 Value &= (~0x6);
2979 Value |= (0x04);
2980 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
2981
2982 // Turn off unused PA or LNA when only 1T or 1R.
2983 if (pAd->Antenna.field.TxPath == 1)
2984 {
2985 TxPinCfg &= 0xFFFFFFF3;
2986 }
2987 if (pAd->Antenna.field.RxPath == 1)
2988 {
2989 TxPinCfg &= 0xFFFFF3FF;
2990 }
2991
2992 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
2993 }
2994 else
2995 {
2996 ULONG TxPinCfg = 0x00050F05;//2007.10.09 by Brian : 0x00050505 ==> 0x00050F05
2997
2998 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
2999 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
3000 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
3001 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
3002
3003 // According the Rory's suggestion to solve the middle range issue.
3004 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R86, &BbpValue);
3005 ASSERT((BbpValue == 0x00));
3006 if ((BbpValue != 0x00))
3007 {
3008 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x00);
3009 }
3010 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
3011 ASSERT((BbpValue == 0x04));
3012
3013 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R92, &BbpValue);
3014 ASSERT((BbpValue == 0x00));
3015
3016 // 5.5GHz band selection PIN, bit1 and bit2 are complement
3017 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
3018 Value &= (~0x6);
3019 Value |= (0x02);
3020 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
3021
3022 // Turn off unused PA or LNA when only 1T or 1R.
3023 if (pAd->Antenna.field.TxPath == 1)
3024 {
3025 TxPinCfg &= 0xFFFFFFF3;
3026 }
3027 if (pAd->Antenna.field.RxPath == 1)
3028 {
3029 TxPinCfg &= 0xFFFFF3FF;
3030 }
3031
3032 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
3033 }
3034
3035 // R66 should be set according to Channel and use 20MHz when scanning
3036 if (Channel <= 14)
3037 {
3038 // BG band
3039 R66 = 0x2E + GET_LNA_GAIN(pAd);
3040 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
3041 }
3042 else
3043 {
3044 // 5.5 GHz band
3045 if (pAd->ate.TxWI.BW == BW_20)
3046 {
3047 R66 = (UCHAR)(0x32 + (GET_LNA_GAIN(pAd)*5)/3);
3048 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
3049 }
3050 else
3051 {
3052 R66 = (UCHAR)(0x3A + (GET_LNA_GAIN(pAd)*5)/3);
3053 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
3054 }
3055 }
3056
3057 //
3058 // On 11A, We should delay and wait RF/BBP to be stable
3059 // and the appropriate time should be 1000 micro seconds
3060 // 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
3061 //
3062 RTMPusecDelay(1000);
3063
3064 if (Channel > 14)
3065 {
3066 // When 5.5GHz band the LSB of TxPwr will be used to reduced 7dB or not.
3067 ATEDBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
3068 Channel,
3069 pAd->RfIcType,
3070 pAd->Antenna.field.TxPath,
3071 pAd->LatchRfRegs.R1,
3072 pAd->LatchRfRegs.R2,
3073 pAd->LatchRfRegs.R3,
3074 pAd->LatchRfRegs.R4));
3075 }
3076 else
3077 {
3078 ATEDBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
3079 Channel,
3080 pAd->RfIcType,
3081 (R3 & 0x00003e00) >> 9,
3082 (R4 & 0x000007c0) >> 6,
3083 pAd->Antenna.field.TxPath,
3084 pAd->LatchRfRegs.R1,
3085 pAd->LatchRfRegs.R2,
3086 pAd->LatchRfRegs.R3,
3087 pAd->LatchRfRegs.R4));
3088 }
3089 }
3090
3091 //
3092 // In fact, no one will call this routine so far !
3093 //
3094 /*
3095 ==========================================================================
3096 Description:
3097 Gives CCK TX rate 2 more dB TX power.
3098 This routine works only in ATE mode.
3099
3100 calculate desired Tx power in RF R3.Tx0~5, should consider -
3101 0. if current radio is a noisy environment (pAd->DrsCounters.fNoisyEnvironment)
3102 1. TxPowerPercentage
3103 2. auto calibration based on TSSI feedback
3104 3. extra 2 db for CCK
3105 4. -10 db upon very-short distance (AvgRSSI >= -40db) to AP
3106
3107 NOTE: Since this routine requires the value of (pAd->DrsCounters.fNoisyEnvironment),
3108 it should be called AFTER MlmeDynamicTxRateSwitching()
3109 ==========================================================================
3110 */
3111 VOID ATEAsicAdjustTxPower(
3112 IN PRTMP_ADAPTER pAd)
3113 {
3114 INT i, j;
3115 CHAR DeltaPwr = 0;
3116 BOOLEAN bAutoTxAgc = FALSE;
3117 UCHAR TssiRef, *pTssiMinusBoundary, *pTssiPlusBoundary, TxAgcStep;
3118 UCHAR BbpR49 = 0, idx;
3119 PCHAR pTxAgcCompensate;
3120 ULONG TxPwr[5];
3121 CHAR Value;
3122
3123 /* no one calls this procedure so far */
3124 if (pAd->ate.TxWI.BW == BW_40)
3125 {
3126 if (pAd->ate.Channel > 14)
3127 {
3128 TxPwr[0] = pAd->Tx40MPwrCfgABand[0];
3129 TxPwr[1] = pAd->Tx40MPwrCfgABand[1];
3130 TxPwr[2] = pAd->Tx40MPwrCfgABand[2];
3131 TxPwr[3] = pAd->Tx40MPwrCfgABand[3];
3132 TxPwr[4] = pAd->Tx40MPwrCfgABand[4];
3133 }
3134 else
3135 {
3136 TxPwr[0] = pAd->Tx40MPwrCfgGBand[0];
3137 TxPwr[1] = pAd->Tx40MPwrCfgGBand[1];
3138 TxPwr[2] = pAd->Tx40MPwrCfgGBand[2];
3139 TxPwr[3] = pAd->Tx40MPwrCfgGBand[3];
3140 TxPwr[4] = pAd->Tx40MPwrCfgGBand[4];
3141 }
3142 }
3143 else
3144 {
3145 if (pAd->ate.Channel > 14)
3146 {
3147 TxPwr[0] = pAd->Tx20MPwrCfgABand[0];
3148 TxPwr[1] = pAd->Tx20MPwrCfgABand[1];
3149 TxPwr[2] = pAd->Tx20MPwrCfgABand[2];
3150 TxPwr[3] = pAd->Tx20MPwrCfgABand[3];
3151 TxPwr[4] = pAd->Tx20MPwrCfgABand[4];
3152 }
3153 else
3154 {
3155 TxPwr[0] = pAd->Tx20MPwrCfgGBand[0];
3156 TxPwr[1] = pAd->Tx20MPwrCfgGBand[1];
3157 TxPwr[2] = pAd->Tx20MPwrCfgGBand[2];
3158 TxPwr[3] = pAd->Tx20MPwrCfgGBand[3];
3159 TxPwr[4] = pAd->Tx20MPwrCfgGBand[4];
3160 }
3161 }
3162
3163 // TX power compensation for temperature variation based on TSSI.
3164 // Do it per 4 seconds.
3165 if (pAd->Mlme.OneSecPeriodicRound % 4 == 0)
3166 {
3167 if (pAd->ate.Channel <= 14)
3168 {
3169 /* bg channel */
3170 bAutoTxAgc = pAd->bAutoTxAgcG;
3171 TssiRef = pAd->TssiRefG;
3172 pTssiMinusBoundary = &pAd->TssiMinusBoundaryG[0];
3173 pTssiPlusBoundary = &pAd->TssiPlusBoundaryG[0];
3174 TxAgcStep = pAd->TxAgcStepG;
3175 pTxAgcCompensate = &pAd->TxAgcCompensateG;
3176 }
3177 else
3178 {
3179 /* a channel */
3180 bAutoTxAgc = pAd->bAutoTxAgcA;
3181 TssiRef = pAd->TssiRefA;
3182 pTssiMinusBoundary = &pAd->TssiMinusBoundaryA[0];
3183 pTssiPlusBoundary = &pAd->TssiPlusBoundaryA[0];
3184 TxAgcStep = pAd->TxAgcStepA;
3185 pTxAgcCompensate = &pAd->TxAgcCompensateA;
3186 }
3187
3188 if (bAutoTxAgc)
3189 {
3190 /* BbpR49 is unsigned char */
3191 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49);
3192
3193 /* (p) TssiPlusBoundaryG[0] = 0 = (m) TssiMinusBoundaryG[0] */
3194 /* compensate: +4 +3 +2 +1 0 -1 -2 -3 -4 * steps */
3195 /* step value is defined in pAd->TxAgcStepG for tx power value */
3196
3197 /* [4]+1+[4] p4 p3 p2 p1 o1 m1 m2 m3 m4 */
3198 /* ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
3199 above value are examined in mass factory production */
3200 /* [4] [3] [2] [1] [0] [1] [2] [3] [4] */
3201
3202 /* plus is 0x10 ~ 0x40, minus is 0x60 ~ 0x90 */
3203 /* if value is between p1 ~ o1 or o1 ~ s1, no need to adjust tx power */
3204 /* if value is 0x65, tx power will be -= TxAgcStep*(2-1) */
3205
3206 if (BbpR49 > pTssiMinusBoundary[1])
3207 {
3208 // Reading is larger than the reference value.
3209 // Check for how large we need to decrease the Tx power.
3210 for (idx = 1; idx < 5; idx++)
3211 {
3212 if (BbpR49 <= pTssiMinusBoundary[idx]) // Found the range
3213 break;
3214 }
3215 // The index is the step we should decrease, idx = 0 means there is nothing to compensate
3216 // if (R3 > (ULONG) (TxAgcStep * (idx-1)))
3217 *pTxAgcCompensate = -(TxAgcStep * (idx-1));
3218 // else
3219 // *pTxAgcCompensate = -((UCHAR)R3);
3220
3221 DeltaPwr += (*pTxAgcCompensate);
3222 ATEDBGPRINT(RT_DEBUG_TRACE, ("-- Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = -%d\n",
3223 BbpR49, TssiRef, TxAgcStep, idx-1));
3224 }
3225 else if (BbpR49 < pTssiPlusBoundary[1])
3226 {
3227 // Reading is smaller than the reference value
3228 // check for how large we need to increase the Tx power
3229 for (idx = 1; idx < 5; idx++)
3230 {
3231 if (BbpR49 >= pTssiPlusBoundary[idx]) // Found the range
3232 break;
3233 }
3234 // The index is the step we should increase, idx = 0 means there is nothing to compensate
3235 *pTxAgcCompensate = TxAgcStep * (idx-1);
3236 DeltaPwr += (*pTxAgcCompensate);
3237 ATEDBGPRINT(RT_DEBUG_TRACE, ("++ Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
3238 BbpR49, TssiRef, TxAgcStep, idx-1));
3239 }
3240 else
3241 {
3242 *pTxAgcCompensate = 0;
3243 ATEDBGPRINT(RT_DEBUG_TRACE, (" Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
3244 BbpR49, TssiRef, TxAgcStep, 0));
3245 }
3246 }
3247 }
3248 else
3249 {
3250 if (pAd->ate.Channel <= 14)
3251 {
3252 bAutoTxAgc = pAd->bAutoTxAgcG;
3253 pTxAgcCompensate = &pAd->TxAgcCompensateG;
3254 }
3255 else
3256 {
3257 bAutoTxAgc = pAd->bAutoTxAgcA;
3258 pTxAgcCompensate = &pAd->TxAgcCompensateA;
3259 }
3260
3261 if (bAutoTxAgc)
3262 DeltaPwr += (*pTxAgcCompensate);
3263 }
3264
3265 /* calculate delta power based on the percentage specified from UI */
3266 // E2PROM setting is calibrated for maximum TX power (i.e. 100%)
3267 // We lower TX power here according to the percentage specified from UI
3268 if (pAd->CommonCfg.TxPowerPercentage == 0xffffffff) // AUTO TX POWER control
3269 ;
3270 else if (pAd->CommonCfg.TxPowerPercentage > 90) // 91 ~ 100% & AUTO, treat as 100% in terms of mW
3271 ;
3272 else if (pAd->CommonCfg.TxPowerPercentage > 60) // 61 ~ 90%, treat as 75% in terms of mW
3273 {
3274 DeltaPwr -= 1;
3275 }
3276 else if (pAd->CommonCfg.TxPowerPercentage > 30) // 31 ~ 60%, treat as 50% in terms of mW
3277 {
3278 DeltaPwr -= 3;
3279 }
3280 else if (pAd->CommonCfg.TxPowerPercentage > 15) // 16 ~ 30%, treat as 25% in terms of mW
3281 {
3282 DeltaPwr -= 6;
3283 }
3284 else if (pAd->CommonCfg.TxPowerPercentage > 9) // 10 ~ 15%, treat as 12.5% in terms of mW
3285 {
3286 DeltaPwr -= 9;
3287 }
3288 else // 0 ~ 9 %, treat as MIN(~3%) in terms of mW
3289 {
3290 DeltaPwr -= 12;
3291 }
3292
3293 /* reset different new tx power for different TX rate */
3294 for(i=0; i<5; i++)
3295 {
3296 if (TxPwr[i] != 0xffffffff)
3297 {
3298 for (j=0; j<8; j++)
3299 {
3300 Value = (CHAR)((TxPwr[i] >> j*4) & 0x0F); /* 0 ~ 15 */
3301
3302 if ((Value + DeltaPwr) < 0)
3303 {
3304 Value = 0; /* min */
3305 }
3306 else if ((Value + DeltaPwr) > 0xF)
3307 {
3308 Value = 0xF; /* max */
3309 }
3310 else
3311 {
3312 Value += DeltaPwr; /* temperature compensation */
3313 }
3314
3315 /* fill new value to CSR offset */
3316 TxPwr[i] = (TxPwr[i] & ~(0x0000000F << j*4)) | (Value << j*4);
3317 }
3318
3319 /* write tx power value to CSR */
3320 /* TX_PWR_CFG_0 (8 tx rate) for TX power for OFDM 12M/18M
3321 TX power for OFDM 6M/9M
3322 TX power for CCK5.5M/11M
3323 TX power for CCK1M/2M */
3324 /* TX_PWR_CFG_1 ~ TX_PWR_CFG_4 */
3325 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, TxPwr[i]);
3326
3327
3328 }
3329 }
3330
3331 }
3332
3333 /*
3334 ========================================================================
3335 Routine Description:
3336 Write TxWI for ATE mode.
3337
3338 Return Value:
3339 None
3340 ========================================================================
3341 */
3342
3343 #ifdef RT2870
3344 static VOID ATEWriteTxWI(
3345 IN PRTMP_ADAPTER pAd,
3346 IN PTXWI_STRUC pTxWI,
3347 IN BOOLEAN FRAG,
3348 IN BOOLEAN InsTimestamp,
3349 IN BOOLEAN AMPDU,
3350 IN BOOLEAN Ack,
3351 IN BOOLEAN NSeq, // HW new a sequence.
3352 IN UCHAR BASize,
3353 IN UCHAR WCID,
3354 IN ULONG Length,
3355 IN UCHAR PID,
3356 IN UCHAR MIMOps,
3357 IN UCHAR Txopmode,
3358 IN BOOLEAN CfAck,
3359 IN HTTRANSMIT_SETTING Transmit)
3360 {
3361 //
3362 // Always use Long preamble before verifiation short preamble functionality works well.
3363 // Todo: remove the following line if short preamble functionality works
3364 //
3365 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
3366 pTxWI->FRAG= FRAG;
3367 pTxWI->TS= InsTimestamp;
3368 pTxWI->AMPDU = AMPDU;
3369
3370 pTxWI->MIMOps = PWR_ACTIVE;
3371 pTxWI->MpduDensity = 4;
3372 pTxWI->ACK = Ack;
3373 pTxWI->txop = Txopmode;
3374 pTxWI->NSEQ = NSeq;
3375 pTxWI->BAWinSize = BASize;
3376
3377 pTxWI->WirelessCliID = WCID;
3378 pTxWI->MPDUtotalByteCount = Length;
3379 pTxWI->PacketId = PID;
3380
3381 pTxWI->BW = Transmit.field.BW;
3382 pTxWI->ShortGI = Transmit.field.ShortGI;
3383 pTxWI->STBC= Transmit.field.STBC;
3384
3385 pTxWI->MCS = Transmit.field.MCS;
3386 pTxWI->PHYMODE= Transmit.field.MODE;
3387
3388 #ifdef DOT11_N_SUPPORT
3389 //
3390 // MMPS is 802.11n features. Because TxWI->MCS > 7 must be HT mode,
3391 // so need not check if it's HT rate.
3392 //
3393 if ((MIMOps == MMPS_STATIC) && (pTxWI->MCS > 7))
3394 pTxWI->MCS = 7;
3395
3396 if ((MIMOps == MMPS_DYNAMIC) && (pTxWI->MCS > 7)) // SMPS protect 2 spatial.
3397 pTxWI->MIMOps = 1;
3398 #endif // DOT11_N_SUPPORT //
3399
3400 pTxWI->CFACK = CfAck;
3401
3402 return;
3403 }
3404 #endif // RT2870 //
3405 /*
3406 ========================================================================
3407
3408 Routine Description:
3409 Disable protection for ATE.
3410 ========================================================================
3411 */
3412 VOID ATEDisableAsicProtect(
3413 IN PRTMP_ADAPTER pAd)
3414 {
3415 PROT_CFG_STRUC ProtCfg, ProtCfg4;
3416 UINT32 Protect[6];
3417 USHORT offset;
3418 UCHAR i;
3419 UINT32 MacReg = 0;
3420
3421 // Config ASIC RTS threshold register
3422 RTMP_IO_READ32(pAd, TX_RTS_CFG, &MacReg);
3423 MacReg &= 0xFF0000FF;
3424 MacReg |= (pAd->CommonCfg.RtsThreshold << 8);
3425 RTMP_IO_WRITE32(pAd, TX_RTS_CFG, MacReg);
3426
3427 // Initial common protection settings
3428 RTMPZeroMemory(Protect, sizeof(Protect));
3429 ProtCfg4.word = 0;
3430 ProtCfg.word = 0;
3431 ProtCfg.field.TxopAllowGF40 = 1;
3432 ProtCfg.field.TxopAllowGF20 = 1;
3433 ProtCfg.field.TxopAllowMM40 = 1;
3434 ProtCfg.field.TxopAllowMM20 = 1;
3435 ProtCfg.field.TxopAllowOfdm = 1;
3436 ProtCfg.field.TxopAllowCck = 1;
3437 ProtCfg.field.RTSThEn = 1;
3438 ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
3439
3440 // Handle legacy(B/G) protection
3441 ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate;
3442 ProtCfg.field.ProtectCtrl = 0;
3443 Protect[0] = ProtCfg.word;
3444 Protect[1] = ProtCfg.word;
3445
3446 // NO PROTECT
3447 // 1.All STAs in the BSS are 20/40 MHz HT
3448 // 2. in ai 20/40MHz BSS
3449 // 3. all STAs are 20MHz in a 20MHz BSS
3450 // Pure HT. no protection.
3451
3452 // MM20_PROT_CFG
3453 // Reserved (31:27)
3454 // PROT_TXOP(25:20) -- 010111
3455 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3456 // PROT_CTRL(17:16) -- 00 (None)
3457 // PROT_RATE(15:0) -- 0x4004 (OFDM 24M)
3458 Protect[2] = 0x01744004;
3459
3460 // MM40_PROT_CFG
3461 // Reserved (31:27)
3462 // PROT_TXOP(25:20) -- 111111
3463 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3464 // PROT_CTRL(17:16) -- 00 (None)
3465 // PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M)
3466 Protect[3] = 0x03f44084;
3467
3468 // CF20_PROT_CFG
3469 // Reserved (31:27)
3470 // PROT_TXOP(25:20) -- 010111
3471 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3472 // PROT_CTRL(17:16) -- 00 (None)
3473 // PROT_RATE(15:0) -- 0x4004 (OFDM 24M)
3474 Protect[4] = 0x01744004;
3475
3476 // CF40_PROT_CFG
3477 // Reserved (31:27)
3478 // PROT_TXOP(25:20) -- 111111
3479 // PROT_NAV(19:18) -- 01 (Short NAV protection)
3480 // PROT_CTRL(17:16) -- 00 (None)
3481 // PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M)
3482 Protect[5] = 0x03f44084;
3483
3484 pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE;
3485
3486 offset = CCK_PROT_CFG;
3487 for (i = 0;i < 6;i++)
3488 RTMP_IO_WRITE32(pAd, offset + i*4, Protect[i]);
3489
3490 }
3491
3492 #ifdef RT2870
3493 /*
3494 ========================================================================
3495 Routine Description:
3496 Write TxInfo for ATE mode.
3497
3498 Return Value:
3499 None
3500 ========================================================================
3501 */
3502 static VOID ATEWriteTxInfo(
3503 IN PRTMP_ADAPTER pAd,
3504 IN PTXINFO_STRUC pTxInfo,
3505 IN USHORT USBDMApktLen,
3506 IN BOOLEAN bWiv,
3507 IN UCHAR QueueSel,
3508 IN UCHAR NextValid,
3509 IN UCHAR TxBurst)
3510 {
3511 pTxInfo->USBDMATxPktLen = USBDMApktLen;
3512 pTxInfo->QSEL = QueueSel;
3513
3514 if (QueueSel != FIFO_EDCA)
3515 ATEDBGPRINT(RT_DEBUG_TRACE, ("=======> QueueSel != FIFO_EDCA<=======\n"));
3516
3517 pTxInfo->USBDMANextVLD = NextValid;
3518 pTxInfo->USBDMATxburst = TxBurst;
3519 pTxInfo->WIV = bWiv;
3520 pTxInfo->SwUseLastRound = 0;
3521 pTxInfo->rsv = 0;
3522 pTxInfo->rsv2 = 0;
3523
3524 return;
3525 }
3526 #endif // RT2870 //
3527
3528 /* There are two ways to convert Rssi */
3529 #if 1
3530 //
3531 // The way used with GET_LNA_GAIN().
3532 //
3533 CHAR ATEConvertToRssi(
3534 IN PRTMP_ADAPTER pAd,
3535 IN CHAR Rssi,
3536 IN UCHAR RssiNumber)
3537 {
3538 UCHAR RssiOffset, LNAGain;
3539
3540 // Rssi equals to zero should be an invalid value
3541 if (Rssi == 0)
3542 return -99;
3543
3544 LNAGain = GET_LNA_GAIN(pAd);
3545 if (pAd->LatchRfRegs.Channel > 14)
3546 {
3547 if (RssiNumber == 0)
3548 RssiOffset = pAd->ARssiOffset0;
3549 else if (RssiNumber == 1)
3550 RssiOffset = pAd->ARssiOffset1;
3551 else
3552 RssiOffset = pAd->ARssiOffset2;
3553 }
3554 else
3555 {
3556 if (RssiNumber == 0)
3557 RssiOffset = pAd->BGRssiOffset0;
3558 else if (RssiNumber == 1)
3559 RssiOffset = pAd->BGRssiOffset1;
3560 else
3561 RssiOffset = pAd->BGRssiOffset2;
3562 }
3563
3564 return (-12 - RssiOffset - LNAGain - Rssi);
3565 }
3566 #else
3567 //
3568 // The way originally used in ATE of rt2860ap.
3569 //
3570 CHAR ATEConvertToRssi(
3571 IN PRTMP_ADAPTER pAd,
3572 IN CHAR Rssi,
3573 IN UCHAR RssiNumber)
3574 {
3575 UCHAR RssiOffset, LNAGain;
3576
3577 // Rssi equals to zero should be an invalid value
3578 if (Rssi == 0)
3579 return -99;
3580
3581 if (pAd->LatchRfRegs.Channel > 14)
3582 {
3583 LNAGain = pAd->ALNAGain;
3584 if (RssiNumber == 0)
3585 RssiOffset = pAd->ARssiOffset0;
3586 else if (RssiNumber == 1)
3587 RssiOffset = pAd->ARssiOffset1;
3588 else
3589 RssiOffset = pAd->ARssiOffset2;
3590 }
3591 else
3592 {
3593 LNAGain = pAd->BLNAGain;
3594 if (RssiNumber == 0)
3595 RssiOffset = pAd->BGRssiOffset0;
3596 else if (RssiNumber == 1)
3597 RssiOffset = pAd->BGRssiOffset1;
3598 else
3599 RssiOffset = pAd->BGRssiOffset2;
3600 }
3601
3602 return (-32 - RssiOffset + LNAGain - Rssi);
3603 }
3604 #endif /* end of #if 1 */
3605
3606 /*
3607 ========================================================================
3608
3609 Routine Description:
3610 Set Japan filter coefficients if needed.
3611 Note:
3612 This routine should only be called when
3613 entering TXFRAME mode or TXCONT mode.
3614
3615 ========================================================================
3616 */
3617 static VOID SetJapanFilter(
3618 IN PRTMP_ADAPTER pAd)
3619 {
3620 UCHAR BbpData = 0;
3621
3622 //
3623 // If Channel=14 and Bandwidth=20M and Mode=CCK, set BBP R4 bit5=1
3624 // (Japan Tx filter coefficients)when (TXFRAME or TXCONT).
3625 //
3626 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BbpData);
3627
3628 if ((pAd->ate.TxWI.PHYMODE == MODE_CCK) && (pAd->ate.Channel == 14) && (pAd->ate.TxWI.BW == BW_20))
3629 {
3630 BbpData |= 0x20; // turn on
3631 ATEDBGPRINT(RT_DEBUG_TRACE, ("SetJapanFilter!!!\n"));
3632 }
3633 else
3634 {
3635 BbpData &= 0xdf; // turn off
3636 ATEDBGPRINT(RT_DEBUG_TRACE, ("ClearJapanFilter!!!\n"));
3637 }
3638
3639 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BbpData);
3640 }
3641
3642 VOID ATESampleRssi(
3643 IN PRTMP_ADAPTER pAd,
3644 IN PRXWI_STRUC pRxWI)
3645 {
3646 /* There are two ways to collect RSSI. */
3647 #if 1
3648 //pAd->LastRxRate = (USHORT)((pRxWI->MCS) + (pRxWI->BW <<7) + (pRxWI->ShortGI <<8)+ (pRxWI->PHYMODE <<14)) ;
3649 if (pRxWI->RSSI0 != 0)
3650 {
3651 pAd->ate.LastRssi0 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI0, RSSI_0);
3652 pAd->ate.AvgRssi0X8 = (pAd->ate.AvgRssi0X8 - pAd->ate.AvgRssi0) + pAd->ate.LastRssi0;
3653 pAd->ate.AvgRssi0 = pAd->ate.AvgRssi0X8 >> 3;
3654 }
3655 if (pRxWI->RSSI1 != 0)
3656 {
3657 pAd->ate.LastRssi1 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI1, RSSI_1);
3658 pAd->ate.AvgRssi1X8 = (pAd->ate.AvgRssi1X8 - pAd->ate.AvgRssi1) + pAd->ate.LastRssi1;
3659 pAd->ate.AvgRssi1 = pAd->ate.AvgRssi1X8 >> 3;
3660 }
3661 if (pRxWI->RSSI2 != 0)
3662 {
3663 pAd->ate.LastRssi2 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI2, RSSI_2);
3664 pAd->ate.AvgRssi2X8 = (pAd->ate.AvgRssi2X8 - pAd->ate.AvgRssi2) + pAd->ate.LastRssi2;
3665 pAd->ate.AvgRssi2 = pAd->ate.AvgRssi2X8 >> 3;
3666 }
3667
3668 pAd->ate.LastSNR0 = (CHAR)(pRxWI->SNR0);// CHAR ==> UCHAR ?
3669 pAd->ate.LastSNR1 = (CHAR)(pRxWI->SNR1);// CHAR ==> UCHAR ?
3670
3671 pAd->ate.NumOfAvgRssiSample ++;
3672 #else
3673 pAd->ate.LastSNR0 = (CHAR)(pRxWI->SNR0);
3674 pAd->ate.LastSNR1 = (CHAR)(pRxWI->SNR1);
3675 pAd->ate.RxCntPerSec++;
3676 pAd->ate.LastRssi0 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI0, RSSI_0);
3677 pAd->ate.LastRssi1 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI1, RSSI_1);
3678 pAd->ate.LastRssi2 = ATEConvertToRssi(pAd, (CHAR) pRxWI->RSSI2, RSSI_2);
3679 pAd->ate.AvgRssi0X8 = (pAd->ate.AvgRssi0X8 - pAd->ate.AvgRssi0) + pAd->ate.LastRssi0;
3680 pAd->ate.AvgRssi0 = pAd->ate.AvgRssi0X8 >> 3;
3681 pAd->ate.AvgRssi1X8 = (pAd->ate.AvgRssi1X8 - pAd->ate.AvgRssi1) + pAd->ate.LastRssi1;
3682 pAd->ate.AvgRssi1 = pAd->ate.AvgRssi1X8 >> 3;
3683 pAd->ate.AvgRssi2X8 = (pAd->ate.AvgRssi2X8 - pAd->ate.AvgRssi2) + pAd->ate.LastRssi2;
3684 pAd->ate.AvgRssi2 = pAd->ate.AvgRssi2X8 >> 3;
3685 pAd->ate.NumOfAvgRssiSample ++;
3686 #endif
3687 }
3688
3689 #ifdef CONFIG_STA_SUPPORT
3690 VOID RTMPStationStop(
3691 IN PRTMP_ADAPTER pAd)
3692 {
3693 // BOOLEAN Cancelled;
3694
3695 ATEDBGPRINT(RT_DEBUG_TRACE, ("==> RTMPStationStop\n"));
3696
3697 // For rx statistics, we need to keep this timer running.
3698 // RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled);
3699
3700 ATEDBGPRINT(RT_DEBUG_TRACE, ("<== RTMPStationStop\n"));
3701 }
3702
3703 VOID RTMPStationStart(
3704 IN PRTMP_ADAPTER pAd)
3705 {
3706 ATEDBGPRINT(RT_DEBUG_TRACE, ("==> RTMPStationStart\n"));
3707 ATEDBGPRINT(RT_DEBUG_TRACE, ("<== RTMPStationStart\n"));
3708 }
3709 #endif // CONFIG_STA_SUPPORT //
3710
3711 /*
3712 ==========================================================================
3713 Description:
3714 Setup Frame format.
3715 NOTE:
3716 This routine should only be used in ATE mode.
3717 ==========================================================================
3718 */
3719
3720 #ifdef RT2870
3721 /*======================Start of RT2870======================*/
3722 /* */
3723 /* */
3724 static INT ATESetUpFrame(
3725 IN PRTMP_ADAPTER pAd,
3726 IN UINT32 TxIdx)
3727 {
3728 UINT j;
3729 PTX_CONTEXT pNullContext;
3730 PUCHAR pDest;
3731 HTTRANSMIT_SETTING TxHTPhyMode;
3732 PTXWI_STRUC pTxWI;
3733 PTXINFO_STRUC pTxInfo;
3734 UINT32 TransferBufferLength, OrgBufferLength = 0;
3735 UCHAR padLen = 0;
3736 #ifdef RALINK_28xx_QA
3737 PHEADER_802_11 pHeader80211 = NULL;
3738 #endif // RALINK_28xx_QA //
3739
3740 if ((RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) ||
3741 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)) ||
3742 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) ||
3743 (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
3744 {
3745 return -1;
3746 }
3747
3748 /* We always use QID_AC_BE and FIFO_EDCA in ATE mode. */
3749
3750 pNullContext = &(pAd->NullContext);
3751 ASSERT(pNullContext != NULL);
3752
3753 if (pNullContext->InUse == FALSE)
3754 {
3755 // Set the in use bit
3756 pNullContext->InUse = TRUE;
3757 NdisZeroMemory(&(pAd->NullFrame), sizeof(HEADER_802_11));
3758
3759 // Fill 802.11 header.
3760 #ifdef RALINK_28xx_QA
3761 if (pAd->ate.bQATxStart == TRUE)
3762 {
3763 pHeader80211 = NdisMoveMemory(&(pAd->NullFrame), pAd->ate.Header, pAd->ate.HLen);
3764 // pDest = NdisMoveMemory(&(pAd->NullFrame), pAd->ate.Header, pAd->ate.HLen);
3765 // pHeader80211 = (PHEADER_802_11)pDest;
3766 }
3767 else
3768 #endif // RALINK_28xx_QA //
3769 {
3770 // Fill 802.11 header.
3771 NdisMoveMemory(&(pAd->NullFrame), TemplateFrame, sizeof(HEADER_802_11));
3772 }
3773 #ifdef RT_BIG_ENDIAN
3774 RTMPFrameEndianChange(pAd, (PUCHAR)&(pAd->NullFrame), DIR_READ, FALSE);
3775 #endif // RT_BIG_ENDIAN //
3776
3777 #ifdef RALINK_28xx_QA
3778 if (pAd->ate.bQATxStart == TRUE)
3779 {
3780 /* modify sequence number.... */
3781 if (pAd->ate.TxDoneCount == 0)
3782 {
3783 pAd->ate.seq = pHeader80211->Sequence;
3784 }
3785 else
3786 {
3787 pHeader80211->Sequence = ++pAd->ate.seq;
3788 }
3789 /* We already got all the addr. fields from QA GUI. */
3790 }
3791 else
3792 #endif // RALINK_28xx_QA //
3793 {
3794 COPY_MAC_ADDR(pAd->NullFrame.Addr1, pAd->ate.Addr1);
3795 COPY_MAC_ADDR(pAd->NullFrame.Addr2, pAd->ate.Addr2);
3796 COPY_MAC_ADDR(pAd->NullFrame.Addr3, pAd->ate.Addr3);
3797 }
3798
3799 RTMPZeroMemory(&pAd->NullContext.TransferBuffer->field.WirelessPacket[0], TX_BUFFER_NORMSIZE);//???
3800 pTxInfo = (PTXINFO_STRUC)&pAd->NullContext.TransferBuffer->field.WirelessPacket[0];
3801
3802 #ifdef RALINK_28xx_QA
3803 if (pAd->ate.bQATxStart == TRUE)
3804 {
3805 // Avoid to exceed the range of WirelessPacket[].
3806 ASSERT(pAd->ate.TxInfo.USBDMATxPktLen <= (MAX_FRAME_SIZE - 34/* == 2312 */));
3807 NdisMoveMemory(pTxInfo, &(pAd->ate.TxInfo), sizeof(pAd->ate.TxInfo));
3808 }
3809 else
3810 #endif // RALINK_28xx_QA //
3811 {
3812 // Avoid to exceed the range of WirelessPacket[].
3813 ASSERT(pAd->ate.TxLength <= (MAX_FRAME_SIZE - 34/* == 2312 */));
3814
3815 // pTxInfo->USBDMATxPktLen will be updated to include padding later.
3816 ATEWriteTxInfo(pAd, pTxInfo, (USHORT)(TXWI_SIZE + pAd->ate.TxLength), TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
3817 pTxInfo->QSEL = FIFO_EDCA;
3818 }
3819
3820 pTxWI = (PTXWI_STRUC)&pAd->NullContext.TransferBuffer->field.WirelessPacket[TXINFO_SIZE];
3821
3822 // Fill TxWI.
3823 if (pAd->ate.bQATxStart == TRUE)
3824 {
3825 TxHTPhyMode.field.BW = pAd->ate.TxWI.BW;
3826 TxHTPhyMode.field.ShortGI = pAd->ate.TxWI.ShortGI;
3827 TxHTPhyMode.field.STBC = pAd->ate.TxWI.STBC;
3828 TxHTPhyMode.field.MCS = pAd->ate.TxWI.MCS;
3829 TxHTPhyMode.field.MODE = pAd->ate.TxWI.PHYMODE;
3830 ATEWriteTxWI(pAd, pTxWI, pAd->ate.TxWI.FRAG, pAd->ate.TxWI.TS, pAd->ate.TxWI.AMPDU, pAd->ate.TxWI.ACK, pAd->ate.TxWI.NSEQ,
3831 pAd->ate.TxWI.BAWinSize, BSSID_WCID, pAd->ate.TxWI.MPDUtotalByteCount/* include 802.11 header */, pAd->ate.TxWI.PacketId, 0, pAd->ate.TxWI.txop/*IFS_HTTXOP*/, pAd->ate.TxWI.CFACK/*FALSE*/, TxHTPhyMode);
3832 }
3833 else
3834 {
3835 TxHTPhyMode.field.BW = pAd->ate.TxWI.BW;
3836 TxHTPhyMode.field.ShortGI = pAd->ate.TxWI.ShortGI;
3837 TxHTPhyMode.field.STBC = 0;
3838 TxHTPhyMode.field.MCS = pAd->ate.TxWI.MCS;
3839 TxHTPhyMode.field.MODE = pAd->ate.TxWI.PHYMODE;
3840
3841 ATEWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE/* No ack required. */, FALSE, 0, BSSID_WCID, pAd->ate.TxLength,
3842 0, 0, IFS_HTTXOP, FALSE, TxHTPhyMode);// "MMPS_STATIC" instead of "MMPS_DYNAMIC" ???
3843 }
3844
3845 RTMPMoveMemory(&pAd->NullContext.TransferBuffer->field.WirelessPacket[TXINFO_SIZE+TXWI_SIZE], &pAd->NullFrame, sizeof(HEADER_802_11));
3846
3847 pDest = &(pAd->NullContext.TransferBuffer->field.WirelessPacket[TXINFO_SIZE+TXWI_SIZE+sizeof(HEADER_802_11)]);
3848
3849 // Prepare frame payload
3850 #ifdef RALINK_28xx_QA
3851 if (pAd->ate.bQATxStart == TRUE)
3852 {
3853 // copy pattern
3854 if ((pAd->ate.PLen != 0))
3855 {
3856 for (j = 0; j < pAd->ate.DLen; j+=pAd->ate.PLen)
3857 {
3858 RTMPMoveMemory(pDest, pAd->ate.Pattern, pAd->ate.PLen);
3859 pDest += pAd->ate.PLen;
3860 }
3861 }
3862 TransferBufferLength = TXINFO_SIZE + TXWI_SIZE + pAd->ate.TxWI.MPDUtotalByteCount;
3863 }
3864 else
3865 #endif // RALINK_28xx_QA //
3866 {
3867 for (j = 0; j < (pAd->ate.TxLength - sizeof(HEADER_802_11)); j++)
3868 {
3869 *pDest = 0xA5;
3870 pDest += 1;
3871 }
3872 TransferBufferLength = TXINFO_SIZE + TXWI_SIZE + pAd->ate.TxLength;
3873 }
3874
3875 #if 1
3876 OrgBufferLength = TransferBufferLength;
3877 TransferBufferLength = (TransferBufferLength + 3) & (~3);
3878
3879 // Always add 4 extra bytes at every packet.
3880 padLen = TransferBufferLength - OrgBufferLength + 4;/* 4 == last packet padding */
3881 ASSERT((padLen <= (RTMP_PKT_TAIL_PADDING - 4/* 4 == MaxBulkOutsize alignment padding */)));
3882
3883 /* Now memzero all extra padding bytes. */
3884 NdisZeroMemory(pDest, padLen);
3885 pDest += padLen;
3886 #else
3887 if ((TransferBufferLength % 4) == 1)
3888 {
3889 NdisZeroMemory(pDest, 7);
3890 pDest += 7;
3891 TransferBufferLength += 3;
3892 }
3893 else if ((TransferBufferLength % 4) == 2)
3894 {
3895 NdisZeroMemory(pDest, 6);
3896 pDest += 6;
3897 TransferBufferLength += 2;
3898 }
3899 else if ((TransferBufferLength % 4) == 3)
3900 {
3901 NdisZeroMemory(pDest, 5);
3902 pDest += 5;
3903 TransferBufferLength += 1;
3904 }
3905 #endif // 1 //
3906
3907 // Update pTxInfo->USBDMATxPktLen to include padding.
3908 pTxInfo->USBDMATxPktLen = TransferBufferLength - TXINFO_SIZE;
3909
3910 TransferBufferLength += 4;
3911
3912 // If TransferBufferLength is multiple of 64, add extra 4 bytes again.
3913 if ((TransferBufferLength % pAd->BulkOutMaxPacketSize) == 0)
3914 {
3915 NdisZeroMemory(pDest, 4);
3916 TransferBufferLength += 4;
3917 }
3918
3919 // Fill out frame length information for global Bulk out arbitor
3920 pAd->NullContext.BulkOutSize = TransferBufferLength;
3921 }
3922 #ifdef RT_BIG_ENDIAN
3923 RTMPWIEndianChange((PUCHAR)pTxWI, TYPE_TXWI);
3924 RTMPFrameEndianChange(pAd, (((PUCHAR)pTxInfo)+TXWI_SIZE+TXINFO_SIZE), DIR_WRITE, FALSE);
3925 RTMPDescriptorEndianChange((PUCHAR)pTxInfo, TYPE_TXINFO);
3926 #endif // RT_BIG_ENDIAN //
3927 return 0;
3928 }
3929
3930 VOID ATE_RTUSBBulkOutDataPacketComplete(purbb_t pUrb, struct pt_regs *pt_regs)
3931 {
3932 PRTMP_ADAPTER pAd;
3933 PTX_CONTEXT pNullContext;
3934 UCHAR BulkOutPipeId;
3935 NTSTATUS Status;
3936 unsigned long IrqFlags;
3937 ULONG OldValue;
3938
3939 pNullContext = (PTX_CONTEXT)pUrb->context;
3940 pAd = pNullContext->pAd;
3941
3942
3943 // Reset Null frame context flags
3944 pNullContext->IRPPending = FALSE;
3945 pNullContext->InUse = FALSE;
3946 Status = pUrb->status;
3947
3948 // Store BulkOut PipeId
3949 BulkOutPipeId = pNullContext->BulkOutPipeId;
3950 pAd->BulkOutDataOneSecCount++;
3951
3952 if (Status == USB_ST_NOERROR)
3953 {
3954 #ifdef RALINK_28xx_QA
3955 if ((ATE_ON(pAd)) && (pAd->ate.bQATxStart == TRUE))
3956 {
3957 if (pAd->ate.QID == BulkOutPipeId)
3958 {
3959 // Let Rx can have a chance to break in during Tx process,
3960 // especially for loopback mode in QA ATE.
3961 // To trade off between tx performance and loopback mode integrity.
3962 /* Q : Now Rx is handled by tasklet, do we still need this delay ? */
3963 /* Ans : Even tasklet is used, Rx/Tx < 1 if we do not delay for a while right here. */
3964 RTMPusecDelay(500);
3965 pAd->ate.TxDoneCount++;
3966 pAd->RalinkCounters.KickTxCount++;
3967 ASSERT(pAd->ate.QID == 0);
3968 pAd->ate.TxAc0++;
3969 }
3970 }
3971 #endif // RALINK_28xx_QA //
3972 pAd->BulkOutComplete++;
3973
3974 pAd->Counters8023.GoodTransmits++;
3975
3976 /* Don't worry about the queue is empty or not. This function will check itself. */
3977 RTMPDeQueuePacket(pAd, TRUE, BulkOutPipeId, MAX_TX_PROCESS);
3978
3979 /* In 28xx, SendTxWaitQueue ==> TxSwQueue */
3980 /*
3981 if (pAd->SendTxWaitQueue[BulkOutPipeId].Number > 0)
3982 {
3983 RTMPDeQueuePacket(pAd, BulkOutPipeId);
3984 }
3985 */
3986 }
3987 else // STATUS_OTHER
3988 {
3989 pAd->BulkOutCompleteOther++;
3990
3991 ATEDBGPRINT(RT_DEBUG_ERROR, ("BulkOutDataPacket Failed STATUS_OTHER = 0x%x . \n", Status));
3992 ATEDBGPRINT(RT_DEBUG_ERROR, (">>BulkOutReq=0x%lx, BulkOutComplete=0x%lx\n", pAd->BulkOutReq, pAd->BulkOutComplete));
3993
3994 if ((!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) &&
3995 (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) &&
3996 (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) &&
3997 (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)))
3998 {
3999 RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET);
4000 /* In 28xx, RT_OID_USB_RESET_BULK_OUT ==> CMDTHREAD_RESET_BULK_OUT */
4001 RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT, NULL, 0);
4002 // Check
4003 BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
4004 pAd->BulkOutPending[BulkOutPipeId] = FALSE;
4005 pAd->bulkResetPipeid = BulkOutPipeId;
4006 BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
4007 return;
4008 }
4009 }
4010
4011
4012
4013 if (atomic_read(&pAd->BulkOutRemained) > 0)
4014 {
4015 atomic_dec(&pAd->BulkOutRemained);
4016 }
4017
4018 // 1st - Transmit Success
4019 OldValue = pAd->WlanCounters.TransmittedFragmentCount.u.LowPart;
4020 pAd->WlanCounters.TransmittedFragmentCount.u.LowPart++;
4021
4022 if (pAd->WlanCounters.TransmittedFragmentCount.u.LowPart < OldValue)
4023 {
4024 pAd->WlanCounters.TransmittedFragmentCount.u.HighPart++;
4025 }
4026
4027 if(((pAd->ContinBulkOut == TRUE ) ||(atomic_read(&pAd->BulkOutRemained) > 0)) && (pAd->ate.Mode & ATE_TXFRAME))
4028 {
4029 RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE);
4030 }
4031 else
4032 {
4033 RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE);
4034 #ifdef RALINK_28xx_QA
4035 pAd->ate.TxStatus = 0;
4036 #endif // RALINK_28xx_QA //
4037 }
4038
4039 BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
4040 pAd->BulkOutPending[BulkOutPipeId] = FALSE;
4041 BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
4042
4043 // Always call Bulk routine, even reset bulk.
4044 // The protection of rest bulk should be in BulkOut routine.
4045 RTUSBKickBulkOut(pAd);
4046 }
4047
4048 /*
4049 ========================================================================
4050
4051 Routine Description:
4052
4053 Arguments:
4054
4055 Return Value:
4056
4057 Note:
4058
4059 ========================================================================
4060 */
4061 VOID ATE_RTUSBBulkOutDataPacket(
4062 IN PRTMP_ADAPTER pAd,
4063 IN UCHAR BulkOutPipeId)
4064 {
4065 PTX_CONTEXT pNullContext = &(pAd->NullContext);
4066 PURB pUrb;
4067 int ret = 0;
4068 unsigned long IrqFlags;
4069
4070
4071 ASSERT(BulkOutPipeId == 0);
4072
4073 /* Build up the frame first. */
4074 // ATESetUpFrame(pAd, 0);
4075
4076 BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
4077
4078 if (pAd->BulkOutPending[BulkOutPipeId] == TRUE)
4079 {
4080 BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
4081 return;
4082 }
4083
4084 pAd->BulkOutPending[BulkOutPipeId] = TRUE;
4085 BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
4086
4087 // Increase Total transmit byte counter
4088 pAd->RalinkCounters.OneSecTransmittedByteCount += pNullContext->BulkOutSize;
4089 pAd->RalinkCounters.TransmittedByteCount += pNullContext->BulkOutSize;
4090
4091 // Clear ATE frame bulk out flag
4092 RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_ATE);
4093
4094 // Init Tx context descriptor
4095 pNullContext->IRPPending = TRUE;
4096 RTUSBInitTxDesc(pAd, pNullContext, BulkOutPipeId, (usb_complete_t)ATE_RTUSBBulkOutDataPacketComplete);
4097 pUrb = pNullContext->pUrb;
4098
4099 if((ret = RTUSB_SUBMIT_URB(pUrb))!=0)
4100 {
4101 ATEDBGPRINT(RT_DEBUG_ERROR, ("ATE_RTUSBBulkOutDataPacket: Submit Tx URB failed %d\n", ret));
4102 return;
4103 }
4104
4105 pAd->BulkOutReq++;
4106 return;
4107
4108 }
4109
4110 /*
4111 ========================================================================
4112
4113 Routine Description:
4114
4115 Arguments:
4116
4117 Return Value:
4118
4119 Note:
4120
4121 ========================================================================
4122 */
4123 VOID ATE_RTUSBCancelPendingBulkInIRP(
4124 IN PRTMP_ADAPTER pAd)
4125 {
4126 PRX_CONTEXT pRxContext;
4127 UINT i;
4128
4129 ATEDBGPRINT(RT_DEBUG_TRACE, ("--->ATE_RTUSBCancelPendingBulkInIRP\n"));
4130 #if 1
4131 for ( i = 0; i < (RX_RING_SIZE); i++)
4132 {
4133 pRxContext = &(pAd->RxContext[i]);
4134 if(pRxContext->IRPPending == TRUE)
4135 {
4136 RTUSB_UNLINK_URB(pRxContext->pUrb);
4137 pRxContext->IRPPending = FALSE;
4138 pRxContext->InUse = FALSE;
4139 //NdisInterlockedDecrement(&pAd->PendingRx);
4140 //pAd->PendingRx--;
4141 }
4142 }
4143 #else
4144 for ( i = 0; i < (RX_RING_SIZE); i++)
4145 {
4146 pRxContext = &(pAd->RxContext[i]);
4147 if(atomic_read(&pRxContext->IrpLock) == IRPLOCK_CANCELABLE)
4148 {
4149 RTUSB_UNLINK_URB(pRxContext->pUrb);
4150 }
4151 InterlockedExchange(&pRxContext->IrpLock, IRPLOCK_CANCE_START);
4152 }
4153 #endif // 1 //
4154 ATEDBGPRINT(RT_DEBUG_TRACE, ("<---ATE_RTUSBCancelPendingBulkInIRP\n"));
4155 return;
4156 }
4157 #endif // RT2870 //
4158
4159 VOID rt_ee_read_all(PRTMP_ADAPTER pAd, USHORT *Data)
4160 {
4161 USHORT i;
4162 USHORT value;
4163
4164 for (i = 0 ; i < EEPROM_SIZE/2 ; )
4165 {
4166 /* "value" is expecially for some compilers... */
4167 RT28xx_EEPROM_READ16(pAd, i*2, value);
4168 Data[i] = value;
4169 i++;
4170 }
4171 }
4172
4173 VOID rt_ee_write_all(PRTMP_ADAPTER pAd, USHORT *Data)
4174 {
4175 USHORT i;
4176 USHORT value;
4177
4178 for (i = 0 ; i < EEPROM_SIZE/2 ; )
4179 {
4180 /* "value" is expecially for some compilers... */
4181 value = Data[i];
4182 RT28xx_EEPROM_WRITE16(pAd, i*2, value);
4183 i ++;
4184 }
4185 }
4186 #ifdef RALINK_28xx_QA
4187 VOID ATE_QA_Statistics(
4188 IN PRTMP_ADAPTER pAd,
4189 IN PRXWI_STRUC pRxWI,
4190 IN PRT28XX_RXD_STRUC pRxD,
4191 IN PHEADER_802_11 pHeader)
4192 {
4193 // update counter first
4194 if (pHeader != NULL)
4195 {
4196 if (pHeader->FC.Type == BTYPE_DATA)
4197 {
4198 if (pRxD->U2M)
4199 pAd->ate.U2M++;
4200 else
4201 pAd->ate.OtherData++;
4202 }
4203 else if (pHeader->FC.Type == BTYPE_MGMT)
4204 {
4205 if (pHeader->FC.SubType == SUBTYPE_BEACON)
4206 pAd->ate.Beacon++;
4207 else
4208 pAd->ate.OtherCount++;
4209 }
4210 else if (pHeader->FC.Type == BTYPE_CNTL)
4211 {
4212 pAd->ate.OtherCount++;
4213 }
4214 }
4215 pAd->ate.RSSI0 = pRxWI->RSSI0;
4216 pAd->ate.RSSI1 = pRxWI->RSSI1;
4217 pAd->ate.RSSI2 = pRxWI->RSSI2;
4218 pAd->ate.SNR0 = pRxWI->SNR0;
4219 pAd->ate.SNR1 = pRxWI->SNR1;
4220 }
4221
4222 /* command id with Cmd Type == 0x0008(for 28xx)/0x0005(for iNIC) */
4223 #define RACFG_CMD_RF_WRITE_ALL 0x0000
4224 #define RACFG_CMD_E2PROM_READ16 0x0001
4225 #define RACFG_CMD_E2PROM_WRITE16 0x0002
4226 #define RACFG_CMD_E2PROM_READ_ALL 0x0003
4227 #define RACFG_CMD_E2PROM_WRITE_ALL 0x0004
4228 #define RACFG_CMD_IO_READ 0x0005
4229 #define RACFG_CMD_IO_WRITE 0x0006
4230 #define RACFG_CMD_IO_READ_BULK 0x0007
4231 #define RACFG_CMD_BBP_READ8 0x0008
4232 #define RACFG_CMD_BBP_WRITE8 0x0009
4233 #define RACFG_CMD_BBP_READ_ALL 0x000a
4234 #define RACFG_CMD_GET_COUNTER 0x000b
4235 #define RACFG_CMD_CLEAR_COUNTER 0x000c
4236
4237 #define RACFG_CMD_RSV1 0x000d
4238 #define RACFG_CMD_RSV2 0x000e
4239 #define RACFG_CMD_RSV3 0x000f
4240
4241 #define RACFG_CMD_TX_START 0x0010
4242 #define RACFG_CMD_GET_TX_STATUS 0x0011
4243 #define RACFG_CMD_TX_STOP 0x0012
4244 #define RACFG_CMD_RX_START 0x0013
4245 #define RACFG_CMD_RX_STOP 0x0014
4246 #define RACFG_CMD_GET_NOISE_LEVEL 0x0015
4247
4248 #define RACFG_CMD_ATE_START 0x0080
4249 #define RACFG_CMD_ATE_STOP 0x0081
4250
4251 #define RACFG_CMD_ATE_START_TX_CARRIER 0x0100
4252 #define RACFG_CMD_ATE_START_TX_CONT 0x0101
4253 #define RACFG_CMD_ATE_START_TX_FRAME 0x0102
4254 #define RACFG_CMD_ATE_SET_BW 0x0103
4255 #define RACFG_CMD_ATE_SET_TX_POWER0 0x0104
4256 #define RACFG_CMD_ATE_SET_TX_POWER1 0x0105
4257 #define RACFG_CMD_ATE_SET_FREQ_OFFSET 0x0106
4258 #define RACFG_CMD_ATE_GET_STATISTICS 0x0107
4259 #define RACFG_CMD_ATE_RESET_COUNTER 0x0108
4260 #define RACFG_CMD_ATE_SEL_TX_ANTENNA 0x0109
4261 #define RACFG_CMD_ATE_SEL_RX_ANTENNA 0x010a
4262 #define RACFG_CMD_ATE_SET_PREAMBLE 0x010b
4263 #define RACFG_CMD_ATE_SET_CHANNEL 0x010c
4264 #define RACFG_CMD_ATE_SET_ADDR1 0x010d
4265 #define RACFG_CMD_ATE_SET_ADDR2 0x010e
4266 #define RACFG_CMD_ATE_SET_ADDR3 0x010f
4267 #define RACFG_CMD_ATE_SET_RATE 0x0110
4268 #define RACFG_CMD_ATE_SET_TX_FRAME_LEN 0x0111
4269 #define RACFG_CMD_ATE_SET_TX_FRAME_COUNT 0x0112
4270 #define RACFG_CMD_ATE_START_RX_FRAME 0x0113
4271 #define RACFG_CMD_ATE_E2PROM_READ_BULK 0x0114
4272 #define RACFG_CMD_ATE_E2PROM_WRITE_BULK 0x0115
4273 #define RACFG_CMD_ATE_IO_WRITE_BULK 0x0116
4274 #define RACFG_CMD_ATE_BBP_READ_BULK 0x0117
4275 #define RACFG_CMD_ATE_BBP_WRITE_BULK 0x0118
4276 #define RACFG_CMD_ATE_RF_READ_BULK 0x0119
4277 #define RACFG_CMD_ATE_RF_WRITE_BULK 0x011a
4278
4279
4280
4281 #define A2Hex(_X, _p) \
4282 { \
4283 UCHAR *p; \
4284 _X = 0; \
4285 p = _p; \
4286 while (((*p >= 'a') && (*p <= 'f')) || ((*p >= 'A') && (*p <= 'F')) || ((*p >= '0') && (*p <= '9'))) \
4287 { \
4288 if ((*p >= 'a') && (*p <= 'f')) \
4289 _X = _X * 16 + *p - 87; \
4290 else if ((*p >= 'A') && (*p <= 'F')) \
4291 _X = _X * 16 + *p - 55; \
4292 else if ((*p >= '0') && (*p <= '9')) \
4293 _X = _X * 16 + *p - 48; \
4294 p++; \
4295 } \
4296 }
4297
4298
4299 static VOID memcpy_exl(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len);
4300 static VOID memcpy_exs(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len);
4301 static VOID RTMP_IO_READ_BULK(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, UINT32 len);
4302
4303 #ifdef UCOS
4304 int ate_copy_to_user(
4305 IN PUCHAR payload,
4306 IN PUCHAR msg,
4307 IN INT len)
4308 {
4309 memmove(payload, msg, len);
4310 return 0;
4311 }
4312
4313 #undef copy_to_user
4314 #define copy_to_user(x,y,z) ate_copy_to_user((PUCHAR)x, (PUCHAR)y, z)
4315 #endif // UCOS //
4316
4317 #define LEN_OF_ARG 16
4318
4319 VOID RtmpDoAte(
4320 IN PRTMP_ADAPTER pAdapter,
4321 IN struct iwreq *wrq)
4322 {
4323 unsigned short Command_Id;
4324 struct ate_racfghdr *pRaCfg;
4325 INT Status = NDIS_STATUS_SUCCESS;
4326
4327
4328
4329 if((pRaCfg = kmalloc(sizeof(struct ate_racfghdr), GFP_KERNEL)) == NULL)
4330 {
4331 Status = -EINVAL;
4332 return;
4333 }
4334
4335 NdisZeroMemory(pRaCfg, sizeof(struct ate_racfghdr));
4336
4337 if (copy_from_user((PUCHAR)pRaCfg, wrq->u.data.pointer, wrq->u.data.length))
4338 {
4339 Status = -EFAULT;
4340 kfree(pRaCfg);
4341 return;
4342 }
4343
4344
4345 Command_Id = ntohs(pRaCfg->command_id);
4346
4347 ATEDBGPRINT(RT_DEBUG_TRACE,("\n%s: Command_Id = 0x%04x !\n", __FUNCTION__, Command_Id));
4348
4349 switch (Command_Id)
4350 {
4351 // We will get this command when QA starts.
4352 case RACFG_CMD_ATE_START:
4353 {
4354 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START\n"));
4355
4356 // prepare feedback as soon as we can to avoid QA timeout.
4357 pRaCfg->length = htons(2);
4358 pRaCfg->status = htons(0);
4359
4360 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4361 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4362 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4363
4364 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4365
4366 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4367 {
4368 ATEDBGPRINT(RT_DEBUG_TRACE, ("copy_to_user() fail in case RACFG_CMD_ATE_START\n"));
4369 Status = -EFAULT;
4370 }
4371 else
4372 {
4373 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START is done !\n"));
4374 }
4375 Set_ATE_Proc(pAdapter, "ATESTART");
4376 }
4377 break;
4378
4379 // We will get this command either QA is closed or ated is killed by user.
4380 case RACFG_CMD_ATE_STOP:
4381 {
4382 #ifndef UCOS
4383 INT32 ret;
4384 #endif // !UCOS //
4385
4386 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_STOP\n"));
4387
4388 // Distinguish this command came from QA(via ated)
4389 // or ate daemon according to the existence of pid in payload.
4390 // No need to prepare feedback if this cmd came directly from ate daemon.
4391 pRaCfg->length = ntohs(pRaCfg->length);
4392
4393 if (pRaCfg->length == sizeof(pAdapter->ate.AtePid))
4394 {
4395 // This command came from QA.
4396 // Get the pid of ATE daemon.
4397 memcpy((UCHAR *)&pAdapter->ate.AtePid,
4398 (&pRaCfg->data[0]) - 2/* == &(pRaCfg->status) */,
4399 sizeof(pAdapter->ate.AtePid));
4400
4401 // prepare feedback as soon as we can to avoid QA timeout.
4402 pRaCfg->length = htons(2);
4403 pRaCfg->status = htons(0);
4404
4405 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4406 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4407 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4408
4409 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4410
4411 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4412 {
4413 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_STOP\n"));
4414 Status = -EFAULT;
4415 }
4416
4417 //
4418 // kill ATE daemon when leaving ATE mode.
4419 // We must kill ATE daemon first before setting ATESTOP,
4420 // or Microsoft will report sth. wrong.
4421 #ifndef UCOS
4422 ret = kill_proc(pAdapter->ate.AtePid, SIGTERM, 1);
4423 if (ret)
4424 {
4425 ATEDBGPRINT(RT_DEBUG_ERROR, ("%s: unable to signal thread\n", pAdapter->net_dev->name));
4426 }
4427 #endif // !UCOS //
4428 }
4429
4430 #ifdef UCOS
4431 // Roger add to avoid error message after close QA
4432 if (pAdapter->CSRBaseAddress == RT2860_CSR_ADDR)
4433 {
4434
4435 // prepare feedback as soon as we can to avoid QA timeout.
4436 pRaCfg->length = htons(2);
4437 pRaCfg->status = htons(0);
4438
4439 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4440 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4441 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4442
4443 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4444 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4445 {
4446 ATEDBGPRINT(RT_DEBUG_TRACE, ("copy_to_user() fail in case RACFG_CMD_AP_START\n"));
4447 Status = -EFAULT;
4448 }
4449 }
4450 #endif // UCOS //
4451
4452 // AP might have in ATE_STOP mode due to cmd from QA.
4453 if (ATE_ON(pAdapter))
4454 {
4455 // Someone has killed ate daemon while QA GUI is still open.
4456 Set_ATE_Proc(pAdapter, "ATESTOP");
4457 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_AP_START is done !\n"));
4458 }
4459 }
4460 break;
4461
4462 case RACFG_CMD_RF_WRITE_ALL:
4463 {
4464 UINT32 R1, R2, R3, R4;
4465 USHORT channel;
4466
4467 memcpy(&R1, pRaCfg->data-2, 4);
4468 memcpy(&R2, pRaCfg->data+2, 4);
4469 memcpy(&R3, pRaCfg->data+6, 4);
4470 memcpy(&R4, pRaCfg->data+10, 4);
4471 memcpy(&channel, pRaCfg->data+14, 2);
4472
4473 pAdapter->LatchRfRegs.R1 = ntohl(R1);
4474 pAdapter->LatchRfRegs.R2 = ntohl(R2);
4475 pAdapter->LatchRfRegs.R3 = ntohl(R3);
4476 pAdapter->LatchRfRegs.R4 = ntohl(R4);
4477 pAdapter->LatchRfRegs.Channel = ntohs(channel);
4478
4479 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R1);
4480 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R2);
4481 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R3);
4482 RTMP_RF_IO_WRITE32(pAdapter, pAdapter->LatchRfRegs.R4);
4483
4484 // prepare feedback
4485 pRaCfg->length = htons(2);
4486 pRaCfg->status = htons(0);
4487
4488 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4489 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4490 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4491
4492 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4493 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4494 {
4495 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RF_WRITE_ALL\n"));
4496 Status = -EFAULT;
4497 }
4498 else
4499 {
4500 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RF_WRITE_ALL is done !\n"));
4501 }
4502 }
4503 break;
4504
4505 case RACFG_CMD_E2PROM_READ16:
4506 {
4507 USHORT offset, value, tmp;
4508
4509 offset = ntohs(pRaCfg->status);
4510 /* "tmp" is expecially for some compilers... */
4511 RT28xx_EEPROM_READ16(pAdapter, offset, tmp);
4512 value = tmp;
4513 value = htons(value);
4514
4515 ATEDBGPRINT(RT_DEBUG_TRACE,("EEPROM Read offset = 0x%04x, value = 0x%04x\n", offset, value));
4516
4517 // prepare feedback
4518 pRaCfg->length = htons(4);
4519 pRaCfg->status = htons(0);
4520 memcpy(pRaCfg->data, &value, 2);
4521
4522 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4523 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4524 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4525
4526 ATEDBGPRINT(RT_DEBUG_TRACE, ("sizeof(struct ate_racfghdr) = %d\n", sizeof(struct ate_racfghdr)));
4527 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
4528
4529 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4530 {
4531 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_READ16\n"));
4532 Status = -EFAULT;
4533 }
4534 else
4535 {
4536 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_E2PROM_READ16 is done !\n"));
4537 }
4538 }
4539 break;
4540
4541 case RACFG_CMD_E2PROM_WRITE16:
4542 {
4543 USHORT offset, value;
4544
4545 offset = ntohs(pRaCfg->status);
4546 memcpy(&value, pRaCfg->data, 2);
4547 value = ntohs(value);
4548 RT28xx_EEPROM_WRITE16(pAdapter, offset, value);
4549
4550 // prepare feedback
4551 pRaCfg->length = htons(2);
4552 pRaCfg->status = htons(0);
4553 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4554 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4555 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4556
4557 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4558 {
4559 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_WRITE16\n"));
4560 Status = -EFAULT;
4561 }
4562 else
4563 {
4564 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_E2PROM_WRITE16 is done !\n"));
4565 }
4566 }
4567 break;
4568
4569 case RACFG_CMD_E2PROM_READ_ALL:
4570 {
4571 USHORT buffer[EEPROM_SIZE/2];
4572
4573 rt_ee_read_all(pAdapter,(USHORT *)buffer);
4574 memcpy_exs(pAdapter, pRaCfg->data, (UCHAR *)buffer, EEPROM_SIZE);
4575
4576 // prepare feedback
4577 pRaCfg->length = htons(2+EEPROM_SIZE);
4578 pRaCfg->status = htons(0);
4579 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4580 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4581 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4582
4583 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4584 {
4585 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_READ_ALL\n"));
4586 Status = -EFAULT;
4587 }
4588 else
4589 {
4590 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_E2PROM_READ_ALL is done !\n"));
4591 }
4592 }
4593 break;
4594
4595 case RACFG_CMD_E2PROM_WRITE_ALL:
4596 {
4597 USHORT buffer[EEPROM_SIZE/2];
4598
4599 NdisZeroMemory((UCHAR *)buffer, EEPROM_SIZE);
4600 memcpy_exs(pAdapter, (UCHAR *)buffer, (UCHAR *)&pRaCfg->status, EEPROM_SIZE);
4601 rt_ee_write_all(pAdapter,(USHORT *)buffer);
4602
4603 // prepare feedback
4604 pRaCfg->length = htons(2);
4605 pRaCfg->status = htons(0);
4606 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4607 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4608 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4609
4610 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4611 {
4612 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_E2PROM_WRITE_ALL\n"));
4613 Status = -EFAULT;
4614 }
4615 else
4616 {
4617 ATEDBGPRINT(RT_DEBUG_ERROR, ("RACFG_CMD_E2PROM_WRITE_ALL is done !\n"));
4618 }
4619
4620 }
4621 break;
4622
4623 case RACFG_CMD_IO_READ:
4624 {
4625 UINT32 offset;
4626 UINT32 value;
4627
4628 memcpy(&offset, &pRaCfg->status, 4);
4629 offset = ntohl(offset);
4630
4631 // We do not need the base address.
4632 // So just extract the offset out.
4633 offset &= 0x0000FFFF;
4634 RTMP_IO_READ32(pAdapter, offset, &value);
4635 value = htonl(value);
4636
4637 // prepare feedback
4638 pRaCfg->length = htons(6);
4639 pRaCfg->status = htons(0);
4640 memcpy(pRaCfg->data, &value, 4);
4641
4642 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4643 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4644 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4645
4646 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4647 {
4648 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_IO_READ\n"));
4649 Status = -EFAULT;
4650 }
4651 else
4652 {
4653 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_IO_READ is done !\n"));
4654 }
4655 }
4656 break;
4657
4658 case RACFG_CMD_IO_WRITE:
4659 {
4660 UINT32 offset, value;
4661
4662 memcpy(&offset, pRaCfg->data-2, 4);
4663 memcpy(&value, pRaCfg->data+2, 4);
4664
4665 offset = ntohl(offset);
4666
4667 // We do not need the base address.
4668 // So just extract out the offset.
4669 offset &= 0x0000FFFF;
4670 value = ntohl(value);
4671 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_IO_WRITE: offset = %x, value = %x\n", offset, value));
4672 RTMP_IO_WRITE32(pAdapter, offset, value);
4673
4674 // prepare feedback
4675 pRaCfg->length = htons(2);
4676 pRaCfg->status = htons(0);
4677 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4678 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4679 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4680
4681 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4682 {
4683 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_IO_WRITE\n"));
4684 Status = -EFAULT;
4685 }
4686 else
4687 {
4688 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_IO_WRITE is done !\n"));
4689 }
4690 }
4691 break;
4692
4693 case RACFG_CMD_IO_READ_BULK:
4694 {
4695 UINT32 offset;
4696 USHORT len;
4697
4698 memcpy(&offset, &pRaCfg->status, 4);
4699 offset = ntohl(offset);
4700
4701 // We do not need the base address.
4702 // So just extract the offset.
4703 offset &= 0x0000FFFF;
4704 memcpy(&len, pRaCfg->data+2, 2);
4705 len = ntohs(len);
4706
4707 if (len > 371)
4708 {
4709 ATEDBGPRINT(RT_DEBUG_TRACE,("len is too large, make it smaller\n"));
4710 pRaCfg->length = htons(2);
4711 pRaCfg->status = htons(1);
4712 break;
4713 }
4714
4715 RTMP_IO_READ_BULK(pAdapter, pRaCfg->data, (UCHAR *)offset, len*4);// unit in four bytes
4716
4717 // prepare feedback
4718 pRaCfg->length = htons(2+len*4);// unit in four bytes
4719 pRaCfg->status = htons(0);
4720 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4721 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4722 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4723
4724 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4725 {
4726 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_IO_READ_BULK\n"));
4727 Status = -EFAULT;
4728 }
4729 else
4730 {
4731 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_IO_READ_BULK is done !\n"));
4732 }
4733 }
4734 break;
4735
4736 case RACFG_CMD_BBP_READ8:
4737 {
4738 USHORT offset;
4739 UCHAR value;
4740
4741 value = 0;
4742 offset = ntohs(pRaCfg->status);
4743
4744 if (ATE_ON(pAdapter))
4745 {
4746 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, offset, &value);
4747 }
4748 else
4749 {
4750 RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, offset, &value);
4751 }
4752 // prepare feedback
4753 pRaCfg->length = htons(3);
4754 pRaCfg->status = htons(0);
4755 pRaCfg->data[0] = value;
4756
4757 ATEDBGPRINT(RT_DEBUG_TRACE,("BBP value = %x\n", value));
4758
4759 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4760 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4761 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4762
4763 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4764 {
4765 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_BBP_READ8\n"));
4766 Status = -EFAULT;
4767 }
4768 else
4769 {
4770 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_BBP_READ8 is done !\n"));
4771 }
4772 }
4773 break;
4774 case RACFG_CMD_BBP_WRITE8:
4775 {
4776 USHORT offset;
4777 UCHAR value;
4778
4779 offset = ntohs(pRaCfg->status);
4780 memcpy(&value, pRaCfg->data, 1);
4781
4782 if (ATE_ON(pAdapter))
4783 {
4784 ATE_BBP_IO_WRITE8_BY_REG_ID(pAdapter, offset, value);
4785 }
4786 else
4787 {
4788 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, offset, value);
4789 }
4790
4791 if ((offset == BBP_R1) || (offset == BBP_R3))
4792 {
4793 SyncTxRxConfig(pAdapter, offset, value);
4794 }
4795
4796 // prepare feedback
4797 pRaCfg->length = htons(2);
4798 pRaCfg->status = htons(0);
4799 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4800 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4801 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4802
4803 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4804 {
4805 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_BBP_WRITE8\n"));
4806 Status = -EFAULT;
4807 }
4808 else
4809 {
4810 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_BBP_WRITE8 is done !\n"));
4811 }
4812 }
4813 break;
4814
4815 case RACFG_CMD_BBP_READ_ALL:
4816 {
4817 USHORT j;
4818
4819 for (j = 0; j < 137; j++)
4820 {
4821 pRaCfg->data[j] = 0;
4822
4823 if (ATE_ON(pAdapter))
4824 {
4825 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j]);
4826 }
4827 else
4828 {
4829 RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j]);
4830 }
4831 }
4832
4833 // prepare feedback
4834 pRaCfg->length = htons(2+137);
4835 pRaCfg->status = htons(0);
4836
4837 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4838 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4839 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4840
4841 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4842 {
4843 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_BBP_READ_ALL\n"));
4844 Status = -EFAULT;
4845 }
4846 else
4847 {
4848 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_BBP_READ_ALL is done !\n"));
4849 }
4850 }
4851
4852 break;
4853
4854 case RACFG_CMD_ATE_E2PROM_READ_BULK:
4855 {
4856 USHORT offset;
4857 USHORT len;
4858 USHORT buffer[EEPROM_SIZE/2];
4859
4860 offset = ntohs(pRaCfg->status);
4861 memcpy(&len, pRaCfg->data, 2);
4862 len = ntohs(len);
4863
4864 rt_ee_read_all(pAdapter,(USHORT *)buffer);
4865 if (offset + len <= EEPROM_SIZE)
4866 memcpy_exs(pAdapter, pRaCfg->data, (UCHAR *)buffer+offset, len);
4867 else
4868 ATEDBGPRINT(RT_DEBUG_ERROR, ("exceed EEPROM size\n"));
4869
4870 // prepare feedback
4871 pRaCfg->length = htons(2+len);
4872 pRaCfg->status = htons(0);
4873 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4874 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4875 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4876
4877 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4878 {
4879 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_E2PROM_READ_BULK\n"));
4880 Status = -EFAULT;
4881 }
4882 else
4883 {
4884 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_E2PROM_READ_BULK is done !\n"));
4885 }
4886
4887 }
4888 break;
4889
4890 case RACFG_CMD_ATE_E2PROM_WRITE_BULK:
4891 {
4892 USHORT offset;
4893 USHORT len;
4894 USHORT buffer[EEPROM_SIZE/2];
4895
4896 offset = ntohs(pRaCfg->status);
4897 memcpy(&len, pRaCfg->data, 2);
4898 len = ntohs(len);
4899
4900 rt_ee_read_all(pAdapter,(USHORT *)buffer);
4901 memcpy_exs(pAdapter, (UCHAR *)buffer + offset, (UCHAR *)pRaCfg->data + 2, len);
4902 rt_ee_write_all(pAdapter,(USHORT *)buffer);
4903
4904 // prepare feedback
4905 pRaCfg->length = htons(2);
4906 pRaCfg->status = htons(0);
4907 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4908 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4909 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4910 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4911 {
4912 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_E2PROM_WRITE_BULK\n"));
4913 Status = -EFAULT;
4914 }
4915 else
4916 {
4917 ATEDBGPRINT(RT_DEBUG_ERROR, ("RACFG_CMD_ATE_E2PROM_WRITE_BULK is done !\n"));
4918 }
4919
4920 }
4921 break;
4922
4923 case RACFG_CMD_ATE_IO_WRITE_BULK:
4924 {
4925 UINT32 offset, i, value;
4926 USHORT len;
4927
4928 memcpy(&offset, &pRaCfg->status, 4);
4929 offset = ntohl(offset);
4930 memcpy(&len, pRaCfg->data+2, 2);
4931 len = ntohs(len);
4932
4933 for (i = 0; i < len; i += 4)
4934 {
4935 memcpy_exl(pAdapter, (UCHAR *)&value, pRaCfg->data+4+i, 4);
4936 printk("Write %x %x\n", offset + i, value);
4937 RTMP_IO_WRITE32(pAdapter, (offset +i) & 0xffff, value);
4938 }
4939
4940 // prepare feedback
4941 pRaCfg->length = htons(2);
4942 pRaCfg->status = htons(0);
4943 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4944 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4945 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4946 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4947 {
4948 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_IO_WRITE_BULK\n"));
4949 Status = -EFAULT;
4950 }
4951 else
4952 {
4953 ATEDBGPRINT(RT_DEBUG_ERROR, ("RACFG_CMD_ATE_IO_WRITE_BULK is done !\n"));
4954 }
4955
4956 }
4957 break;
4958
4959 case RACFG_CMD_ATE_BBP_READ_BULK:
4960 {
4961 USHORT offset;
4962 USHORT len;
4963 USHORT j;
4964
4965 offset = ntohs(pRaCfg->status);
4966 memcpy(&len, pRaCfg->data, 2);
4967 len = ntohs(len);
4968
4969
4970 for (j = offset; j < (offset+len); j++)
4971 {
4972 pRaCfg->data[j - offset] = 0;
4973
4974 if (pAdapter->ate.Mode == ATE_STOP)
4975 {
4976 RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j - offset]);
4977 }
4978 else
4979 {
4980 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, j, &pRaCfg->data[j - offset]);
4981 }
4982 }
4983
4984 // prepare feedback
4985 pRaCfg->length = htons(2+len);
4986 pRaCfg->status = htons(0);
4987 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
4988 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
4989 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
4990
4991 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
4992 {
4993 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_BBP_READ_BULK\n"));
4994 Status = -EFAULT;
4995 }
4996 else
4997 {
4998 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_BBP_READ_BULK is done !\n"));
4999 }
5000
5001 }
5002 break;
5003
5004 case RACFG_CMD_ATE_BBP_WRITE_BULK:
5005 {
5006 USHORT offset;
5007 USHORT len;
5008 USHORT j;
5009 UCHAR *value;
5010
5011 offset = ntohs(pRaCfg->status);
5012 memcpy(&len, pRaCfg->data, 2);
5013 len = ntohs(len);
5014
5015 for (j = offset; j < (offset+len); j++)
5016 {
5017 value = pRaCfg->data + 2 + (j - offset);
5018 if (pAdapter->ate.Mode == ATE_STOP)
5019 {
5020 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, j, *value);
5021 }
5022 else
5023 {
5024 ATE_BBP_IO_WRITE8_BY_REG_ID(pAdapter, j, *value);
5025 }
5026 }
5027
5028 // prepare feedback
5029 pRaCfg->length = htons(2);
5030 pRaCfg->status = htons(0);
5031 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5032 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5033 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5034
5035 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5036 {
5037 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_BBP_WRITE_BULK\n"));
5038 Status = -EFAULT;
5039 }
5040 else
5041 {
5042 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_BBP_WRITE_BULK is done !\n"));
5043 }
5044 }
5045 break;
5046
5047 #ifdef CONFIG_RALINK_RT3052
5048 case RACFG_CMD_ATE_RF_READ_BULK:
5049 {
5050 USHORT offset;
5051 USHORT len;
5052 USHORT j;
5053
5054 offset = ntohs(pRaCfg->status);
5055 memcpy(&len, pRaCfg->data, 2);
5056 len = ntohs(len);
5057
5058 for (j = offset; j < (offset+len); j++)
5059 {
5060 pRaCfg->data[j - offset] = 0;
5061 RT30xxReadRFRegister(pAdapter, j, &pRaCfg->data[j - offset]);
5062 }
5063
5064 // prepare feedback
5065 pRaCfg->length = htons(2+len);
5066 pRaCfg->status = htons(0);
5067 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5068 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5069 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5070
5071 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5072 {
5073 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_RF_READ_BULK\n"));
5074 Status = -EFAULT;
5075 }
5076 else
5077 {
5078 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_RF_READ_BULK is done !\n"));
5079 }
5080
5081 }
5082 break;
5083
5084 case RACFG_CMD_ATE_RF_WRITE_BULK:
5085 {
5086 USHORT offset;
5087 USHORT len;
5088 USHORT j;
5089 UCHAR *value;
5090
5091 offset = ntohs(pRaCfg->status);
5092 memcpy(&len, pRaCfg->data, 2);
5093 len = ntohs(len);
5094
5095 for (j = offset; j < (offset+len); j++)
5096 {
5097 value = pRaCfg->data + 2 + (j - offset);
5098 RT30xxWriteRFRegister(pAdapter, j, *value);
5099 }
5100
5101 // prepare feedback
5102 pRaCfg->length = htons(2);
5103 pRaCfg->status = htons(0);
5104 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5105 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5106 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5107
5108 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5109 {
5110 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_RF_WRITE_BULK\n"));
5111 Status = -EFAULT;
5112 }
5113 else
5114 {
5115 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_RF_WRITE_BULK is done !\n"));
5116 }
5117
5118 }
5119 break;
5120 #endif
5121
5122
5123 case RACFG_CMD_GET_NOISE_LEVEL:
5124 {
5125 UCHAR channel;
5126 INT32 buffer[3][10];/* 3 : RxPath ; 10 : no. of per rssi samples */
5127
5128 channel = (ntohs(pRaCfg->status) & 0x00FF);
5129 CalNoiseLevel(pAdapter, channel, buffer);
5130 memcpy_exl(pAdapter, (UCHAR *)pRaCfg->data, (UCHAR *)&(buffer[0][0]), (sizeof(INT32)*3*10));
5131
5132 // prepare feedback
5133 pRaCfg->length = htons(2 + (sizeof(INT32)*3*10));
5134 pRaCfg->status = htons(0);
5135 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5136 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5137 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5138
5139 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5140 {
5141 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_GET_NOISE_LEVEL\n"));
5142 Status = -EFAULT;
5143 }
5144 else
5145 {
5146 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_GET_NOISE_LEVEL is done !\n"));
5147 }
5148 }
5149 break;
5150
5151 case RACFG_CMD_GET_COUNTER:
5152 {
5153 memcpy_exl(pAdapter, &pRaCfg->data[0], (UCHAR *)&pAdapter->ate.U2M, 4);
5154 memcpy_exl(pAdapter, &pRaCfg->data[4], (UCHAR *)&pAdapter->ate.OtherData, 4);
5155 memcpy_exl(pAdapter, &pRaCfg->data[8], (UCHAR *)&pAdapter->ate.Beacon, 4);
5156 memcpy_exl(pAdapter, &pRaCfg->data[12], (UCHAR *)&pAdapter->ate.OtherCount, 4);
5157 memcpy_exl(pAdapter, &pRaCfg->data[16], (UCHAR *)&pAdapter->ate.TxAc0, 4);
5158 memcpy_exl(pAdapter, &pRaCfg->data[20], (UCHAR *)&pAdapter->ate.TxAc1, 4);
5159 memcpy_exl(pAdapter, &pRaCfg->data[24], (UCHAR *)&pAdapter->ate.TxAc2, 4);
5160 memcpy_exl(pAdapter, &pRaCfg->data[28], (UCHAR *)&pAdapter->ate.TxAc3, 4);
5161 memcpy_exl(pAdapter, &pRaCfg->data[32], (UCHAR *)&pAdapter->ate.TxHCCA, 4);
5162 memcpy_exl(pAdapter, &pRaCfg->data[36], (UCHAR *)&pAdapter->ate.TxMgmt, 4);
5163 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&pAdapter->ate.RSSI0, 4);
5164 memcpy_exl(pAdapter, &pRaCfg->data[44], (UCHAR *)&pAdapter->ate.RSSI1, 4);
5165 memcpy_exl(pAdapter, &pRaCfg->data[48], (UCHAR *)&pAdapter->ate.RSSI2, 4);
5166 memcpy_exl(pAdapter, &pRaCfg->data[52], (UCHAR *)&pAdapter->ate.SNR0, 4);
5167 memcpy_exl(pAdapter, &pRaCfg->data[56], (UCHAR *)&pAdapter->ate.SNR1, 4);
5168
5169 pRaCfg->length = htons(2+60);
5170 pRaCfg->status = htons(0);
5171 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5172 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5173 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5174
5175 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5176 {
5177 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_GET_COUNTER\n"));
5178 Status = -EFAULT;
5179 }
5180 else
5181 {
5182 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_GET_COUNTER is done !\n"));
5183 }
5184 }
5185 break;
5186
5187 case RACFG_CMD_CLEAR_COUNTER:
5188 {
5189 pAdapter->ate.U2M = 0;
5190 pAdapter->ate.OtherData = 0;
5191 pAdapter->ate.Beacon = 0;
5192 pAdapter->ate.OtherCount = 0;
5193 pAdapter->ate.TxAc0 = 0;
5194 pAdapter->ate.TxAc1 = 0;
5195 pAdapter->ate.TxAc2 = 0;
5196 pAdapter->ate.TxAc3 = 0;
5197 pAdapter->ate.TxHCCA = 0;
5198 pAdapter->ate.TxMgmt = 0;
5199 pAdapter->ate.TxDoneCount = 0;
5200
5201 pRaCfg->length = htons(2);
5202 pRaCfg->status = htons(0);
5203
5204 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5205 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5206 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5207
5208 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5209 {
5210 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_CLEAR_COUNTER\n"));
5211 Status = -EFAULT;
5212 }
5213 else
5214 {
5215 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_CLEAR_COUNTER is done !\n"));
5216 }
5217 }
5218
5219 break;
5220
5221 case RACFG_CMD_TX_START:
5222 {
5223 USHORT *p;
5224 USHORT err = 1;
5225 UCHAR Bbp22Value = 0, Bbp24Value = 0;
5226
5227 if ((pAdapter->ate.TxStatus != 0) && (pAdapter->ate.Mode & ATE_TXFRAME))
5228 {
5229 ATEDBGPRINT(RT_DEBUG_TRACE,("Ate Tx is already running, to run next Tx, you must stop it first\n"));
5230 err = 2;
5231 goto TX_START_ERROR;
5232 }
5233 else if ((pAdapter->ate.TxStatus != 0) && !(pAdapter->ate.Mode & ATE_TXFRAME))
5234 {
5235 int i = 0;
5236
5237 while ((i++ < 10) && (pAdapter->ate.TxStatus != 0))
5238 {
5239 RTMPusecDelay(5000);
5240 }
5241
5242 // force it to stop
5243 pAdapter->ate.TxStatus = 0;
5244 pAdapter->ate.TxDoneCount = 0;
5245 //pAdapter->ate.Repeat = 0;
5246 pAdapter->ate.bQATxStart = FALSE;
5247 }
5248
5249 // If pRaCfg->length == 0, this "RACFG_CMD_TX_START" is for Carrier test or Carrier Suppression.
5250 if (ntohs(pRaCfg->length) != 0)
5251 {
5252 // Get frame info
5253 #ifdef RT2870
5254 NdisMoveMemory(&pAdapter->ate.TxInfo, pRaCfg->data - 2, 4);
5255 #ifdef RT_BIG_ENDIAN
5256 RTMPDescriptorEndianChange((PUCHAR) &pAdapter->ate.TxInfo, TYPE_TXINFO);
5257 #endif // RT_BIG_ENDIAN //
5258 #endif // RT2870 //
5259
5260 NdisMoveMemory(&pAdapter->ate.TxWI, pRaCfg->data + 2, 16);
5261 #ifdef RT_BIG_ENDIAN
5262 RTMPWIEndianChange((PUCHAR)&pAdapter->ate.TxWI, TYPE_TXWI);
5263 #endif // RT_BIG_ENDIAN //
5264
5265 NdisMoveMemory(&pAdapter->ate.TxCount, pRaCfg->data + 18, 4);
5266 pAdapter->ate.TxCount = ntohl(pAdapter->ate.TxCount);
5267
5268 p = (USHORT *)(&pRaCfg->data[22]);
5269 //p = pRaCfg->data + 22;
5270 // always use QID_AC_BE
5271 pAdapter->ate.QID = 0;
5272 p = (USHORT *)(&pRaCfg->data[24]);
5273 //p = pRaCfg->data + 24;
5274 pAdapter->ate.HLen = ntohs(*p);
5275
5276 if (pAdapter->ate.HLen > 32)
5277 {
5278 ATEDBGPRINT(RT_DEBUG_ERROR,("pAdapter->ate.HLen > 32\n"));
5279 err = 3;
5280 goto TX_START_ERROR;
5281 }
5282
5283 NdisMoveMemory(&pAdapter->ate.Header, pRaCfg->data + 26, pAdapter->ate.HLen);
5284
5285
5286 pAdapter->ate.PLen = ntohs(pRaCfg->length) - (pAdapter->ate.HLen + 28);
5287
5288 if (pAdapter->ate.PLen > 32)
5289 {
5290 ATEDBGPRINT(RT_DEBUG_ERROR,("pAdapter->ate.PLen > 32\n"));
5291 err = 4;
5292 goto TX_START_ERROR;
5293 }
5294
5295 NdisMoveMemory(&pAdapter->ate.Pattern, pRaCfg->data + 26 + pAdapter->ate.HLen, pAdapter->ate.PLen);
5296 pAdapter->ate.DLen = pAdapter->ate.TxWI.MPDUtotalByteCount - pAdapter->ate.HLen;
5297 }
5298
5299 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R22, &Bbp22Value);
5300
5301 switch (Bbp22Value)
5302 {
5303 case BBP22_TXFRAME:
5304 {
5305 if (pAdapter->ate.TxCount == 0)
5306 {
5307 }
5308 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXFRAME\n"));
5309 pAdapter->ate.bQATxStart = TRUE;
5310 Set_ATE_Proc(pAdapter, "TXFRAME");
5311 }
5312 break;
5313
5314 case BBP22_TXCONT_OR_CARRSUPP:
5315 {
5316 ATEDBGPRINT(RT_DEBUG_TRACE,("BBP22_TXCONT_OR_CARRSUPP\n"));
5317 ATE_BBP_IO_READ8_BY_REG_ID(pAdapter, 24, &Bbp24Value);
5318
5319 switch (Bbp24Value)
5320 {
5321 case BBP24_TXCONT:
5322 {
5323 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCONT\n"));
5324 pAdapter->ate.bQATxStart = TRUE;
5325 Set_ATE_Proc(pAdapter, "TXCONT");
5326 }
5327 break;
5328
5329 case BBP24_CARRSUPP:
5330 {
5331 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCARRSUPP\n"));
5332 pAdapter->ate.bQATxStart = TRUE;
5333 pAdapter->ate.Mode |= ATE_TXCARRSUPP;
5334 }
5335 break;
5336
5337 default:
5338 {
5339 ATEDBGPRINT(RT_DEBUG_ERROR,("Unknown Start TX subtype !"));
5340 }
5341 break;
5342 }
5343 }
5344 break;
5345
5346 case BBP22_TXCARR:
5347 {
5348 ATEDBGPRINT(RT_DEBUG_TRACE,("START TXCARR\n"));
5349 pAdapter->ate.bQATxStart = TRUE;
5350 Set_ATE_Proc(pAdapter, "TXCARR");
5351 }
5352 break;
5353
5354 default:
5355 {
5356 ATEDBGPRINT(RT_DEBUG_ERROR,("Unknown Start TX subtype !"));
5357 }
5358 break;
5359 }
5360
5361 if (pAdapter->ate.bQATxStart == TRUE)
5362 {
5363 // prepare feedback
5364 pRaCfg->length = htons(2);
5365 pRaCfg->status = htons(0);
5366
5367 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5368 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5369 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5370
5371 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5372 {
5373 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() was failed in case RACFG_CMD_TX_START\n"));
5374 Status = -EFAULT;
5375 }
5376 else
5377 {
5378 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_TX_START is done !\n"));
5379 }
5380 break;
5381 }
5382
5383 TX_START_ERROR:
5384 // prepare feedback
5385 pRaCfg->length = htons(2);
5386 pRaCfg->status = htons(err);
5387
5388 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5389 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5390 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5391 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5392 {
5393 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_TX_START\n"));
5394 Status = -EFAULT;
5395 }
5396 else
5397 {
5398 ATEDBGPRINT(RT_DEBUG_TRACE, ("feedback of TX_START_ERROR is done !\n"));
5399 }
5400 }
5401 break;
5402
5403 case RACFG_CMD_GET_TX_STATUS:
5404 {
5405 UINT32 count;
5406
5407 // prepare feedback
5408 pRaCfg->length = htons(6);
5409 pRaCfg->status = htons(0);
5410 count = htonl(pAdapter->ate.TxDoneCount);
5411 NdisMoveMemory(pRaCfg->data, &count, 4);
5412 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5413 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5414 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5415
5416 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5417 {
5418 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_GET_TX_STATUS\n"));
5419 Status = -EFAULT;
5420 }
5421 else
5422 {
5423 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_GET_TX_STATUS is done !\n"));
5424 }
5425 }
5426 break;
5427
5428 case RACFG_CMD_TX_STOP:
5429 {
5430 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_TX_STOP\n"));
5431
5432 Set_ATE_Proc(pAdapter, "TXSTOP");
5433
5434 // prepare feedback
5435 pRaCfg->length = htons(2);
5436 pRaCfg->status = htons(0);
5437 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5438 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5439 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5440
5441 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5442 {
5443 ATEDBGPRINT(RT_DEBUG_TRACE, ("copy_to_user() fail in case RACFG_CMD_TX_STOP\n"));
5444 Status = -EFAULT;
5445 }
5446 else
5447 {
5448 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_TX_STOP is done !\n"));
5449 }
5450 }
5451 break;
5452
5453 case RACFG_CMD_RX_START:
5454 {
5455 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n"));
5456
5457 pAdapter->ate.bQARxStart = TRUE;
5458 Set_ATE_Proc(pAdapter, "RXFRAME");
5459
5460 // prepare feedback
5461 pRaCfg->length = htons(2);
5462 pRaCfg->status = htons(0);
5463 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5464 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5465 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5466
5467 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5468 {
5469 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RX_START\n"));
5470 Status = -EFAULT;
5471 }
5472 else
5473 {
5474 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RX_START is done !\n"));
5475 }
5476 }
5477 break;
5478
5479 case RACFG_CMD_RX_STOP:
5480 {
5481 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_STOP\n"));
5482
5483 Set_ATE_Proc(pAdapter, "RXSTOP");
5484
5485 // prepare feedback
5486 pRaCfg->length = htons(2);
5487 pRaCfg->status = htons(0);
5488 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5489 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5490 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5491
5492 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5493 {
5494 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RX_STOP\n"));
5495 Status = -EFAULT;
5496 }
5497 else
5498 {
5499 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RX_STOP is done !\n"));
5500 }
5501 }
5502 break;
5503
5504 /* The following cases are for new ATE GUI(not QA). */
5505 /*==================================================*/
5506 case RACFG_CMD_ATE_START_TX_CARRIER:
5507 {
5508 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CARRIER\n"));
5509
5510 Set_ATE_Proc(pAdapter, "TXCARR");
5511
5512 pRaCfg->length = htons(2);
5513 pRaCfg->status = htons(0);
5514
5515 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5516 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5517 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5518
5519 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
5520
5521 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5522 {
5523 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_START_TX_CARRIER\n"));
5524 Status = -EFAULT;
5525 }
5526 else
5527 {
5528 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START_TX_CARRIER is done !\n"));
5529 }
5530 }
5531 break;
5532
5533 case RACFG_CMD_ATE_START_TX_CONT:
5534 {
5535 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_CONT\n"));
5536
5537 Set_ATE_Proc(pAdapter, "TXCONT");
5538
5539 pRaCfg->length = htons(2);
5540 pRaCfg->status = htons(0);
5541
5542 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5543 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5544 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5545
5546 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
5547
5548 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5549 {
5550 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_START_TX_CONT\n"));
5551 Status = -EFAULT;
5552 }
5553 else
5554 {
5555 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START_TX_CONT is done !\n"));
5556 }
5557 }
5558 break;
5559
5560 case RACFG_CMD_ATE_START_TX_FRAME:
5561 {
5562 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_START_TX_FRAME\n"));
5563
5564 Set_ATE_Proc(pAdapter, "TXFRAME");
5565
5566 pRaCfg->length = htons(2);
5567 pRaCfg->status = htons(0);
5568
5569 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5570 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5571 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5572
5573 ATEDBGPRINT(RT_DEBUG_TRACE, ("wrq->u.data.length = %d\n", wrq->u.data.length));
5574
5575 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5576 {
5577 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_START_TX_FRAME\n"));
5578 Status = -EFAULT;
5579 }
5580 else
5581 {
5582 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_START_TX_FRAME is done !\n"));
5583 }
5584 }
5585 break;
5586
5587 case RACFG_CMD_ATE_SET_BW:
5588 {
5589 SHORT value = 0;
5590 UCHAR str[LEN_OF_ARG];
5591
5592 NdisZeroMemory(str, LEN_OF_ARG);
5593
5594 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_BW\n"));
5595
5596 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5597 value = ntohs(value);
5598 sprintf((PCHAR)str, "%d", value);
5599
5600 Set_ATE_TX_BW_Proc(pAdapter, str);
5601
5602 // prepare feedback
5603 pRaCfg->length = htons(2);
5604 pRaCfg->status = htons(0);
5605 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5606 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5607 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5608
5609 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5610 {
5611 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_BW\n"));
5612 Status = -EFAULT;
5613 }
5614 else
5615 {
5616 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_BW is done !\n"));
5617 }
5618 }
5619 break;
5620
5621 case RACFG_CMD_ATE_SET_TX_POWER0:
5622 {
5623 SHORT value = 0;
5624 UCHAR str[LEN_OF_ARG];
5625
5626 NdisZeroMemory(str, LEN_OF_ARG);
5627
5628 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER0\n"));
5629
5630 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5631 value = ntohs(value);
5632 sprintf((PCHAR)str, "%d", value);
5633 Set_ATE_TX_POWER0_Proc(pAdapter, str);
5634
5635 // prepare feedback
5636 pRaCfg->length = htons(2);
5637 pRaCfg->status = htons(0);
5638 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5639 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5640 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5641
5642 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5643 {
5644 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_POWER0\n"));
5645 Status = -EFAULT;
5646 }
5647 else
5648 {
5649 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_POWER0 is done !\n"));
5650 }
5651 }
5652 break;
5653
5654 case RACFG_CMD_ATE_SET_TX_POWER1:
5655 {
5656 SHORT value = 0;
5657 UCHAR str[LEN_OF_ARG];
5658
5659 NdisZeroMemory(str, LEN_OF_ARG);
5660
5661 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_POWER1\n"));
5662
5663 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5664 value = ntohs(value);
5665 sprintf((PCHAR)str, "%d", value);
5666 Set_ATE_TX_POWER1_Proc(pAdapter, str);
5667
5668 // prepare feedback
5669 pRaCfg->length = htons(2);
5670 pRaCfg->status = htons(0);
5671 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5672 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5673 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5674
5675 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5676 {
5677 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_POWER1\n"));
5678 Status = -EFAULT;
5679 }
5680 else
5681 {
5682 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_POWER1 is done !\n"));
5683 }
5684 }
5685 break;
5686
5687 case RACFG_CMD_ATE_SET_FREQ_OFFSET:
5688 {
5689 SHORT value = 0;
5690 UCHAR str[LEN_OF_ARG];
5691
5692 NdisZeroMemory(str, LEN_OF_ARG);
5693
5694 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_FREQ_OFFSET\n"));
5695
5696 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5697 value = ntohs(value);
5698 sprintf((PCHAR)str, "%d", value);
5699 Set_ATE_TX_FREQOFFSET_Proc(pAdapter, str);
5700
5701 // prepare feedback
5702 pRaCfg->length = htons(2);
5703 pRaCfg->status = htons(0);
5704 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5705 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5706 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5707
5708 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5709 {
5710 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_FREQ_OFFSET\n"));
5711 Status = -EFAULT;
5712 }
5713 else
5714 {
5715 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_FREQ_OFFSET is done !\n"));
5716 }
5717 }
5718 break;
5719
5720 case RACFG_CMD_ATE_GET_STATISTICS:
5721 {
5722 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_GET_STATISTICS\n"));
5723
5724 memcpy_exl(pAdapter, &pRaCfg->data[0], (UCHAR *)&pAdapter->ate.TxDoneCount, 4);
5725 memcpy_exl(pAdapter, &pRaCfg->data[4], (UCHAR *)&pAdapter->WlanCounters.RetryCount.u.LowPart, 4);
5726 memcpy_exl(pAdapter, &pRaCfg->data[8], (UCHAR *)&pAdapter->WlanCounters.FailedCount.u.LowPart, 4);
5727 memcpy_exl(pAdapter, &pRaCfg->data[12], (UCHAR *)&pAdapter->WlanCounters.RTSSuccessCount.u.LowPart, 4);
5728 memcpy_exl(pAdapter, &pRaCfg->data[16], (UCHAR *)&pAdapter->WlanCounters.RTSFailureCount.u.LowPart, 4);
5729 memcpy_exl(pAdapter, &pRaCfg->data[20], (UCHAR *)&pAdapter->WlanCounters.ReceivedFragmentCount.QuadPart, 4);
5730 memcpy_exl(pAdapter, &pRaCfg->data[24], (UCHAR *)&pAdapter->WlanCounters.FCSErrorCount.u.LowPart, 4);
5731 memcpy_exl(pAdapter, &pRaCfg->data[28], (UCHAR *)&pAdapter->Counters8023.RxNoBuffer, 4);
5732 memcpy_exl(pAdapter, &pRaCfg->data[32], (UCHAR *)&pAdapter->WlanCounters.FrameDuplicateCount.u.LowPart, 4);
5733 memcpy_exl(pAdapter, &pRaCfg->data[36], (UCHAR *)&pAdapter->RalinkCounters.OneSecFalseCCACnt, 4);
5734
5735 if (pAdapter->ate.RxAntennaSel == 0)
5736 {
5737 INT32 RSSI0 = 0;
5738 INT32 RSSI1 = 0;
5739 INT32 RSSI2 = 0;
5740
5741 RSSI0 = (INT32)(pAdapter->ate.LastRssi0 - pAdapter->BbpRssiToDbmDelta);
5742 RSSI1 = (INT32)(pAdapter->ate.LastRssi1 - pAdapter->BbpRssiToDbmDelta);
5743 RSSI2 = (INT32)(pAdapter->ate.LastRssi2 - pAdapter->BbpRssiToDbmDelta);
5744 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4);
5745 memcpy_exl(pAdapter, &pRaCfg->data[44], (UCHAR *)&RSSI1, 4);
5746 memcpy_exl(pAdapter, &pRaCfg->data[48], (UCHAR *)&RSSI2, 4);
5747 pRaCfg->length = htons(2+52);
5748 }
5749 else
5750 {
5751 INT32 RSSI0 = 0;
5752
5753 RSSI0 = (INT32)(pAdapter->ate.LastRssi0 - pAdapter->BbpRssiToDbmDelta);
5754 memcpy_exl(pAdapter, &pRaCfg->data[40], (UCHAR *)&RSSI0, 4);
5755 pRaCfg->length = htons(2+44);
5756 }
5757 pRaCfg->status = htons(0);
5758 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5759 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5760 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5761
5762 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5763 {
5764 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_GET_STATISTICS\n"));
5765 Status = -EFAULT;
5766 }
5767 else
5768 {
5769 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_GET_STATISTICS is done !\n"));
5770 }
5771 }
5772 break;
5773
5774 case RACFG_CMD_ATE_RESET_COUNTER:
5775 {
5776 SHORT value = 1;
5777 UCHAR str[LEN_OF_ARG];
5778
5779 NdisZeroMemory(str, LEN_OF_ARG);
5780
5781 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_RESET_COUNTER\n"));
5782
5783 sprintf((PCHAR)str, "%d", value);
5784 Set_ResetStatCounter_Proc(pAdapter, str);
5785
5786 pAdapter->ate.TxDoneCount = 0;
5787
5788 pRaCfg->length = htons(2);
5789 pRaCfg->status = htons(0);
5790
5791 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5792 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5793 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5794
5795 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5796 {
5797 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_RESET_COUNTER\n"));
5798 Status = -EFAULT;
5799 }
5800 else
5801 {
5802 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_RESET_COUNTER is done !\n"));
5803 }
5804 }
5805
5806 break;
5807
5808 case RACFG_CMD_ATE_SEL_TX_ANTENNA:
5809 {
5810 SHORT value = 0;
5811 UCHAR str[LEN_OF_ARG];
5812
5813 NdisZeroMemory(str, LEN_OF_ARG);
5814
5815 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_TX_ANTENNA\n"));
5816
5817 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5818 value = ntohs(value);
5819 sprintf((PCHAR)str, "%d", value);
5820 Set_ATE_TX_Antenna_Proc(pAdapter, str);
5821
5822 // prepare feedback
5823 pRaCfg->length = htons(2);
5824 pRaCfg->status = htons(0);
5825 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5826 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5827 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5828
5829 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5830 {
5831 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SEL_TX_ANTENNA\n"));
5832 Status = -EFAULT;
5833 }
5834 else
5835 {
5836 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SEL_TX_ANTENNA is done !\n"));
5837 }
5838 }
5839 break;
5840
5841 case RACFG_CMD_ATE_SEL_RX_ANTENNA:
5842 {
5843 SHORT value = 0;
5844 UCHAR str[LEN_OF_ARG];
5845
5846 NdisZeroMemory(str, LEN_OF_ARG);
5847
5848 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SEL_RX_ANTENNA\n"));
5849
5850 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5851 value = ntohs(value);
5852 sprintf((PCHAR)str, "%d", value);
5853 Set_ATE_RX_Antenna_Proc(pAdapter, str);
5854
5855 // prepare feedback
5856 pRaCfg->length = htons(2);
5857 pRaCfg->status = htons(0);
5858 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5859 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5860 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5861
5862 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5863 {
5864 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SEL_RX_ANTENNA\n"));
5865 Status = -EFAULT;
5866 }
5867 else
5868 {
5869 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SEL_RX_ANTENNA is done !\n"));
5870 }
5871 }
5872 break;
5873
5874 case RACFG_CMD_ATE_SET_PREAMBLE:
5875 {
5876 SHORT value = 0;
5877 UCHAR str[LEN_OF_ARG];
5878
5879 NdisZeroMemory(str, LEN_OF_ARG);
5880
5881 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_PREAMBLE\n"));
5882
5883 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5884 value = ntohs(value);
5885 sprintf((PCHAR)str, "%d", value);
5886 Set_ATE_TX_MODE_Proc(pAdapter, str);
5887
5888 // prepare feedback
5889 pRaCfg->length = htons(2);
5890 pRaCfg->status = htons(0);
5891 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5892 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5893 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5894
5895 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5896 {
5897 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_PREAMBLE\n"));
5898 Status = -EFAULT;
5899 }
5900 else
5901 {
5902 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_PREAMBLE is done !\n"));
5903 }
5904 }
5905 break;
5906
5907 case RACFG_CMD_ATE_SET_CHANNEL:
5908 {
5909 SHORT value = 0;
5910 UCHAR str[LEN_OF_ARG];
5911
5912 NdisZeroMemory(str, LEN_OF_ARG);
5913
5914 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_CHANNEL\n"));
5915
5916 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
5917 value = ntohs(value);
5918 sprintf((PCHAR)str, "%d", value);
5919 Set_ATE_CHANNEL_Proc(pAdapter, str);
5920
5921 // prepare feedback
5922 pRaCfg->length = htons(2);
5923 pRaCfg->status = htons(0);
5924 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5925 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5926 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5927
5928 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5929 {
5930 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_CHANNEL\n"));
5931 Status = -EFAULT;
5932 }
5933 else
5934 {
5935 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_CHANNEL is done !\n"));
5936 }
5937 }
5938 break;
5939
5940 case RACFG_CMD_ATE_SET_ADDR1:
5941 {
5942 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR1\n"));
5943
5944 // Addr is an array of UCHAR,
5945 // so no need to perform endian swap.
5946 memcpy(pAdapter->ate.Addr1, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5947
5948 // prepare feedback
5949 pRaCfg->length = htons(2);
5950 pRaCfg->status = htons(0);
5951 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5952 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5953 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5954
5955 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5956 {
5957 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_ADDR1\n"));
5958 Status = -EFAULT;
5959 }
5960 else
5961 {
5962 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_ADDR1 is done !\n (ADDR1 = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAdapter->ate.Addr1[0],
5963 pAdapter->ate.Addr1[1], pAdapter->ate.Addr1[2], pAdapter->ate.Addr1[3], pAdapter->ate.Addr1[4], pAdapter->ate.Addr1[5]));
5964 }
5965 }
5966 break;
5967
5968 case RACFG_CMD_ATE_SET_ADDR2:
5969 {
5970 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR2\n"));
5971
5972 // Addr is an array of UCHAR,
5973 // so no need to perform endian swap.
5974 memcpy(pAdapter->ate.Addr2, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
5975
5976 // prepare feedback
5977 pRaCfg->length = htons(2);
5978 pRaCfg->status = htons(0);
5979 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
5980 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
5981 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
5982
5983 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
5984 {
5985 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_ADDR2\n"));
5986 Status = -EFAULT;
5987 }
5988 else
5989 {
5990 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_ADDR2 is done !\n (ADDR2 = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAdapter->ate.Addr2[0],
5991 pAdapter->ate.Addr2[1], pAdapter->ate.Addr2[2], pAdapter->ate.Addr2[3], pAdapter->ate.Addr2[4], pAdapter->ate.Addr2[5]));
5992 }
5993 }
5994 break;
5995
5996 case RACFG_CMD_ATE_SET_ADDR3:
5997 {
5998 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_ADDR3\n"));
5999
6000 // Addr is an array of UCHAR,
6001 // so no need to perform endian swap.
6002 memcpy(pAdapter->ate.Addr3, (PUCHAR)(pRaCfg->data - 2), MAC_ADDR_LEN);
6003
6004 // prepare feedback
6005 pRaCfg->length = htons(2);
6006 pRaCfg->status = htons(0);
6007 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
6008 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
6009 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
6010
6011 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
6012 {
6013 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_ADDR3\n"));
6014 Status = -EFAULT;
6015 }
6016 else
6017 {
6018 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_ADDR3 is done !\n (ADDR3 = %2X:%2X:%2X:%2X:%2X:%2X)\n", pAdapter->ate.Addr3[0],
6019 pAdapter->ate.Addr3[1], pAdapter->ate.Addr3[2], pAdapter->ate.Addr3[3], pAdapter->ate.Addr3[4], pAdapter->ate.Addr3[5]));
6020 }
6021 }
6022 break;
6023
6024 case RACFG_CMD_ATE_SET_RATE:
6025 {
6026 SHORT value = 0;
6027 UCHAR str[LEN_OF_ARG];
6028
6029 NdisZeroMemory(str, LEN_OF_ARG);
6030
6031 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_RATE\n"));
6032
6033 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
6034 value = ntohs(value);
6035 sprintf((PCHAR)str, "%d", value);
6036 Set_ATE_TX_MCS_Proc(pAdapter, str);
6037
6038 // prepare feedback
6039 pRaCfg->length = htons(2);
6040 pRaCfg->status = htons(0);
6041 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
6042 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
6043 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
6044
6045 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
6046 {
6047 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_RATE\n"));
6048 Status = -EFAULT;
6049 }
6050 else
6051 {
6052 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_RATE is done !\n"));
6053 }
6054 }
6055 break;
6056
6057 case RACFG_CMD_ATE_SET_TX_FRAME_LEN:
6058 {
6059 SHORT value = 0;
6060 UCHAR str[LEN_OF_ARG];
6061
6062 NdisZeroMemory(str, LEN_OF_ARG);
6063
6064 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_LEN\n"));
6065
6066 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
6067 value = ntohs(value);
6068 sprintf((PCHAR)str, "%d", value);
6069 Set_ATE_TX_LENGTH_Proc(pAdapter, str);
6070
6071 // prepare feedback
6072 pRaCfg->length = htons(2);
6073 pRaCfg->status = htons(0);
6074 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
6075 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
6076 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
6077
6078 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
6079 {
6080 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_FRAME_LEN\n"));
6081 Status = -EFAULT;
6082 }
6083 else
6084 {
6085 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_FRAME_LEN is done !\n"));
6086 }
6087 }
6088 break;
6089
6090 case RACFG_CMD_ATE_SET_TX_FRAME_COUNT:
6091 {
6092 USHORT value = 0;
6093 UCHAR str[LEN_OF_ARG];
6094
6095 NdisZeroMemory(str, LEN_OF_ARG);
6096
6097 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_ATE_SET_TX_FRAME_COUNT\n"));
6098
6099 memcpy((PUCHAR)&value, (PUCHAR)&(pRaCfg->status), 2);
6100 value = ntohs(value);
6101 {
6102 sprintf((PCHAR)str, "%d", value);
6103 Set_ATE_TX_COUNT_Proc(pAdapter, str);
6104 }
6105
6106 // prepare feedback
6107 pRaCfg->length = htons(2);
6108 pRaCfg->status = htons(0);
6109 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
6110 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
6111 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
6112
6113 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
6114 {
6115 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_ATE_SET_TX_FRAME_COUNT\n"));
6116 Status = -EFAULT;
6117 }
6118 else
6119 {
6120 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_ATE_SET_TX_FRAME_COUNT is done !\n"));
6121 }
6122 }
6123 break;
6124
6125 case RACFG_CMD_ATE_START_RX_FRAME:
6126 {
6127 ATEDBGPRINT(RT_DEBUG_TRACE,("RACFG_CMD_RX_START\n"));
6128
6129 Set_ATE_Proc(pAdapter, "RXFRAME");
6130
6131 // prepare feedback
6132 pRaCfg->length = htons(2);
6133 pRaCfg->status = htons(0);
6134 wrq->u.data.length = sizeof(pRaCfg->magic_no) + sizeof(pRaCfg->command_type)
6135 + sizeof(pRaCfg->command_id) + sizeof(pRaCfg->length)
6136 + sizeof(pRaCfg->sequence) + ntohs(pRaCfg->length);
6137
6138 if (copy_to_user(wrq->u.data.pointer, pRaCfg, wrq->u.data.length))
6139 {
6140 ATEDBGPRINT(RT_DEBUG_ERROR, ("copy_to_user() fail in case RACFG_CMD_RX_START\n"));
6141 Status = -EFAULT;
6142 }
6143 else
6144 {
6145 ATEDBGPRINT(RT_DEBUG_TRACE, ("RACFG_CMD_RX_START is done !\n"));
6146 }
6147 }
6148 break;
6149 default:
6150 break;
6151 }
6152 ASSERT(pRaCfg != NULL);
6153 if (pRaCfg != NULL)
6154 {
6155 kfree(pRaCfg);
6156 }
6157 return;
6158 }
6159
6160 VOID BubbleSort(INT32 n, INT32 a[])
6161 {
6162 INT32 k, j, temp;
6163
6164 for (k = n-1; k>0; k--)
6165 {
6166 for (j = 0; j<k; j++)
6167 {
6168 if(a[j] > a[j+1])
6169 {
6170 temp = a[j];
6171 a[j]=a[j+1];
6172 a[j+1]=temp;
6173 }
6174 }
6175 }
6176 }
6177
6178 VOID CalNoiseLevel(PRTMP_ADAPTER pAd, UCHAR channel, INT32 RSSI[3][10])
6179 {
6180 INT32 RSSI0, RSSI1, RSSI2;
6181 CHAR Rssi0Offset, Rssi1Offset, Rssi2Offset;
6182 UCHAR BbpR50Rssi0 = 0, BbpR51Rssi1 = 0, BbpR52Rssi2 = 0;
6183 UCHAR Org_BBP66value = 0, Org_BBP69value = 0, Org_BBP70value = 0, data = 0;
6184 USHORT LNA_Gain = 0;
6185 INT32 j = 0;
6186 UCHAR Org_Channel = pAd->ate.Channel;
6187 USHORT GainValue = 0, OffsetValue = 0;
6188
6189 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &Org_BBP66value);
6190 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R69, &Org_BBP69value);
6191 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R70, &Org_BBP70value);
6192
6193 //**********************************************************************
6194 // Read the value of LNA gain and Rssi offset
6195 //**********************************************************************
6196 RT28xx_EEPROM_READ16(pAd, EEPROM_LNA_OFFSET, GainValue);
6197
6198 // for Noise Level
6199 if (channel <= 14)
6200 {
6201 LNA_Gain = GainValue & 0x00FF;
6202
6203 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET, OffsetValue);
6204 Rssi0Offset = OffsetValue & 0x00FF;
6205 Rssi1Offset = (OffsetValue & 0xFF00) >> 8;
6206 RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_BG_OFFSET + 2)/* 0x48 */, OffsetValue);
6207 Rssi2Offset = OffsetValue & 0x00FF;
6208 }
6209 else
6210 {
6211 LNA_Gain = (GainValue & 0xFF00) >> 8;
6212
6213 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_A_OFFSET, OffsetValue);
6214 Rssi0Offset = OffsetValue & 0x00FF;
6215 Rssi1Offset = (OffsetValue & 0xFF00) >> 8;
6216 RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_A_OFFSET + 2)/* 0x4C */, OffsetValue);
6217 Rssi2Offset = OffsetValue & 0x00FF;
6218 }
6219 //**********************************************************************
6220 {
6221 pAd->ate.Channel = channel;
6222 ATEAsicSwitchChannel(pAd);
6223 mdelay(5);
6224
6225 data = 0x10;
6226 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, data);
6227 data = 0x40;
6228 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, data);
6229 data = 0x40;
6230 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, data);
6231 mdelay(5);
6232
6233 // Start Rx
6234 pAd->ate.bQARxStart = TRUE;
6235 Set_ATE_Proc(pAd, "RXFRAME");
6236
6237 mdelay(5);
6238
6239 for (j = 0; j < 10; j++)
6240 {
6241 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R50, &BbpR50Rssi0);
6242 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R51, &BbpR51Rssi1);
6243 ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R52, &BbpR52Rssi2);
6244
6245 mdelay(10);
6246
6247 // Calculate RSSI 0
6248 if (BbpR50Rssi0 == 0)
6249 {
6250 RSSI0 = -100;
6251 }
6252 else
6253 {
6254 RSSI0 = (INT32)(-12 - BbpR50Rssi0 - LNA_Gain - Rssi0Offset);
6255 }
6256 RSSI[0][j] = RSSI0;
6257
6258 if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
6259 {
6260 // Calculate RSSI 1
6261 if (BbpR51Rssi1 == 0)
6262 {
6263 RSSI1 = -100;
6264 }
6265 else
6266 {
6267 RSSI1 = (INT32)(-12 - BbpR51Rssi1 - LNA_Gain - Rssi1Offset);
6268 }
6269 RSSI[1][j] = RSSI1;
6270 }
6271
6272 if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
6273 {
6274 // Calculate RSSI 2
6275 if (BbpR52Rssi2 == 0)
6276 RSSI2 = -100;
6277 else
6278 RSSI2 = (INT32)(-12 - BbpR52Rssi2 - LNA_Gain - Rssi2Offset);
6279
6280 RSSI[2][j] = RSSI2;
6281 }
6282 }
6283
6284 // Stop Rx
6285 Set_ATE_Proc(pAd, "RXSTOP");
6286
6287 mdelay(5);
6288
6289 BubbleSort(10, RSSI[0]); // 1R
6290
6291 if ( pAd->Antenna.field.RxPath >= 2 ) // 2R
6292 {
6293 BubbleSort(10, RSSI[1]);
6294 }
6295
6296 if ( pAd->Antenna.field.RxPath >= 3 ) // 3R
6297 {
6298 BubbleSort(10, RSSI[2]);
6299 }
6300
6301 }
6302
6303 pAd->ate.Channel = Org_Channel;
6304 ATEAsicSwitchChannel(pAd);
6305
6306 // Restore original value
6307 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Org_BBP66value);
6308 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, Org_BBP69value);
6309 ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, Org_BBP70value);
6310
6311 return;
6312 }
6313
6314 BOOLEAN SyncTxRxConfig(PRTMP_ADAPTER pAd, USHORT offset, UCHAR value)
6315 {
6316 UCHAR tmp = 0, bbp_data = 0;
6317
6318 if (ATE_ON(pAd))
6319 {
6320 ATE_BBP_IO_READ8_BY_REG_ID(pAd, offset, &bbp_data);
6321 }
6322 else
6323 {
6324 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, offset, &bbp_data);
6325 }
6326
6327 /* confirm again */
6328 ASSERT(bbp_data == value);
6329
6330 switch(offset)
6331 {
6332 case BBP_R1:
6333 /* Need to sync. tx configuration with legacy ATE. */
6334 tmp = (bbp_data & ((1 << 4) | (1 << 3))/* 0x18 */) >> 3;
6335 switch(tmp)
6336 {
6337 /* The BBP R1 bit[4:3] = 2 :: Both DACs will be used by QA. */
6338 case 2:
6339 /* All */
6340 pAd->ate.TxAntennaSel = 0;
6341 break;
6342 /* The BBP R1 bit[4:3] = 0 :: DAC 0 will be used by QA. */
6343 case 0:
6344 /* Antenna one */
6345 pAd->ate.TxAntennaSel = 1;
6346 break;
6347 /* The BBP R1 bit[4:3] = 1 :: DAC 1 will be used by QA. */
6348 case 1:
6349 /* Antenna two */
6350 pAd->ate.TxAntennaSel = 2;
6351 break;
6352 default:
6353 DBGPRINT(RT_DEBUG_TRACE, ("%s -- Sth. wrong! : return FALSE; \n", __FUNCTION__));
6354 return FALSE;
6355 }
6356 break;/* case BBP_R1 */
6357
6358 case BBP_R3:
6359 /* Need to sync. rx configuration with legacy ATE. */
6360 tmp = (bbp_data & ((1 << 1) | (1 << 0))/* 0x03 */);
6361 switch(tmp)
6362 {
6363 /* The BBP R3 bit[1:0] = 3 :: All ADCs will be used by QA. */
6364 case 3:
6365 /* All */
6366 pAd->ate.RxAntennaSel = 0;
6367 break;
6368 /* The BBP R3 bit[1:0] = 0 :: ADC 0 will be used by QA, */
6369 /* unless the BBP R3 bit[4:3] = 2 */
6370 case 0:
6371 /* Antenna one */
6372 pAd->ate.RxAntennaSel = 1;
6373 tmp = ((bbp_data & ((1 << 4) | (1 << 3))/* 0x03 */) >> 3);
6374 if (tmp == 2)// 3R
6375 {
6376 /* Default : All ADCs will be used by QA */
6377 pAd->ate.RxAntennaSel = 0;
6378 }
6379 break;
6380 /* The BBP R3 bit[1:0] = 1 :: ADC 1 will be used by QA. */
6381 case 1:
6382 /* Antenna two */
6383 pAd->ate.RxAntennaSel = 2;
6384 break;
6385 /* The BBP R3 bit[1:0] = 2 :: ADC 2 will be used by QA. */
6386 case 2:
6387 /* Antenna three */
6388 pAd->ate.RxAntennaSel = 3;
6389 break;
6390 default:
6391 DBGPRINT(RT_DEBUG_ERROR, ("%s -- Impossible! : return FALSE; \n", __FUNCTION__));
6392 return FALSE;
6393 }
6394 break;/* case BBP_R3 */
6395
6396 default:
6397 DBGPRINT(RT_DEBUG_ERROR, ("%s -- Sth. wrong! : return FALSE; \n", __FUNCTION__));
6398 return FALSE;
6399
6400 }
6401 return TRUE;
6402 }
6403
6404 static VOID memcpy_exl(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len)
6405 {
6406 ULONG i, Value = 0;
6407 ULONG *pDst, *pSrc;
6408 UCHAR *p8;
6409
6410 p8 = src;
6411 pDst = (ULONG *) dst;
6412 pSrc = (ULONG *) src;
6413
6414 for (i = 0 ; i < (len/4); i++)
6415 {
6416 /* For alignment issue, we need a variable "Value". */
6417 memmove(&Value, pSrc, 4);
6418 Value = htonl(Value);
6419 memmove(pDst, &Value, 4);
6420 pDst++;
6421 pSrc++;
6422 }
6423 if ((len % 4) != 0)
6424 {
6425 /* wish that it will never reach here */
6426 memmove(&Value, pSrc, (len % 4));
6427 Value = htonl(Value);
6428 memmove(pDst, &Value, (len % 4));
6429 }
6430 }
6431
6432 static VOID memcpy_exs(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, ULONG len)
6433 {
6434 ULONG i;
6435 UCHAR *pDst, *pSrc;
6436
6437 pDst = dst;
6438 pSrc = src;
6439
6440 for (i = 0; i < (len/2); i++)
6441 {
6442 memmove(pDst, pSrc, 2);
6443 *((USHORT *)pDst) = htons(*((USHORT *)pDst));
6444 pDst+=2;
6445 pSrc+=2;
6446 }
6447
6448 if ((len % 2) != 0)
6449 {
6450 memmove(pDst, pSrc, 1);
6451 }
6452 }
6453
6454 static VOID RTMP_IO_READ_BULK(PRTMP_ADAPTER pAd, UCHAR *dst, UCHAR *src, UINT32 len)
6455 {
6456 UINT32 i, Value;
6457 UINT32 *pDst, *pSrc;
6458
6459 pDst = (UINT32 *) dst;
6460 pSrc = (UINT32 *) src;
6461
6462 for (i = 0 ; i < (len/4); i++)
6463 {
6464 RTMP_IO_READ32(pAd, (ULONG)pSrc, &Value);
6465 Value = htonl(Value);
6466 memmove(pDst, &Value, 4);
6467 pDst++;
6468 pSrc++;
6469 }
6470 return;
6471 }
6472
6473 INT Set_TxStop_Proc(
6474 IN PRTMP_ADAPTER pAd,
6475 IN PUCHAR arg)
6476 {
6477 ATEDBGPRINT(RT_DEBUG_TRACE,("Set_TxStop_Proc\n"));
6478
6479 if (Set_ATE_Proc(pAd, "TXSTOP"))
6480 {
6481 return TRUE;
6482 }
6483 else
6484 {
6485 return FALSE;
6486 }
6487 }
6488
6489 INT Set_RxStop_Proc(
6490 IN PRTMP_ADAPTER pAd,
6491 IN PUCHAR arg)
6492 {
6493 ATEDBGPRINT(RT_DEBUG_TRACE,("Set_RxStop_Proc\n"));
6494
6495 if (Set_ATE_Proc(pAd, "RXSTOP"))
6496 {
6497 return TRUE;
6498 }
6499 else
6500 {
6501 return FALSE;
6502 }
6503 }
6504 #endif // RALINK_28xx_QA //
6505 #endif // RALINK_ATE //
6506
x86 "subsystem" repository