3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
25 #include <linux/config.h>
29 #include <asm/pgtable.h>
30 #include <asm/cputable.h>
31 #include <asm/cache.h>
32 #include <asm/thread_info.h>
33 #include <asm/ppc_asm.h>
34 #include <asm/asm-offsets.h>
37 #include <asm/amigappc.h>
40 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
41 #define LOAD_BAT(n, reg, RA, RB) \
42 /* see the comment for clear_bats() -- Cort */ \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_DBAT##n##U,RA; \
46 lwz RA,(n*16)+0(reg); \
47 lwz RB,(n*16)+4(reg); \
48 mtspr SPRN_IBAT##n##U,RA; \
49 mtspr SPRN_IBAT##n##L,RB; \
51 lwz RA,(n*16)+8(reg); \
52 lwz RB,(n*16)+12(reg); \
53 mtspr SPRN_DBAT##n##U,RA; \
54 mtspr SPRN_DBAT##n##L,RB; \
58 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
59 .stabs "head_32.S",N_SO,0,0,0f
65 * _start is defined this way because the XCOFF loader in the OpenFirmware
66 * on the powermac expects the entry point to be a procedure descriptor.
72 * These are here for legacy reasons, the kernel used to
73 * need to look like a coff function entry for the pmac
74 * but we're always started by some kind of bootloader now.
77 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
78 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
82 * Enter here with the kernel text, data and bss loaded starting at
83 * 0, running with virtual == physical mapping.
84 * r5 points to the prom entry point (the client interface handler
85 * address). Address translation is turned on, with the prom
86 * managing the hash table. Interrupts are disabled. The stack
87 * pointer (r1) points to just below the end of the half-meg region
88 * from 0x380000 - 0x400000, which is mapped in already.
90 * If we are booted from MacOS via BootX, we enter with the kernel
91 * image loaded somewhere, and the following values in registers:
92 * r3: 'BooX' (0x426f6f58)
93 * r4: virtual address of boot_infos_t
98 * r4: physical address of memory base
99 * Linux/m68k style BootInfo structure at &_end.
102 * This is jumped to on prep systems right after the kernel is relocated
103 * to its proper place in memory by the boot loader. The expected layout
105 * r3: ptr to residual data
106 * r4: initrd_start or if no initrd then 0
107 * r5: initrd_end - unused if r4 is 0
108 * r6: Start of command line string
109 * r7: End of command line string
111 * This just gets a minimal mmu environment setup so we can call
112 * start_here() to do the real work.
119 * We have to do any OF calls before we map ourselves to KERNELBASE,
120 * because OF may have I/O devices mapped into that area
121 * (particularly on CHRP).
129 * Check for BootX signature when supporting PowerMac and branch to
130 * appropriate trampoline if it's present
132 #ifdef CONFIG_PPC_PMAC
139 #endif /* CONFIG_PPC_PMAC */
141 1: mr r31,r3 /* save parameters */
146 * early_init() does the early machine identification and does
147 * the necessary low-level setup and clears the BSS
148 * -- Cort <cort@fsmlabs.com>
153 /* On APUS the __va/__pa constants need to be set to the correct
154 * values before continuing.
158 #endif /* CONFIG_APUS */
160 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
161 * the physical address we are running at, returned by early_init()
169 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
174 * Call setup_cpu for CPU 0 and initialize 6xx Idle
178 bl call_setup_cpu /* Call setup_cpu for this CPU */
182 #endif /* CONFIG_6xx */
187 * We need to run with _start at physical address 0.
188 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
189 * the exception vectors at 0 (and therefore this copy
190 * overwrites OF's exception vectors with our own).
191 * The MMU is off at this point.
195 addis r4,r3,KERNELBASE@h /* current address of _start */
196 cmpwi 0,r4,0 /* are we already running at 0? */
198 #endif /* CONFIG_APUS */
200 * we now have the 1st 16M of ram mapped with the bats.
201 * prep needs the mmu to be turned on here, but pmac already has it on.
202 * this shouldn't bother the pmac since it just gets turned on again
203 * as we jump to our code at KERNELBASE. -- Cort
204 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
205 * off, and in other cases, we now turn it off before changing BATs above.
209 ori r0,r0,MSR_DR|MSR_IR
212 ori r0,r0,start_here@l
215 RFI /* enables MMU */
218 * We need __secondary_hold as a place to hold the other cpus on
219 * an SMP machine, even when we are running a UP kernel.
221 . = 0xc0 /* for prep bootloader */
222 li r3,1 /* MTX only has 1 cpu */
223 .globl __secondary_hold
225 /* tell the master we're here */
226 stw r3,__secondary_hold_acknowledge@l(0)
229 /* wait until we're told to start */
232 /* our cpu # was at addr 0 - go */
233 mr r24,r3 /* cpu # */
237 #endif /* CONFIG_SMP */
239 .globl __secondary_hold_spinloop
240 __secondary_hold_spinloop:
242 .globl __secondary_hold_acknowledge
243 __secondary_hold_acknowledge:
247 * Exception entry code. This code runs with address translation
248 * turned off, i.e. using physical addresses.
249 * We assume sprg3 has the physical address of the current
250 * task's thread_struct.
252 #define EXCEPTION_PROLOG \
253 mtspr SPRN_SPRG0,r10; \
254 mtspr SPRN_SPRG1,r11; \
256 EXCEPTION_PROLOG_1; \
259 #define EXCEPTION_PROLOG_1 \
260 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
261 andi. r11,r11,MSR_PR; \
262 tophys(r11,r1); /* use tophys(r1) if kernel */ \
264 mfspr r11,SPRN_SPRG3; \
265 lwz r11,THREAD_INFO-THREAD(r11); \
266 addi r11,r11,THREAD_SIZE; \
268 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
271 #define EXCEPTION_PROLOG_2 \
273 stw r10,_CCR(r11); /* save registers */ \
274 stw r12,GPR12(r11); \
276 mfspr r10,SPRN_SPRG0; \
277 stw r10,GPR10(r11); \
278 mfspr r12,SPRN_SPRG1; \
279 stw r12,GPR11(r11); \
281 stw r10,_LINK(r11); \
282 mfspr r12,SPRN_SRR0; \
283 mfspr r9,SPRN_SRR1; \
286 tovirt(r1,r11); /* set new kernel sp */ \
287 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
288 MTMSRD(r10); /* (except for mach check in rtas) */ \
290 lis r10,0x7265; /* put exception frame marker */ \
291 addi r10,r10,0x6773; \
293 SAVE_4GPRS(3, r11); \
297 * Note: code which follows this uses cr0.eq (set if from kernel),
298 * r11, r12 (SRR0), and r9 (SRR1).
300 * Note2: once we have set r1 we are in a position to take exceptions
301 * again, and we could thus set MSR:RI at that point.
307 #define EXCEPTION(n, label, hdlr, xfer) \
311 addi r3,r1,STACK_FRAME_OVERHEAD; \
314 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
316 stw r10,_TRAP(r11); \
324 #define COPY_EE(d, s) rlwimi d,s,0,16,16
327 #define EXC_XFER_STD(n, hdlr) \
328 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
329 ret_from_except_full)
331 #define EXC_XFER_LITE(n, hdlr) \
332 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
335 #define EXC_XFER_EE(n, hdlr) \
336 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
337 ret_from_except_full)
339 #define EXC_XFER_EE_LITE(n, hdlr) \
340 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
344 /* core99 pmac starts the seconary here by changing the vector, and
345 putting it back to what it was (unknown_exception) when done. */
346 #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
348 b __secondary_start_gemini
350 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
355 * On CHRP, this is complicated by the fact that we could get a
356 * machine check inside RTAS, and we have no guarantee that certain
357 * critical registers will have the values we expect. The set of
358 * registers that might have bad values includes all the GPRs
359 * and all the BATs. We indicate that we are in RTAS by putting
360 * a non-zero value, the address of the exception frame to use,
361 * in SPRG2. The machine check handler checks SPRG2 and uses its
362 * value if it is non-zero. If we ever needed to free up SPRG2,
363 * we could use a field in the thread_info or thread_struct instead.
364 * (Other exception handlers assume that r1 is a valid kernel stack
365 * pointer when we take an exception from supervisor mode.)
372 #ifdef CONFIG_PPC_CHRP
376 #endif /* CONFIG_PPC_CHRP */
378 7: EXCEPTION_PROLOG_2
379 addi r3,r1,STACK_FRAME_OVERHEAD
380 #ifdef CONFIG_PPC_CHRP
385 EXC_XFER_STD(0x200, machine_check_exception)
386 #ifdef CONFIG_PPC_CHRP
387 1: b machine_check_in_rtas
390 /* Data access exception. */
395 andis. r0,r10,0xa470 /* weird error? */
396 bne 1f /* if not, try to put a PTE */
397 mfspr r4,SPRN_DAR /* into the hash table */
398 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
400 1: stw r10,_DSISR(r11)
403 EXC_XFER_EE_LITE(0x300, handle_page_fault)
406 /* Instruction access exception. */
410 andis. r0,r9,0x4000 /* no pte found? */
411 beq 1f /* if so, try to put a PTE */
412 li r3,0 /* into the hash table */
413 mr r4,r12 /* SRR0 is fault address */
417 EXC_XFER_EE_LITE(0x400, handle_page_fault)
419 /* External interrupt */
420 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
422 /* Alignment exception */
430 addi r3,r1,STACK_FRAME_OVERHEAD
431 EXC_XFER_EE(0x600, alignment_exception)
433 /* Program check exception */
434 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
436 /* Floating-point unavailable */
440 bne load_up_fpu /* if from user, just load it up */
441 addi r3,r1,STACK_FRAME_OVERHEAD
442 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
445 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
447 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
448 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
454 EXC_XFER_EE_LITE(0xc00, DoSyscall)
456 /* Single step - not used on 601 */
457 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
458 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
461 * The Altivec unavailable trap is at 0x0f20. Foo.
462 * We effectively remap it to 0x3000.
463 * We include an altivec unavailable exception vector even if
464 * not configured for Altivec, so that you can't panic a
465 * non-altivec kernel running on a machine with altivec just
466 * by executing an altivec instruction.
476 addi r3,r1,STACK_FRAME_OVERHEAD
477 EXC_XFER_EE(0xf00, unknown_exception)
480 * Handle TLB miss for instruction on 603/603e.
481 * Note: we get an alternate set of r0 - r3 to use automatically.
487 * r1: linux style pte ( later becomes ppc hardware pte )
488 * r2: ptr to linux-style pte
492 /* Get PTE (linux-style) and check access */
494 lis r1,KERNELBASE@h /* check if kernel address */
497 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
500 lis r2,swapper_pg_dir@ha /* if kernel address, use */
501 addi r2,r2,swapper_pg_dir@l /* kernel page table */
502 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
503 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
505 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
506 lwz r2,0(r2) /* get pmd entry */
507 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
508 beq- InstructionAddressInvalid /* return if no mapping */
509 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
510 lwz r3,0(r2) /* get linux-style pte */
511 andc. r1,r1,r3 /* check access & ~permission */
512 bne- InstructionAddressInvalid /* return if access not permitted */
513 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
515 * NOTE! We are assuming this is not an SMP system, otherwise
516 * we would need to update the pte atomically with lwarx/stwcx.
518 stw r3,0(r2) /* update PTE (accessed bit) */
519 /* Convert linux-style PTE to low word of PPC-style PTE */
520 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
521 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
522 and r1,r1,r2 /* writable if _RW and _DIRTY */
523 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
524 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
525 ori r1,r1,0xe14 /* clear out reserved bits and M */
526 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
530 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
533 InstructionAddressInvalid:
535 rlwinm r1,r3,9,6,6 /* Get load/store bit */
538 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
539 mtctr r0 /* Restore CTR */
540 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
543 mfspr r1,SPRN_IMISS /* Get failing address */
544 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
545 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
547 mtspr SPRN_DAR,r1 /* Set fault address */
548 mfmsr r0 /* Restore "normal" registers */
549 xoris r0,r0,MSR_TGPR>>16
550 mtcrf 0x80,r3 /* Restore CR0 */
555 * Handle TLB miss for DATA Load operation on 603/603e
561 * r1: linux style pte ( later becomes ppc hardware pte )
562 * r2: ptr to linux-style pte
566 /* Get PTE (linux-style) and check access */
568 lis r1,KERNELBASE@h /* check if kernel address */
571 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
574 lis r2,swapper_pg_dir@ha /* if kernel address, use */
575 addi r2,r2,swapper_pg_dir@l /* kernel page table */
576 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
577 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
579 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
580 lwz r2,0(r2) /* get pmd entry */
581 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
582 beq- DataAddressInvalid /* return if no mapping */
583 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
584 lwz r3,0(r2) /* get linux-style pte */
585 andc. r1,r1,r3 /* check access & ~permission */
586 bne- DataAddressInvalid /* return if access not permitted */
587 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
589 * NOTE! We are assuming this is not an SMP system, otherwise
590 * we would need to update the pte atomically with lwarx/stwcx.
592 stw r3,0(r2) /* update PTE (accessed bit) */
593 /* Convert linux-style PTE to low word of PPC-style PTE */
594 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
595 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
596 and r1,r1,r2 /* writable if _RW and _DIRTY */
597 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
598 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
599 ori r1,r1,0xe14 /* clear out reserved bits and M */
600 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
604 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
609 rlwinm r1,r3,9,6,6 /* Get load/store bit */
612 mtctr r0 /* Restore CTR */
613 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
615 mfspr r1,SPRN_DMISS /* Get failing address */
616 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
617 beq 20f /* Jump if big endian */
619 20: mtspr SPRN_DAR,r1 /* Set fault address */
620 mfmsr r0 /* Restore "normal" registers */
621 xoris r0,r0,MSR_TGPR>>16
622 mtcrf 0x80,r3 /* Restore CR0 */
627 * Handle TLB miss for DATA Store on 603/603e
633 * r1: linux style pte ( later becomes ppc hardware pte )
634 * r2: ptr to linux-style pte
638 /* Get PTE (linux-style) and check access */
640 lis r1,KERNELBASE@h /* check if kernel address */
643 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
646 lis r2,swapper_pg_dir@ha /* if kernel address, use */
647 addi r2,r2,swapper_pg_dir@l /* kernel page table */
648 mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
649 rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
651 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
652 lwz r2,0(r2) /* get pmd entry */
653 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
654 beq- DataAddressInvalid /* return if no mapping */
655 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
656 lwz r3,0(r2) /* get linux-style pte */
657 andc. r1,r1,r3 /* check access & ~permission */
658 bne- DataAddressInvalid /* return if access not permitted */
659 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
661 * NOTE! We are assuming this is not an SMP system, otherwise
662 * we would need to update the pte atomically with lwarx/stwcx.
664 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
665 /* Convert linux-style PTE to low word of PPC-style PTE */
666 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
667 li r1,0xe15 /* clear out reserved bits and M */
668 andc r1,r3,r1 /* PP = user? 2: 0 */
672 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
676 #ifndef CONFIG_ALTIVEC
677 #define altivec_assist_exception unknown_exception
680 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
681 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
682 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
684 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
685 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
686 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
687 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
688 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
689 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
690 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
691 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
692 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
693 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
694 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
695 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
696 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
697 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
698 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
699 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
700 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
701 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
702 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
703 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
704 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
705 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
706 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
707 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
708 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
710 .globl mol_trampoline
711 .set mol_trampoline, i0x2f00
717 #ifdef CONFIG_ALTIVEC
718 bne load_up_altivec /* if from user, just load it up */
719 #endif /* CONFIG_ALTIVEC */
720 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
722 #ifdef CONFIG_ALTIVEC
723 /* Note that the AltiVec support is closely modeled after the FP
724 * support. Changes to one are likely to be applicable to the
728 * Disable AltiVec for the task which had AltiVec previously,
729 * and save its AltiVec registers in its thread_struct.
730 * Enables AltiVec for use in the kernel on return.
731 * On SMP we know the AltiVec units are free, since we give it up every
736 MTMSRD(r5) /* enable use of AltiVec now */
739 * For SMP, we don't do lazy AltiVec switching because it just gets too
740 * horrendously complex, especially when a task switches from one CPU
741 * to another. Instead we call giveup_altivec in switch_to.
745 addis r3,r6,last_task_used_altivec@ha
746 lwz r4,last_task_used_altivec@l(r3)
750 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
757 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
759 andc r4,r4,r10 /* disable altivec for previous task */
760 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
762 #endif /* CONFIG_SMP */
763 /* enable use of AltiVec after return */
765 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
768 stw r4,THREAD_USED_VR(r5)
775 stw r4,last_task_used_altivec@l(r3)
776 #endif /* CONFIG_SMP */
777 /* restore registers and return */
778 /* we haven't used ctr or xer or lr */
779 b fast_exception_return
782 * AltiVec unavailable trap from kernel - print a message, but let
783 * the task use AltiVec in the kernel until it returns to user mode.
788 stw r3,_MSR(r1) /* enable use of AltiVec after return */
791 mr r4,r2 /* current */
795 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
799 * giveup_altivec(tsk)
800 * Disable AltiVec for the task given as the argument,
801 * and save the AltiVec registers in its thread_struct.
802 * Enables AltiVec for use in the kernel on return.
805 .globl giveup_altivec
810 MTMSRD(r5) /* enable use of AltiVec now */
813 beqlr- /* if no previous owner, done */
814 addi r3,r3,THREAD /* want THREAD of task */
817 SAVE_32VRS(0, r4, r3)
822 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
824 andc r4,r4,r3 /* disable AltiVec for previous task */
825 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
829 lis r4,last_task_used_altivec@ha
830 stw r5,last_task_used_altivec@l(r4)
831 #endif /* CONFIG_SMP */
833 #endif /* CONFIG_ALTIVEC */
836 * This code is jumped to from the startup code to copy
837 * the kernel image to physical address 0.
840 addis r9,r26,klimit@ha /* fetch klimit */
842 addis r25,r25,-KERNELBASE@h
843 li r3,0 /* Destination base address */
844 li r6,0 /* Destination offset */
845 li r5,0x4000 /* # bytes of memory to copy */
846 bl copy_and_flush /* copy the first 0x4000 bytes */
847 addi r0,r3,4f@l /* jump to the address of 4f */
848 mtctr r0 /* in copy and do the rest. */
849 bctr /* jump to the copy */
851 bl copy_and_flush /* copy the rest */
855 * Copy routine used to copy the kernel to start at physical address 0
856 * and flush and invalidate the caches as needed.
857 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
858 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
860 _GLOBAL(copy_and_flush)
863 4: li r0,L1_CACHE_BYTES/4
865 3: addi r6,r6,4 /* copy a cache line */
869 dcbst r6,r3 /* write it to memory */
871 icbi r6,r3 /* flush the icache line */
874 sync /* additional sync needed on g4 */
882 * On APUS the physical base address of the kernel is not known at compile
883 * time, which means the __pa/__va constants used are incorrect. In the
884 * __init section is recorded the virtual addresses of instructions using
885 * these constants, so all that has to be done is fix these before
886 * continuing the kernel boot.
888 * r4 = The physical address of the kernel base.
892 addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */
893 neg r11,r10 /* phys_to_virt constant */
895 lis r12,__vtop_table_begin@h
896 ori r12,r12,__vtop_table_begin@l
897 add r12,r12,r10 /* table begin phys address */
898 lis r13,__vtop_table_end@h
899 ori r13,r13,__vtop_table_end@l
900 add r13,r13,r10 /* table end phys address */
903 1: lwzu r14,4(r12) /* virt address of instruction */
904 add r14,r14,r10 /* phys address of instruction */
905 lwz r15,0(r14) /* instruction, now insert top */
906 rlwimi r15,r10,16,16,31 /* half of vp const in low half */
907 stw r15,0(r14) /* of instruction and restore. */
908 dcbst r0,r14 /* write it to memory */
910 icbi r0,r14 /* flush the icache line */
913 sync /* additional sync needed on g4 */
917 * Map the memory where the exception handlers will
918 * be copied to when hash constants have been patched.
920 #ifdef CONFIG_APUS_FAST_EXCEPT
925 ori r8,r8,0x2 /* 128KB, supervisor */
929 lis r12,__ptov_table_begin@h
930 ori r12,r12,__ptov_table_begin@l
931 add r12,r12,r10 /* table begin phys address */
932 lis r13,__ptov_table_end@h
933 ori r13,r13,__ptov_table_end@l
934 add r13,r13,r10 /* table end phys address */
937 1: lwzu r14,4(r12) /* virt address of instruction */
938 add r14,r14,r10 /* phys address of instruction */
939 lwz r15,0(r14) /* instruction, now insert top */
940 rlwimi r15,r11,16,16,31 /* half of pv const in low half*/
941 stw r15,0(r14) /* of instruction and restore. */
942 dcbst r0,r14 /* write it to memory */
944 icbi r0,r14 /* flush the icache line */
948 sync /* additional sync needed on g4 */
949 isync /* No speculative loading until now */
952 /***********************************************************************
953 * Please note that on APUS the exception handlers are located at the
954 * physical address 0xfff0000. For this reason, the exception handlers
955 * cannot use relative branches to access the code below.
956 ***********************************************************************/
957 #endif /* CONFIG_APUS */
961 .globl __secondary_start_gemini
962 __secondary_start_gemini:
971 #endif /* CONFIG_GEMINI */
973 .globl __secondary_start_pmac_0
974 __secondary_start_pmac_0:
975 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
984 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
985 set to map the 0xf0000000 - 0xffffffff region */
987 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
992 .globl __secondary_start
994 /* Copy some CPU settings from CPU 0 */
995 bl __restore_cpu_setup
999 bl call_setup_cpu /* Call setup_cpu for this CPU */
1001 lis r3,-KERNELBASE@h
1003 #endif /* CONFIG_6xx */
1005 /* get current_thread_info and current */
1006 lis r1,secondary_ti@ha
1008 lwz r1,secondary_ti@l(r1)
1013 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1018 /* load up the MMU */
1021 /* ptr to phys current thread */
1023 addi r4,r4,THREAD /* phys address of our thread_struct */
1027 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1029 /* enable MMU and jump to start_secondary */
1032 lis r3,start_secondary@h
1033 ori r3,r3,start_secondary@l
1038 #endif /* CONFIG_SMP */
1041 * Those generic dummy functions are kept for CPUs not
1042 * included in CONFIG_6xx
1044 #if !defined(CONFIG_6xx)
1045 _GLOBAL(__save_cpu_setup)
1047 _GLOBAL(__restore_cpu_setup)
1049 #endif /* !defined(CONFIG_6xx) */
1053 * Load stuff into the MMU. Intended to be called with
1057 sync /* Force all PTE updates to finish */
1059 tlbia /* Clear all TLB entries */
1060 sync /* wait for tlbia/tlbie to finish */
1061 TLBSYNC /* ... on all CPUs */
1062 /* Load the SDR1 register (hash table base & size) */
1067 li r0,16 /* load up segment register values */
1068 mtctr r0 /* for context 0 */
1069 lis r3,0x2000 /* Ku = 1, VSID = 0 */
1072 addi r3,r3,0x111 /* increment VSID */
1073 addis r4,r4,0x1000 /* address of next segment */
1076 /* Load the BAT registers with the values set up by MMU_init.
1077 MMU_init takes care of whether we're on a 601 or not. */
1084 LOAD_BAT(0,r3,r4,r5)
1085 LOAD_BAT(1,r3,r4,r5)
1086 LOAD_BAT(2,r3,r4,r5)
1087 LOAD_BAT(3,r3,r4,r5)
1092 * This is where the main kernel code starts.
1095 /* ptr to current */
1097 ori r2,r2,init_task@l
1098 /* Set up for using our exception vectors */
1099 /* ptr to phys current thread */
1101 addi r4,r4,THREAD /* init task's THREAD */
1105 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1108 lis r1,init_thread_union@ha
1109 addi r1,r1,init_thread_union@l
1111 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1113 * Do early platform-specific initialization,
1114 * and set up the MMU.
1123 /* Copy exception code to exception vector base on APUS. */
1125 #ifdef CONFIG_APUS_FAST_EXCEPT
1126 lis r3,0xfff0 /* Copy to 0xfff00000 */
1128 lis r3,0 /* Copy to 0x00000000 */
1130 li r5,0x4000 /* # bytes of memory to copy */
1132 bl copy_and_flush /* copy the first 0x4000 bytes */
1133 #endif /* CONFIG_APUS */
1136 * Go back to running unmapped so we can load up new values
1137 * for SDR1 (hash table pointer) and the segment registers
1138 * and change to using our exception vectors.
1143 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1149 /* Load up the kernel context */
1152 #ifdef CONFIG_BDI_SWITCH
1153 /* Add helper information for the Abatron bdiGDB debugger.
1154 * We do this here because we know the mmu is disabled, and
1155 * will be enabled for real in just a few instructions.
1157 lis r5, abatron_pteptrs@h
1158 ori r5, r5, abatron_pteptrs@l
1159 stw r5, 0xf0(r0) /* This much match your Abatron config */
1160 lis r6, swapper_pg_dir@h
1161 ori r6, r6, swapper_pg_dir@l
1164 #endif /* CONFIG_BDI_SWITCH */
1166 /* Now turn on the MMU for real! */
1169 lis r3,start_kernel@h
1170 ori r3,r3,start_kernel@l
1177 * Set up the segment registers for a new context.
1179 _GLOBAL(set_context)
1180 mulli r3,r3,897 /* multiply context by skew factor */
1181 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1182 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1183 li r0,NUM_USER_SEGMENTS
1186 #ifdef CONFIG_BDI_SWITCH
1187 /* Context switch the PTE pointer for the Abatron BDI2000.
1188 * The PGDIR is passed as second argument.
1190 lis r5, KERNELBASE@h
1198 addi r3,r3,0x111 /* next VSID */
1199 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1200 addis r4,r4,0x1000 /* address of next segment */
1207 * An undocumented "feature" of 604e requires that the v bit
1208 * be cleared before changing BAT values.
1210 * Also, newer IBM firmware does not clear bat3 and 4 so
1211 * this makes sure it's done.
1217 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1221 mtspr SPRN_DBAT0U,r10
1222 mtspr SPRN_DBAT0L,r10
1223 mtspr SPRN_DBAT1U,r10
1224 mtspr SPRN_DBAT1L,r10
1225 mtspr SPRN_DBAT2U,r10
1226 mtspr SPRN_DBAT2L,r10
1227 mtspr SPRN_DBAT3U,r10
1228 mtspr SPRN_DBAT3L,r10
1230 mtspr SPRN_IBAT0U,r10
1231 mtspr SPRN_IBAT0L,r10
1232 mtspr SPRN_IBAT1U,r10
1233 mtspr SPRN_IBAT1L,r10
1234 mtspr SPRN_IBAT2U,r10
1235 mtspr SPRN_IBAT2L,r10
1236 mtspr SPRN_IBAT3U,r10
1237 mtspr SPRN_IBAT3L,r10
1239 /* Here's a tweak: at this point, CPU setup have
1240 * not been called yet, so HIGH_BAT_EN may not be
1241 * set in HID0 for the 745x processors. However, it
1242 * seems that doesn't affect our ability to actually
1243 * write to these SPRs.
1245 mtspr SPRN_DBAT4U,r10
1246 mtspr SPRN_DBAT4L,r10
1247 mtspr SPRN_DBAT5U,r10
1248 mtspr SPRN_DBAT5L,r10
1249 mtspr SPRN_DBAT6U,r10
1250 mtspr SPRN_DBAT6L,r10
1251 mtspr SPRN_DBAT7U,r10
1252 mtspr SPRN_DBAT7L,r10
1253 mtspr SPRN_IBAT4U,r10
1254 mtspr SPRN_IBAT4L,r10
1255 mtspr SPRN_IBAT5U,r10
1256 mtspr SPRN_IBAT5L,r10
1257 mtspr SPRN_IBAT6U,r10
1258 mtspr SPRN_IBAT6L,r10
1259 mtspr SPRN_IBAT7U,r10
1260 mtspr SPRN_IBAT7L,r10
1261 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1266 1: addic. r10, r10, -0x1000
1273 addi r4, r3, __after_mmu_off - _start
1275 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1284 * Use the first pair of BAT registers to map the 1st 16MB
1285 * of RAM to KERNELBASE. From this point on we can't safely
1289 lis r11,KERNELBASE@h
1291 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1294 ori r11,r11,4 /* set up BAT registers for 601 */
1295 li r8,0x7f /* valid, block length = 8MB */
1296 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1297 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1298 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1299 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1300 mtspr SPRN_IBAT1U,r9
1301 mtspr SPRN_IBAT1L,r10
1307 ori r8,r8,0x12 /* R/W access, M=1 */
1309 ori r8,r8,2 /* R/W access */
1310 #endif /* CONFIG_SMP */
1312 ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */
1314 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1315 #endif /* CONFIG_APUS */
1317 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1318 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1319 mtspr SPRN_IBAT0L,r8
1320 mtspr SPRN_IBAT0U,r11
1325 #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT)
1328 * setup the display bat prepared for us in prom.c
1333 addis r8,r3,disp_BAT@ha
1334 addi r8,r8,disp_BAT@l
1340 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1343 mtspr SPRN_DBAT3L,r8
1344 mtspr SPRN_DBAT3U,r11
1346 1: mtspr SPRN_IBAT3L,r8
1347 mtspr SPRN_IBAT3U,r11
1349 #endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */
1352 /* Jump into the system reset for the rom.
1353 * We first disable the MMU, and then jump to the ROM reset address.
1355 * r3 is the board info structure, r4 is the location for starting.
1356 * I use this for building a small kernel that can load other kernels,
1357 * rather than trying to write or rely on a rom monitor that can tftp load.
1362 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1366 mfspr r11, SPRN_HID0
1368 ori r10,r10,HID0_ICE|HID0_DCE
1370 mtspr SPRN_HID0, r11
1372 li r5, MSR_ME|MSR_RI
1374 addis r6,r6,-KERNELBASE@h
1388 * We put a few things here that have to be page-aligned.
1389 * This stuff goes at the beginning of the data segment,
1390 * which is page-aligned.
1395 .globl empty_zero_page
1399 .globl swapper_pg_dir
1404 * This space gets a copy of optional info passed to us by the bootstrap
1405 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1411 .globl intercept_table
1413 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1414 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1415 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1416 .long 0, 0, 0, 0, 0, 0, 0, 0
1417 .long 0, 0, 0, 0, 0, 0, 0, 0
1418 .long 0, 0, 0, 0, 0, 0, 0, 0
1420 /* Room for two PTE pointers, usually the kernel and current user pointers
1421 * to their respective root page table.