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Automatic merge of /spare/repo/linux-2.6/.git branch HEAD
[linux-2.6/x86.git] / drivers / scsi / ata_piix.c
blob3be546439252332131fac6aca81cbdea71d9934a
1 /*
2
3 ata_piix.c - Intel PATA/SATA controllers
4
5 Maintained by: Jeff Garzik <jgarzik@pobox.com>
6 Please ALWAYS copy linux-ide@vger.kernel.org
7 on emails.
8
9
10 Copyright 2003-2004 Red Hat Inc
11 Copyright 2003-2004 Jeff Garzik
12
13
14 Copyright header from piix.c:
15
16 Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
17 Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
18 Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
19
20 May be copied or modified under the terms of the GNU General Public License
21
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include "scsi.h"
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
33
34 #define DRV_NAME "ata_piix"
35 #define DRV_VERSION "1.03"
36
37 enum {
38 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
39 ICH5_PMR = 0x90, /* port mapping register */
40 ICH5_PCS = 0x92, /* port control and status */
41
42 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
43 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
44 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
45
46 /* combined mode. if set, PATA is channel 0.
47 * if clear, PATA is channel 1.
48 */
49 PIIX_COMB_PATA_P0 = (1 << 1),
50 PIIX_COMB = (1 << 2), /* combined mode enabled? */
51
52 PIIX_PORT_PRESENT = (1 << 0),
53 PIIX_PORT_ENABLED = (1 << 4),
54
55 PIIX_80C_PRI = (1 << 5) | (1 << 4),
56 PIIX_80C_SEC = (1 << 7) | (1 << 6),
57
58 ich5_pata = 0,
59 ich5_sata = 1,
60 piix4_pata = 2,
61 ich6_sata = 3,
62 ich6_sata_rm = 4,
63 ich7_sata = 5,
64 esb2_sata = 6,
65 };
66
67 static int piix_init_one (struct pci_dev *pdev,
68 const struct pci_device_id *ent);
69
70 static void piix_pata_phy_reset(struct ata_port *ap);
71 static void piix_sata_phy_reset(struct ata_port *ap);
72 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
73 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
74
75 static unsigned int in_module_init = 1;
76
77 static struct pci_device_id piix_pci_tbl[] = {
78 #ifdef ATA_ENABLE_PATA
79 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
80 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
81 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
82 #endif
83
84 /* NOTE: The following PCI ids must be kept in sync with the
85 * list in drivers/pci/quirks.c.
86 */
87
88 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
89 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
90 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
91 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
92 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
93 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
94 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
95 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
96 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
97 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },
98
99 { } /* terminate list */
100 };
101
102 static struct pci_driver piix_pci_driver = {
103 .name = DRV_NAME,
104 .id_table = piix_pci_tbl,
105 .probe = piix_init_one,
106 .remove = ata_pci_remove_one,
107 };
108
109 static Scsi_Host_Template piix_sht = {
110 .module = THIS_MODULE,
111 .name = DRV_NAME,
112 .ioctl = ata_scsi_ioctl,
113 .queuecommand = ata_scsi_queuecmd,
114 .eh_strategy_handler = ata_scsi_error,
115 .can_queue = ATA_DEF_QUEUE,
116 .this_id = ATA_SHT_THIS_ID,
117 .sg_tablesize = LIBATA_MAX_PRD,
118 .max_sectors = ATA_MAX_SECTORS,
119 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
120 .emulated = ATA_SHT_EMULATED,
121 .use_clustering = ATA_SHT_USE_CLUSTERING,
122 .proc_name = DRV_NAME,
123 .dma_boundary = ATA_DMA_BOUNDARY,
124 .slave_configure = ata_scsi_slave_config,
125 .bios_param = ata_std_bios_param,
126 .ordered_flush = 1,
127 };
128
129 static struct ata_port_operations piix_pata_ops = {
130 .port_disable = ata_port_disable,
131 .set_piomode = piix_set_piomode,
132 .set_dmamode = piix_set_dmamode,
133
134 .tf_load = ata_tf_load,
135 .tf_read = ata_tf_read,
136 .check_status = ata_check_status,
137 .exec_command = ata_exec_command,
138 .dev_select = ata_std_dev_select,
139
140 .phy_reset = piix_pata_phy_reset,
141
142 .bmdma_setup = ata_bmdma_setup,
143 .bmdma_start = ata_bmdma_start,
144 .bmdma_stop = ata_bmdma_stop,
145 .bmdma_status = ata_bmdma_status,
146 .qc_prep = ata_qc_prep,
147 .qc_issue = ata_qc_issue_prot,
148
149 .eng_timeout = ata_eng_timeout,
150
151 .irq_handler = ata_interrupt,
152 .irq_clear = ata_bmdma_irq_clear,
153
154 .port_start = ata_port_start,
155 .port_stop = ata_port_stop,
156 .host_stop = ata_host_stop,
157 };
158
159 static struct ata_port_operations piix_sata_ops = {
160 .port_disable = ata_port_disable,
161
162 .tf_load = ata_tf_load,
163 .tf_read = ata_tf_read,
164 .check_status = ata_check_status,
165 .exec_command = ata_exec_command,
166 .dev_select = ata_std_dev_select,
167
168 .phy_reset = piix_sata_phy_reset,
169
170 .bmdma_setup = ata_bmdma_setup,
171 .bmdma_start = ata_bmdma_start,
172 .bmdma_stop = ata_bmdma_stop,
173 .bmdma_status = ata_bmdma_status,
174 .qc_prep = ata_qc_prep,
175 .qc_issue = ata_qc_issue_prot,
176
177 .eng_timeout = ata_eng_timeout,
178
179 .irq_handler = ata_interrupt,
180 .irq_clear = ata_bmdma_irq_clear,
181
182 .port_start = ata_port_start,
183 .port_stop = ata_port_stop,
184 .host_stop = ata_host_stop,
185 };
186
187 static struct ata_port_info piix_port_info[] = {
188 /* ich5_pata */
189 {
190 .sht = &piix_sht,
191 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
192 PIIX_FLAG_CHECKINTR,
193 .pio_mask = 0x1f, /* pio0-4 */
194 #if 0
195 .mwdma_mask = 0x06, /* mwdma1-2 */
196 #else
197 .mwdma_mask = 0x00, /* mwdma broken */
198 #endif
199 .udma_mask = 0x3f, /* udma0-5 */
200 .port_ops = &piix_pata_ops,
201 },
202
203 /* ich5_sata */
204 {
205 .sht = &piix_sht,
206 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
207 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
208 .pio_mask = 0x1f, /* pio0-4 */
209 .mwdma_mask = 0x07, /* mwdma0-2 */
210 .udma_mask = 0x7f, /* udma0-6 */
211 .port_ops = &piix_sata_ops,
212 },
213
214 /* piix4_pata */
215 {
216 .sht = &piix_sht,
217 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
218 .pio_mask = 0x1f, /* pio0-4 */
219 #if 0
220 .mwdma_mask = 0x06, /* mwdma1-2 */
221 #else
222 .mwdma_mask = 0x00, /* mwdma broken */
223 #endif
224 .udma_mask = ATA_UDMA_MASK_40C,
225 .port_ops = &piix_pata_ops,
226 },
227
228 /* ich6_sata */
229 {
230 .sht = &piix_sht,
231 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
232 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
233 ATA_FLAG_SLAVE_POSS,
234 .pio_mask = 0x1f, /* pio0-4 */
235 .mwdma_mask = 0x07, /* mwdma0-2 */
236 .udma_mask = 0x7f, /* udma0-6 */
237 .port_ops = &piix_sata_ops,
238 },
239
240 /* ich6_sata_rm */
241 {
242 .sht = &piix_sht,
243 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
244 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
245 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
246 .pio_mask = 0x1f, /* pio0-4 */
247 .mwdma_mask = 0x07, /* mwdma0-2 */
248 .udma_mask = 0x7f, /* udma0-6 */
249 .port_ops = &piix_sata_ops,
250 },
251
252 /* ich7_sata */
253 {
254 .sht = &piix_sht,
255 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
256 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
257 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
258 .pio_mask = 0x1f, /* pio0-4 */
259 .mwdma_mask = 0x07, /* mwdma0-2 */
260 .udma_mask = 0x7f, /* udma0-6 */
261 .port_ops = &piix_sata_ops,
262 },
263
264 /* esb2_sata */
265 {
266 .sht = &piix_sht,
267 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
268 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
269 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
270 .pio_mask = 0x1f, /* pio0-4 */
271 .mwdma_mask = 0x07, /* mwdma0-2 */
272 .udma_mask = 0x7f, /* udma0-6 */
273 .port_ops = &piix_sata_ops,
274 },
275 };
276
277 static struct pci_bits piix_enable_bits[] = {
278 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
279 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
280 };
281
282 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
283 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
284 MODULE_LICENSE("GPL");
285 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
286 MODULE_VERSION(DRV_VERSION);
287
288 /**
289 * piix_pata_cbl_detect - Probe host controller cable detect info
290 * @ap: Port for which cable detect info is desired
291 *
292 * Read 80c cable indicator from ATA PCI device's PCI config
293 * register. This register is normally set by firmware (BIOS).
294 *
295 * LOCKING:
296 * None (inherited from caller).
297 */
298 static void piix_pata_cbl_detect(struct ata_port *ap)
299 {
300 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
301 u8 tmp, mask;
302
303 /* no 80c support in host controller? */
304 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
305 goto cbl40;
306
307 /* check BIOS cable detect results */
308 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
309 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
310 if ((tmp & mask) == 0)
311 goto cbl40;
312
313 ap->cbl = ATA_CBL_PATA80;
314 return;
315
316 cbl40:
317 ap->cbl = ATA_CBL_PATA40;
318 ap->udma_mask &= ATA_UDMA_MASK_40C;
319 }
320
321 /**
322 * piix_pata_phy_reset - Probe specified port on PATA host controller
323 * @ap: Port to probe
324 *
325 * Probe PATA phy.
326 *
327 * LOCKING:
328 * None (inherited from caller).
329 */
330
331 static void piix_pata_phy_reset(struct ata_port *ap)
332 {
333 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
334
335 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
336 ata_port_disable(ap);
337 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
338 return;
339 }
340
341 piix_pata_cbl_detect(ap);
342
343 ata_port_probe(ap);
344
345 ata_bus_reset(ap);
346 }
347
348 /**
349 * piix_sata_probe - Probe PCI device for present SATA devices
350 * @ap: Port associated with the PCI device we wish to probe
351 *
352 * Reads SATA PCI device's PCI config register Port Configuration
353 * and Status (PCS) to determine port and device availability.
354 *
355 * LOCKING:
356 * None (inherited from caller).
357 *
358 * RETURNS:
359 * Non-zero if device detected, zero otherwise.
360 */
361 static int piix_sata_probe (struct ata_port *ap)
362 {
363 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
364 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
365 int orig_mask, mask, i;
366 u8 pcs;
367
368 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
369 (PIIX_PORT_ENABLED << ap->hard_port_no);
370
371 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
372 orig_mask = (int) pcs & 0xff;
373
374 /* TODO: this is vaguely wrong for ICH6 combined mode,
375 * where only two of the four SATA ports are mapped
376 * onto a single ATA channel. It is also vaguely inaccurate
377 * for ICH5, which has only two ports. However, this is ok,
378 * as further device presence detection code will handle
379 * any false positives produced here.
380 */
381
382 for (i = 0; i < 4; i++) {
383 mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
384
385 if ((orig_mask & mask) == mask)
386 if (combined || (i == ap->hard_port_no))
387 return 1;
388 }
389
390 return 0;
391 }
392
393 /**
394 * piix_sata_phy_reset - Probe specified port on SATA host controller
395 * @ap: Port to probe
396 *
397 * Probe SATA phy.
398 *
399 * LOCKING:
400 * None (inherited from caller).
401 */
402
403 static void piix_sata_phy_reset(struct ata_port *ap)
404 {
405 if (!piix_sata_probe(ap)) {
406 ata_port_disable(ap);
407 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
408 return;
409 }
410
411 ap->cbl = ATA_CBL_SATA;
412
413 ata_port_probe(ap);
414
415 ata_bus_reset(ap);
416 }
417
418 /**
419 * piix_set_piomode - Initialize host controller PATA PIO timings
420 * @ap: Port whose timings we are configuring
421 * @adev: um
422 * @pio: PIO mode, 0 - 4
423 *
424 * Set PIO mode for device, in host controller PCI config space.
425 *
426 * LOCKING:
427 * None (inherited from caller).
428 */
429
430 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
431 {
432 unsigned int pio = adev->pio_mode - XFER_PIO_0;
433 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
434 unsigned int is_slave = (adev->devno != 0);
435 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
436 unsigned int slave_port = 0x44;
437 u16 master_data;
438 u8 slave_data;
439
440 static const /* ISP RTC */
441 u8 timings[][2] = { { 0, 0 },
442 { 0, 0 },
443 { 1, 0 },
444 { 2, 1 },
445 { 2, 3 }, };
446
447 pci_read_config_word(dev, master_port, &master_data);
448 if (is_slave) {
449 master_data |= 0x4000;
450 /* enable PPE, IE and TIME */
451 master_data |= 0x0070;
452 pci_read_config_byte(dev, slave_port, &slave_data);
453 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
454 slave_data |=
455 (timings[pio][0] << 2) |
456 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
457 } else {
458 master_data &= 0xccf8;
459 /* enable PPE, IE and TIME */
460 master_data |= 0x0007;
461 master_data |=
462 (timings[pio][0] << 12) |
463 (timings[pio][1] << 8);
464 }
465 pci_write_config_word(dev, master_port, master_data);
466 if (is_slave)
467 pci_write_config_byte(dev, slave_port, slave_data);
468 }
469
470 /**
471 * piix_set_dmamode - Initialize host controller PATA PIO timings
472 * @ap: Port whose timings we are configuring
473 * @adev: um
474 * @udma: udma mode, 0 - 6
475 *
476 * Set UDMA mode for device, in host controller PCI config space.
477 *
478 * LOCKING:
479 * None (inherited from caller).
480 */
481
482 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
483 {
484 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
485 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
486 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
487 u8 speed = udma;
488 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
489 int a_speed = 3 << (drive_dn * 4);
490 int u_flag = 1 << drive_dn;
491 int v_flag = 0x01 << drive_dn;
492 int w_flag = 0x10 << drive_dn;
493 int u_speed = 0;
494 int sitre;
495 u16 reg4042, reg4a;
496 u8 reg48, reg54, reg55;
497
498 pci_read_config_word(dev, maslave, &reg4042);
499 DPRINTK("reg4042 = 0x%04x\n", reg4042);
500 sitre = (reg4042 & 0x4000) ? 1 : 0;
501 pci_read_config_byte(dev, 0x48, &reg48);
502 pci_read_config_word(dev, 0x4a, &reg4a);
503 pci_read_config_byte(dev, 0x54, &reg54);
504 pci_read_config_byte(dev, 0x55, &reg55);
505
506 switch(speed) {
507 case XFER_UDMA_4:
508 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
509 case XFER_UDMA_6:
510 case XFER_UDMA_5:
511 case XFER_UDMA_3:
512 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
513 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
514 case XFER_MW_DMA_2:
515 case XFER_MW_DMA_1: break;
516 default:
517 BUG();
518 return;
519 }
520
521 if (speed >= XFER_UDMA_0) {
522 if (!(reg48 & u_flag))
523 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
524 if (speed == XFER_UDMA_5) {
525 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
526 } else {
527 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
528 }
529 if ((reg4a & a_speed) != u_speed)
530 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
531 if (speed > XFER_UDMA_2) {
532 if (!(reg54 & v_flag))
533 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
534 } else
535 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
536 } else {
537 if (reg48 & u_flag)
538 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
539 if (reg4a & a_speed)
540 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
541 if (reg54 & v_flag)
542 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
543 if (reg55 & w_flag)
544 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
545 }
546 }
547
548 /* move to PCI layer, integrate w/ MSI stuff */
549 static void pci_enable_intx(struct pci_dev *pdev)
550 {
551 u16 pci_command;
552
553 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
554 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
555 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
556 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
557 }
558 }
559
560 #define AHCI_PCI_BAR 5
561 #define AHCI_GLOBAL_CTL 0x04
562 #define AHCI_ENABLE (1 << 31)
563 static int piix_disable_ahci(struct pci_dev *pdev)
564 {
565 void *mmio;
566 unsigned long addr;
567 u32 tmp;
568 int rc = 0;
569
570 /* BUG: pci_enable_device has not yet been called. This
571 * works because this device is usually set up by BIOS.
572 */
573
574 addr = pci_resource_start(pdev, AHCI_PCI_BAR);
575 if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
576 return 0;
577
578 mmio = ioremap(addr, 64);
579 if (!mmio)
580 return -ENOMEM;
581
582 tmp = readl(mmio + AHCI_GLOBAL_CTL);
583 if (tmp & AHCI_ENABLE) {
584 tmp &= ~AHCI_ENABLE;
585 writel(tmp, mmio + AHCI_GLOBAL_CTL);
586
587 tmp = readl(mmio + AHCI_GLOBAL_CTL);
588 if (tmp & AHCI_ENABLE)
589 rc = -EIO;
590 }
591
592 iounmap(mmio);
593 return rc;
594 }
595
596 /**
597 * piix_init_one - Register PIIX ATA PCI device with kernel services
598 * @pdev: PCI device to register
599 * @ent: Entry in piix_pci_tbl matching with @pdev
600 *
601 * Called from kernel PCI layer. We probe for combined mode (sigh),
602 * and then hand over control to libata, for it to do the rest.
603 *
604 * LOCKING:
605 * Inherited from PCI layer (may sleep).
606 *
607 * RETURNS:
608 * Zero on success, or -ERRNO value.
609 */
610
611 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
612 {
613 static int printed_version;
614 struct ata_port_info *port_info[2];
615 unsigned int combined = 0, n_ports = 1;
616 unsigned int pata_chan = 0, sata_chan = 0;
617
618 if (!printed_version++)
619 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
620
621 /* no hotplugging support (FIXME) */
622 if (!in_module_init)
623 return -ENODEV;
624
625 port_info[0] = &piix_port_info[ent->driver_data];
626 port_info[1] = NULL;
627
628 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
629 int rc = piix_disable_ahci(pdev);
630 if (rc)
631 return rc;
632 }
633
634 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
635 u8 tmp;
636 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
637
638 if (tmp & PIIX_COMB) {
639 combined = 1;
640 if (tmp & PIIX_COMB_PATA_P0)
641 sata_chan = 1;
642 else
643 pata_chan = 1;
644 }
645 }
646
647 /* On ICH5, some BIOSen disable the interrupt using the
648 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
649 * On ICH6, this bit has the same effect, but only when
650 * MSI is disabled (and it is disabled, as we don't use
651 * message-signalled interrupts currently).
652 */
653 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
654 pci_enable_intx(pdev);
655
656 if (combined) {
657 port_info[sata_chan] = &piix_port_info[ent->driver_data];
658 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
659 port_info[pata_chan] = &piix_port_info[ich5_pata];
660 n_ports++;
661
662 printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
663 }
664
665 return ata_pci_init_one(pdev, port_info, n_ports);
666 }
667
668 static int __init piix_init(void)
669 {
670 int rc;
671
672 DPRINTK("pci_module_init\n");
673 rc = pci_module_init(&piix_pci_driver);
674 if (rc)
675 return rc;
676
677 in_module_init = 0;
678
679 DPRINTK("done\n");
680 return 0;
681 }
682
683 static void __exit piix_exit(void)
684 {
685 pci_unregister_driver(&piix_pci_driver);
686 }
687
688 module_init(piix_init);
689 module_exit(piix_exit);
690
x86 "subsystem" repository