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Staging: otus: remove unused variables
[linux-2.6/x86.git] / drivers / staging / otus / hal / hpmain.c
blob8dff5b97dfe3d7b73c017090905039b051748d75
1 /*
2 * Copyright (c) 2007-2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include "../80211core/cprecomp.h"
17 #include "hpani.h"
18 #include "hpusb.h"
19 #include "otus.ini"
20
21 extern const u32_t zcFwImage[];
22 extern const u32_t zcFwImageSize;
23 extern const u32_t zcDKFwImage[];
24 extern const u32_t zcDKFwImageSize;
25 extern const u32_t zcFwImageSPI[];
26 extern const u32_t zcFwImageSPISize;
27
28 #ifdef ZM_OTUS_LINUX_PHASE_2
29 extern const u32_t zcFwBufImage[];
30 extern const u32_t zcFwBufImageSize;
31 extern const u32_t zcP2FwImage[];
32 extern const u32_t zcP2FwImageSize;
33 #endif
34 extern void zfInitCmdQueue(zdev_t* dev);
35 extern u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen,
36 u16_t src, u8_t* buf);
37 extern void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen);
38 extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val);
39 extern u16_t zfFlushDelayWrite(zdev_t* dev);
40 extern void zfUsbInit(zdev_t* dev);
41 extern u16_t zfFirmwareDownload(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
42 extern u16_t zfFirmwareDownloadNotJump(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
43 extern void zfUsbFree(zdev_t* dev);
44 extern u16_t zfCwmIsExtChanBusy(u32_t ctlBusy, u32_t extBusy);
45 extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy);
46
47 /* Prototypes */
48 void zfInitRf(zdev_t* dev, u32_t frequency);
49 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40);
50 void zfInitMac(zdev_t* dev);
51
52 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset);
53 void zfInitPowerCal(zdev_t* dev);
54
55 #ifdef ZM_DRV_INIT_USB_MODE
56 void zfInitUsbMode(zdev_t* dev);
57 u16_t zfHpUsbReset(zdev_t* dev);
58 #endif
59
60 /* Bank 0 1 2 3 5 6 7 */
61 void zfSetRfRegs(zdev_t* dev, u32_t frequency);
62 /* Bank 4 */
63 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
64 u8_t extOffset);
65 /* Get param for turnoffdyn */
66 void zfGetHwTurnOffdynParam(zdev_t* dev,
67 u32_t frequency, u8_t bw40, u8_t extOffset,
68 int* delta_slope_coeff_exp,
69 int* delta_slope_coeff_man,
70 int* delta_slope_coeff_exp_shgi,
71 int* delta_slope_coeff_man_shgi);
72
73 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency);
74 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value);
75
76
77
78 #define zm_hp_priv(x) (((struct zsHpPriv*)wd->hpPrivate)->x)
79 static struct zsHpPriv zgHpPriv;
80
81 #define ZM_FIRMWARE_WLAN_ADDR 0x200000
82 #define ZM_FIRMWARE_SPI_ADDR 0x114000
83 /* 0: real chip 1: FPGA test */
84 #define ZM_FPGA_PHY 0
85
86 #define reg_write(addr, val) zfDelayWriteInternalReg(dev, addr+0x1bc000, val)
87 #define zm_min(A, B) ((A>B)? B:A)
88
89
90 /******************** Intialization ********************/
91 u16_t zfHpInit(zdev_t* dev, u32_t frequency)
92 {
93 u16_t ret;
94 zmw_get_wlan_dev(dev);
95
96 /* Initializa HAL Plus private variables */
97 wd->hpPrivate = &zgHpPriv;
98
99 ((struct zsHpPriv*)wd->hpPrivate)->halCapability = ZM_HP_CAP_11N;
100
101 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = 0;
102 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = 0;
103 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = 0;
104
105 ((struct zsHpPriv*)wd->hpPrivate)->disableDfsCh = 0;
106
107 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0] = 1;
108 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[1] = 1;
109 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
110 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
111
112 ((struct zsHpPriv*)wd->hpPrivate)->slotType = 1;
113 ((struct zsHpPriv*)wd->hpPrivate)->aggPktNum = 0x10000a;
114
115 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageIndex = 0;
116
117
118 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq = 0;
119 #ifdef ZM_OTUS_RX_STREAM_MODE
120 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
121 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
122 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
123 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
124 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
125 #endif
126
127 ((struct zsHpPriv*)wd->hpPrivate)->enableBBHeavyClip = 1;
128 ((struct zsHpPriv*)wd->hpPrivate)->hwBBHeavyClip = 1; // force enable 8107
129 ((struct zsHpPriv*)wd->hpPrivate)->doBBHeavyClip = 0;
130 ((struct zsHpPriv*)wd->hpPrivate)->setValueHeavyClip = 0;
131
132
133 /* Initialize driver core */
134 zfInitCmdQueue(dev);
135
136 /* Initialize USB */
137 zfUsbInit(dev);
138
139 #if ZM_SW_LOOP_BACK != 1
140
141 /* TODO : [Download FW] */
142 if (wd->modeMDKEnable)
143 {
144 /* download the MDK firmware */
145 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcDKFwImage,
146 (u32_t)zcDKFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
147 {
148 /* TODO : exception handling */
149 //return 1;
150 }
151 }
152 else
153 {
154 #ifndef ZM_OTUS_LINUX_PHASE_2
155 /* download the normal firmware */
156 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
157 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
158 {
159 /* TODO : exception handling */
160 //return 1;
161 }
162 #else
163
164 // 1-PH fw: ReadMac() store some global variable
165 if ((ret = zfFirmwareDownloadNotJump(dev, (u32_t*)zcFwBufImage,
166 (u32_t)zcFwBufImageSize, 0x102800)) != ZM_SUCCESS)
167 {
168 DbgPrint("Dl zcFwBufImage failed!");
169 }
170
171 zfwSleep(dev, 1000);
172
173 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
174 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
175 {
176 DbgPrint("Dl zcFwBufImage failed!");
177 }
178 #endif
179 }
180 #endif
181
182 #ifdef ZM_DRV_INIT_USB_MODE
183 /* Init USB Mode */
184 zfInitUsbMode(dev);
185
186 /* Do the USB Reset */
187 zfHpUsbReset(dev);
188 #endif
189
190 /* Register setting */
191 /* ZM_DRIVER_MODEL_TYPE_MDK
192 * 1=>for MDK, disable init RF, PHY, and MAC,
193 * 0=>normal init
194 */
195 //#if ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1))
196 #if ZM_SW_LOOP_BACK != 1
197 if(!wd->modeMDKEnable)
198 {
199 /* Init MAC */
200 zfInitMac(dev);
201
202 #if ZM_FW_LOOP_BACK != 1
203 /* Init PHY */
204 zfInitPhy(dev, frequency, 0);
205
206 /* Init RF */
207 zfInitRf(dev, frequency);
208
209 #if ZM_FPGA_PHY == 0
210 /* BringUp issue */
211 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
212 //zfFlushDelayWrite(dev);
213 #endif
214
215 #endif /* end of ZM_FW_LOOP_BACK != 1 */
216 }
217 #endif /* end of ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1)) */
218
219 zfHpEchoCommand(dev, 0xAABBCCDD);
220
221 return 0;
222 }
223
224
225 u16_t zfHpReinit(zdev_t* dev, u32_t frequency)
226 {
227 u16_t ret;
228 zmw_get_wlan_dev(dev);
229
230 ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 1;
231
232 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
233 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
234
235 #ifdef ZM_OTUS_RX_STREAM_MODE
236 if (((struct zsHpPriv*)wd->hpPrivate)->remainBuf != NULL)
237 {
238 zfwBufFree(dev, ((struct zsHpPriv*)wd->hpPrivate)->remainBuf, 0);
239 }
240 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
241 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
242 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
243 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
244 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
245 #endif
246
247 zfInitCmdQueue(dev);
248 zfCoreReinit(dev);
249
250 #ifndef ZM_OTUS_LINUX_PHASE_2
251 /* Download firmware */
252 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
253 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
254 {
255 /* TODO : exception handling */
256 //return 1;
257 }
258 #else
259 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcP2FwImage,
260 (u32_t)zcP2FwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
261 {
262 /* TODO : exception handling */
263 //return 1;
264 }
265 #endif
266
267 #ifdef ZM_DRV_INIT_USB_MODE
268 /* Init USB Mode */
269 zfInitUsbMode(dev);
270
271 /* Do the USB Reset */
272 zfHpUsbReset(dev);
273 #endif
274
275 /* Init MAC */
276 zfInitMac(dev);
277
278 /* Init PHY */
279 zfInitPhy(dev, frequency, 0);
280 /* Init RF */
281 zfInitRf(dev, frequency);
282
283 #if ZM_FPGA_PHY == 0
284 /* BringUp issue */
285 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
286 //zfFlushDelayWrite(dev);
287 #endif
288
289 zfHpEchoCommand(dev, 0xAABBCCDD);
290
291 return 0;
292 }
293
294
295 u16_t zfHpRelease(zdev_t* dev)
296 {
297 /* Free USB resource */
298 zfUsbFree(dev);
299
300 return 0;
301 }
302
303 /* MDK mode setting for dontRetransmit */
304 void zfHpConfigFM(zdev_t* dev, u32_t RxMaxSize, u32_t DontRetransmit)
305 {
306 u32_t cmd[3];
307 u16_t ret;
308
309 cmd[0] = 8 | (ZM_CMD_CONFIG << 8);
310 cmd[1] = RxMaxSize; /* zgRxMaxSize */
311 cmd[2] = DontRetransmit; /* zgDontRetransmit */
312
313 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, 0);
314 }
315
316 const u8_t zcXpdToPd[16] =
317 {
318 /* 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF */
319 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2, 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
320 };
321
322 /******************** RF and PHY ********************/
323
324 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40)
325 {
326 u16_t i, j, k;
327 u16_t entries;
328 u16_t modesIndex = 0;
329 u16_t freqIndex = 0;
330 u32_t tmp, tmp1;
331 struct zsHpPriv* hpPriv;
332
333 u32_t eepromBoardData[15][6] = {
334 /* Register A-20 A-20/40 G-20/40 G-20 G-Turbo */
335 {0x9964, 0, 0, 0, 0, 0},
336 {0x9960, 0, 0, 0, 0, 0},
337 {0xb960, 0, 0, 0, 0, 0},
338 {0x9844, 0, 0, 0, 0, 0},
339 {0x9850, 0, 0, 0, 0, 0},
340 {0x9834, 0, 0, 0, 0, 0},
341 {0x9828, 0, 0, 0, 0, 0},
342 {0xc864, 0, 0, 0, 0, 0},
343 {0x9848, 0, 0, 0, 0, 0},
344 {0xb848, 0, 0, 0, 0, 0},
345 {0xa20c, 0, 0, 0, 0, 0},
346 {0xc20c, 0, 0, 0, 0, 0},
347 {0x9920, 0, 0, 0, 0, 0},
348 {0xb920, 0, 0, 0, 0, 0},
349 {0xa258, 0, 0, 0, 0, 0},
350 };
351
352 zmw_get_wlan_dev(dev);
353 hpPriv=wd->hpPrivate;
354
355 /* #1 Save the initial value of the related RIFS register settings */
356 //((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy++;
357
358 /*
359 * Setup the indices for the next set of register array writes
360 * PHY mode is static20 / 2040
361 * Frequency is 2.4GHz (B) / 5GHz (A)
362 */
363 if ( frequency > ZM_CH_G_14 )
364 {
365 /* 5GHz */
366 freqIndex = 1;
367 if (bw40)
368 {
369 modesIndex = 2;
370 zm_debug_msg0("init ar5416Modes in 2: A-20/40");
371 }
372 else
373 {
374 modesIndex = 1;
375 zm_debug_msg0("init ar5416Modes in 1: A-20");
376 }
377 }
378 else
379 {
380 /* 2.4GHz */
381 freqIndex = 2;
382 if (bw40)
383 {
384 modesIndex = 3;
385 zm_debug_msg0("init ar5416Modes in 3: G-20/40");
386 }
387 else
388 {
389 modesIndex = 4;
390 zm_debug_msg0("init ar5416Modes in 4: G-20");
391 }
392 }
393
394
395 #if ZM_FPGA_PHY == 1
396 /* Starting External Hainan Register Initialization */
397 /* TODO: */
398
399 zfwSleep(dev, 10);
400 #endif
401
402 /*
403 *Set correct Baseband to analog shift setting to access analog chips.
404 */
405 //reg_write(PHY_BASE, 0x00000007);
406 // reg_write(0x9800, 0x00000007);
407
408 /*
409 * Write addac shifts
410 */
411 // do this in firmware
412
413
414
415 /* Zeroize board data */
416 for (j=0; j<15; j++)
417 {
418 for (k=1; k<=4; k++)
419 {
420 eepromBoardData[j][k] = 0;
421 }
422 }
423 /*
424 * Register setting by mode
425 */
426
427 entries = sizeof(ar5416Modes) / sizeof(*ar5416Modes);
428 zm_msg1_scan(ZM_LV_2, "Modes register setting entries=", entries);
429 for (i=0; i<entries; i++)
430 {
431 #if 0
432 if ( ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit && (ar5416Modes[i][0] == 0xa27c) )
433 {
434 /* Force disable CR671 bit20 / 7823 */
435 /* The bug has to do with the polarity of the pdadc offset calibration. There */
436 /* is an initial calibration that is OK, and there is a continuous */
437 /* calibration that updates the pddac with the wrong polarity. Fortunately */
438 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
439
440 reg_write(ar5416Modes[i][0], (ar5416Modes[i][modesIndex]& 0xffefffff) );
441 ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit = 1;
442 }
443 else
444 {
445 #endif
446 /* FirstTime Init or not 0xa27c(CR671) */
447 reg_write(ar5416Modes[i][0], ar5416Modes[i][modesIndex]);
448 // }
449 /* Initialize board data */
450 for (j=0; j<15; j++)
451 {
452 if (ar5416Modes[i][0] == eepromBoardData[j][0])
453 {
454 for (k=1; k<=4; k++)
455 {
456 eepromBoardData[j][k] = ar5416Modes[i][k];
457 }
458 }
459 }
460 /* #1 Save the initial value of the related RIFS register settings */
461 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
462 {
463 switch(ar5416Modes[i][0])
464 {
465 case 0x9850 :
466 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = ar5416Modes[i][modesIndex];
467 break;
468 case 0x985c :
469 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = ar5416Modes[i][modesIndex];
470 break;
471 case 0x9860 :
472 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = ar5416Modes[i][modesIndex];
473 break;
474 case 0x9918 :
475 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = ar5416Modes[i][modesIndex];
476 break;
477 case 0x99ec :
478 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = ar5416Modes[i][modesIndex];
479 break;
480 case 0xa388 :
481 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = ar5416Modes[i][modesIndex];
482 default :
483 break;
484 }
485 }
486 }
487 #if 0
488 zfFlushDelayWrite(dev);
489
490 /*
491 * Common Register setting
492 */
493 entries = sizeof(ar5416Common) / sizeof(*ar5416Common);
494 for (i=0; i<entries; i++)
495 {
496 reg_write(ar5416Common[i][0], ar5416Common[i][1]);
497 }
498 zfFlushDelayWrite(dev);
499
500 /*
501 * RF Gain setting by freqIndex
502 */
503 entries = sizeof(ar5416BB_RfGain) / sizeof(*ar5416BB_RfGain);
504 for (i=0; i<entries; i++)
505 {
506 reg_write(ar5416BB_RfGain[i][0], ar5416BB_RfGain[i][freqIndex]);
507 }
508 zfFlushDelayWrite(dev);
509
510 /*
511 * Moved ar5416InitChainMask() here to ensure the swap bit is set before
512 * the pdadc table is written. Swap must occur before any radio dependent
513 * replicated register access. The pdadc curve addressing in particular
514 * depends on the consistent setting of the swap bit.
515 */
516 //ar5416InitChainMask(pDev);
517
518 /* Setup the transmit power values. */
519 // TODO
520 #endif
521
522 /* Update 5G board data */
523 //Ant control common
524 tmp = hpPriv->eepromImage[0x100+0x144*2/4];
525 eepromBoardData[0][1] = tmp;
526 eepromBoardData[0][2] = tmp;
527 //Ant control chain 0
528 tmp = hpPriv->eepromImage[0x100+0x140*2/4];
529 eepromBoardData[1][1] = tmp;
530 eepromBoardData[1][2] = tmp;
531 //Ant control chain 2
532 tmp = hpPriv->eepromImage[0x100+0x142*2/4];
533 eepromBoardData[2][1] = tmp;
534 eepromBoardData[2][2] = tmp;
535 //SwSettle
536 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
537 tmp = (tmp >> 16) & 0x7f;
538 eepromBoardData[3][1] &= (~((u32_t)0x3f80));
539 eepromBoardData[3][1] |= (tmp << 7);
540 #if 0
541 //swSettleHt40
542 tmp = hpPriv->eepromImage[0x100+0x158*2/4];
543 tmp = (tmp) & 0x7f;
544 eepromBoardData[3][2] &= (~((u32_t)0x3f80));
545 eepromBoardData[3][2] |= (tmp << 7);
546 #endif
547 //adcDesired, pdaDesired
548 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
549 tmp = (tmp >> 24);
550 tmp1 = hpPriv->eepromImage[0x100+0x14a*2/4];
551 tmp1 = tmp1 & 0xff;
552 tmp = tmp + (tmp1<<8);
553 eepromBoardData[4][1] &= (~((u32_t)0xffff));
554 eepromBoardData[4][1] |= tmp;
555 eepromBoardData[4][2] &= (~((u32_t)0xffff));
556 eepromBoardData[4][2] |= tmp;
557 //TxEndToXpaOff, TxFrameToXpaOn
558 tmp = hpPriv->eepromImage[0x100+0x14a*2/4];
559 tmp = (tmp >> 24) & 0xff;
560 tmp1 = hpPriv->eepromImage[0x100+0x14c*2/4];
561 tmp1 = (tmp1 >> 8) & 0xff;
562 tmp = (tmp<<24) + (tmp<<16) + (tmp1<<8) + tmp1;
563 eepromBoardData[5][1] = tmp;
564 eepromBoardData[5][2] = tmp;
565 //TxEnaToRxOm
566 tmp = hpPriv->eepromImage[0x100+0x14c*2/4] & 0xff;
567 eepromBoardData[6][1] &= (~((u32_t)0xff0000));
568 eepromBoardData[6][1] |= (tmp<<16);
569 eepromBoardData[6][2] &= (~((u32_t)0xff0000));
570 eepromBoardData[6][2] |= (tmp<<16);
571 //Thresh62
572 tmp = hpPriv->eepromImage[0x100+0x14c*2/4];
573 tmp = (tmp >> 16) & 0x7f;
574 eepromBoardData[7][1] &= (~((u32_t)0x7f000));
575 eepromBoardData[7][1] |= (tmp<<12);
576 eepromBoardData[7][2] &= (~((u32_t)0x7f000));
577 eepromBoardData[7][2] |= (tmp<<12);
578 //TxRxAtten chain_0
579 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
580 tmp = (tmp >> 24) & 0x3f;
581 eepromBoardData[8][1] &= (~((u32_t)0x3f000));
582 eepromBoardData[8][1] |= (tmp<<12);
583 eepromBoardData[8][2] &= (~((u32_t)0x3f000));
584 eepromBoardData[8][2] |= (tmp<<12);
585 //TxRxAtten chain_2
586 tmp = hpPriv->eepromImage[0x100+0x148*2/4] & 0x3f;
587 eepromBoardData[9][1] &= (~((u32_t)0x3f000));
588 eepromBoardData[9][1] |= (tmp<<12);
589 eepromBoardData[9][2] &= (~((u32_t)0x3f000));
590 eepromBoardData[9][2] |= (tmp<<12);
591 //TxRxMargin chain_0
592 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
593 tmp = (tmp >> 8) & 0x3f;
594 eepromBoardData[10][1] &= (~((u32_t)0xfc0000));
595 eepromBoardData[10][1] |= (tmp<<18);
596 eepromBoardData[10][2] &= (~((u32_t)0xfc0000));
597 eepromBoardData[10][2] |= (tmp<<18);
598 //TxRxMargin chain_2
599 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
600 tmp = (tmp >> 16) & 0x3f;
601 eepromBoardData[11][1] &= (~((u32_t)0xfc0000));
602 eepromBoardData[11][1] |= (tmp<<18);
603 eepromBoardData[11][2] &= (~((u32_t)0xfc0000));
604 eepromBoardData[11][2] |= (tmp<<18);
605 //iqCall chain_0, iqCallQ chain_0
606 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
607 tmp = (tmp >> 24) & 0x3f;
608 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
609 tmp1 = (tmp1 >> 8) & 0x1f;
610 tmp = (tmp<<5) + tmp1;
611 eepromBoardData[12][1] &= (~((u32_t)0x7ff));
612 eepromBoardData[12][1] |= (tmp);
613 eepromBoardData[12][2] &= (~((u32_t)0x7ff));
614 eepromBoardData[12][2] |= (tmp);
615 //iqCall chain_2, iqCallQ chain_2
616 tmp = hpPriv->eepromImage[0x100+0x150*2/4];
617 tmp = tmp & 0x3f;
618 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
619 tmp1 = (tmp1 >> 16) & 0x1f;
620 tmp = (tmp<<5) + tmp1;
621 eepromBoardData[13][1] &= (~((u32_t)0x7ff));
622 eepromBoardData[13][1] |= (tmp);
623 eepromBoardData[13][2] &= (~((u32_t)0x7ff));
624 eepromBoardData[13][2] |= (tmp);
625 //bsw_Margin chain_0
626 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
627 tmp = (tmp >> 16) & 0xf;
628 eepromBoardData[10][1] &= (~((u32_t)0x3c00));
629 eepromBoardData[10][1] |= (tmp << 10);
630 eepromBoardData[10][2] &= (~((u32_t)0x3c00));
631 eepromBoardData[10][2] |= (tmp << 10);
632 //xpd gain mask
633 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
634 tmp = (tmp >> 8) & 0xf;
635 eepromBoardData[14][1] &= (~((u32_t)0xf0000));
636 eepromBoardData[14][1] |= (zcXpdToPd[tmp] << 16);
637 eepromBoardData[14][2] &= (~((u32_t)0xf0000));
638 eepromBoardData[14][2] |= (zcXpdToPd[tmp] << 16);
639 #if 0
640 //bsw_Atten chain_0
641 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
642 tmp = (tmp) & 0x1f;
643 eepromBoardData[10][1] &= (~((u32_t)0x1f));
644 eepromBoardData[10][1] |= (tmp);
645 eepromBoardData[10][2] &= (~((u32_t)0x1f));
646 eepromBoardData[10][2] |= (tmp);
647 //bsw_Margin chain_2
648 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
649 tmp = (tmp >> 24) & 0xf;
650 eepromBoardData[11][1] &= (~((u32_t)0x3c00));
651 eepromBoardData[11][1] |= (tmp << 10);
652 eepromBoardData[11][2] &= (~((u32_t)0x3c00));
653 eepromBoardData[11][2] |= (tmp << 10);
654 //bsw_Atten chain_2
655 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
656 tmp = (tmp >> 8) & 0x1f;
657 eepromBoardData[11][1] &= (~((u32_t)0x1f));
658 eepromBoardData[11][1] |= (tmp);
659 eepromBoardData[11][2] &= (~((u32_t)0x1f));
660 eepromBoardData[11][2] |= (tmp);
661 #endif
662
663 /* Update 2.4G board data */
664 //Ant control common
665 tmp = hpPriv->eepromImage[0x100+0x170*2/4];
666 tmp = tmp >> 24;
667 tmp1 = hpPriv->eepromImage[0x100+0x172*2/4];
668 tmp = tmp + (tmp1 << 8);
669 eepromBoardData[0][3] = tmp;
670 eepromBoardData[0][4] = tmp;
671 //Ant control chain 0
672 tmp = hpPriv->eepromImage[0x100+0x16c*2/4];
673 tmp = tmp >> 24;
674 tmp1 = hpPriv->eepromImage[0x100+0x16e*2/4];
675 tmp = tmp + (tmp1 << 8);
676 eepromBoardData[1][3] = tmp;
677 eepromBoardData[1][4] = tmp;
678 //Ant control chain 2
679 tmp = hpPriv->eepromImage[0x100+0x16e*2/4];
680 tmp = tmp >> 24;
681 tmp1 = hpPriv->eepromImage[0x100+0x170*2/4];
682 tmp = tmp + (tmp1 << 8);
683 eepromBoardData[2][3] = tmp;
684 eepromBoardData[2][4] = tmp;
685 //SwSettle
686 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
687 tmp = (tmp >> 8) & 0x7f;
688 eepromBoardData[3][4] &= (~((u32_t)0x3f80));
689 eepromBoardData[3][4] |= (tmp << 7);
690 #if 0
691 //swSettleHt40
692 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
693 tmp = (tmp >> 24) & 0x7f;
694 eepromBoardData[3][3] &= (~((u32_t)0x3f80));
695 eepromBoardData[3][3] |= (tmp << 7);
696 #endif
697 //adcDesired, pdaDesired
698 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
699 tmp = (tmp >> 16) & 0xff;
700 tmp1 = hpPriv->eepromImage[0x100+0x176*2/4];
701 tmp1 = tmp1 >> 24;
702 tmp = tmp + (tmp1<<8);
703 eepromBoardData[4][3] &= (~((u32_t)0xffff));
704 eepromBoardData[4][3] |= tmp;
705 eepromBoardData[4][4] &= (~((u32_t)0xffff));
706 eepromBoardData[4][4] |= tmp;
707 //TxEndToXpaOff, TxFrameToXpaOn
708 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
709 tmp = (tmp >> 16) & 0xff;
710 tmp1 = hpPriv->eepromImage[0x100+0x17a*2/4];
711 tmp1 = tmp1 & 0xff;
712 tmp = (tmp << 24) + (tmp << 16) + (tmp1 << 8) + tmp1;
713 eepromBoardData[5][3] = tmp;
714 eepromBoardData[5][4] = tmp;
715 //TxEnaToRxOm
716 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
717 tmp = (tmp >> 24);
718 eepromBoardData[6][3] &= (~((u32_t)0xff0000));
719 eepromBoardData[6][3] |= (tmp<<16);
720 eepromBoardData[6][4] &= (~((u32_t)0xff0000));
721 eepromBoardData[6][4] |= (tmp<<16);
722 //Thresh62
723 tmp = hpPriv->eepromImage[0x100+0x17a*2/4];
724 tmp = (tmp >> 8) & 0x7f;
725 eepromBoardData[7][3] &= (~((u32_t)0x7f000));
726 eepromBoardData[7][3] |= (tmp<<12);
727 eepromBoardData[7][4] &= (~((u32_t)0x7f000));
728 eepromBoardData[7][4] |= (tmp<<12);
729 //TxRxAtten chain_0
730 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
731 tmp = (tmp >> 16) & 0x3f;
732 eepromBoardData[8][3] &= (~((u32_t)0x3f000));
733 eepromBoardData[8][3] |= (tmp<<12);
734 eepromBoardData[8][4] &= (~((u32_t)0x3f000));
735 eepromBoardData[8][4] |= (tmp<<12);
736 //TxRxAtten chain_2
737 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
738 tmp = (tmp >> 24) & 0x3f;
739 eepromBoardData[9][3] &= (~((u32_t)0x3f000));
740 eepromBoardData[9][3] |= (tmp<<12);
741 eepromBoardData[9][4] &= (~((u32_t)0x3f000));
742 eepromBoardData[9][4] |= (tmp<<12);
743 //TxRxMargin chain_0
744 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
745 tmp = (tmp) & 0x3f;
746 eepromBoardData[10][3] &= (~((u32_t)0xfc0000));
747 eepromBoardData[10][3] |= (tmp<<18);
748 eepromBoardData[10][4] &= (~((u32_t)0xfc0000));
749 eepromBoardData[10][4] |= (tmp<<18);
750 //TxRxMargin chain_2
751 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
752 tmp = (tmp >> 8) & 0x3f;
753 eepromBoardData[11][3] &= (~((u32_t)0xfc0000));
754 eepromBoardData[11][3] |= (tmp<<18);
755 eepromBoardData[11][4] &= (~((u32_t)0xfc0000));
756 eepromBoardData[11][4] |= (tmp<<18);
757 //iqCall chain_0, iqCallQ chain_0
758 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
759 tmp = (tmp >> 16) & 0x3f;
760 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
761 tmp1 = (tmp1) & 0x1f;
762 tmp = (tmp<<5) + tmp1;
763 eepromBoardData[12][3] &= (~((u32_t)0x7ff));
764 eepromBoardData[12][3] |= (tmp);
765 eepromBoardData[12][4] &= (~((u32_t)0x7ff));
766 eepromBoardData[12][4] |= (tmp);
767 //iqCall chain_2, iqCallQ chain_2
768 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
769 tmp = (tmp>>24) & 0x3f;
770 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
771 tmp1 = (tmp1 >> 8) & 0x1f;
772 tmp = (tmp<<5) + tmp1;
773 eepromBoardData[13][3] &= (~((u32_t)0x7ff));
774 eepromBoardData[13][3] |= (tmp);
775 eepromBoardData[13][4] &= (~((u32_t)0x7ff));
776 eepromBoardData[13][4] |= (tmp);
777 //xpd gain mask
778 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
779 tmp = tmp & 0xf;
780 DbgPrint("xpd=0x%x, pd=0x%x\n", tmp, zcXpdToPd[tmp]);
781 eepromBoardData[14][3] &= (~((u32_t)0xf0000));
782 eepromBoardData[14][3] |= (zcXpdToPd[tmp] << 16);
783 eepromBoardData[14][4] &= (~((u32_t)0xf0000));
784 eepromBoardData[14][4] |= (zcXpdToPd[tmp] << 16);
785 #if 0
786 //bsw_Margin chain_0
787 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
788 tmp = (tmp >> 8) & 0xf;
789 eepromBoardData[10][3] &= (~((u32_t)0x3c00));
790 eepromBoardData[10][3] |= (tmp << 10);
791 eepromBoardData[10][4] &= (~((u32_t)0x3c00));
792 eepromBoardData[10][4] |= (tmp << 10);
793 //bsw_Atten chain_0
794 tmp = hpPriv->eepromImage[0x100+0x182*2/4];
795 tmp = (tmp>>24) & 0x1f;
796 eepromBoardData[10][3] &= (~((u32_t)0x1f));
797 eepromBoardData[10][3] |= (tmp);
798 eepromBoardData[10][4] &= (~((u32_t)0x1f));
799 eepromBoardData[10][4] |= (tmp);
800 //bsw_Margin chain_2
801 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
802 tmp = (tmp >> 16) & 0xf;
803 eepromBoardData[11][3] &= (~((u32_t)0x3c00));
804 eepromBoardData[11][3] |= (tmp << 10);
805 eepromBoardData[11][4] &= (~((u32_t)0x3c00));
806 eepromBoardData[11][4] |= (tmp << 10);
807 //bsw_Atten chain_2
808 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
809 tmp = (tmp) & 0x1f;
810 eepromBoardData[11][3] &= (~((u32_t)0x1f));
811 eepromBoardData[11][3] |= (tmp);
812 eepromBoardData[11][4] &= (~((u32_t)0x1f));
813 eepromBoardData[11][4] |= (tmp);
814 #endif
815
816 #if 0
817 for (j=0; j<14; j++)
818 {
819 DbgPrint("%04x, %08x, %08x, %08x, %08x\n", eepromBoardData[j][0], eepromBoardData[j][1], eepromBoardData[j][2], eepromBoardData[j][3], eepromBoardData[j][4]);
820 }
821 #endif
822
823 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
824 {
825 /* Update board data to registers */
826 for (j=0; j<15; j++)
827 {
828 reg_write(eepromBoardData[j][0], eepromBoardData[j][modesIndex]);
829
830 /* #1 Save the initial value of the related RIFS register settings */
831 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
832 {
833 switch(eepromBoardData[j][0])
834 {
835 case 0x9850 :
836 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = eepromBoardData[j][modesIndex];
837 break;
838 case 0x985c :
839 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = eepromBoardData[j][modesIndex];
840 break;
841 case 0x9860 :
842 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = eepromBoardData[j][modesIndex];
843 break;
844 case 0x9918 :
845 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = eepromBoardData[j][modesIndex];
846 break;
847 case 0x99ec :
848 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = eepromBoardData[j][modesIndex];
849 break;
850 case 0xa388 :
851 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = eepromBoardData[j][modesIndex];
852 default :
853 break;
854 }
855 }
856 }
857 } /* if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE */
858
859
860 /* Bringup issue : force tx gain */
861 //reg_write(0xa258, 0x0cc65381);
862 //reg_write(0xa274, 0x0a1a7c15);
863 zfInitPowerCal(dev);
864
865 if(frequency > ZM_CH_G_14)
866 {
867 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5143);
868 }
869 else
870 {
871 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5163);
872 }
873
874 zfFlushDelayWrite(dev);
875 }
876
877
878 void zfInitRf(zdev_t* dev, u32_t frequency)
879 {
880 u32_t cmd[8];
881 u16_t ret;
882 int delta_slope_coeff_exp;
883 int delta_slope_coeff_man;
884 int delta_slope_coeff_exp_shgi;
885 int delta_slope_coeff_man_shgi;
886
887 zmw_get_wlan_dev(dev);
888
889 zm_debug_msg1(" initRf frequency = ", frequency);
890
891 if (frequency == 0)
892 {
893 frequency = 2412;
894 }
895
896 /* Bank 0 1 2 3 5 6 7 */
897 zfSetRfRegs(dev, frequency);
898 /* Bank 4 */
899 zfSetBank4AndPowerTable(dev, frequency, 0, 0);
900
901 /* stroe frequency */
902 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
903
904 zfGetHwTurnOffdynParam(dev,
905 frequency, 0, 0,
906 &delta_slope_coeff_exp,
907 &delta_slope_coeff_man,
908 &delta_slope_coeff_exp_shgi,
909 &delta_slope_coeff_man_shgi);
910
911 /* related functions */
912 frequency = frequency*1000;
913 cmd[0] = 28 | (ZM_CMD_RF_INIT << 8);
914 cmd[1] = frequency;
915 cmd[2] = 0;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
916 cmd[3] = 1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
917 cmd[4] = delta_slope_coeff_exp;
918 cmd[5] = delta_slope_coeff_man;
919 cmd[6] = delta_slope_coeff_exp_shgi;
920 cmd[7] = delta_slope_coeff_man_shgi;
921
922 ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, 0);
923
924 // delay temporarily, wait for new PHY and RF
925 zfwSleep(dev, 1000);
926 }
927
928 int tn(int exp)
929 {
930 int i;
931 int tmp = 1;
932 for(i=0; i<exp; i++)
933 tmp = tmp*2;
934
935 return tmp;
936 }
937
938 /*int zfFloor(double indata)
939 {
940 if(indata<0)
941 return (int)indata-1;
942 else
943 return (int)indata;
944 }
945 */
946 u32_t reverse_bits(u32_t chan_sel)
947 {
948 /* reverse_bits */
949 u32_t chansel = 0;
950 u8_t i;
951
952 for (i=0; i<8; i++)
953 chansel |= ((chan_sel>>(7-i) & 0x1) << i);
954 return chansel;
955 }
956
957 /* Bank 0 1 2 3 5 6 7 */
958 void zfSetRfRegs(zdev_t* dev, u32_t frequency)
959 {
960 u16_t entries;
961 u16_t freqIndex = 0;
962 u16_t i;
963
964 //zmw_get_wlan_dev(dev);
965
966 if ( frequency > ZM_CH_G_14 )
967 {
968 /* 5G */
969 freqIndex = 1;
970 zm_msg0_scan(ZM_LV_2, "Set to 5GHz");
971
972 }
973 else
974 {
975 /* 2.4G */
976 freqIndex = 2;
977 zm_msg0_scan(ZM_LV_2, "Set to 2.4GHz");
978 }
979
980 #if 1
981 entries = sizeof(otusBank) / sizeof(*otusBank);
982 for (i=0; i<entries; i++)
983 {
984 reg_write(otusBank[i][0], otusBank[i][freqIndex]);
985 }
986 #else
987 /* Bank0 */
988 entries = sizeof(ar5416Bank0) / sizeof(*ar5416Bank0);
989 for (i=0; i<entries; i++)
990 {
991 reg_write(ar5416Bank0[i][0], ar5416Bank0[i][1]);
992 }
993 /* Bank1 */
994 entries = sizeof(ar5416Bank1) / sizeof(*ar5416Bank1);
995 for (i=0; i<entries; i++)
996 {
997 reg_write(ar5416Bank1[i][0], ar5416Bank1[i][1]);
998 }
999 /* Bank2 */
1000 entries = sizeof(ar5416Bank2) / sizeof(*ar5416Bank2);
1001 for (i=0; i<entries; i++)
1002 {
1003 reg_write(ar5416Bank2[i][0], ar5416Bank2[i][1]);
1004 }
1005 /* Bank3 */
1006 entries = sizeof(ar5416Bank3) / sizeof(*ar5416Bank3);
1007 for (i=0; i<entries; i++)
1008 {
1009 reg_write(ar5416Bank3[i][0], ar5416Bank3[i][freqIndex]);
1010 }
1011 /* Bank5 */
1012 reg_write (0x98b0, 0x00000013);
1013 reg_write (0x98e4, 0x00000002);
1014 /* Bank6 */
1015 entries = sizeof(ar5416Bank6) / sizeof(*ar5416Bank6);
1016 for (i=0; i<entries; i++)
1017 {
1018 reg_write(ar5416Bank6[i][0], ar5416Bank6[i][freqIndex]);
1019 }
1020 /* Bank7 */
1021 entries = sizeof(ar5416Bank7) / sizeof(*ar5416Bank7);
1022 for (i=0; i<entries; i++)
1023 {
1024 reg_write(ar5416Bank7[i][0], ar5416Bank7[i][1]);
1025 }
1026 #endif
1027
1028 zfFlushDelayWrite(dev);
1029 }
1030
1031 /* Bank 4 */
1032 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
1033 u8_t extOffset)
1034 {
1035 u32_t chup = 1;
1036 u32_t bmode_LF_synth_freq = 0;
1037 u32_t amode_refsel_1 = 0;
1038 u32_t amode_refsel_0 = 1;
1039 u32_t addr2 = 1;
1040 u32_t addr1 = 0;
1041 u32_t addr0 = 0;
1042
1043 u32_t d1;
1044 u32_t d0;
1045 u32_t tmp_0;
1046 u32_t tmp_1;
1047 u32_t data0;
1048 u32_t data1;
1049
1050 u8_t chansel;
1051 u8_t chan_sel;
1052 u32_t temp_chan_sel;
1053
1054 u16_t i;
1055
1056 zmw_get_wlan_dev(dev);
1057
1058
1059 /* if enable 802.11h, need to record curent channel index in channel array */
1060 if (wd->sta.DFSEnable)
1061 {
1062 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
1063 {
1064 if (wd->regulationTable.allowChannel[i].channel == frequency)
1065 break;
1066 }
1067 wd->regulationTable.CurChIndex = i;
1068 }
1069
1070 if (bw40 == 1)
1071 {
1072 if (extOffset == 1)
1073 {
1074 frequency += 10;
1075 }
1076 else
1077 {
1078 frequency -= 10;
1079 }
1080
1081 }
1082
1083
1084 if ( frequency > 3000 )
1085 {
1086 if ( frequency % 10 )
1087 {
1088 /* 5M */
1089 chan_sel = (u8_t)((frequency - 4800)/5);
1090 chan_sel = (u8_t)(chan_sel & 0xff);
1091 chansel = (u8_t)reverse_bits(chan_sel);
1092 }
1093 else
1094 {
1095 /* 10M : improve Tx EVM */
1096 chan_sel = (u8_t)((frequency - 4800)/10);
1097 chan_sel = (u8_t)(chan_sel & 0xff)<<1;
1098 chansel = (u8_t)reverse_bits(chan_sel);
1099
1100 amode_refsel_1 = 1;
1101 amode_refsel_0 = 0;
1102 }
1103 }
1104 else
1105 {
1106 //temp_chan_sel = (((frequency - 672)*2) - 3040)/10;
1107 if (frequency == 2484)
1108 {
1109 temp_chan_sel = 10 + (frequency - 2274)/5 ;
1110 bmode_LF_synth_freq = 1;
1111 }
1112 else
1113 {
1114 temp_chan_sel = 16 + (frequency - 2272)/5 ;
1115 bmode_LF_synth_freq = 0;
1116 }
1117 chan_sel = (u8_t)(temp_chan_sel << 2) & 0xff;
1118 chansel = (u8_t)reverse_bits(chan_sel);
1119 }
1120
1121 d1 = chansel; //# 8 bits of chan
1122 d0 = addr0<<7 | addr1<<6 | addr2<<5
1123 | amode_refsel_0<<3 | amode_refsel_1<<2
1124 | bmode_LF_synth_freq<<1 | chup;
1125
1126 tmp_0 = d0 & 0x1f; //# 5-1
1127 tmp_1 = d1 & 0x1f; //# 5-1
1128 data0 = tmp_1<<5 | tmp_0;
1129
1130 tmp_0 = d0>>5 & 0x7; //# 8-6
1131 tmp_1 = d1>>5 & 0x7; //# 8-6
1132 data1 = tmp_1<<5 | tmp_0;
1133
1134 /* Bank4 */
1135 reg_write (0x9800+(0x2c<<2), data0);
1136 reg_write (0x9800+(0x3a<<2), data1);
1137 //zm_debug_msg1("0x9800+(0x2c<<2 = ", data0);
1138 //zm_debug_msg1("0x9800+(0x3a<<2 = ", data1);
1139
1140
1141 zfFlushDelayWrite(dev);
1142
1143 zfwSleep(dev, 10);
1144
1145 return;
1146 }
1147
1148
1149 struct zsPhyFreqPara
1150 {
1151 u32_t coeff_exp;
1152 u32_t coeff_man;
1153 u32_t coeff_exp_shgi;
1154 u32_t coeff_man_shgi;
1155 };
1156
1157 struct zsPhyFreqTable
1158 {
1159 u32_t frequency;
1160 struct zsPhyFreqPara FpgaDynamicHT;
1161 struct zsPhyFreqPara FpgaStaticHT;
1162 struct zsPhyFreqPara ChipST20Mhz;
1163 struct zsPhyFreqPara Chip2040Mhz;
1164 struct zsPhyFreqPara Chip2040ExtAbove;
1165 };
1166
1167 const struct zsPhyFreqTable zgPhyFreqCoeff[] =
1168 {
1169 /*Index freq FPGA DYNAMIC_HT2040_EN FPGA STATIC_HT20 Real Chip static20MHz Real Chip 2040MHz Real Chip 2040Mhz */
1170 /* fclk = 10.8 21.6 40 ext below 40 ext above 40 */
1171 /* 0 */ {2412, {5, 23476, 5, 21128}, {4, 23476, 4, 21128}, {3, 21737, 3, 19563}, {3, 21827, 3, 19644}, {3, 21647, 3, 19482}},
1172 /* 1 */ {2417, {5, 23427, 5, 21084}, {4, 23427, 4, 21084}, {3, 21692, 3, 19523}, {3, 21782, 3, 19604}, {3, 21602, 3, 19442}},
1173 /* 2 */ {2422, {5, 23379, 5, 21041}, {4, 23379, 4, 21041}, {3, 21647, 3, 19482}, {3, 21737, 3, 19563}, {3, 21558, 3, 19402}},
1174 /* 3 */ {2427, {5, 23330, 5, 20997}, {4, 23330, 4, 20997}, {3, 21602, 3, 19442}, {3, 21692, 3, 19523}, {3, 21514, 3, 19362}},
1175 /* 4 */ {2432, {5, 23283, 5, 20954}, {4, 23283, 4, 20954}, {3, 21558, 3, 19402}, {3, 21647, 3, 19482}, {3, 21470, 3, 19323}},
1176 /* 5 */ {2437, {5, 23235, 5, 20911}, {4, 23235, 4, 20911}, {3, 21514, 3, 19362}, {3, 21602, 3, 19442}, {3, 21426, 3, 19283}},
1177 /* 6 */ {2442, {5, 23187, 5, 20868}, {4, 23187, 4, 20868}, {3, 21470, 3, 19323}, {3, 21558, 3, 19402}, {3, 21382, 3, 19244}},
1178 /* 7 */ {2447, {5, 23140, 5, 20826}, {4, 23140, 4, 20826}, {3, 21426, 3, 19283}, {3, 21514, 3, 19362}, {3, 21339, 3, 19205}},
1179 /* 8 */ {2452, {5, 23093, 5, 20783}, {4, 23093, 4, 20783}, {3, 21382, 3, 19244}, {3, 21470, 3, 19323}, {3, 21295, 3, 19166}},
1180 /* 9 */ {2457, {5, 23046, 5, 20741}, {4, 23046, 4, 20741}, {3, 21339, 3, 19205}, {3, 21426, 3, 19283}, {3, 21252, 3, 19127}},
1181 /* 10 */ {2462, {5, 22999, 5, 20699}, {4, 22999, 4, 20699}, {3, 21295, 3, 19166}, {3, 21382, 3, 19244}, {3, 21209, 3, 19088}},
1182 /* 11 */ {2467, {5, 22952, 5, 20657}, {4, 22952, 4, 20657}, {3, 21252, 3, 19127}, {3, 21339, 3, 19205}, {3, 21166, 3, 19050}},
1183 /* 12 */ {2472, {5, 22906, 5, 20615}, {4, 22906, 4, 20615}, {3, 21209, 3, 19088}, {3, 21295, 3, 19166}, {3, 21124, 3, 19011}},
1184 /* 13 */ {2484, {5, 22795, 5, 20516}, {4, 22795, 4, 20516}, {3, 21107, 3, 18996}, {3, 21192, 3, 19073}, {3, 21022, 3, 18920}},
1185 /* 14 */ {4920, {6, 23018, 6, 20716}, {5, 23018, 5, 20716}, {4, 21313, 4, 19181}, {4, 21356, 4, 19220}, {4, 21269, 4, 19142}},
1186 /* 15 */ {4940, {6, 22924, 6, 20632}, {5, 22924, 5, 20632}, {4, 21226, 4, 19104}, {4, 21269, 4, 19142}, {4, 21183, 4, 19065}},
1187 /* 16 */ {4960, {6, 22832, 6, 20549}, {5, 22832, 5, 20549}, {4, 21141, 4, 19027}, {4, 21183, 4, 19065}, {4, 21098, 4, 18988}},
1188 /* 17 */ {4980, {6, 22740, 6, 20466}, {5, 22740, 5, 20466}, {4, 21056, 4, 18950}, {4, 21098, 4, 18988}, {4, 21014, 4, 18912}},
1189 /* 18 */ {5040, {6, 22469, 6, 20223}, {5, 22469, 5, 20223}, {4, 20805, 4, 18725}, {4, 20846, 4, 18762}, {4, 20764, 4, 18687}},
1190 /* 19 */ {5060, {6, 22381, 6, 20143}, {5, 22381, 5, 20143}, {4, 20723, 4, 18651}, {4, 20764, 4, 18687}, {4, 20682, 4, 18614}},
1191 /* 20 */ {5080, {6, 22293, 6, 20063}, {5, 22293, 5, 20063}, {4, 20641, 4, 18577}, {4, 20682, 4, 18614}, {4, 20601, 4, 18541}},
1192 /* 21 */ {5180, {6, 21862, 6, 19676}, {5, 21862, 5, 19676}, {4, 20243, 4, 18219}, {4, 20282, 4, 18254}, {4, 20204, 4, 18183}},
1193 /* 22 */ {5200, {6, 21778, 6, 19600}, {5, 21778, 5, 19600}, {4, 20165, 4, 18148}, {4, 20204, 4, 18183}, {4, 20126, 4, 18114}},
1194 /* 23 */ {5220, {6, 21695, 6, 19525}, {5, 21695, 5, 19525}, {4, 20088, 4, 18079}, {4, 20126, 4, 18114}, {4, 20049, 4, 18044}},
1195 /* 24 */ {5240, {6, 21612, 6, 19451}, {5, 21612, 5, 19451}, {4, 20011, 4, 18010}, {4, 20049, 4, 18044}, {4, 19973, 4, 17976}},
1196 /* 25 */ {5260, {6, 21530, 6, 19377}, {5, 21530, 5, 19377}, {4, 19935, 4, 17941}, {4, 19973, 4, 17976}, {4, 19897, 4, 17907}},
1197 /* 26 */ {5280, {6, 21448, 6, 19303}, {5, 21448, 5, 19303}, {4, 19859, 4, 17873}, {4, 19897, 4, 17907}, {4, 19822, 4, 17840}},
1198 /* 27 */ {5300, {6, 21367, 6, 19230}, {5, 21367, 5, 19230}, {4, 19784, 4, 17806}, {4, 19822, 4, 17840}, {4, 19747, 4, 17772}},
1199 /* 28 */ {5320, {6, 21287, 6, 19158}, {5, 21287, 5, 19158}, {4, 19710, 4, 17739}, {4, 19747, 4, 17772}, {4, 19673, 4, 17706}},
1200 /* 29 */ {5500, {6, 20590, 6, 18531}, {5, 20590, 5, 18531}, {4, 19065, 4, 17159}, {4, 19100, 4, 17190}, {4, 19030, 4, 17127}},
1201 /* 30 */ {5520, {6, 20516, 6, 18464}, {5, 20516, 5, 18464}, {4, 18996, 4, 17096}, {4, 19030, 4, 17127}, {4, 18962, 4, 17065}},
1202 /* 31 */ {5540, {6, 20442, 6, 18397}, {5, 20442, 5, 18397}, {4, 18927, 4, 17035}, {4, 18962, 4, 17065}, {4, 18893, 4, 17004}},
1203 /* 32 */ {5560, {6, 20368, 6, 18331}, {5, 20368, 5, 18331}, {4, 18859, 4, 16973}, {4, 18893, 4, 17004}, {4, 18825, 4, 16943}},
1204 /* 33 */ {5580, {6, 20295, 6, 18266}, {5, 20295, 5, 18266}, {4, 18792, 4, 16913}, {4, 18825, 4, 16943}, {4, 18758, 4, 16882}},
1205 /* 34 */ {5600, {6, 20223, 6, 18200}, {5, 20223, 5, 18200}, {4, 18725, 4, 16852}, {4, 18758, 4, 16882}, {4, 18691, 4, 16822}},
1206 /* 35 */ {5620, {6, 20151, 6, 18136}, {5, 20151, 5, 18136}, {4, 18658, 4, 16792}, {4, 18691, 4, 16822}, {4, 18625, 4, 16762}},
1207 /* 36 */ {5640, {6, 20079, 6, 18071}, {5, 20079, 5, 18071}, {4, 18592, 4, 16733}, {4, 18625, 4, 16762}, {4, 18559, 4, 16703}},
1208 /* 37 */ {5660, {6, 20008, 6, 18007}, {5, 20008, 5, 18007}, {4, 18526, 4, 16673}, {4, 18559, 4, 16703}, {4, 18493, 4, 16644}},
1209 /* 38 */ {5680, {6, 19938, 6, 17944}, {5, 19938, 5, 17944}, {4, 18461, 4, 16615}, {4, 18493, 4, 16644}, {4, 18428, 4, 16586}},
1210 /* 39 */ {5700, {6, 19868, 6, 17881}, {5, 19868, 5, 17881}, {4, 18396, 4, 16556}, {4, 18428, 4, 16586}, {4, 18364, 4, 16527}},
1211 /* 40 */ {5745, {6, 19712, 6, 17741}, {5, 19712, 5, 17741}, {4, 18252, 4, 16427}, {4, 18284, 4, 16455}, {4, 18220, 4, 16398}},
1212 /* 41 */ {5765, {6, 19644, 6, 17679}, {5, 19644, 5, 17679}, {4, 18189, 5, 32740}, {4, 18220, 4, 16398}, {4, 18157, 5, 32683}},
1213 /* 42 */ {5785, {6, 19576, 6, 17618}, {5, 19576, 5, 17618}, {4, 18126, 5, 32626}, {4, 18157, 5, 32683}, {4, 18094, 5, 32570}},
1214 /* 43 */ {5805, {6, 19508, 6, 17558}, {5, 19508, 5, 17558}, {4, 18063, 5, 32514}, {4, 18094, 5, 32570}, {4, 18032, 5, 32458}},
1215 /* 44 */ {5825, {6, 19441, 6, 17497}, {5, 19441, 5, 17497}, {4, 18001, 5, 32402}, {4, 18032, 5, 32458}, {4, 17970, 5, 32347}},
1216 /* 45 */ {5170, {6, 21904, 6, 19714}, {5, 21904, 5, 19714}, {4, 20282, 4, 18254}, {4, 20321, 4, 18289}, {4, 20243, 4, 18219}},
1217 /* 46 */ {5190, {6, 21820, 6, 19638}, {5, 21820, 5, 19638}, {4, 20204, 4, 18183}, {4, 20243, 4, 18219}, {4, 20165, 4, 18148}},
1218 /* 47 */ {5210, {6, 21736, 6, 19563}, {5, 21736, 5, 19563}, {4, 20126, 4, 18114}, {4, 20165, 4, 18148}, {4, 20088, 4, 18079}},
1219 /* 48 */ {5230, {6, 21653, 6, 19488}, {5, 21653, 5, 19488}, {4, 20049, 4, 18044}, {4, 20088, 4, 18079}, {4, 20011, 4, 18010}}
1220 };
1221 /* to reduce search time, please modify this define if you add or delete channel in table */
1222 #define First5GChannelIndex 14
1223
1224 void zfGetHwTurnOffdynParam(zdev_t* dev,
1225 u32_t frequency, u8_t bw40, u8_t extOffset,
1226 int* delta_slope_coeff_exp,
1227 int* delta_slope_coeff_man,
1228 int* delta_slope_coeff_exp_shgi,
1229 int* delta_slope_coeff_man_shgi)
1230 {
1231 /* Get param for turnoffdyn */
1232 u16_t i, arraySize;
1233
1234 //zmw_get_wlan_dev(dev);
1235
1236 arraySize = sizeof(zgPhyFreqCoeff)/sizeof(struct zsPhyFreqTable);
1237 if (frequency < 3000)
1238 {
1239 /* 2.4GHz Channel */
1240 for (i = 0; i < First5GChannelIndex; i++)
1241 {
1242 if (frequency == zgPhyFreqCoeff[i].frequency)
1243 break;
1244 }
1245
1246 if (i < First5GChannelIndex)
1247 {
1248 }
1249 else
1250 {
1251 zm_msg1_scan(ZM_LV_0, "Unsupported 2.4G frequency = ", frequency);
1252 return;
1253 }
1254 }
1255 else
1256 {
1257 /* 5GHz Channel */
1258 for (i = First5GChannelIndex; i < arraySize; i++)
1259 {
1260 if (frequency == zgPhyFreqCoeff[i].frequency)
1261 break;
1262 }
1263
1264 if (i < arraySize)
1265 {
1266 }
1267 else
1268 {
1269 zm_msg1_scan(ZM_LV_0, "Unsupported 5G frequency = ", frequency);
1270 return;
1271 }
1272 }
1273
1274 /* FPGA DYNAMIC_HT2040_EN fclk = 10.8 */
1275 /* FPGA STATIC_HT20_ fclk = 21.6 */
1276 /* Real Chip fclk = 40 */
1277 #if ZM_FPGA_PHY == 1
1278 //fclk = 10.8;
1279 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp;
1280 *delta_slope_coeff_man = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man;
1281 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp_shgi;
1282 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man_shgi;
1283 #else
1284 //fclk = 40;
1285 if (bw40)
1286 {
1287 /* ht2040 */
1288 if (extOffset == 1) {
1289 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp;
1290 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man;
1291 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp_shgi;
1292 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man_shgi;
1293 }
1294 else {
1295 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp;
1296 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man;
1297 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp_shgi;
1298 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man_shgi;
1299 }
1300 }
1301 else
1302 {
1303 /* static 20 */
1304 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp;
1305 *delta_slope_coeff_man = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man;
1306 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp_shgi;
1307 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man_shgi;
1308 }
1309 #endif
1310 }
1311
1312 /* Main routin frequency setting function */
1313 /* If 2.4G/5G switch, PHY need resetting BB and RF for band switch */
1314 /* Do the setting switch in zfSendFrequencyCmd() */
1315 void zfHpSetFrequencyEx(zdev_t* dev, u32_t frequency, u8_t bw40,
1316 u8_t extOffset, u8_t initRF)
1317 {
1318 u32_t cmd[9];
1319 u16_t ret;
1320 u8_t old_band;
1321 u8_t new_band;
1322 u32_t checkLoopCount;
1323 u32_t tmpValue;
1324
1325 int delta_slope_coeff_exp;
1326 int delta_slope_coeff_man;
1327 int delta_slope_coeff_exp_shgi;
1328 int delta_slope_coeff_man_shgi;
1329 struct zsHpPriv* hpPriv;
1330
1331 zmw_get_wlan_dev(dev);
1332 hpPriv = wd->hpPrivate;
1333
1334 zm_msg1_scan(ZM_LV_1, "Frequency = ", frequency);
1335 zm_msg1_scan(ZM_LV_1, "bw40 = ", bw40);
1336 zm_msg1_scan(ZM_LV_1, "extOffset = ", extOffset);
1337
1338 if ( hpPriv->coldResetNeedFreq )
1339 {
1340 hpPriv->coldResetNeedFreq = 0;
1341 initRF = 2;
1342 zm_debug_msg0("zfHpSetFrequencyEx: Do ColdReset ");
1343 }
1344 if ( hpPriv->isSiteSurvey == 2 )
1345 {
1346 /* wait time for AGC and noise calibration : not in sitesurvey and connected */
1347 checkLoopCount = 2000; /* 2000*100 = 200ms */
1348 }
1349 else
1350 {
1351 /* wait time for AGC and noise calibration : in sitesurvey */
1352 checkLoopCount = 1000; /* 1000*100 = 100ms */
1353 }
1354
1355 hpPriv->latestFrequency = frequency;
1356 hpPriv->latestBw40 = bw40;
1357 hpPriv->latestExtOffset = extOffset;
1358
1359 if ((hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_GENERAL) ||
1360 (hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK))
1361 {
1362 if ( frequency <= ZM_CH_G_14 )
1363 {
1364 /* workaround for 11g Ad Hoc beacon distribution */
1365 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 0x7f0007);
1366 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, 0x1c04901c);
1367 }
1368 }
1369
1370 /* AHB, DAC, ADC clock selection by static20/ht2040 */
1371 zfSelAdcClk(dev, bw40, frequency);
1372
1373 /* clear bb_heavy_clip_enable */
1374 reg_write(0x99e0, 0x200);
1375 zfFlushDelayWrite(dev);
1376
1377 /* Set CTS/RTS rate */
1378 if ( frequency > ZM_CH_G_14 )
1379 {
1380 //zfHpSetRTSCTSRate(dev, 0x10b010b); /* OFDM 6M */
1381 new_band = 1;
1382 }
1383 else
1384 {
1385 //zfHpSetRTSCTSRate(dev, 0x30003); /* CCK 11M */
1386 new_band = 0;
1387 }
1388
1389 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency > ZM_CH_G_14)
1390 old_band = 1;
1391 else
1392 old_band = 0;
1393
1394 //Workaround for 2.4GHz only device
1395 if ((hpPriv->OpFlags & 0x1) == 0)
1396 {
1397 if ((((struct zsHpPriv*)wd->hpPrivate)->hwFrequency == ZM_CH_G_1) && (frequency == ZM_CH_G_2))
1398 {
1399 /* Force to do band switching */
1400 old_band = 1;
1401 }
1402 }
1403
1404 /* Notify channel switch to firmware */
1405 /* TX/RX must be stopped by now */
1406 cmd[0] = 0 | (ZM_CMD_FREQ_STRAT << 8);
1407 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, 0);
1408
1409 if ((initRF != 0) || (new_band != old_band)
1410 || (((struct zsHpPriv*)wd->hpPrivate)->hwBw40 != bw40))
1411 {
1412 /* band switch */
1413 zm_msg0_scan(ZM_LV_1, "=====band switch=====");
1414
1415 if (initRF == 2 )
1416 {
1417 //Cold reset BB/ADDA
1418 zfDelayWriteInternalReg(dev, 0x1d4004, 0x800);
1419 zfFlushDelayWrite(dev);
1420 zm_msg0_scan(ZM_LV_1, "Do cold reset BB/ADDA");
1421 }
1422 else
1423 {
1424 //Warm reset BB/ADDA
1425 zfDelayWriteInternalReg(dev, 0x1d4004, 0x400);
1426 zfFlushDelayWrite(dev);
1427 }
1428
1429 /* reset workaround state to default */
1430 hpPriv->rxStrongRSSI = 0;
1431 hpPriv->strongRSSI = 0;
1432
1433 zfDelayWriteInternalReg(dev, 0x1d4004, 0x0);
1434 zfFlushDelayWrite(dev);
1435
1436 zfInitPhy(dev, frequency, bw40);
1437
1438 // zfiCheckRifs(dev);
1439
1440 /* Bank 0 1 2 3 5 6 7 */
1441 zfSetRfRegs(dev, frequency);
1442 /* Bank 4 */
1443 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1444
1445 cmd[0] = 32 | (ZM_CMD_RF_INIT << 8);
1446 }
1447 else //((new_band == old_band) && !initRF)
1448 {
1449 /* same band */
1450
1451 /* Force disable CR671 bit20 / 7823 */
1452 /* The bug has to do with the polarity of the pdadc offset calibration. There */
1453 /* is an initial calibration that is OK, and there is a continuous */
1454 /* calibration that updates the pddac with the wrong polarity. Fortunately */
1455 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
1456 #if 0
1457 cmdB[0] = 8 | (ZM_CMD_BITAND << 8);;
1458 cmdB[1] = (0xa27c + 0x1bc000);
1459 cmdB[2] = 0xffefffff;
1460 ret = zfIssueCmd(dev, cmdB, 12, ZM_OID_INTERNAL_WRITE, 0);
1461 #endif
1462
1463 /* Bank 4 */
1464 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1465
1466
1467 cmd[0] = 32 | (ZM_CMD_FREQUENCY << 8);
1468 }
1469
1470 /* Compatibility for new layout UB83 */
1471 /* Setting code at CR1 here move from the func:zfHwHTEnable() in firmware */
1472 if (((struct zsHpPriv*)wd->hpPrivate)->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
1473 {
1474 /* UB83 : one stream */
1475 tmpValue = 0;
1476 }
1477 else
1478 {
1479 /* UB81, UB82 : two stream */
1480 tmpValue = 0x100;
1481 }
1482
1483 if (1) //if (((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE == 1)
1484 {
1485 if (bw40 == 1)
1486 {
1487 if (extOffset == 1) {
1488 reg_write(0x9804, tmpValue | 0x2d4); //3d4 for real
1489 }
1490 else {
1491 reg_write(0x9804, tmpValue | 0x2c4); //3c4 for real
1492 }
1493 //# Dyn HT2040.Refer to Reg 1.
1494 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1495 //#[c]:allow short GI for HT40 packets; enable HT detection.
1496 //#[4]:enable 20/40 MHz channel detection.
1497 }
1498 else
1499 {
1500 reg_write(0x9804, tmpValue | 0x240);
1501 //# Static HT20
1502 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1503 //#[4]:Otus don't allow short GI for HT20 packets yet; enable HT detection.
1504 //#[0]:disable 20/40 MHz channel detection.
1505 }
1506 }
1507 else
1508 {
1509 reg_write(0x9804, 0x0);
1510 //# Legacy;# Direct Mapping for each chain.
1511 //#Be modified by Oligo to add dynanic for legacy.
1512 if (bw40 == 1)
1513 {
1514 reg_write(0x9804, 0x4); //# Dyn Legacy .Refer to reg 1.
1515 }
1516 else
1517 {
1518 reg_write(0x9804, 0x0); //# Static Legacy
1519 }
1520 }
1521 zfFlushDelayWrite(dev);
1522 /* end of ub83 compatibility */
1523
1524 /* Set Power, TPC, Gain table... */
1525 zfSetPowerCalTable(dev, frequency, bw40, extOffset);
1526
1527
1528 /* store frequency */
1529 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
1530 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = bw40;
1531 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = extOffset;
1532
1533 zfGetHwTurnOffdynParam(dev,
1534 frequency, bw40, extOffset,
1535 &delta_slope_coeff_exp,
1536 &delta_slope_coeff_man,
1537 &delta_slope_coeff_exp_shgi,
1538 &delta_slope_coeff_man_shgi);
1539
1540 /* related functions */
1541 frequency = frequency*1000;
1542 /* len[36] : type[0x30] : seq[?] */
1543 // cmd[0] = 28 | (ZM_CMD_FREQUENCY << 8);
1544 cmd[1] = frequency;
1545 cmd[2] = bw40;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
1546 cmd[3] = (extOffset<<2)|0x1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
1547 cmd[4] = delta_slope_coeff_exp;
1548 cmd[5] = delta_slope_coeff_man;
1549 cmd[6] = delta_slope_coeff_exp_shgi;
1550 cmd[7] = delta_slope_coeff_man_shgi;
1551 cmd[8] = checkLoopCount;
1552
1553 ret = zfIssueCmd(dev, cmd, 36, ZM_CMD_SET_FREQUENCY, 0);
1554
1555 // delay temporarily, wait for new PHY and RF
1556 //zfwSleep(dev, 1000);
1557 }
1558
1559
1560 /******************** Key ********************/
1561
1562 u16_t zfHpResetKeyCache(zdev_t* dev)
1563 {
1564 u8_t i;
1565 u32_t key[4] = {0, 0, 0, 0};
1566 struct zsHpPriv* hpPriv;
1567
1568 zmw_get_wlan_dev(dev);
1569 hpPriv=wd->hpPrivate;
1570
1571 for(i=0;i<4;i++)
1572 {
1573 zfHpSetDefaultKey(dev, i, ZM_WEP64, key, NULL);
1574 }
1575 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, 0x00);
1576 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, 0x00);
1577 zfFlushDelayWrite(dev);
1578
1579 hpPriv->camRollCallTable = (u64_t) 0;
1580
1581 return 0;
1582 }
1583
1584
1585 /************************************************************************/
1586 /* */
1587 /* FUNCTION DESCRIPTION zfSetKey */
1588 /* Set key. */
1589 /* */
1590 /* INPUTS */
1591 /* dev : device pointer */
1592 /* */
1593 /* OUTPUTS */
1594 /* 0 : success */
1595 /* other : fail */
1596 /* */
1597 /* AUTHOR */
1598 /* Stephen Chen ZyDAS Technology Corporation 2006.1 */
1599 /* */
1600 /************************************************************************/
1601 /* ! please use zfCoreSetKey() in 80211Core for SetKey */
1602 u32_t zfHpSetKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t type,
1603 u16_t* mac, u32_t* key)
1604 {
1605 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1606 u16_t ret;
1607 u16_t i;
1608 struct zsHpPriv* hpPriv;
1609
1610 zmw_get_wlan_dev(dev);
1611 hpPriv=wd->hpPrivate;
1612
1613 #if 0 /* remove to zfCoreSetKey() */
1614 zmw_declare_for_critical_section();
1615
1616 zmw_enter_critical_section(dev);
1617 wd->sta.flagKeyChanging++;
1618 zm_debug_msg1(" zfHpSetKey++++ ", wd->sta.flagKeyChanging);
1619 zmw_leave_critical_section(dev);
1620 #endif
1621
1622 cmd[0] = 0x0000281C;
1623 cmd[1] = ((u32_t)keyId<<16) + (u32_t)user;
1624 cmd[2] = ((u32_t)mac[0]<<16) + (u32_t)type;
1625 cmd[3] = ((u32_t)mac[2]<<16) + ((u32_t)mac[1]);
1626
1627 for (i=0; i<4; i++)
1628 {
1629 cmd[4+i] = key[i];
1630 }
1631
1632 if (user < 64)
1633 {
1634 hpPriv->camRollCallTable |= ((u64_t) 1) << user;
1635 }
1636
1637 //ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, NULL);
1638 ret = zfIssueCmd(dev, cmd, 32, ZM_CMD_SET_KEY, NULL);
1639 return ret;
1640 }
1641
1642
1643 u32_t zfHpSetApPairwiseKey(zdev_t* dev, u16_t* staMacAddr, u8_t type,
1644 u32_t* key, u32_t* micKey, u16_t staAid)
1645 {
1646 if ((staAid!=0) && (staAid<64))
1647 {
1648 zfHpSetKey(dev, (staAid-1), 0, type, staMacAddr, key);
1649 if ((type == ZM_TKIP)
1650 #ifdef ZM_ENABLE_CENC
1651 || (type == ZM_CENC)
1652 #endif //ZM_ENABLE_CENC
1653 )
1654 zfHpSetKey(dev, (staAid-1), 1, type, staMacAddr, micKey);
1655 return 0;
1656 }
1657 return 1;
1658 }
1659
1660 u32_t zfHpSetApGroupKey(zdev_t* dev, u16_t* apMacAddr, u8_t type,
1661 u32_t* key, u32_t* micKey, u16_t vapId)
1662 {
1663 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 0, type, apMacAddr, key); // 6D18 modify from 0 to 1 ??
1664 if ((type == ZM_TKIP)
1665 #ifdef ZM_ENABLE_CENC
1666 || (type == ZM_CENC)
1667 #endif //ZM_ENABLE_CENC
1668 )
1669 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 1, type, apMacAddr, micKey);
1670 return 0;
1671 }
1672
1673 u32_t zfHpSetDefaultKey(zdev_t* dev, u8_t keyId, u8_t type, u32_t* key, u32_t* micKey)
1674 {
1675 u16_t macAddr[3] = {0, 0, 0};
1676
1677 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1678 struct zsHpPriv* hpPriv;
1679
1680 zmw_get_wlan_dev(dev);
1681 hpPriv = wd->hpPrivate;
1682
1683 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1684 { /* If not wpa2psk , use traditional */
1685 /* Because the bug of chip , defaultkey should follow the key map rule in register 700 */
1686 if ( keyId == 0 )
1687 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1688 else
1689 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, key);
1690 }
1691 else
1692 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1693 #else
1694 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1695 #endif
1696 if ((type == ZM_TKIP)
1697
1698 #ifdef ZM_ENABLE_CENC
1699 || (type == ZM_CENC)
1700 #endif //ZM_ENABLE_CENC
1701 )
1702 {
1703 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, micKey);
1704 }
1705
1706 return 0;
1707 }
1708
1709 u32_t zfHpSetPerUserKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t* mac, u8_t type, u32_t* key, u32_t* micKey)
1710 {
1711 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1712 struct zsHpPriv* hpPriv;
1713
1714 zmw_get_wlan_dev(dev);
1715 hpPriv = wd->hpPrivate;
1716
1717 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1718 { /* If not wpa2psk , use traditional */
1719 if(keyId)
1720 { /* Set Group Key */
1721 zfHpSetKey(dev, user, 1, type, (u16_t *)mac, key);
1722 }
1723 else if(keyId == 0)
1724 { /* Set Pairwise Key */
1725 zfHpSetKey(dev, user, 0, type, (u16_t *)mac, key);
1726 }
1727 }
1728 else
1729 {
1730 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1731 }
1732 #else
1733 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1734 #endif
1735
1736 if ((type == ZM_TKIP)
1737 #ifdef ZM_ENABLE_CENC
1738 || (type == ZM_CENC)
1739 #endif //ZM_ENABLE_CENC
1740 )
1741 {
1742 zfHpSetKey(dev, user, keyId + 1, type, (u16_t *)mac, micKey);
1743 }
1744 return 0;
1745 }
1746
1747 /************************************************************************/
1748 /* */
1749 /* FUNCTION DESCRIPTION zfHpRemoveKey */
1750 /* Remove key. */
1751 /* */
1752 /* INPUTS */
1753 /* dev : device pointer */
1754 /* */
1755 /* OUTPUTS */
1756 /* 0 : success */
1757 /* other : fail */
1758 /* */
1759 /* AUTHOR */
1760 /* Yuan-Gu Wei ZyDAS Technology Corporation 2006.6 */
1761 /* */
1762 /************************************************************************/
1763 u16_t zfHpRemoveKey(zdev_t* dev, u16_t user)
1764 {
1765 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1766 u16_t ret = 0;
1767
1768 cmd[0] = 0x00002904;
1769 cmd[1] = (u32_t)user;
1770
1771 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
1772 return ret;
1773 }
1774
1775
1776
1777 /******************** DMA ********************/
1778 u16_t zfHpStartRecv(zdev_t* dev)
1779 {
1780 zfDelayWriteInternalReg(dev, 0x1c3d30, 0x100);
1781 zfFlushDelayWrite(dev);
1782
1783 return 0;
1784 }
1785
1786 u16_t zfHpStopRecv(zdev_t* dev)
1787 {
1788 return 0;
1789 }
1790
1791
1792 /******************** MAC ********************/
1793 void zfInitMac(zdev_t* dev)
1794 {
1795 /* ACK extension register */
1796 // jhlee temp : change value 0x2c -> 0x40
1797 // honda resolve short preamble problem : 0x40 -> 0x75
1798 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_EXTENSION, 0x40); // 0x28 -> 0x2c 6522:yflee
1799
1800 /* TxQ0/1/2/3 Retry MAX=2 => transmit 3 times and degrade rate for retry */
1801 /* PB42 AP crash issue: */
1802 /* Workaround the crash issue by CTS/RTS, set retry max to zero for */
1803 /* workaround tx underrun which enable CTS/RTS */
1804 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RETRY_MAX, 0); // 0x11111 => 0
1805
1806 /* use hardware MIC check */
1807 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1808
1809 /* Set Rx threshold to 1600 */
1810 #if ZM_LARGEPAYLOAD_TEST == 1
1811 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc4000);
1812 #else
1813 #ifndef ZM_DISABLE_AMSDU8K_SUPPORT
1814 /* The maximum A-MSDU length is 3839/7935 */
1815 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc1f80);
1816 #else
1817 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc0f80);
1818 #endif
1819 #endif
1820
1821 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
1822 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_PE_DELAY, 0x70);
1823 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
1824 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
1825
1826 /* CF-END mode */
1827 zfDelayWriteInternalReg(dev, 0x1c3b2c, 0x19000000);
1828
1829 //NAV protects ACK only (in TXOP)
1830 zfDelayWriteInternalReg(dev, 0x1c3b38, 0x201);
1831
1832
1833 /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
1834 /* OTUS set AM to 0x1 */
1835 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_HT1, 0x8000170);
1836
1837 /* TODO : wep backoff protection 0x63c */
1838 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BACKOFF_PROTECT, 0x105);
1839
1840 /* AGG test code*/
1841 /* Aggregation MAX number and timeout */
1842 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x10000a);
1843 /* Filter any control frames, BAR is bit 24 */
1844 zfDelayWriteInternalReg(dev, 0x1c368c, 0x0500ffff);
1845 /* Enable deaggregator */
1846 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1847
1848 /* Basic rate */
1849 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, 0x150f);
1850 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MANDATORY_RATE, 0x150f);
1851 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
1852
1853 /* MIMO resposne control */
1854 zfDelayWriteInternalReg(dev, 0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
1855
1856 /* Enable LED0 and LED1 */
1857 zfDelayWriteInternalReg(dev, 0x1d0100, 0x3);
1858 zfDelayWriteInternalReg(dev, 0x1d0104, 0x3);
1859
1860 /* switch MAC to OTUS interface */
1861 zfDelayWriteInternalReg(dev, 0x1c3600, 0x3);
1862
1863 /* RXMAC A-MPDU length threshold */
1864 zfDelayWriteInternalReg(dev, 0x1c3c50, 0xffff);
1865
1866 /* Phy register read timeout */
1867 zfDelayWriteInternalReg(dev, 0x1c3680, 0xf00008);
1868
1869 /* Disable Rx TimeOut : workaround for BB.
1870 * OTUS would interrupt the rx frame that sent by OWL TxUnderRun
1871 * because OTUS rx timeout behavior, then OTUS would not ack the BA for
1872 * this AMPDU from OWL.
1873 * Fix by Perry Hwang. 2007/05/10.
1874 * 0x1c362c : Rx timeout value : bit 27~16
1875 */
1876 zfDelayWriteInternalReg(dev, 0x1c362c, 0x0);
1877
1878 //Set USB Rx stream mode MAX packet number to 2
1879 // Max packet number = *0x1e1110 + 1
1880 zfDelayWriteInternalReg(dev, 0x1e1110, 0x4);
1881 //Set USB Rx stream mode timeout to 10us
1882 zfDelayWriteInternalReg(dev, 0x1e1114, 0x80);
1883
1884 //Set CPU clock frequency to 88/80MHz
1885 zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
1886
1887 //Set WLAN DMA interrupt mode : generate int per packet
1888 zfDelayWriteInternalReg(dev, 0x1c3d7c, 0x110011);
1889
1890 /* 7807 */
1891 /* enable func : Reset FIFO1 and FIFO2 when queue-gnt is low */
1892 /* 0x1c3bb0 Bit2 */
1893 /* Disable SwReset in firmware for TxHang, enable reset FIFO func. */
1894 zfDelayWriteInternalReg(dev, 0x1c3bb0, 0x4);
1895
1896 /* Disables the CF_END frame */
1897 zfDelayWriteInternalReg(dev, ZM_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141E0F48);
1898
1899 /* Disable the SW Decrypt*/
1900 zfDelayWriteInternalReg(dev, 0x1c3678, 0x70);
1901 zfFlushDelayWrite(dev);
1902 //---------------------
1903
1904 /* Set TxQs CWMIN, CWMAX, AIFS and TXO to WME STA default. */
1905 zfUpdateDefaultQosParameter(dev, 0);
1906
1907 //zfSelAdcClk(dev, 0);
1908
1909 return;
1910 }
1911
1912
1913 u16_t zfHpSetSnifferMode(zdev_t* dev, u16_t on)
1914 {
1915 if (on != 0)
1916 {
1917 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000001);
1918 }
1919 else
1920 {
1921 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1922 }
1923 zfFlushDelayWrite(dev);
1924 return 0;
1925 }
1926
1927
1928 u16_t zfHpSetApStaMode(zdev_t* dev, u8_t mode)
1929 {
1930 struct zsHpPriv* hpPriv;
1931
1932 zmw_get_wlan_dev(dev);
1933 hpPriv = wd->hpPrivate;
1934 hpPriv->dot11Mode = mode;
1935
1936 switch(mode)
1937 {
1938 case ZM_HAL_80211_MODE_AP:
1939 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000a1);
1940 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1941 break;
1942
1943 case ZM_HAL_80211_MODE_STA:
1944 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000002);
1945 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1946 break;
1947
1948 case ZM_HAL_80211_MODE_IBSS_GENERAL:
1949 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000000);
1950 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1951 break;
1952
1953 case ZM_HAL_80211_MODE_IBSS_WPA2PSK:
1954 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000e0);
1955 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x41); // for multiple ( > 2 ) stations IBSS network
1956 break;
1957
1958 default:
1959 goto skip;
1960 }
1961
1962 zfFlushDelayWrite(dev);
1963
1964 skip:
1965 return 0;
1966 }
1967
1968
1969 u16_t zfHpSetBssid(zdev_t* dev, u8_t* bssidSrc)
1970 {
1971 u32_t address;
1972 u16_t *bssid = (u16_t *)bssidSrc;
1973
1974 address = bssid[0] + (((u32_t)bssid[1]) << 16);
1975 zfDelayWriteInternalReg(dev, 0x1c3618, address);
1976
1977 address = (u32_t)bssid[2];
1978 zfDelayWriteInternalReg(dev, 0x1c361C, address);
1979 zfFlushDelayWrite(dev);
1980 return 0;
1981 }
1982
1983
1984 /************************************************************************/
1985 /* */
1986 /* FUNCTION DESCRIPTION zfHpUpdateQosParameter */
1987 /* Update TxQs CWMIN, CWMAX, AIFS and TXOP. */
1988 /* */
1989 /* INPUTS */
1990 /* dev : device pointer */
1991 /* cwminTbl : CWMIN parameter for TxQs */
1992 /* cwmaxTbl : CWMAX parameter for TxQs */
1993 /* aifsTbl: AIFS parameter for TxQs */
1994 /* txopTbl : TXOP parameter for TxQs */
1995 /* */
1996 /* OUTPUTS */
1997 /* none */
1998 /* */
1999 /* AUTHOR */
2000 /* Stephen ZyDAS Technology Corporation 2006.6 */
2001 /* */
2002 /************************************************************************/
2003 u8_t zfHpUpdateQosParameter(zdev_t* dev, u16_t* cwminTbl, u16_t* cwmaxTbl,
2004 u16_t* aifsTbl, u16_t* txopTbl)
2005 {
2006 struct zsHpPriv* hpPriv;
2007
2008 zmw_get_wlan_dev(dev);
2009 hpPriv = wd->hpPrivate;
2010
2011 zm_msg0_mm(ZM_LV_0, "zfHalUpdateQosParameter()");
2012
2013 /* Note : Do not change cwmin for Q0 in Ad Hoc mode */
2014 /* otherwise driver will fail in Wifi beacon distribution */
2015 if (hpPriv->dot11Mode == ZM_HAL_80211_MODE_STA)
2016 {
2017 #if 0 //Restore CWmin to improve down link throughput
2018 //cheating in BE traffic
2019 if (wd->sta.EnableHT == 1)
2020 {
2021 //cheating in BE traffic
2022 cwminTbl[0] = 7;//15;
2023 }
2024 #endif
2025 cwmaxTbl[0] = 127;//1023;
2026 aifsTbl[0] = 2*9+10;//3 * 9 + 10;
2027 }
2028
2029 /* CWMIN and CWMAX */
2030 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, cwminTbl[0]
2031 + ((u32_t)cwmaxTbl[0]<<16));
2032 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_CW, cwminTbl[1]
2033 + ((u32_t)cwmaxTbl[1]<<16));
2034 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC2_CW, cwminTbl[2]
2035 + ((u32_t)cwmaxTbl[2]<<16));
2036 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_CW, cwminTbl[3]
2037 + ((u32_t)cwmaxTbl[3]<<16));
2038 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC4_CW, cwminTbl[4]
2039 + ((u32_t)cwmaxTbl[4]<<16));
2040
2041 /* AIFS */
2042 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, aifsTbl[0]
2043 +((u32_t)aifsTbl[0]<<12)+((u32_t)aifsTbl[0]<<24));
2044 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_AIFS, (aifsTbl[0]>>8)
2045 +((u32_t)aifsTbl[0]<<4)+((u32_t)aifsTbl[0]<<16));
2046
2047 /* TXOP */
2048 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, txopTbl[0]
2049 + ((u32_t)txopTbl[1]<<16));
2050 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_TXOP, txopTbl[2]
2051 + ((u32_t)txopTbl[3]<<16));
2052
2053 zfFlushDelayWrite(dev);
2054
2055 hpPriv->txop[0] = txopTbl[0];
2056 hpPriv->txop[1] = txopTbl[1];
2057 hpPriv->txop[2] = txopTbl[2];
2058 hpPriv->txop[3] = txopTbl[3];
2059 hpPriv->cwmin[0] = cwminTbl[0];
2060 hpPriv->cwmax[0] = cwmaxTbl[0];
2061 hpPriv->cwmin[1] = cwminTbl[1];
2062 hpPriv->cwmax[1] = cwmaxTbl[1];
2063
2064 return 0;
2065 }
2066
2067
2068 void zfHpSetAtimWindow(zdev_t* dev, u16_t atimWin)
2069 {
2070 zm_msg1_mm(ZM_LV_0, "Set ATIM window to ", atimWin);
2071 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ATIM_WINDOW, atimWin);
2072 zfFlushDelayWrite(dev);
2073 }
2074
2075
2076 void zfHpSetBasicRateSet(zdev_t* dev, u16_t bRateBasic, u16_t gRateBasic)
2077 {
2078 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, bRateBasic
2079 | ((u16_t)gRateBasic<<8));
2080 zfFlushDelayWrite(dev);
2081 }
2082
2083
2084 /* HT40 send by OFDM 6M */
2085 /* otherwise use reg 0x638 */
2086 void zfHpSetRTSCTSRate(zdev_t* dev, u32_t rate)
2087 {
2088 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, rate);
2089 zfFlushDelayWrite(dev);
2090 }
2091
2092 void zfHpSetMacAddress(zdev_t* dev, u16_t* macAddr, u16_t macAddrId)
2093 {
2094 if (macAddrId == 0)
2095 {
2096 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L,
2097 (((u32_t)macAddr[1])<<16) | macAddr[0]);
2098 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, macAddr[2]);
2099 }
2100 else if (macAddrId <= 7)
2101 {
2102 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8),
2103 macAddr[0] + ((u32_t)macAddr[1]<<16));
2104 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8)+4,
2105 macAddr[2]);
2106 }
2107 zfFlushDelayWrite(dev);
2108 }
2109
2110 void zfHpSetMulticastList(zdev_t* dev, u8_t size, u8_t* pList, u8_t bAllMulticast)
2111 {
2112 struct zsMulticastAddr* pMacList = (struct zsMulticastAddr*) pList;
2113 u8_t i;
2114 u32_t value;
2115 u32_t swRegMulHashValueH, swRegMulHashValueL;
2116
2117 swRegMulHashValueH = 0x80000000;
2118 swRegMulHashValueL = 0;
2119
2120 if ( bAllMulticast )
2121 {
2122 swRegMulHashValueH = swRegMulHashValueL = ~0;
2123 }
2124 else
2125 {
2126 for(i=0; i<size; i++)
2127 {
2128 value = pMacList[i].addr[5] >> 2;
2129
2130 if ( value < 32 )
2131 {
2132 swRegMulHashValueL |= (1 << value);
2133 }
2134 else
2135 {
2136 swRegMulHashValueH |= (1 << (value-32));
2137 }
2138 }
2139 }
2140
2141 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_L,
2142 swRegMulHashValueL);
2143 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_H,
2144 swRegMulHashValueH);
2145 zfFlushDelayWrite(dev);
2146 return;
2147 }
2148
2149 /******************** Beacon ********************/
2150 void zfHpEnableBeacon(zdev_t* dev, u16_t mode, u16_t bcnInterval, u16_t dtim, u8_t enableAtim)
2151 {
2152 u32_t value;
2153
2154 zmw_get_wlan_dev(dev);
2155
2156 /* Beacon Ready */
2157 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_CTRL, 0);
2158 /* Beacon DMA buffer address */
2159 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2160
2161 value = bcnInterval;
2162
2163 value |= (((u32_t) dtim) << 16);
2164
2165 if (mode == ZM_MODE_AP)
2166 {
2167
2168 value |= 0x1000000;
2169 }
2170 else if (mode == ZM_MODE_IBSS)
2171 {
2172 value |= 0x2000000;
2173
2174 if ( enableAtim )
2175 {
2176 value |= 0x4000000;
2177 }
2178 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 1;
2179 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnInterval = value;
2180 }
2181 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
2182
2183 /* Beacon period and beacon enable */
2184 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, value);
2185 zfFlushDelayWrite(dev);
2186 }
2187
2188 void zfHpDisableBeacon(zdev_t* dev)
2189 {
2190 zmw_get_wlan_dev(dev);
2191
2192 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 0;
2193
2194 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
2195 zfFlushDelayWrite(dev);
2196 }
2197
2198 void zfHpLedCtrl(zdev_t* dev, u16_t ledId, u8_t mode)
2199 {
2200 u16_t state;
2201 zmw_get_wlan_dev(dev);
2202
2203 //zm_debug_msg1("LED ID=", ledId);
2204 //zm_debug_msg1("LED mode=", mode);
2205 if (ledId < 2)
2206 {
2207 if (((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] != mode)
2208 {
2209 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] = mode;
2210
2211 state = ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0]
2212 | (((struct zsHpPriv*)wd->hpPrivate)->ledMode[1]<<1);
2213 zfDelayWriteInternalReg(dev, 0x1d0104, state);
2214 zfFlushDelayWrite(dev);
2215 //zm_debug_msg0("Update LED");
2216 }
2217 }
2218 }
2219
2220 /************************************************************************/
2221 /* */
2222 /* FUNCTION DESCRIPTION zfHpResetTxRx */
2223 /* Reset Tx and Rx Desc. */
2224 /* */
2225 /* INPUTS */
2226 /* dev : device pointer */
2227 /* */
2228 /* OUTPUTS */
2229 /* 0 : success */
2230 /* other : fail */
2231 /* */
2232 /* AUTHOR */
2233 /* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */
2234 /* */
2235 /************************************************************************/
2236 u16_t zfHpUsbReset(zdev_t* dev)
2237 {
2238 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2239 u16_t ret = 0;
2240
2241 //zm_debug_msg0("CWY - Reset Tx and Rx");
2242
2243 cmd[0] = 0 | (ZM_CMD_RESET << 8);
2244
2245 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL);
2246 return ret;
2247 }
2248
2249 u16_t zfHpDKReset(zdev_t* dev, u8_t flag)
2250 {
2251 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2252 u16_t ret = 0;
2253
2254 //zm_debug_msg0("CWY - Reset Tx and Rx");
2255
2256 cmd[0] = 4 | (ZM_CMD_DKRESET << 8);
2257 cmd[1] = flag;
2258
2259 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
2260 return ret;
2261 }
2262
2263 u32_t zfHpCwmUpdate(zdev_t* dev)
2264 {
2265 //u32_t cmd[3];
2266 //u16_t ret;
2267 //
2268 //cmd[0] = 0x00000008;
2269 //cmd[1] = 0x1c36e8;
2270 //cmd[2] = 0x1c36ec;
2271 //
2272 //ret = zfIssueCmd(dev, cmd, 12, ZM_CWM_READ, 0);
2273 //return ret;
2274
2275 struct zsHpPriv* hpPriv;
2276
2277 zmw_get_wlan_dev(dev);
2278 hpPriv=wd->hpPrivate;
2279
2280 zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(hpPriv->ctlBusy, hpPriv->extBusy));
2281
2282 hpPriv->ctlBusy = 0;
2283 hpPriv->extBusy = 0;
2284
2285 return 0;
2286 }
2287
2288 u32_t zfHpAniUpdate(zdev_t* dev)
2289 {
2290 u32_t cmd[5];
2291 u16_t ret;
2292
2293 cmd[0] = 0x00000010;
2294 cmd[1] = 0x1c36e8;
2295 cmd[2] = 0x1c36ec;
2296 cmd[3] = 0x1c3cb4;
2297 cmd[4] = 0x1c3cb8;
2298
2299 ret = zfIssueCmd(dev, cmd, 20, ZM_ANI_READ, 0);
2300 return ret;
2301 }
2302
2303 /*
2304 * Update Beacon RSSI in ANI
2305 */
2306 u32_t zfHpAniUpdateRssi(zdev_t* dev, u8_t rssi)
2307 {
2308 struct zsHpPriv* hpPriv;
2309
2310 zmw_get_wlan_dev(dev);
2311 hpPriv=wd->hpPrivate;
2312
2313 hpPriv->stats.ast_nodestats.ns_avgbrssi = rssi;
2314
2315 return 0;
2316 }
2317
2318 #define ZM_SEEPROM_MAC_ADDRESS_OFFSET (0x1400 + (0x106<<1))
2319 #define ZM_SEEPROM_REGDOMAIN_OFFSET (0x1400 + (0x104<<1))
2320 #define ZM_SEEPROM_VERISON_OFFSET (0x1400 + (0x102<<1))
2321 #define ZM_SEEPROM_HARDWARE_TYPE_OFFSET (0x1374)
2322 #define ZM_SEEPROM_HW_HEAVY_CLIP (0x161c)
2323
2324 u32_t zfHpGetMacAddress(zdev_t* dev)
2325 {
2326 u32_t cmd[7];
2327 u16_t ret;
2328
2329 cmd[0] = 0x00000000 | 24;
2330 cmd[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET;
2331 cmd[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4;
2332 cmd[3] = ZM_SEEPROM_REGDOMAIN_OFFSET;
2333 cmd[4] = ZM_SEEPROM_VERISON_OFFSET;
2334 cmd[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET;
2335 cmd[6] = ZM_SEEPROM_HW_HEAVY_CLIP;
2336
2337 ret = zfIssueCmd(dev, cmd, 28, ZM_MAC_READ, 0);
2338 return ret;
2339 }
2340
2341 u32_t zfHpGetTransmitPower(zdev_t* dev)
2342 {
2343 struct zsHpPriv* hpPriv;
2344 u16_t tpc = 0;
2345
2346 zmw_get_wlan_dev(dev);
2347 hpPriv = wd->hpPrivate;
2348
2349 if (hpPriv->hwFrequency < 3000) {
2350 tpc = hpPriv->tPow2x2g[0] & 0x3f;
2351 wd->maxTxPower2 &= 0x3f;
2352 tpc = (tpc > wd->maxTxPower2)? wd->maxTxPower2 : tpc;
2353 } else {
2354 tpc = hpPriv->tPow2x5g[0] & 0x3f;
2355 wd->maxTxPower5 &= 0x3f;
2356 tpc = (tpc > wd->maxTxPower5)? wd->maxTxPower5 : tpc;
2357 }
2358
2359 return tpc;
2360 }
2361
2362 u8_t zfHpGetMinTxPower(zdev_t* dev)
2363 {
2364 struct zsHpPriv* hpPriv;
2365 u8_t tpc = 0;
2366
2367 zmw_get_wlan_dev(dev);
2368 hpPriv = wd->hpPrivate;
2369
2370 if (hpPriv->hwFrequency < 3000)
2371 {
2372 if(wd->BandWidth40)
2373 {
2374 //40M
2375 tpc = (hpPriv->tPow2x2gHt40[7]&0x3f);
2376 }
2377 else
2378 {
2379 //20M
2380 tpc = (hpPriv->tPow2x2gHt20[7]&0x3f);
2381 }
2382 }
2383 else
2384 {
2385 if(wd->BandWidth40)
2386 {
2387 //40M
2388 tpc = (hpPriv->tPow2x5gHt40[7]&0x3f);
2389 }
2390 else
2391 {
2392 //20M
2393 tpc = (hpPriv->tPow2x5gHt20[7]&0x3f);
2394 }
2395 }
2396
2397 return tpc;
2398 }
2399
2400 u8_t zfHpGetMaxTxPower(zdev_t* dev)
2401 {
2402 struct zsHpPriv* hpPriv;
2403 u8_t tpc = 0;
2404
2405 zmw_get_wlan_dev(dev);
2406 hpPriv = wd->hpPrivate;
2407
2408 if (hpPriv->hwFrequency < 3000)
2409 {
2410 tpc = (hpPriv->tPow2xCck[0]&0x3f);
2411 }
2412 else
2413 {
2414 tpc =(hpPriv->tPow2x5g[0]&0x3f);
2415 }
2416
2417 return tpc;
2418 }
2419
2420 u32_t zfHpLoadEEPROMFromFW(zdev_t* dev)
2421 {
2422 u32_t cmd[16];
2423 u32_t ret=0, i, j;
2424 zmw_get_wlan_dev(dev);
2425
2426 i = ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq;
2427
2428 cmd[0] = ZM_HAL_MAX_EEPROM_PRQ*4;
2429
2430 for (j=0; j<ZM_HAL_MAX_EEPROM_PRQ; j++)
2431 {
2432 cmd[j+1] = 0x1000 + (((i*ZM_HAL_MAX_EEPROM_PRQ) + j)*4);
2433 }
2434
2435 ret = zfIssueCmd(dev, cmd, (ZM_HAL_MAX_EEPROM_PRQ+1)*4, ZM_EEPROM_READ, 0);
2436
2437 return ret;
2438 }
2439
2440 void zfHpHeartBeat(zdev_t* dev)
2441 {
2442 struct zsHpPriv* hpPriv;
2443 u8_t polluted = 0;
2444 u8_t ackTpc;
2445
2446 zmw_get_wlan_dev(dev);
2447 hpPriv=wd->hpPrivate;
2448
2449 /* Workaround : Make OTUS fire more beacon in ad hoc mode in 2.4GHz */
2450 if (hpPriv->ibssBcnEnabled != 0)
2451 {
2452 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2453 {
2454 if ((wd->tick % 10) == 0)
2455 {
2456 if ((wd->tick % 40) == 0)
2457 {
2458 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval-1);
2459 polluted = 1;
2460 }
2461 else
2462 {
2463 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval);
2464 polluted = 1;
2465 }
2466 }
2467 }
2468 }
2469
2470 if ((wd->tick & 0x3f) == 0x25)
2471 {
2472 /* Workaround for beacon stuck after SW reset */
2473 if (hpPriv->ibssBcnEnabled != 0)
2474 {
2475 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2476 polluted = 1;
2477 }
2478
2479 //DbgPrint("hpPriv->aggMaxDurationBE=%d", hpPriv->aggMaxDurationBE);
2480 //DbgPrint("wd->sta.avgSizeOfReceivePackets=%d", wd->sta.avgSizeOfReceivePackets);
2481 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2482 && (zfStaIsConnected(dev))
2483 && (wd->sta.EnableHT == 1) //11n mode
2484 && (wd->BandWidth40 == 1) //40MHz mode
2485 && (wd->sta.enableDrvBA ==0) //Marvel AP
2486 && (hpPriv->aggMaxDurationBE > 2000) //BE TXOP > 2ms
2487 && (wd->sta.avgSizeOfReceivePackets > 1420))
2488 {
2489 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x8000a);
2490 polluted = 1;
2491 }
2492 else
2493 {
2494 zfDelayWriteInternalReg(dev, 0x1c3b9c, hpPriv->aggPktNum);
2495 polluted = 1;
2496 }
2497
2498 if (wd->dynamicSIFSEnable == 0)
2499 {
2500 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2501 && (zfStaIsConnected(dev))
2502 && (wd->sta.EnableHT == 1) //11n mode
2503 && (wd->BandWidth40 == 0) //20MHz mode
2504 && (wd->sta.enableDrvBA ==0)) //Marvel AP
2505 {
2506 zfDelayWriteInternalReg(dev, 0x1c3698, 0x5144000);
2507 polluted = 1;
2508 }
2509 else
2510 {
2511 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2512 polluted = 1;
2513 }
2514 }
2515 else
2516 {
2517 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2518 && (zfStaIsConnected(dev))
2519 && (wd->sta.EnableHT == 1) //11n mode
2520 && (wd->sta.athOwlAp == 1)) //Atheros AP
2521 {
2522 if (hpPriv->retransmissionEvent)
2523 {
2524 switch(hpPriv->latestSIFS)
2525 {
2526 case 0:
2527 hpPriv->latestSIFS = 1;
2528 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0x8144000);
2529 break;
2530 case 1:
2531 hpPriv->latestSIFS = 2;
2532 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2533 break;
2534 case 2:
2535 hpPriv->latestSIFS = 3;
2536 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xc144000);
2537 break;
2538 case 3:
2539 hpPriv->latestSIFS = 0;
2540 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2541 break;
2542 default:
2543 hpPriv->latestSIFS = 0;
2544 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2545 break;
2546 }
2547 polluted = 1;
2548 zm_debug_msg1("##### Correct Tx retransmission issue #####, ", hpPriv->latestSIFS);
2549 hpPriv->retransmissionEvent = 0;
2550 }
2551 }
2552 else
2553 {
2554 hpPriv->latestSIFS = 0;
2555 hpPriv->retransmissionEvent = 0;
2556 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2557 polluted = 1;
2558 }
2559 }
2560
2561 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2562 {
2563 #define ZM_SIGNAL_THRESHOLD 66
2564 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2565 && (zfStaIsConnected(dev))
2566 && (wd->SignalStrength > ZM_SIGNAL_THRESHOLD))
2567 {
2568 /* remove state handle, always rewrite register setting */
2569 //if (hpPriv->strongRSSI == 0)
2570 {
2571 hpPriv->strongRSSI = 1;
2572 /* Strong RSSI, set ACK to one Tx stream and lower Tx power 7dbm */
2573 if (hpPriv->currentAckRtsTpc > (14+10))
2574 {
2575 ackTpc = hpPriv->currentAckRtsTpc - 14;
2576 }
2577 else
2578 {
2579 ackTpc = 10;
2580 }
2581 zfDelayWriteInternalReg(dev, 0x1c3694, ((ackTpc) << 20) | (0x1<<26));
2582 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((ackTpc) << 5 ) | (0x1<<11) |
2583 ((ackTpc) << 21) | (0x1<<27) );
2584 polluted = 1;
2585 }
2586 }
2587 else
2588 {
2589 /* remove state handle, always rewrite register setting */
2590 //if (hpPriv->strongRSSI == 1)
2591 {
2592 hpPriv->strongRSSI = 0;
2593 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
2594 {
2595 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x1<<26));
2596 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x1<<11) |
2597 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x1<<27) );
2598 }
2599 else
2600 {
2601 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
2602 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
2603 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
2604 }
2605 polluted = 1;
2606 }
2607 }
2608 #undef ZM_SIGNAL_THRESHOLD
2609 }
2610
2611 if ((hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) == 0)
2612 {
2613 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2614 {
2615 #define ZM_RX_SIGNAL_THRESHOLD_H 71
2616 #define ZM_RX_SIGNAL_THRESHOLD_L 66
2617 u8_t rxSignalThresholdH = ZM_RX_SIGNAL_THRESHOLD_H;
2618 u8_t rxSignalThresholdL = ZM_RX_SIGNAL_THRESHOLD_L;
2619 #undef ZM_RX_SIGNAL_THRESHOLD_H
2620 #undef ZM_RX_SIGNAL_THRESHOLD_L
2621
2622 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2623 && (zfStaIsConnected(dev))
2624 && (wd->SignalStrength > rxSignalThresholdH)
2625 )//&& (hpPriv->rxStrongRSSI == 0))
2626 {
2627 hpPriv->rxStrongRSSI = 1;
2628 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1220);
2629 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x900);
2630 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x900);
2631 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x900);
2632 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2633 {
2634 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2635 {
2636 zfDelayWriteInternalReg(dev, 0x1c8960, 0x900);
2637 }
2638 else
2639 {
2640 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2641 }
2642 }
2643 else
2644 {
2645 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2646 }
2647 polluted = 1;
2648 }
2649 else if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2650 && (zfStaIsConnected(dev))
2651 && (wd->SignalStrength > rxSignalThresholdL)
2652 )//&& (hpPriv->rxStrongRSSI == 1))
2653 {
2654 //Do nothing to prevent frequently Rx switching
2655 }
2656 else
2657 {
2658 /* remove state handle, always rewrite register setting */
2659 //if (hpPriv->rxStrongRSSI == 1)
2660 {
2661 hpPriv->rxStrongRSSI = 0;
2662 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1120);
2663 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x9b40);
2664 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x9b40);
2665 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x9b40);
2666 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2667 {
2668 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2669 {
2670 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2671 }
2672 else
2673 {
2674 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2675 }
2676 }
2677 else
2678 {
2679 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
2680 }
2681 polluted = 1;
2682 }
2683 }
2684
2685 }
2686 }
2687
2688 if (hpPriv->usbAcSendBytes[3] > (hpPriv->usbAcSendBytes[0]*2))
2689 {
2690 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[3]);
2691 polluted = 1;
2692 }
2693 else if (hpPriv->usbAcSendBytes[2] > (hpPriv->usbAcSendBytes[0]*2))
2694 {
2695 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[2]);
2696 polluted = 1;
2697 }
2698 else if (hpPriv->usbAcSendBytes[1] > (hpPriv->usbAcSendBytes[0]*2))
2699 {
2700 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[1]+((u32_t)hpPriv->cwmax[1]<<16));
2701 polluted = 1;
2702 }
2703 else
2704 {
2705 if (hpPriv->slotType == 1)
2706 {
2707 if ((wd->sta.enableDrvBA ==0) //Marvel AP
2708 && (hpPriv->aggMaxDurationBE > 2000)) //BE TXOP > 2ms
2709 {
2710 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, (hpPriv->cwmin[0]/2)+((u32_t)hpPriv->cwmax[0]<<16));
2711 }
2712 else
2713 {
2714 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2715 }
2716 polluted = 1;
2717 }
2718 else
2719 {
2720 /* Compensation for 20us slot time */
2721 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 58+((u32_t)hpPriv->cwmax[0]<<16));
2722 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2723 polluted = 1;
2724 }
2725
2726 if ((wd->sta.SWEncryptEnable & (ZM_SW_TKIP_ENCRY_EN|ZM_SW_WEP_ENCRY_EN)) == 0)
2727 {
2728 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[0]);
2729 polluted = 1;
2730 }
2731 else
2732 {
2733 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, 0x30);
2734 polluted = 1;
2735 }
2736
2737 }
2738 hpPriv->usbAcSendBytes[3] = 0;
2739 hpPriv->usbAcSendBytes[2] = 0;
2740 hpPriv->usbAcSendBytes[1] = 0;
2741 hpPriv->usbAcSendBytes[0] = 0;
2742 }
2743
2744 if (polluted == 1)
2745 {
2746 zfFlushDelayWrite(dev);
2747 }
2748
2749 return;
2750 }
2751
2752 /*
2753 * 0x1d4008 : AHB, DAC, ADC clock selection
2754 * bit1~0 AHB_CLK : AHB clock selection,
2755 * 00 : OSC 40MHz;
2756 * 01 : 20MHz in A mode, 22MHz in G mode;
2757 * 10 : 40MHz in A mode, 44MHz in G mode;
2758 * 11 : 80MHz in A mode, 88MHz in G mode.
2759 * bit3~2 CLK_SEL : Select the clock source of clk160 in ADDAC.
2760 * 00 : PLL divider's output;
2761 * 01 : PLL divider's output divided by 2;
2762 * 10 : PLL divider's output divided by 4;
2763 * 11 : REFCLK from XTALOSCPAD.
2764 */
2765 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency)
2766 {
2767 if(bw40 == 1)
2768 {
2769 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
2770 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
2771 zfFlushDelayWrite(dev);
2772 }
2773 else
2774 {
2775 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x70);
2776 if ( frequency <= ZM_CH_G_14 )
2777 {
2778 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x105);
2779 }
2780 else
2781 {
2782 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x104);
2783 }
2784 zfFlushDelayWrite(dev);
2785 }
2786 }
2787
2788 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value)
2789 {
2790 u32_t cmd[2];
2791 u16_t ret;
2792
2793 cmd[0] = 0x00008004;
2794 cmd[1] = value;
2795
2796 ret = zfIssueCmd(dev, cmd, 8, ZM_CMD_ECHO, NULL);
2797 return ret;
2798 }
2799
2800 #ifdef ZM_DRV_INIT_USB_MODE
2801
2802 #define ZM_USB_US_STREAM_MODE 0x00000000
2803 #define ZM_USB_US_PACKET_MODE 0x00000008
2804 #define ZM_USB_DS_ENABLE 0x00000001
2805 #define ZM_USB_US_ENABLE 0x00000002
2806
2807 #define ZM_USB_RX_STREAM_4K 0x00000000
2808 #define ZM_USB_RX_STREAM_8K 0x00000010
2809 #define ZM_USB_RX_STREAM_16K 0x00000020
2810 #define ZM_USB_RX_STREAM_32K 0x00000030
2811
2812 #define ZM_USB_TX_STREAM_MODE 0x00000040
2813
2814 #define ZM_USB_MODE_CTRL_REG 0x001E1108
2815
2816 void zfInitUsbMode(zdev_t* dev)
2817 {
2818 u32_t mode;
2819 zmw_get_wlan_dev(dev);
2820
2821 /* TODO: Set USB mode by reading registery */
2822 mode = ZM_USB_DS_ENABLE | ZM_USB_US_ENABLE | ZM_USB_US_PACKET_MODE;
2823
2824 zfDelayWriteInternalReg(dev, ZM_USB_MODE_CTRL_REG, mode);
2825 zfFlushDelayWrite(dev);
2826 }
2827 #endif
2828
2829 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage);
2830 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40);
2831 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40);
2832
2833
2834 s32_t zfInterpolateFunc(s32_t x, s32_t x1, s32_t y1, s32_t x2, s32_t y2)
2835 {
2836 s32_t y;
2837
2838 if (y2 == y1)
2839 {
2840 y = y1;
2841 }
2842 else if (x == x1)
2843 {
2844 y = y1;
2845 }
2846 else if (x == x2)
2847 {
2848 y = y2;
2849 }
2850 else if (x2 != x1)
2851 {
2852 y = y1 + (((y2-y1) * (x-x1))/(x2-x1));
2853 }
2854 else
2855 {
2856 y = y1;
2857 }
2858
2859 return y;
2860 }
2861
2862 //#define ZM_ENABLE_TPC_WINDOWS_DEBUG
2863 //#define ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
2864
2865 /* the tx power offset workaround for ART vs NDIS/MDK */
2866 #define HALTX_POWER_OFFSET 0
2867
2868 u8_t zfInterpolateFuncX(u8_t x, u8_t x1, u8_t y1, u8_t x2, u8_t y2)
2869 {
2870 s32_t y;
2871 s32_t inc;
2872
2873 #define ZM_MULTIPLIER 8
2874 y = zfInterpolateFunc((s32_t)x<<ZM_MULTIPLIER,
2875 (s32_t)x1<<ZM_MULTIPLIER,
2876 (s32_t)y1<<ZM_MULTIPLIER,
2877 (s32_t)x2<<ZM_MULTIPLIER,
2878 (s32_t)y2<<ZM_MULTIPLIER);
2879
2880 inc = (y & (1<<(ZM_MULTIPLIER-1))) >> (ZM_MULTIPLIER-1);
2881 y = (y >> ZM_MULTIPLIER) + inc;
2882 #undef ZM_MULTIPLIER
2883
2884 return (u8_t)y;
2885 }
2886
2887 u8_t zfGetInterpolatedValue(u8_t x, u8_t* x_array, u8_t* y_array)
2888 {
2889 s32_t y;
2890 u16_t xIndex;
2891
2892 if (x <= x_array[1])
2893 {
2894 xIndex = 0;
2895 }
2896 else if (x <= x_array[2])
2897 {
2898 xIndex = 1;
2899 }
2900 else if (x <= x_array[3])
2901 {
2902 xIndex = 2;
2903 }
2904 else //(x > x_array[3])
2905 {
2906 xIndex = 3;
2907 }
2908
2909 y = zfInterpolateFuncX(x,
2910 x_array[xIndex],
2911 y_array[xIndex],
2912 x_array[xIndex+1],
2913 y_array[xIndex+1]);
2914
2915 return (u8_t)y;
2916 }
2917
2918 u8_t zfFindFreqIndex(u8_t f, u8_t* fArray, u8_t fArraySize)
2919 {
2920 u8_t i;
2921 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2922 DbgPrint("f=%d ", f);
2923 for (i=0; i<fArraySize; i++)
2924 {
2925 DbgPrint("%d ", fArray[i]);
2926 }
2927 DbgPrint("\n");
2928 #endif
2929 i=fArraySize-2;
2930 while(1)
2931 {
2932 if (f >= fArray[i])
2933 {
2934 return i;
2935 }
2936 if (i!=0)
2937 {
2938 i--;
2939 }
2940 else
2941 {
2942 return 0;
2943 }
2944 }
2945 }
2946
2947
2948
2949
2950 void zfInitPowerCal(zdev_t* dev)
2951 {
2952 //Program PHY Tx power relatives registers
2953 #define zm_write_phy_reg(cr, val) reg_write((cr*4)+0x9800, val)
2954
2955 zm_write_phy_reg(79, 0x7f);
2956 zm_write_phy_reg(77, 0x3f3f3f3f);
2957 zm_write_phy_reg(78, 0x3f3f3f3f);
2958 zm_write_phy_reg(653, 0x3f3f3f3f);
2959 zm_write_phy_reg(654, 0x3f3f3f3f);
2960 zm_write_phy_reg(739, 0x3f3f3f3f);
2961 zm_write_phy_reg(740, 0x3f3f3f3f);
2962 zm_write_phy_reg(755, 0x3f3f3f3f);
2963 zm_write_phy_reg(756, 0x3f3f3f3f);
2964 zm_write_phy_reg(757, 0x3f3f3f3f);
2965
2966 #undef zm_write_phy_reg
2967 }
2968
2969
2970
2971 void zfPrintTp(u8_t* pwr0, u8_t* vpd0, u8_t* pwr1, u8_t* vpd1)
2972 {
2973 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2974 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
2975 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
2976 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
2977 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
2978 #endif
2979 }
2980
2981
2982 /*
2983 * To find CTL index(0~23)
2984 * return 24(AR5416_NUM_CTLS)=>no desired index found
2985 */
2986 u8_t zfFindCtlEdgesIndex(zdev_t* dev, u8_t desired_CtlIndex)
2987 {
2988 u8_t i;
2989 struct zsHpPriv* hpPriv;
2990 struct ar5416Eeprom* eepromImage;
2991
2992 zmw_get_wlan_dev(dev);
2993
2994 hpPriv = wd->hpPrivate;
2995
2996 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
2997
2998 //for (i = 0; (i < AR5416_NUM_CTLS) && eepromImage->ctlIndex[i]; i++)
2999 for (i = 0; i < AR5416_NUM_CTLS; i++)
3000 {
3001 if(desired_CtlIndex == eepromImage->ctlIndex[i])
3002 break;
3003 }
3004 return i;
3005 }
3006
3007 /**************************************************************************
3008 * fbin2freq
3009 *
3010 * Get channel value from binary representation held in eeprom
3011 * RETURNS: the frequency in MHz
3012 */
3013 u32_t
3014 fbin2freq(u8_t fbin, u8_t is2GHz)
3015 {
3016 /*
3017 * Reserved value 0xFF provides an empty definition both as
3018 * an fbin and as a frequency - do not convert
3019 */
3020 if (fbin == AR5416_BCHAN_UNUSED) {
3021 return fbin;
3022 }
3023
3024 return (u32_t)((is2GHz==1) ? (2300 + fbin) : (4800 + 5 * fbin));
3025 }
3026
3027
3028 u8_t zfGetMaxEdgePower(zdev_t* dev, CAL_CTL_EDGES *pCtlEdges, u32_t freq)
3029 {
3030 u8_t i;
3031 u8_t maxEdgePower;
3032 u8_t is2GHz;
3033 struct zsHpPriv* hpPriv;
3034 struct ar5416Eeprom* eepromImage;
3035
3036 zmw_get_wlan_dev(dev);
3037
3038 hpPriv = wd->hpPrivate;
3039
3040 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3041
3042 if(freq > ZM_CH_G_14)
3043 is2GHz = 0;
3044 else
3045 is2GHz = 1;
3046
3047 maxEdgePower = AR5416_MAX_RATE_POWER;
3048
3049 /* Get the edge power */
3050 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3051 {
3052 /*
3053 * If there's an exact channel match or an inband flag set
3054 * on the lower channel use the given rdEdgePower
3055 */
3056 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3057 {
3058 maxEdgePower = pCtlEdges[i].tPower;
3059 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3060 zm_dbg(("zfGetMaxEdgePower index i = %d \n", i));
3061 #endif
3062 break;
3063 }
3064 else if ((i > 0) && (freq < fbin2freq(pCtlEdges[i].bChannel, is2GHz)))
3065 {
3066 if (fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) < freq && pCtlEdges[i - 1].flag)
3067 {
3068 maxEdgePower = pCtlEdges[i - 1].tPower;
3069 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3070 zm_dbg(("zfGetMaxEdgePower index i-1 = %d \n", i-1));
3071 #endif
3072 }
3073 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
3074 break;
3075 }
3076
3077 }
3078
3079 if( i == AR5416_NUM_BAND_EDGES )
3080 {
3081 if (freq > fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) && pCtlEdges[i - 1].flag)
3082 {
3083 maxEdgePower = pCtlEdges[i - 1].tPower;
3084 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3085 zm_dbg(("zfGetMaxEdgePower index=>i-1 = %d \n", i-1));
3086 #endif
3087 }
3088 }
3089
3090 zm_assert(maxEdgePower > 0);
3091
3092 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3093 if ( maxEdgePower == AR5416_MAX_RATE_POWER )
3094 {
3095 zm_dbg(("zfGetMaxEdgePower = %d !!!\n", AR5416_MAX_RATE_POWER));
3096 }
3097 #endif
3098 return maxEdgePower;
3099 }
3100
3101 u32_t zfAdjustHT40FreqOffset(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3102 {
3103 u32_t newFreq = frequency;
3104
3105 if (bw40 == 1)
3106 {
3107 if (extOffset == 1)
3108 {
3109 newFreq += 10;
3110 }
3111 else
3112 {
3113 newFreq -= 10;
3114 }
3115 }
3116 return newFreq;
3117 }
3118
3119 u32_t zfHpCheckDoHeavyClip(zdev_t* dev, u32_t freq, CAL_CTL_EDGES *pCtlEdges, u8_t bw40)
3120 {
3121 u32_t ret = 0;
3122 u8_t i;
3123 u8_t is2GHz;
3124 struct zsHpPriv* hpPriv;
3125
3126 zmw_get_wlan_dev(dev);
3127
3128 hpPriv = wd->hpPrivate;
3129
3130 if(freq > ZM_CH_G_14)
3131 is2GHz = 0;
3132 else
3133 is2GHz = 1;
3134
3135 /* HT40 force enable heavy clip */
3136 if (bw40)
3137 {
3138 ret |= 0xf0;
3139 }
3140 #if 1
3141 /* HT20 : frequency bandedge */
3142 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3143 {
3144 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3145 {
3146 if (pCtlEdges[i].flag == 0)
3147 {
3148 ret |= 0xf;
3149 }
3150 break;
3151 }
3152 }
3153 #endif
3154
3155 return ret;
3156 }
3157
3158
3159 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3160 {
3161 struct ar5416Eeprom* eepromImage;
3162 u8_t pwr0[5];
3163 u8_t pwr1[5];
3164 u8_t vpd0[5];
3165 u8_t vpd1[5];
3166 u8_t vpd_chain1[128];
3167 u8_t vpd_chain3[128];
3168 u16_t boundary1 = 18; //CR 667
3169 u16_t powerTxMax = 63; //CR 79
3170 u8_t i;
3171 struct zsHpPriv* hpPriv;
3172 u8_t fbin;
3173 u8_t index, max2gIndex, max5gIndex;
3174 u8_t chain0pwrPdg0[5];
3175 u8_t chain0vpdPdg0[5];
3176 u8_t chain0pwrPdg1[5];
3177 u8_t chain0vpdPdg1[5];
3178 u8_t chain2pwrPdg0[5];
3179 u8_t chain2vpdPdg0[5];
3180 u8_t chain2pwrPdg1[5];
3181 u8_t chain2vpdPdg1[5];
3182 u8_t fbinArray[8];
3183
3184 /* 4 CTL */
3185 u8_t ctl_i;
3186 u8_t desired_CtlIndex;
3187
3188 u8_t ctlEdgesMaxPowerCCK = AR5416_MAX_RATE_POWER;
3189 u8_t ctlEdgesMaxPower2G = AR5416_MAX_RATE_POWER;
3190 u8_t ctlEdgesMaxPower2GHT20 = AR5416_MAX_RATE_POWER;
3191 u8_t ctlEdgesMaxPower2GHT40 = AR5416_MAX_RATE_POWER;
3192 u8_t ctlEdgesMaxPower5G = AR5416_MAX_RATE_POWER;
3193 u8_t ctlEdgesMaxPower5GHT20 = AR5416_MAX_RATE_POWER;
3194 u8_t ctlEdgesMaxPower5GHT40 = AR5416_MAX_RATE_POWER;
3195
3196 u8_t ctlOffset;
3197
3198 zmw_get_wlan_dev(dev);
3199
3200 hpPriv = wd->hpPrivate;
3201
3202 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3203
3204 // Check the total bytes of the EEPROM structure to see the dongle have been calibrated or not.
3205 if (eepromImage->baseEepHeader.length == 0xffff)
3206 {
3207 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3208 zm_dbg(("Warning! This dongle not been calibrated\n"));
3209 #endif
3210 return;
3211 }
3212
3213 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3214 DbgPrint("-----zfSetPowerCalTable : frequency=%d-----\n", frequency);
3215 #endif
3216 /* TODO : 1. boundary1 and powerTxMax should be refered to CR667 and CR79 */
3217 /* in otus.ini file */
3218
3219 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3220 /* 2. Interpolate pwr and vpd test points from frequency */
3221 DbgPrint("calFreqPier5G : %d, %d, %d, %d ,%d, %d, %d, %d\n",
3222 eepromImage->calFreqPier5G[0]*5+4800,
3223 eepromImage->calFreqPier5G[1]*5+4800,
3224 eepromImage->calFreqPier5G[2]*5+4800,
3225 eepromImage->calFreqPier5G[3]*5+4800,
3226 eepromImage->calFreqPier5G[4]*5+4800,
3227 eepromImage->calFreqPier5G[5]*5+4800,
3228 eepromImage->calFreqPier5G[6]*5+4800,
3229 eepromImage->calFreqPier5G[7]*5+4800
3230 );
3231 DbgPrint("calFreqPier2G : %d, %d, %d, %d\n",
3232 eepromImage->calFreqPier2G[0]+2300,
3233 eepromImage->calFreqPier2G[1]+2300,
3234 eepromImage->calFreqPier2G[2]+2300,
3235 eepromImage->calFreqPier2G[3]+2300
3236 );
3237 #endif
3238 if (frequency < 3000)
3239 {
3240 for (i=0; i<4; i++)
3241 {
3242 if (eepromImage->calFreqPier2G[i] == 0xff)
3243 {
3244 break;
3245 }
3246 }
3247 max2gIndex = i;
3248 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3249 DbgPrint("max2gIndex : %d\n", max2gIndex);
3250 #endif
3251 fbin = (u8_t)(frequency - 2300);
3252 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier2G, max2gIndex);
3253 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3254 DbgPrint("2G index : %d\n", index);
3255 DbgPrint("chain 0 index\n");
3256 #endif
3257 zfPrintTp(&eepromImage->calPierData2G[0][index].pwrPdg[0][0],
3258 &eepromImage->calPierData2G[0][index].vpdPdg[0][0],
3259 &eepromImage->calPierData2G[0][index].pwrPdg[1][0],
3260 &eepromImage->calPierData2G[0][index].vpdPdg[1][0]
3261 );
3262 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3263 DbgPrint("chain 0 index+1\n");
3264 #endif
3265 zfPrintTp(&eepromImage->calPierData2G[0][index+1].pwrPdg[0][0],
3266 &eepromImage->calPierData2G[0][index+1].vpdPdg[0][0],
3267 &eepromImage->calPierData2G[0][index+1].pwrPdg[1][0],
3268 &eepromImage->calPierData2G[0][index+1].vpdPdg[1][0]
3269 );
3270
3271 for (i=0; i<5; i++)
3272 {
3273 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3274 eepromImage->calFreqPier2G[index],
3275 eepromImage->calPierData2G[0][index].pwrPdg[0][i],
3276 eepromImage->calFreqPier2G[index+1],
3277 eepromImage->calPierData2G[0][index+1].pwrPdg[0][i]
3278 );
3279 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3280 eepromImage->calFreqPier2G[index],
3281 eepromImage->calPierData2G[0][index].vpdPdg[0][i],
3282 eepromImage->calFreqPier2G[index+1],
3283 eepromImage->calPierData2G[0][index+1].vpdPdg[0][i]
3284 );
3285 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3286 eepromImage->calFreqPier2G[index],
3287 eepromImage->calPierData2G[0][index].pwrPdg[1][i],
3288 eepromImage->calFreqPier2G[index+1],
3289 eepromImage->calPierData2G[0][index+1].pwrPdg[1][i]
3290 );
3291 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3292 eepromImage->calFreqPier2G[index],
3293 eepromImage->calPierData2G[0][index].vpdPdg[1][i],
3294 eepromImage->calFreqPier2G[index+1],
3295 eepromImage->calPierData2G[0][index+1].vpdPdg[1][i]
3296 );
3297
3298 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3299 eepromImage->calFreqPier2G[index],
3300 eepromImage->calPierData2G[1][index].pwrPdg[0][i],
3301 eepromImage->calFreqPier2G[index+1],
3302 eepromImage->calPierData2G[1][index+1].pwrPdg[0][i]
3303 );
3304 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3305 eepromImage->calFreqPier2G[index],
3306 eepromImage->calPierData2G[1][index].vpdPdg[0][i],
3307 eepromImage->calFreqPier2G[index+1],
3308 eepromImage->calPierData2G[1][index+1].vpdPdg[0][i]
3309 );
3310 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3311 eepromImage->calFreqPier2G[index],
3312 eepromImage->calPierData2G[1][index].pwrPdg[1][i],
3313 eepromImage->calFreqPier2G[index+1],
3314 eepromImage->calPierData2G[1][index+1].pwrPdg[1][i]
3315 );
3316 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3317 eepromImage->calFreqPier2G[index],
3318 eepromImage->calPierData2G[1][index].vpdPdg[1][i],
3319 eepromImage->calFreqPier2G[index+1],
3320 eepromImage->calPierData2G[1][index+1].vpdPdg[1][i]
3321 );
3322 }
3323 }
3324 else
3325 {
3326 for (i=0; i<8; i++)
3327 {
3328 if (eepromImage->calFreqPier5G[i] == 0xff)
3329 {
3330 break;
3331 }
3332 }
3333 max5gIndex = i;
3334 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3335 DbgPrint("max5gIndex : %d\n", max5gIndex);
3336 #endif
3337 fbin = (u8_t)((frequency - 4800)/5);
3338 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier5G, max5gIndex);
3339 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3340 DbgPrint("5G index : %d\n", index);
3341 #endif
3342
3343 for (i=0; i<5; i++)
3344 {
3345 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3346 eepromImage->calFreqPier5G[index],
3347 eepromImage->calPierData5G[0][index].pwrPdg[0][i],
3348 eepromImage->calFreqPier5G[index+1],
3349 eepromImage->calPierData5G[0][index+1].pwrPdg[0][i]
3350 );
3351 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3352 eepromImage->calFreqPier5G[index],
3353 eepromImage->calPierData5G[0][index].vpdPdg[0][i],
3354 eepromImage->calFreqPier5G[index+1],
3355 eepromImage->calPierData5G[0][index+1].vpdPdg[0][i]
3356 );
3357 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3358 eepromImage->calFreqPier5G[index],
3359 eepromImage->calPierData5G[0][index].pwrPdg[1][i],
3360 eepromImage->calFreqPier5G[index+1],
3361 eepromImage->calPierData5G[0][index+1].pwrPdg[1][i]
3362 );
3363 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3364 eepromImage->calFreqPier5G[index],
3365 eepromImage->calPierData5G[0][index].vpdPdg[1][i],
3366 eepromImage->calFreqPier5G[index+1],
3367 eepromImage->calPierData5G[0][index+1].vpdPdg[1][i]
3368 );
3369
3370 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3371 eepromImage->calFreqPier5G[index],
3372 eepromImage->calPierData5G[1][index].pwrPdg[0][i],
3373 eepromImage->calFreqPier5G[index+1],
3374 eepromImage->calPierData5G[1][index+1].pwrPdg[0][i]
3375 );
3376 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3377 eepromImage->calFreqPier5G[index],
3378 eepromImage->calPierData5G[1][index].vpdPdg[0][i],
3379 eepromImage->calFreqPier5G[index+1],
3380 eepromImage->calPierData5G[1][index+1].vpdPdg[0][i]
3381 );
3382 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3383 eepromImage->calFreqPier5G[index],
3384 eepromImage->calPierData5G[1][index].pwrPdg[1][i],
3385 eepromImage->calFreqPier5G[index+1],
3386 eepromImage->calPierData5G[1][index+1].pwrPdg[1][i]
3387 );
3388 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3389 eepromImage->calFreqPier5G[index],
3390 eepromImage->calPierData5G[1][index].vpdPdg[1][i],
3391 eepromImage->calFreqPier5G[index+1],
3392 eepromImage->calPierData5G[1][index+1].vpdPdg[1][i]
3393 );
3394 }
3395
3396 }
3397
3398
3399 /* Chain 1 */
3400 /* Get pwr and vpd test points from frequency */
3401 for (i=0; i<5; i++)
3402 {
3403 pwr0[i] = chain0pwrPdg0[i]>>1;
3404 vpd0[i] = chain0vpdPdg0[i];
3405 pwr1[i] = chain0pwrPdg1[i]>>1;
3406 vpd1[i] = chain0vpdPdg1[i];
3407 }
3408 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3409 DbgPrint("Test Points\n");
3410 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3411 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3412 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3413 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3414 #endif
3415 /* Generate the vpd arrays */
3416 for (i=0; i<boundary1+1+6; i++)
3417 {
3418 vpd_chain1[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3419 }
3420 for (; i<powerTxMax+1+6+6; i++)
3421 {
3422 vpd_chain1[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3423 }
3424 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3425 DbgPrint("vpd_chain1\n");
3426 for (i=0; i<powerTxMax+1+6+6; i+=10)
3427 {
3428 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3429 vpd_chain1[i+0], vpd_chain1[i+1], vpd_chain1[i+2], vpd_chain1[i+3], vpd_chain1[i+4],
3430 vpd_chain1[i+5], vpd_chain1[i+6], vpd_chain1[i+7], vpd_chain1[i+8], vpd_chain1[i+9]);
3431 }
3432 #endif
3433 /* Write PHY regs 672-703 */
3434 for (i=0; i<128; i+=4)
3435 {
3436 u32_t val;
3437
3438 val = ((u32_t)vpd_chain1[i+3]<<24) |
3439 ((u32_t)vpd_chain1[i+2]<<16) |
3440 ((u32_t)vpd_chain1[i+1]<<8) |
3441 ((u32_t)vpd_chain1[i]);
3442
3443 #ifndef ZM_OTUS_LINUX_PHASE_2
3444 reg_write(regAddr + i, val); /* CR672 */
3445 #endif
3446 }
3447
3448 /* Chain 2 */
3449 /* Get pwr and vpd test points from frequency */
3450 for (i=0; i<5; i++)
3451 {
3452 pwr0[i] = chain2pwrPdg0[i]>>1;
3453 vpd0[i] = chain2vpdPdg0[i];
3454 pwr1[i] = chain2pwrPdg1[i]>>1;
3455 vpd1[i] = chain2vpdPdg1[i];
3456 }
3457 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3458 DbgPrint("Test Points\n");
3459 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3460 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3461 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3462 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3463 #endif
3464 /* Generate the vpd arrays */
3465 for (i=0; i<boundary1+1+6; i++)
3466 {
3467 vpd_chain3[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3468 }
3469 for (; i<powerTxMax+1+6+6; i++)
3470 {
3471 vpd_chain3[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3472 }
3473 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3474 DbgPrint("vpd_chain3\n");
3475 for (i=0; i<powerTxMax+1+6+6; i+=10)
3476 {
3477 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3478 vpd_chain3[i+0], vpd_chain3[i+1], vpd_chain3[i+2], vpd_chain3[i+3], vpd_chain3[i+4],
3479 vpd_chain3[i+5], vpd_chain3[i+6], vpd_chain3[i+7], vpd_chain3[i+8], vpd_chain3[i+9]);
3480 }
3481 #endif
3482
3483 /* Write PHY regs 672-703 + 0x1000 */
3484 for (i=0; i<128; i+=4)
3485 {
3486 u32_t val;
3487
3488 val = ((u32_t)vpd_chain3[i+3]<<24) |
3489 ((u32_t)vpd_chain3[i+2]<<16) |
3490 ((u32_t)vpd_chain3[i+1]<<8) |
3491 ((u32_t)vpd_chain3[i]);
3492
3493 #ifndef ZM_OTUS_LINUX_PHASE_2
3494 reg_write(regAddr + i, val); /* CR672 */
3495 #endif
3496 }
3497
3498 zfFlushDelayWrite(dev);
3499
3500 /* 3. Generate target power table */
3501 if (frequency < 3000)
3502 {
3503 for (i=0; i<3; i++)
3504 {
3505 if (eepromImage->calTargetPowerCck[i].bChannel != 0xff)
3506 {
3507 fbinArray[i] = eepromImage->calTargetPowerCck[i].bChannel;
3508 }
3509 else
3510 {
3511 break;
3512 }
3513
3514 }
3515 index = zfFindFreqIndex(fbin, fbinArray, i);
3516 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3517 DbgPrint("CCK index=%d\n", index);
3518 #endif
3519 for (i=0; i<4; i++)
3520 {
3521 hpPriv->tPow2xCck[i] = zfInterpolateFuncX(fbin,
3522 eepromImage->calTargetPowerCck[index].bChannel,
3523 eepromImage->calTargetPowerCck[index].tPow2x[i],
3524 eepromImage->calTargetPowerCck[index+1].bChannel,
3525 eepromImage->calTargetPowerCck[index+1].tPow2x[i]
3526 );
3527 }
3528
3529 for (i=0; i<4; i++)
3530 {
3531 if (eepromImage->calTargetPower2G[i].bChannel != 0xff)
3532 {
3533 fbinArray[i] = eepromImage->calTargetPower2G[i].bChannel;
3534 }
3535 else
3536 {
3537 break;
3538 }
3539
3540 }
3541 index = zfFindFreqIndex(fbin, fbinArray, i);
3542 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3543 DbgPrint("2G index=%d\n", index);
3544 #endif
3545 for (i=0; i<4; i++)
3546 {
3547 hpPriv->tPow2x2g[i] = zfInterpolateFuncX(fbin,
3548 eepromImage->calTargetPower2G[index].bChannel,
3549 eepromImage->calTargetPower2G[index].tPow2x[i],
3550 eepromImage->calTargetPower2G[index+1].bChannel,
3551 eepromImage->calTargetPower2G[index+1].tPow2x[i]
3552 );
3553 }
3554
3555 for (i=0; i<4; i++)
3556 {
3557 if (eepromImage->calTargetPower2GHT20[i].bChannel != 0xff)
3558 {
3559 fbinArray[i] = eepromImage->calTargetPower2GHT20[i].bChannel;
3560 }
3561 else
3562 {
3563 break;
3564 }
3565
3566 }
3567 index = zfFindFreqIndex(fbin, fbinArray, i);
3568 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3569 DbgPrint("2G HT20 index=%d\n", index);
3570 #endif
3571 for (i=0; i<8; i++)
3572 {
3573 hpPriv->tPow2x2gHt20[i] = zfInterpolateFuncX(fbin,
3574 eepromImage->calTargetPower2GHT20[index].bChannel,
3575 eepromImage->calTargetPower2GHT20[index].tPow2x[i],
3576 eepromImage->calTargetPower2GHT20[index+1].bChannel,
3577 eepromImage->calTargetPower2GHT20[index+1].tPow2x[i]
3578 );
3579 }
3580
3581 for (i=0; i<4; i++)
3582 {
3583 if (eepromImage->calTargetPower2GHT40[i].bChannel != 0xff)
3584 {
3585 fbinArray[i] = eepromImage->calTargetPower2GHT40[i].bChannel;
3586 }
3587 else
3588 {
3589 break;
3590 }
3591
3592 }
3593 index = zfFindFreqIndex( (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3594 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3595 DbgPrint("2G HT40 index=%d\n", index);
3596 #endif
3597 for (i=0; i<8; i++)
3598 {
3599 hpPriv->tPow2x2gHt40[i] = zfInterpolateFuncX(
3600 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3601 eepromImage->calTargetPower2GHT40[index].bChannel,
3602 eepromImage->calTargetPower2GHT40[index].tPow2x[i],
3603 eepromImage->calTargetPower2GHT40[index+1].bChannel,
3604 eepromImage->calTargetPower2GHT40[index+1].tPow2x[i]
3605 );
3606 }
3607
3608 zfPrintTargetPower2G(hpPriv->tPow2xCck,
3609 hpPriv->tPow2x2g,
3610 hpPriv->tPow2x2gHt20,
3611 hpPriv->tPow2x2gHt40);
3612 }
3613 else
3614 {
3615 /* 5G */
3616 for (i=0; i<8; i++)
3617 {
3618 if (eepromImage->calTargetPower5G[i].bChannel != 0xff)
3619 {
3620 fbinArray[i] = eepromImage->calTargetPower5G[i].bChannel;
3621 }
3622 else
3623 {
3624 break;
3625 }
3626
3627 }
3628 index = zfFindFreqIndex(fbin, fbinArray, i);
3629 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3630 DbgPrint("5G index=%d\n", index);
3631 #endif
3632 for (i=0; i<4; i++)
3633 {
3634 hpPriv->tPow2x5g[i] = zfInterpolateFuncX(fbin,
3635 eepromImage->calTargetPower5G[index].bChannel,
3636 eepromImage->calTargetPower5G[index].tPow2x[i],
3637 eepromImage->calTargetPower5G[index+1].bChannel,
3638 eepromImage->calTargetPower5G[index+1].tPow2x[i]
3639 );
3640 }
3641
3642 for (i=0; i<8; i++)
3643 {
3644 if (eepromImage->calTargetPower5GHT20[i].bChannel != 0xff)
3645 {
3646 fbinArray[i] = eepromImage->calTargetPower5GHT20[i].bChannel;
3647 }
3648 else
3649 {
3650 break;
3651 }
3652
3653 }
3654 index = zfFindFreqIndex(fbin, fbinArray, i);
3655 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3656 DbgPrint("5G HT20 index=%d\n", index);
3657 #endif
3658 for (i=0; i<8; i++)
3659 {
3660 hpPriv->tPow2x5gHt20[i] = zfInterpolateFuncX(fbin,
3661 eepromImage->calTargetPower5GHT20[index].bChannel,
3662 eepromImage->calTargetPower5GHT20[index].tPow2x[i],
3663 eepromImage->calTargetPower5GHT20[index+1].bChannel,
3664 eepromImage->calTargetPower5GHT20[index+1].tPow2x[i]
3665 );
3666 }
3667
3668 for (i=0; i<8; i++)
3669 {
3670 if (eepromImage->calTargetPower5GHT40[i].bChannel != 0xff)
3671 {
3672 fbinArray[i] = eepromImage->calTargetPower5GHT40[i].bChannel;
3673 }
3674 else
3675 {
3676 break;
3677 }
3678
3679 }
3680 index = zfFindFreqIndex((u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3681 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3682 DbgPrint("5G HT40 index=%d\n", index);
3683 #endif
3684 for (i=0; i<8; i++)
3685 {
3686 hpPriv->tPow2x5gHt40[i] = zfInterpolateFuncX(
3687 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3688 eepromImage->calTargetPower5GHT40[index].bChannel,
3689 eepromImage->calTargetPower5GHT40[index].tPow2x[i],
3690 eepromImage->calTargetPower5GHT40[index+1].bChannel,
3691 eepromImage->calTargetPower5GHT40[index+1].tPow2x[i]
3692 );
3693 }
3694
3695 zfPrintTargetPower5G(
3696 hpPriv->tPow2x5g,
3697 hpPriv->tPow2x5gHt20,
3698 hpPriv->tPow2x5gHt40);
3699 }
3700
3701
3702
3703 /* 4. CTL */
3704 /*
3705 * 4.1 Get the bandedges tx power by frequency
3706 * 2.4G we get ctlEdgesMaxPowerCCK
3707 * ctlEdgesMaxPower2G
3708 * ctlEdgesMaxPower2GHT20
3709 * ctlEdgesMaxPower2GHT40
3710 * 5G we get ctlEdgesMaxPower5G
3711 * ctlEdgesMaxPower5GHT20
3712 * ctlEdgesMaxPower5GHT40
3713 * 4.2 Update (3.) target power table by 4.1
3714 * 4.3 Tx power offset for ART - NDIS/MDK
3715 * 4.4 Write MAC reg 0x694 for ACK's TPC
3716 *
3717 */
3718
3719 //zfDumpEepBandEdges(eepromImage);
3720
3721 /* get the cfg from Eeprom: regionCode => RegulatoryDomain : 0x10-FFC 0x30-eu 0x40-jap */
3722 desired_CtlIndex = zfHpGetRegulatoryDomain(dev);
3723 if ((desired_CtlIndex == 0x30) || (desired_CtlIndex == 0x40) || (desired_CtlIndex == 0x0))
3724 {
3725 /* skip CTL and heavy clip */
3726 hpPriv->enableBBHeavyClip = 0;
3727 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3728 zm_dbg(("RegulatoryDomain = 0, skip CTL and heavy clip\n"));
3729 #endif
3730 }
3731 else
3732 {
3733 hpPriv->enableBBHeavyClip = 1;
3734
3735 if (desired_CtlIndex == 0xff)
3736 {
3737 /* desired index not found */
3738 desired_CtlIndex = 0x10;
3739 }
3740
3741 /* first part : 2.4G */
3742 if (frequency <= ZM_CH_G_14)
3743 {
3744 /* 2.4G - CTL_11B */
3745 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11B);
3746 if(ctl_i<AR5416_NUM_CTLS)
3747 {
3748 ctlEdgesMaxPowerCCK = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3749 }
3750 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3751 zm_dbg(("CTL_11B ctl_i = %d\n", ctl_i));
3752 #endif
3753
3754 /* 2.4G - CTL_11G */
3755 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3756 if(ctl_i<AR5416_NUM_CTLS)
3757 {
3758 ctlEdgesMaxPower2G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3759 }
3760 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3761 zm_dbg(("CTL_11G ctl_i = %d\n", ctl_i));
3762 #endif
3763
3764 /* 2.4G - CTL_2GHT20 */
3765 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT20);
3766 if(ctl_i<AR5416_NUM_CTLS)
3767 {
3768 ctlEdgesMaxPower2GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3769 }
3770 else
3771 {
3772 /* workaround for no data in Eeprom, replace by normal 2G */
3773 ctlEdgesMaxPower2GHT20 = ctlEdgesMaxPower2G;
3774 }
3775 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3776 zm_dbg(("CTL_2GHT20 ctl_i = %d\n", ctl_i));
3777 #endif
3778
3779 /* 2.4G - CTL_2GHT40 */
3780 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT40);
3781 if(ctl_i<AR5416_NUM_CTLS)
3782 {
3783 ctlEdgesMaxPower2GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3784 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3785 }
3786 else
3787 {
3788 /* workaround for no data in Eeprom, replace by normal 2G */
3789 ctlEdgesMaxPower2GHT40 = ctlEdgesMaxPower2G;
3790 }
3791 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3792 zm_dbg(("CTL_2GHT40 ctl_i = %d\n", ctl_i));
3793 #endif
3794
3795
3796 /* 7a17 : */
3797 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3798 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3799 {
3800 if (wd->regulationTable.allowChannel[i].channel == frequency)
3801 {
3802 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3803 {
3804 zm_debug_msg1("frequency use DFS -- ", frequency);
3805 ctlEdgesMaxPowerCCK = zm_min(ctlEdgesMaxPowerCCK, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3806 ctlEdgesMaxPower2G = zm_min(ctlEdgesMaxPower2G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3807 ctlEdgesMaxPower2GHT20 = zm_min(ctlEdgesMaxPower2GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3808 ctlEdgesMaxPower2GHT40 = zm_min(ctlEdgesMaxPower2GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3809 }
3810 break;
3811 }
3812 }
3813
3814 /* Apply ctl mode to correct target power set */
3815 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3816 zm_debug_msg1("ctlEdgesMaxPowerCCK = ", ctlEdgesMaxPowerCCK);
3817 zm_debug_msg1("ctlEdgesMaxPower2G = ", ctlEdgesMaxPower2G);
3818 zm_debug_msg1("ctlEdgesMaxPower2GHT20 = ", ctlEdgesMaxPower2GHT20);
3819 zm_debug_msg1("ctlEdgesMaxPower2GHT40 = ", ctlEdgesMaxPower2GHT40);
3820 #endif
3821 for (i=0; i<4; i++)
3822 {
3823 hpPriv->tPow2xCck[i] = zm_min(hpPriv->tPow2xCck[i], ctlEdgesMaxPowerCCK) + HALTX_POWER_OFFSET;
3824 }
3825 hpPriv->tPow2x2g24HeavyClipOffset = 0;
3826 if (hpPriv->enableBBHeavyClip)
3827 {
3828 ctlOffset = 2;
3829 }
3830 else
3831 {
3832 ctlOffset = 0;
3833 }
3834 for (i=0; i<4; i++)
3835 {
3836 if (((frequency == 2412) || (frequency == 2462)))
3837 {
3838 if (i != 0)
3839 {
3840 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G-ctlOffset) + HALTX_POWER_OFFSET;
3841 }
3842 else
3843 {
3844 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3845 if (hpPriv->tPow2x2g[i] > (ctlEdgesMaxPower2G-ctlOffset))
3846 {
3847 hpPriv->tPow2x2g24HeavyClipOffset = hpPriv->tPow2x2g[i] - (ctlEdgesMaxPower2G-ctlOffset);
3848 }
3849 }
3850 }
3851 else
3852 {
3853 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3854 }
3855 }
3856 for (i=0; i<8; i++)
3857 {
3858 if (((frequency == 2412) || (frequency == 2462)) && (i>=3))
3859 {
3860 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20-ctlOffset) + HALTX_POWER_OFFSET;
3861 }
3862 else
3863 {
3864 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20) + HALTX_POWER_OFFSET;
3865 }
3866 }
3867 for (i=0; i<8; i++)
3868 {
3869 if ((frequency == 2412) && (i>=3))
3870 {
3871 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-ctlOffset) + HALTX_POWER_OFFSET;
3872 }
3873 else if ((frequency == 2462) && (i>=3))
3874 {
3875 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-(ctlOffset*2)) + HALTX_POWER_OFFSET;
3876 }
3877 else
3878 {
3879 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40) + HALTX_POWER_OFFSET;
3880 }
3881 }
3882 }
3883 else
3884 {
3885 /* 5G - CTL_11A */
3886 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3887 if(ctl_i<AR5416_NUM_CTLS)
3888 {
3889 ctlEdgesMaxPower5G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3890 }
3891 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3892 zm_dbg(("CTL_11A ctl_i = %d\n", ctl_i));
3893 #endif
3894
3895 /* 5G - CTL_5GHT20 */
3896 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT20);
3897 if(ctl_i<AR5416_NUM_CTLS)
3898 {
3899 ctlEdgesMaxPower5GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3900 }
3901 else
3902 {
3903 /* workaround for no data in Eeprom, replace by normal 5G */
3904 ctlEdgesMaxPower5GHT20 = ctlEdgesMaxPower5G;
3905 }
3906 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3907 zm_dbg(("CTL_5GHT20 ctl_i = %d\n", ctl_i));
3908 #endif
3909
3910 /* 5G - CTL_5GHT40 */
3911 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT40);
3912 if(ctl_i<AR5416_NUM_CTLS)
3913 {
3914 ctlEdgesMaxPower5GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3915 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3916 }
3917 else
3918 {
3919 /* workaround for no data in Eeprom, replace by normal 5G */
3920 ctlEdgesMaxPower5GHT40 = ctlEdgesMaxPower5G;
3921 }
3922 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3923 zm_dbg(("CTL_5GHT40 ctl_i = %d\n", ctl_i));
3924 #endif
3925
3926 /* 7a17 : */
3927 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3928 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3929 {
3930 if (wd->regulationTable.allowChannel[i].channel == frequency)
3931 {
3932 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3933 {
3934 zm_debug_msg1("frequency use DFS -- ", frequency);
3935 ctlEdgesMaxPower5G = zm_min(ctlEdgesMaxPower5G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3936 ctlEdgesMaxPower5GHT20 = zm_min(ctlEdgesMaxPower5GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3937 ctlEdgesMaxPower5GHT40 = zm_min(ctlEdgesMaxPower5GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3938 }
3939 break;
3940 }
3941 }
3942
3943
3944 /* Apply ctl mode to correct target power set */
3945 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3946 zm_debug_msg1("ctlEdgesMaxPower5G = ", ctlEdgesMaxPower5G);
3947 zm_debug_msg1("ctlEdgesMaxPower5GHT20 = ", ctlEdgesMaxPower5GHT20);
3948 zm_debug_msg1("ctlEdgesMaxPower5GHT40 = ", ctlEdgesMaxPower5GHT40);
3949 #endif
3950 for (i=0; i<4; i++)
3951 {
3952 hpPriv->tPow2x5g[i] = zm_min(hpPriv->tPow2x5g[i], ctlEdgesMaxPower5G) + HALTX_POWER_OFFSET;
3953 }
3954 for (i=0; i<8; i++)
3955 {
3956 hpPriv->tPow2x5gHt20[i] = zm_min(hpPriv->tPow2x5gHt20[i], ctlEdgesMaxPower5GHT20) + HALTX_POWER_OFFSET;
3957 }
3958 for (i=0; i<8; i++)
3959 {
3960 hpPriv->tPow2x5gHt40[i] = zm_min(hpPriv->tPow2x5gHt40[i], ctlEdgesMaxPower5GHT40) + HALTX_POWER_OFFSET;
3961 }
3962
3963 }/* end of bandedges of 5G */
3964 }/* end of if ((desired_CtlIndex = zfHpGetRegulatoryDomain(dev)) == 0) */
3965
3966 /* workaround */
3967 /* 5. BB heavy clip */
3968 /* only 2.4G do heavy clip */
3969 if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && (frequency <= ZM_CH_G_14))
3970 {
3971 if (frequency <= ZM_CH_G_14)
3972 {
3973 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3974 }
3975 else
3976 {
3977 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3978 }
3979
3980 hpPriv->setValueHeavyClip = zfHpCheckDoHeavyClip(dev, frequency, eepromImage->ctlData[ctl_i].ctlEdges[1], bw40);
3981
3982 if (hpPriv->setValueHeavyClip)
3983 {
3984 hpPriv->doBBHeavyClip = 1;
3985 }
3986 else
3987 {
3988 hpPriv->doBBHeavyClip = 0;
3989 }
3990 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3991 zm_dbg(("zfHpCheckDoHeavyClip ret = %02x, doBBHeavyClip = %d\n",
3992 hpPriv->setValueHeavyClip, hpPriv->doBBHeavyClip));
3993 #endif
3994
3995 if (hpPriv->doBBHeavyClip)
3996 {
3997 if (hpPriv->setValueHeavyClip & 0xf0)
3998 {
3999 hpPriv->tPow2x2gHt40[0] -= 1;
4000 hpPriv->tPow2x2gHt40[1] -= 1;
4001 hpPriv->tPow2x2gHt40[2] -= 1;
4002 }
4003
4004 if (hpPriv->setValueHeavyClip & 0xf)
4005 {
4006 hpPriv->tPow2x2gHt20[0] += 1;
4007 hpPriv->tPow2x2gHt20[1] += 1;
4008 hpPriv->tPow2x2gHt20[2] += 1;
4009 }
4010 }
4011 }
4012 else
4013 {
4014 hpPriv->doBBHeavyClip = 0;
4015 hpPriv->setValueHeavyClip = 0;
4016 }
4017
4018 /* Final : write MAC register for some ctrl frame Tx power */
4019 /* first part : 2.4G */
4020 if (frequency <= ZM_CH_G_14)
4021 {
4022 /* Write MAC reg 0x694 for ACK's TPC */
4023 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4024 /* Always use two stream for low legacy rate */
4025 #if 0
4026 //if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4027 //{
4028 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x1<<26));
4029 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x1<<11) |
4030 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x1<<27) );
4031 //}
4032 #endif
4033 #if 1
4034 //else
4035 {
4036 #ifndef ZM_OTUS_LINUX_PHASE_2
4037 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x5<<26));
4038 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x5<<11) |
4039 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x5<<27) );
4040 #endif
4041 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4042 }
4043 #endif
4044 zfFlushDelayWrite(dev);
4045
4046 zfPrintTargetPower2G(hpPriv->tPow2xCck,
4047 hpPriv->tPow2x2g,
4048 hpPriv->tPow2x2gHt20,
4049 hpPriv->tPow2x2gHt40);
4050 }
4051 else
4052 {
4053 /* Write MAC reg 0x694 for ACK's TPC */
4054 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4055 /* Always use two stream for low legacy rate */
4056 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4057 {
4058 #ifndef ZM_OTUS_LINUX_PHASE_2
4059 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x1<<26));
4060 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x1<<11) |
4061 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x1<<27) );
4062 #endif
4063 }
4064 else
4065 {
4066 #ifndef ZM_OTUS_LINUX_PHASE_2
4067 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x5<<26));
4068 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x5<<11) |
4069 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x5<<27) );
4070 #endif
4071 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4072 }
4073
4074
4075 zfFlushDelayWrite(dev);
4076
4077 zfPrintTargetPower5G(
4078 hpPriv->tPow2x5g,
4079 hpPriv->tPow2x5gHt20,
4080 hpPriv->tPow2x5gHt40);
4081 }/* end of bandedges of 5G */
4082
4083 }
4084
4085 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage)
4086 {
4087 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4088 u8_t i, j, k;
4089
4090 #if 0
4091 zm_dbg(("\n === BandEdges index dump ==== \n"));
4092
4093 for (i = 0; i < AR5416_NUM_CTLS; i++)
4094 {
4095 zm_dbg(("%02x ", eepromImage->ctlIndex[i]));
4096 }
4097
4098 zm_dbg(("\n === BandEdges data dump ==== \n"));
4099
4100 for (i = 0; i < AR5416_NUM_CTLS; i++)
4101 {
4102 for (j = 0; j < 2; j++)
4103 {
4104 for(k = 0; k < AR5416_NUM_BAND_EDGES; k++)
4105 {
4106 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j][k]);
4107 zm_dbg(("(%02x %02x)", pdata[0], pdata[1]));
4108 }
4109 zm_dbg(("\n"));
4110 }
4111 }
4112 #else
4113 zm_dbg(("\n === BandEdges index dump ==== \n"));
4114 for (i = 0; i < 24; i+=8)
4115 {
4116 zm_dbg(("%02x %02x %02x %02x %02x %02x %02x %02x",
4117 eepromImage->ctlIndex[i+0], eepromImage->ctlIndex[i+1], eepromImage->ctlIndex[i+2], eepromImage->ctlIndex[i+3],
4118 eepromImage->ctlIndex[i+4], eepromImage->ctlIndex[i+5], eepromImage->ctlIndex[i+6], eepromImage->ctlIndex[i+7]
4119 ));
4120 }
4121
4122 zm_dbg(("\n === BandEdges data dump ==== \n"));
4123
4124 for (i = 0; i < AR5416_NUM_CTLS; i++)
4125 {
4126 for (j = 0; j < 2; j++)
4127 {
4128 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j]);
4129 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4130 pdata[0], pdata[1], pdata[2], pdata[3],
4131 pdata[4], pdata[5], pdata[6], pdata[7]
4132 ));
4133 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4134 pdata[8], pdata[9], pdata[10], pdata[11],
4135 pdata[12], pdata[13], pdata[14], pdata[15]
4136 ));
4137 }
4138 }
4139 #endif
4140 #endif
4141 }
4142
4143 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40)
4144 {
4145 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4146 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4147 DbgPrint("targetPwr CCK : %d, %d, %d, %d\n",
4148 tPow2xCck[0],
4149 tPow2xCck[1],
4150 tPow2xCck[2],
4151 tPow2xCck[3]
4152 );
4153 DbgPrint("targetPwr 2G : %d, %d, %d, %d\n",
4154 tPow2x2g[0],
4155 tPow2x2g[1],
4156 tPow2x2g[2],
4157 tPow2x2g[3]
4158 );
4159 DbgPrint("targetPwr 2GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4160 tPow2x2gHt20[0],
4161 tPow2x2gHt20[1],
4162 tPow2x2gHt20[2],
4163 tPow2x2gHt20[3],
4164 tPow2x2gHt20[4],
4165 tPow2x2gHt20[5],
4166 tPow2x2gHt20[6],
4167 tPow2x2gHt20[7]
4168 );
4169 DbgPrint("targetPwr 2GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4170 tPow2x2gHt40[0],
4171 tPow2x2gHt40[1],
4172 tPow2x2gHt40[2],
4173 tPow2x2gHt40[3],
4174 tPow2x2gHt40[4],
4175 tPow2x2gHt40[5],
4176 tPow2x2gHt40[6],
4177 tPow2x2gHt40[7]
4178 );
4179 #endif
4180 return;
4181 }
4182
4183 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40)
4184 {
4185 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4186 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4187 DbgPrint("targetPwr 5G : %d, %d, %d, %d\n",
4188 tPow2x5g[0],
4189 tPow2x5g[1],
4190 tPow2x5g[2],
4191 tPow2x5g[3]
4192 );
4193 DbgPrint("targetPwr 5GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4194 tPow2x5gHt20[0],
4195 tPow2x5gHt20[1],
4196 tPow2x5gHt20[2],
4197 tPow2x5gHt20[3],
4198 tPow2x5gHt20[4],
4199 tPow2x5gHt20[5],
4200 tPow2x5gHt20[6],
4201 tPow2x5gHt20[7]
4202 );
4203 DbgPrint("targetPwr 5GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4204 tPow2x5gHt40[0],
4205 tPow2x5gHt40[1],
4206 tPow2x5gHt40[2],
4207 tPow2x5gHt40[3],
4208 tPow2x5gHt40[4],
4209 tPow2x5gHt40[5],
4210 tPow2x5gHt40[6],
4211 tPow2x5gHt40[7]
4212 );
4213 #endif
4214 return;
4215 }
4216
4217 void zfHpPowerSaveSetMode(zdev_t* dev, u8_t staMode, u8_t psMode, u16_t bcnInterval)
4218 {
4219 if ( staMode == 0 )
4220 {
4221 if ( psMode == 0 )
4222 {
4223 // Turn off pre-TBTT interrupt
4224 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, 0);
4225 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
4226 zfFlushDelayWrite(dev);
4227 }
4228 else
4229 {
4230 // Turn on pre-TBTT interrupt
4231 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
4232 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, bcnInterval);
4233 zfFlushDelayWrite(dev);
4234 }
4235 }
4236 }
4237
4238 void zfHpPowerSaveSetState(zdev_t* dev, u8_t psState)
4239 {
4240 struct zsHpPriv* hpPriv;
4241
4242 zmw_get_wlan_dev(dev);
4243 hpPriv = wd->hpPrivate;
4244
4245 //DbgPrint("INTO zfHpPowerSaveSetState");
4246
4247 if ( psState == 0 ) //power up
4248 {
4249 //DbgPrint("zfHpPowerSaveSetState Wake up from PS\n");
4250 reg_write(0x982C, 0x0000a000); //wake up ADDAC
4251 reg_write(0x9808, 0x0); //enable all agc gain and offset updates to a2
4252 //# bank 3
4253 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4254 {
4255 /* 11g */
4256 //reg_write (0x98f0, 0x01c00018);
4257 reg_write (0x98f0, 0x01c20098);//syn_on+RX_ON
4258 }
4259 else
4260 {
4261 /* 11a */
4262 //reg_write (0x98f0, 0x01400018);
4263 reg_write (0x98f0, 0x01420098);//syn_on+RX_ON
4264 }
4265
4266 ////#bank 5
4267 //reg_write(0x98b0, 0x00000013);
4268 //reg_write(0x98e4, 0x00000002);
4269
4270
4271 zfFlushDelayWrite(dev);
4272 }
4273 else //power down
4274 {
4275 //DbgPrint("zfHpPowerSaveSetState Go to PS\n");
4276 //reg_write(0x982C, 0xa000a000);
4277 reg_write(0x9808, 0x8000000); //disable all agc gain and offset updates to a2
4278 reg_write(0x982C, 0xa000a000); //power down ADDAC
4279 //# bank 3
4280 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4281 {
4282 /* 11g */
4283 reg_write (0x98f0, 0x00c00018);//syn_off+RX_off
4284 }
4285 else
4286 {
4287 /* 11a */
4288 reg_write (0x98f0, 0x00400018);//syn_off+RX_off
4289 }
4290
4291 ////#bank 5
4292 //reg_write(0x98b0, 0x000e0013);
4293 //reg_write(0x98e4, 0x00018002);
4294
4295
4296 zfFlushDelayWrite(dev);
4297 }
4298 }
4299
4300 void zfHpSetAggPktNum(zdev_t* dev, u32_t num)
4301 {
4302 struct zsHpPriv* hpPriv;
4303
4304 zmw_get_wlan_dev(dev);
4305 hpPriv = wd->hpPrivate;
4306
4307 num = (num << 16) | (0xa);
4308
4309 hpPriv->aggPktNum = num;
4310
4311 //aggregation number will be update in HAL heart beat
4312 //zfDelayWriteInternalReg(dev, 0x1c3b9c, num);
4313 //zfFlushDelayWrite(dev);
4314 }
4315
4316 void zfHpSetMPDUDensity(zdev_t* dev, u8_t density)
4317 {
4318 u32_t value;
4319
4320 if (density > ZM_MPDU_DENSITY_8US)
4321 {
4322 return;
4323 }
4324
4325 /* Default value in this register */
4326 value = 0x140A00 | density;
4327
4328 zfDelayWriteInternalReg(dev, 0x1c3ba0, value);
4329 zfFlushDelayWrite(dev);
4330 return;
4331 }
4332
4333 void zfHpSetSlotTime(zdev_t* dev, u8_t type)
4334 {
4335 struct zsHpPriv* hpPriv;
4336
4337 zmw_get_wlan_dev(dev);
4338 hpPriv = wd->hpPrivate;
4339
4340 if (type == 0)
4341 {
4342 //normal slot = 20us
4343 hpPriv->slotType = 0;
4344 }
4345 else //if (type == 1)
4346 {
4347 //short slot = 9us
4348 hpPriv->slotType = 1;
4349 }
4350
4351 return;
4352 }
4353
4354 void zfHpSetSlotTimeRegister(zdev_t* dev, u8_t type)
4355 {
4356 if(type == 0)
4357 {
4358 //normal slot = 20us
4359 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 20<<10);
4360 }
4361 else
4362 {
4363 //short slot = 9us
4364 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
4365 }
4366 }
4367
4368 void zfHpSetRifs(zdev_t* dev, u8_t ht_enable, u8_t ht2040, u8_t g_mode)
4369 {
4370 zfDelayWriteInternalReg(dev, 0x1c6388, 0x0c000000);
4371
4372 zfDelayWriteInternalReg(dev, 0x1c59ec, 0x0cc80caa);
4373
4374 if (ht_enable)
4375 {
4376 if (ht2040)
4377 {
4378 zfDelayWriteInternalReg(dev, 0x1c5918, 40);
4379 }
4380 else
4381 {
4382 zfDelayWriteInternalReg(dev, 0x1c5918, 20);
4383 }
4384 }
4385
4386 if (g_mode)
4387 {
4388 zfDelayWriteInternalReg(dev, 0x1c5850, 0xec08b4e2);
4389 zfDelayWriteInternalReg(dev, 0x1c585c, 0x313a5d5e);
4390 }
4391 else
4392 {
4393 zfDelayWriteInternalReg(dev, 0x1c5850, 0xede8b4e0);
4394 zfDelayWriteInternalReg(dev, 0x1c585c, 0x3139605e);
4395 }
4396
4397 zfFlushDelayWrite(dev);
4398 return;
4399 }
4400
4401 void zfHpBeginSiteSurvey(zdev_t* dev, u8_t status)
4402 {
4403 struct zsHpPriv* hpPriv;
4404
4405 zmw_get_wlan_dev(dev);
4406 hpPriv=wd->hpPrivate;
4407
4408 if ( status == 1 )
4409 { // Connected
4410 hpPriv->isSiteSurvey = 1;
4411 }
4412 else
4413 { // Not connected
4414 hpPriv->isSiteSurvey = 0;
4415 }
4416
4417 /* reset workaround state to default */
4418 // if (hpPriv->rxStrongRSSI == 1)
4419 {
4420 hpPriv->rxStrongRSSI = 0;
4421 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
4422 {
4423 if (hpPriv->hwFrequency <= ZM_CH_G_14)
4424 {
4425 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
4426 }
4427 else
4428 {
4429 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
4430 }
4431 }
4432 else
4433 {
4434 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
4435 }
4436 zfFlushDelayWrite(dev);
4437 }
4438 // if (hpPriv->strongRSSI == 1)
4439 {
4440 hpPriv->strongRSSI = 0;
4441 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
4442 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
4443 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
4444 zfFlushDelayWrite(dev);
4445 }
4446 }
4447
4448 void zfHpFinishSiteSurvey(zdev_t* dev, u8_t status)
4449 {
4450 struct zsHpPriv* hpPriv;
4451
4452 zmw_get_wlan_dev(dev);
4453 hpPriv=wd->hpPrivate;
4454
4455 zmw_declare_for_critical_section();
4456
4457 zmw_enter_critical_section(dev);
4458 if ( status == 1 )
4459 {
4460 hpPriv->isSiteSurvey = 2;
4461 }
4462 else
4463 {
4464 hpPriv->isSiteSurvey = 0;
4465 }
4466 zmw_leave_critical_section(dev);
4467 }
4468
4469 u16_t zfFwRetry(zdev_t* dev, u8_t enable)
4470 {
4471 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
4472 u16_t ret = 0;
4473
4474 cmd[0] = 4 | (0x92 << 8);
4475 cmd[1] = (enable == 1) ? 0x01 : 0x00;
4476
4477 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
4478 return ret;
4479 }
4480
4481 u16_t zfHpEnableHwRetry(zdev_t* dev)
4482 {
4483 u16_t ret;
4484
4485 ret = zfFwRetry(dev, 0);
4486
4487 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x33333);
4488 zfFlushDelayWrite(dev);
4489
4490 return ret;
4491 }
4492
4493 u16_t zfHpDisableHwRetry(zdev_t* dev)
4494 {
4495 u16_t ret;
4496
4497 ret = zfFwRetry(dev, 1);
4498
4499 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x00000);
4500 zfFlushDelayWrite(dev);
4501
4502 return ret;
4503 }
4504
4505 /* Download SPI Fw */
4506 #define ZM_FIRMWARE_WLAN 0
4507 #define ZM_FIRMWARE_SPI_FLASH 1
4508
4509
4510 u16_t zfHpFirmwareDownload(zdev_t* dev, u8_t fwType)
4511 {
4512 u16_t ret = ZM_SUCCESS;
4513
4514 if (fwType == ZM_FIRMWARE_WLAN)
4515 {
4516 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
4517 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
4518 }
4519 else if (fwType == ZM_FIRMWARE_SPI_FLASH)
4520 {
4521 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImageSPI,
4522 (u32_t)zcFwImageSPISize, ZM_FIRMWARE_SPI_ADDR);
4523 }
4524 else
4525 {
4526 zm_debug_msg1("Unknown firmware type = ", fwType);
4527 ret = ZM_ERR_FIRMWARE_WRONG_TYPE;
4528 }
4529
4530 return ret;
4531 }
4532
4533 /* Enable software decryption */
4534 void zfHpSWDecrypt(zdev_t* dev, u8_t enable)
4535 {
4536 u32_t value = 0x70;
4537
4538 /* Bit 4 for enable software decryption */
4539 if (enable == 1)
4540 {
4541 value = 0x78;
4542 }
4543
4544 zfDelayWriteInternalReg(dev, 0x1c3678, value);
4545 zfFlushDelayWrite(dev);
4546 }
4547
4548 /* Enable software encryption */
4549 void zfHpSWEncrypt(zdev_t* dev, u8_t enable)
4550 {
4551 /* Because encryption by software or hardware is judged by driver in Otus,
4552 we don't need to do anything in the HAL layer.
4553 */
4554 }
4555
4556 u32_t zfHpCapability(zdev_t* dev)
4557 {
4558 struct zsHpPriv* hpPriv;
4559
4560 zmw_get_wlan_dev(dev);
4561 hpPriv=wd->hpPrivate;
4562
4563 return hpPriv->halCapability;
4564 }
4565
4566 void zfHpSetRollCallTable(zdev_t* dev)
4567 {
4568 struct zsHpPriv* hpPriv;
4569
4570 zmw_get_wlan_dev(dev);
4571 hpPriv=wd->hpPrivate;
4572
4573 if (hpPriv->camRollCallTable != (u64_t) 0)
4574 {
4575 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, (u32_t)(hpPriv->camRollCallTable & 0xffffffff));
4576 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, (u32_t)((hpPriv->camRollCallTable >> 32) & 0xffffffff));
4577 zfFlushDelayWrite(dev);
4578 }
4579 }
4580
4581 void zfHpSetTTSIFSTime(zdev_t* dev, u8_t sifs_time)
4582 {
4583 u32_t reg_value = 0;
4584
4585 sifs_time &= 0x3f;
4586 reg_value = 0x14400b | (((u32_t)sifs_time)<<24);
4587
4588 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, reg_value);
4589 zfFlushDelayWrite(dev);
4590 }
4591
4592 /* #3 Enable RIFS function if the RIFS pattern matched ! */
4593 void zfHpEnableRifs(zdev_t* dev, u8_t mode24g, u8_t modeHt, u8_t modeHt2040)
4594 {
4595
4596 /* # Enable Reset TDOMAIN
4597 * $rddata = &$phyreg_read(0x9800+(738<<2));
4598 * $wrdata = $rddata | (0x1 << 26) | (0x1 << 27);
4599 * &$phyreg_write(0x9800+(738<<2), $wrdata);
4600 */
4601 reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26) | (0x1 << 27));
4602 //reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26));
4603
4604 /* # reg 123: heavy clip factor, xr / RIFS search parameters */
4605 reg_write (0x99ec, 0x0cc80caa);
4606
4607 /* # Reduce Search Start Delay for RIFS */
4608 if (modeHt == 1) /* ($HT_ENABLE == 1) */
4609 {
4610 if (modeHt2040 == 0x1) /* ($DYNAMIC_HT2040_EN == 0x1) */
4611 {
4612 reg_write(0x9800+(70<<2), 40);/*40*/
4613 }
4614 else
4615 {
4616 reg_write(0x9800+(70<<2), 20);
4617 if(mode24g == 0x0)
4618 {
4619 /* $rddata = &$phyreg_read(0x9800+(24<<2));#0x9860;0x1c5860
4620 *$wrdata = ($rddata & 0xffffffc7) | (0x4 << 3);
4621 * &$phyreg_write(0x9800+(24<<2), $wrdata);
4622 */
4623 reg_write(0x9800+(24<<2), (0x0004dd10 & 0xffffffc7) | (0x4 << 3));
4624 }
4625 }
4626 }
4627
4628 if (mode24g == 0x1)
4629 {
4630 reg_write(0x9850, 0xece8b4e4);/*org*/
4631 //reg_write(0x9850, 0xece8b4e2);
4632 reg_write(0x985c, 0x313a5d5e);
4633 }
4634 else
4635 {
4636 reg_write(0x9850, 0xede8b4e4);
4637 reg_write(0x985c, 0x3139605e);
4638 }
4639
4640 zfFlushDelayWrite(dev);
4641
4642 return;
4643 }
4644
4645 /* #4 Disable RIFS function if the RIFS timer is timeout ! */
4646 void zfHpDisableRifs(zdev_t* dev)
4647 {
4648 zmw_get_wlan_dev(dev);
4649
4650 /* Disable RIFS function is to store these HW register initial value while the device plug-in and
4651 re-write to these register if the RIFS function is disabled */
4652
4653 // reg : 9850
4654 reg_write(0x9850, ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize);
4655
4656 // reg : 985c
4657 reg_write(0x985c, ((struct zsHpPriv*)wd->hpPrivate)->initAGC);
4658
4659 // reg : 9860
4660 reg_write(0x9800+(24<<2), ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl);
4661
4662 // reg : 9918
4663 reg_write(0x9800+(70<<2), ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay);
4664
4665 // reg : 991c
4666 reg_write (0x99ec, ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams);
4667
4668 // reg : a388
4669 reg_write (0x9800+(738<<2), ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl);
4670
4671 zfFlushDelayWrite(dev);
4672
4673 return;
4674 }
x86 "subsystem" repository