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[PATCH] shpchp: Mask Global SERR and Intr at controller release time
[linux-2.6/x86.git] / drivers / pci / hotplug / shpchp_hpc.c
blob8b63f772a6f2465bff8e06bbaae3ca3d6577ba7a
1 /*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 #include "shpchp.h"
37
38 #ifdef DEBUG
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
47
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49
50 #define DBG_PRINT( dbg_flags, args... ) \
51 do { \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
53 { \
54 int len; \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
59 } \
60 } while (0)
61
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64 #else
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
68 #endif /* DEBUG */
69
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
75
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
84
85 /* Slot Configuration */
86 #define SLOT_NUM 0x0000001F
87 #define FIRST_DEV_NUM 0x00001F00
88 #define PSN 0x07FF0000
89 #define UPDOWN 0x20000000
90 #define MRLSENSOR 0x40000000
91 #define ATTN_BUTTON 0x80000000
92
93 /*
94 * Controller SERR-INT Register
95 */
96 #define GLOBAL_INTR_MASK (1 << 0)
97 #define GLOBAL_SERR_MASK (1 << 1)
98 #define COMMAND_INTR_MASK (1 << 2)
99 #define ARBITER_SERR_MASK (1 << 3)
100 #define COMMAND_DETECTED (1 << 16)
101 #define ARBITER_DETECTED (1 << 17)
102 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
103
104 /*
105 * Logical Slot Register definitions
106 */
107 #define SLOT_REG(i) (SLOT1 + (4 * i))
108
109 #define SLOT_STATE_SHIFT (0)
110 #define SLOT_STATE_MASK (3 << 0)
111 #define SLOT_STATE_PWRONLY (1)
112 #define SLOT_STATE_ENABLED (2)
113 #define SLOT_STATE_DISABLED (3)
114 #define PWR_LED_STATE_SHIFT (2)
115 #define PWR_LED_STATE_MASK (3 << 2)
116 #define ATN_LED_STATE_SHIFT (4)
117 #define ATN_LED_STATE_MASK (3 << 4)
118 #define ATN_LED_STATE_ON (1)
119 #define ATN_LED_STATE_BLINK (2)
120 #define ATN_LED_STATE_OFF (3)
121 #define POWER_FAULT (1 << 6)
122 #define ATN_BUTTON (1 << 7)
123 #define MRL_SENSOR (1 << 8)
124 #define MHZ66_CAP (1 << 9)
125 #define PRSNT_SHIFT (10)
126 #define PRSNT_MASK (3 << 10)
127 #define PCIX_CAP_SHIFT (12)
128 #define PCIX_CAP_MASK_PI1 (3 << 12)
129 #define PCIX_CAP_MASK_PI2 (7 << 12)
130 #define PRSNT_CHANGE_DETECTED (1 << 16)
131 #define ISO_PFAULT_DETECTED (1 << 17)
132 #define BUTTON_PRESS_DETECTED (1 << 18)
133 #define MRL_CHANGE_DETECTED (1 << 19)
134 #define CON_PFAULT_DETECTED (1 << 20)
135 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
136 #define ISO_PFAULT_INTR_MASK (1 << 25)
137 #define BUTTON_PRESS_INTR_MASK (1 << 26)
138 #define MRL_CHANGE_INTR_MASK (1 << 27)
139 #define CON_PFAULT_INTR_MASK (1 << 28)
140 #define MRL_CHANGE_SERR_MASK (1 << 29)
141 #define CON_PFAULT_SERR_MASK (1 << 30)
142 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
143
144 /* SHPC 'write' operations/commands */
145
146 /* Slot operation - 0x00h to 0x3Fh */
147
148 #define NO_CHANGE 0x00
149
150 /* Slot state - Bits 0 & 1 of controller command register */
151 #define SET_SLOT_PWR 0x01
152 #define SET_SLOT_ENABLE 0x02
153 #define SET_SLOT_DISABLE 0x03
154
155 /* Power indicator state - Bits 2 & 3 of controller command register*/
156 #define SET_PWR_ON 0x04
157 #define SET_PWR_BLINK 0x08
158 #define SET_PWR_OFF 0x0C
159
160 /* Attention indicator state - Bits 4 & 5 of controller command register*/
161 #define SET_ATTN_ON 0x010
162 #define SET_ATTN_BLINK 0x020
163 #define SET_ATTN_OFF 0x030
164
165 /* Set bus speed/mode A - 0x40h to 0x47h */
166 #define SETA_PCI_33MHZ 0x40
167 #define SETA_PCI_66MHZ 0x41
168 #define SETA_PCIX_66MHZ 0x42
169 #define SETA_PCIX_100MHZ 0x43
170 #define SETA_PCIX_133MHZ 0x44
171 #define RESERV_1 0x45
172 #define RESERV_2 0x46
173 #define RESERV_3 0x47
174
175 /* Set bus speed/mode B - 0x50h to 0x5fh */
176 #define SETB_PCI_33MHZ 0x50
177 #define SETB_PCI_66MHZ 0x51
178 #define SETB_PCIX_66MHZ_PM 0x52
179 #define SETB_PCIX_100MHZ_PM 0x53
180 #define SETB_PCIX_133MHZ_PM 0x54
181 #define SETB_PCIX_66MHZ_EM 0x55
182 #define SETB_PCIX_100MHZ_EM 0x56
183 #define SETB_PCIX_133MHZ_EM 0x57
184 #define SETB_PCIX_66MHZ_266 0x58
185 #define SETB_PCIX_100MHZ_266 0x59
186 #define SETB_PCIX_133MHZ_266 0x5a
187 #define SETB_PCIX_66MHZ_533 0x5b
188 #define SETB_PCIX_100MHZ_533 0x5c
189 #define SETB_PCIX_133MHZ_533 0x5d
190
191
192 /* Power-on all slots - 0x48h */
193 #define SET_PWR_ON_ALL 0x48
194
195 /* Enable all slots - 0x49h */
196 #define SET_ENABLE_ALL 0x49
197
198 /* SHPC controller command error code */
199 #define SWITCH_OPEN 0x1
200 #define INVALID_CMD 0x2
201 #define INVALID_SPEED_MODE 0x4
202
203 /* For accessing SHPC Working Register Set */
204 #define DWORD_SELECT 0x2
205 #define DWORD_DATA 0x4
206 #define BASE_OFFSET 0x0
207
208 /* Field Offset in Logical Slot Register - byte boundary */
209 #define SLOT_EVENT_LATCH 0x2
210 #define SLOT_SERR_INT_MASK 0x3
211
212 static spinlock_t hpc_event_lock;
213
214 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
215 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
216 static int ctlr_seq_num = 0; /* Controller sequenc # */
217 static spinlock_t list_lock;
218
219 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
220
221 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
222 static int hpc_check_cmd_status(struct controller *ctrl);
223
224 static inline u8 shpc_readb(struct controller *ctrl, int reg)
225 {
226 return readb(ctrl->hpc_ctlr_handle->creg + reg);
227 }
228
229 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
230 {
231 writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
232 }
233
234 static inline u16 shpc_readw(struct controller *ctrl, int reg)
235 {
236 return readw(ctrl->hpc_ctlr_handle->creg + reg);
237 }
238
239 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
240 {
241 writew(val, ctrl->hpc_ctlr_handle->creg + reg);
242 }
243
244 static inline u32 shpc_readl(struct controller *ctrl, int reg)
245 {
246 return readl(ctrl->hpc_ctlr_handle->creg + reg);
247 }
248
249 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
250 {
251 writel(val, ctrl->hpc_ctlr_handle->creg + reg);
252 }
253
254 static inline int shpc_indirect_read(struct controller *ctrl, int index,
255 u32 *value)
256 {
257 int rc;
258 u32 cap_offset = ctrl->cap_offset;
259 struct pci_dev *pdev = ctrl->pci_dev;
260
261 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
262 if (rc)
263 return rc;
264 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
265 }
266
267 /* This is the interrupt polling timeout function. */
268 static void int_poll_timeout(unsigned long lphp_ctlr)
269 {
270 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
271
272 DBG_ENTER_ROUTINE
273
274 if ( !php_ctlr ) {
275 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
276 return;
277 }
278
279 /* Poll for interrupt events. regs == NULL => polling */
280 shpc_isr( 0, (void *)php_ctlr, NULL );
281
282 init_timer(&php_ctlr->int_poll_timer);
283 if (!shpchp_poll_time)
284 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
285
286 start_int_poll_timer(php_ctlr, shpchp_poll_time);
287
288 return;
289 }
290
291 /* This function starts the interrupt polling timer. */
292 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
293 {
294 if (!php_ctlr) {
295 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
296 return;
297 }
298
299 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
300 seconds = 2; /* Clamp to sane value */
301
302 php_ctlr->int_poll_timer.function = &int_poll_timeout;
303 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
304 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
305 add_timer(&php_ctlr->int_poll_timer);
306
307 return;
308 }
309
310 static inline int shpc_wait_cmd(struct controller *ctrl)
311 {
312 int retval = 0;
313 unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000;
314 unsigned long timeout = msecs_to_jiffies(timeout_msec);
315 int rc = wait_event_interruptible_timeout(ctrl->queue,
316 !ctrl->cmd_busy, timeout);
317 if (!rc) {
318 retval = -EIO;
319 err("Command not completed in %d msec\n", timeout_msec);
320 } else if (rc < 0) {
321 retval = -EINTR;
322 info("Command was interrupted by a signal\n");
323 }
324 ctrl->cmd_busy = 0;
325
326 return retval;
327 }
328
329 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
330 {
331 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
332 struct controller *ctrl = slot->ctrl;
333 u16 cmd_status;
334 int retval = 0;
335 u16 temp_word;
336 int i;
337
338 DBG_ENTER_ROUTINE
339
340 mutex_lock(&slot->ctrl->cmd_lock);
341
342 if (!php_ctlr) {
343 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
344 retval = -EINVAL;
345 goto out;
346 }
347
348 for (i = 0; i < 10; i++) {
349 cmd_status = shpc_readw(ctrl, CMD_STATUS);
350
351 if (!(cmd_status & 0x1))
352 break;
353 /* Check every 0.1 sec for a total of 1 sec*/
354 msleep(100);
355 }
356
357 cmd_status = shpc_readw(ctrl, CMD_STATUS);
358
359 if (cmd_status & 0x1) {
360 /* After 1 sec and and the controller is still busy */
361 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
362 retval = -EBUSY;
363 goto out;
364 }
365
366 ++t_slot;
367 temp_word = (t_slot << 8) | (cmd & 0xFF);
368 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
369
370 /* To make sure the Controller Busy bit is 0 before we send out the
371 * command.
372 */
373 slot->ctrl->cmd_busy = 1;
374 shpc_writew(ctrl, CMD, temp_word);
375
376 /*
377 * Wait for command completion.
378 */
379 retval = shpc_wait_cmd(slot->ctrl);
380 if (retval)
381 goto out;
382
383 cmd_status = hpc_check_cmd_status(slot->ctrl);
384 if (cmd_status) {
385 err("%s: Failed to issued command 0x%x (error code = %d)\n",
386 __FUNCTION__, cmd, cmd_status);
387 retval = -EIO;
388 }
389 out:
390 mutex_unlock(&slot->ctrl->cmd_lock);
391
392 DBG_LEAVE_ROUTINE
393 return retval;
394 }
395
396 static int hpc_check_cmd_status(struct controller *ctrl)
397 {
398 u16 cmd_status;
399 int retval = 0;
400
401 DBG_ENTER_ROUTINE
402
403 if (!ctrl->hpc_ctlr_handle) {
404 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
405 return -1;
406 }
407
408 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
409
410 switch (cmd_status >> 1) {
411 case 0:
412 retval = 0;
413 break;
414 case 1:
415 retval = SWITCH_OPEN;
416 err("%s: Switch opened!\n", __FUNCTION__);
417 break;
418 case 2:
419 retval = INVALID_CMD;
420 err("%s: Invalid HPC command!\n", __FUNCTION__);
421 break;
422 case 4:
423 retval = INVALID_SPEED_MODE;
424 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
425 break;
426 default:
427 retval = cmd_status;
428 }
429
430 DBG_LEAVE_ROUTINE
431 return retval;
432 }
433
434
435 static int hpc_get_attention_status(struct slot *slot, u8 *status)
436 {
437 struct controller *ctrl = slot->ctrl;
438 u32 slot_reg;
439 u8 state;
440
441 DBG_ENTER_ROUTINE
442
443 if (!slot->ctrl->hpc_ctlr_handle) {
444 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
445 return -1;
446 }
447
448 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
449 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
450
451 switch (state) {
452 case ATN_LED_STATE_ON:
453 *status = 1; /* On */
454 break;
455 case ATN_LED_STATE_BLINK:
456 *status = 2; /* Blink */
457 break;
458 case ATN_LED_STATE_OFF:
459 *status = 0; /* Off */
460 break;
461 default:
462 *status = 0xFF; /* Reserved */
463 break;
464 }
465
466 DBG_LEAVE_ROUTINE
467 return 0;
468 }
469
470 static int hpc_get_power_status(struct slot * slot, u8 *status)
471 {
472 struct controller *ctrl = slot->ctrl;
473 u32 slot_reg;
474 u8 state;
475
476 DBG_ENTER_ROUTINE
477
478 if (!slot->ctrl->hpc_ctlr_handle) {
479 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
480 return -1;
481 }
482
483 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
484 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
485
486 switch (state) {
487 case SLOT_STATE_PWRONLY:
488 *status = 2; /* Powered only */
489 break;
490 case SLOT_STATE_ENABLED:
491 *status = 1; /* Enabled */
492 break;
493 case SLOT_STATE_DISABLED:
494 *status = 0; /* Disabled */
495 break;
496 default:
497 *status = 0xFF; /* Reserved */
498 break;
499 }
500
501 DBG_LEAVE_ROUTINE
502 return 0;
503 }
504
505
506 static int hpc_get_latch_status(struct slot *slot, u8 *status)
507 {
508 struct controller *ctrl = slot->ctrl;
509 u32 slot_reg;
510
511 DBG_ENTER_ROUTINE
512
513 if (!slot->ctrl->hpc_ctlr_handle) {
514 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
515 return -1;
516 }
517
518 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
519 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
520
521 DBG_LEAVE_ROUTINE
522 return 0;
523 }
524
525 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
526 {
527 struct controller *ctrl = slot->ctrl;
528 u32 slot_reg;
529 u8 state;
530
531 DBG_ENTER_ROUTINE
532
533 if (!slot->ctrl->hpc_ctlr_handle) {
534 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
535 return -1;
536 }
537
538 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
539 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
540 *status = (state != 0x3) ? 1 : 0;
541
542 DBG_LEAVE_ROUTINE
543 return 0;
544 }
545
546 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
547 {
548 struct controller *ctrl = slot->ctrl;
549
550 DBG_ENTER_ROUTINE
551
552 if (!slot->ctrl->hpc_ctlr_handle) {
553 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
554 return -1;
555 }
556
557 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
558
559 DBG_LEAVE_ROUTINE
560 return 0;
561 }
562
563 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
564 {
565 int retval = 0;
566 struct controller *ctrl = slot->ctrl;
567 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
568 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
569 u8 pi, pcix_cap;
570
571 DBG_ENTER_ROUTINE
572
573 if ((retval = hpc_get_prog_int(slot, &pi)))
574 return retval;
575
576 switch (pi) {
577 case 1:
578 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
579 break;
580 case 2:
581 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
582 break;
583 default:
584 return -ENODEV;
585 }
586
587 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
588 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
589
590 switch (pcix_cap) {
591 case 0x0:
592 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
593 break;
594 case 0x1:
595 *value = PCI_SPEED_66MHz_PCIX;
596 break;
597 case 0x3:
598 *value = PCI_SPEED_133MHz_PCIX;
599 break;
600 case 0x4:
601 *value = PCI_SPEED_133MHz_PCIX_266;
602 break;
603 case 0x5:
604 *value = PCI_SPEED_133MHz_PCIX_533;
605 break;
606 case 0x2:
607 default:
608 *value = PCI_SPEED_UNKNOWN;
609 retval = -ENODEV;
610 break;
611 }
612
613 dbg("Adapter speed = %d\n", *value);
614 DBG_LEAVE_ROUTINE
615 return retval;
616 }
617
618 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
619 {
620 struct controller *ctrl = slot->ctrl;
621 u16 sec_bus_status;
622 u8 pi;
623 int retval = 0;
624
625 DBG_ENTER_ROUTINE
626
627 if (!slot->ctrl->hpc_ctlr_handle) {
628 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
629 return -1;
630 }
631
632 pi = shpc_readb(ctrl, PROG_INTERFACE);
633 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
634
635 if (pi == 2) {
636 *mode = (sec_bus_status & 0x0100) >> 8;
637 } else {
638 retval = -1;
639 }
640
641 dbg("Mode 1 ECC cap = %d\n", *mode);
642
643 DBG_LEAVE_ROUTINE
644 return retval;
645 }
646
647 static int hpc_query_power_fault(struct slot * slot)
648 {
649 struct controller *ctrl = slot->ctrl;
650 u32 slot_reg;
651
652 DBG_ENTER_ROUTINE
653
654 if (!slot->ctrl->hpc_ctlr_handle) {
655 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
656 return -1;
657 }
658
659 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
660
661 DBG_LEAVE_ROUTINE
662 /* Note: Logic 0 => fault */
663 return !(slot_reg & POWER_FAULT);
664 }
665
666 static int hpc_set_attention_status(struct slot *slot, u8 value)
667 {
668 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
669 u8 slot_cmd = 0;
670 int rc = 0;
671
672 if (!slot->ctrl->hpc_ctlr_handle) {
673 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
674 return -1;
675 }
676
677 if (slot->hp_slot >= php_ctlr->num_slots) {
678 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
679 return -1;
680 }
681
682 switch (value) {
683 case 0 :
684 slot_cmd = 0x30; /* OFF */
685 break;
686 case 1:
687 slot_cmd = 0x10; /* ON */
688 break;
689 case 2:
690 slot_cmd = 0x20; /* BLINK */
691 break;
692 default:
693 return -1;
694 }
695
696 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
697
698 return rc;
699 }
700
701
702 static void hpc_set_green_led_on(struct slot *slot)
703 {
704 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
705 u8 slot_cmd;
706
707 if (!slot->ctrl->hpc_ctlr_handle) {
708 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
709 return ;
710 }
711
712 if (slot->hp_slot >= php_ctlr->num_slots) {
713 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
714 return ;
715 }
716
717 slot_cmd = 0x04;
718
719 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
720
721 return;
722 }
723
724 static void hpc_set_green_led_off(struct slot *slot)
725 {
726 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
727 u8 slot_cmd;
728
729 if (!slot->ctrl->hpc_ctlr_handle) {
730 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
731 return ;
732 }
733
734 if (slot->hp_slot >= php_ctlr->num_slots) {
735 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
736 return ;
737 }
738
739 slot_cmd = 0x0C;
740
741 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
742
743 return;
744 }
745
746 static void hpc_set_green_led_blink(struct slot *slot)
747 {
748 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
749 u8 slot_cmd;
750
751 if (!slot->ctrl->hpc_ctlr_handle) {
752 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
753 return ;
754 }
755
756 if (slot->hp_slot >= php_ctlr->num_slots) {
757 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
758 return ;
759 }
760
761 slot_cmd = 0x08;
762
763 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
764
765 return;
766 }
767
768 int shpc_get_ctlr_slot_config(struct controller *ctrl,
769 int *num_ctlr_slots, /* number of slots in this HPC */
770 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
771 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
772 int *updown, /* physical_slot_num increament: 1 or -1 */
773 int *flags)
774 {
775 u32 slot_config;
776
777 DBG_ENTER_ROUTINE
778
779 if (!ctrl->hpc_ctlr_handle) {
780 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
781 return -1;
782 }
783
784 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
785 *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
786 *num_ctlr_slots = slot_config & SLOT_NUM;
787 *physical_slot_num = (slot_config & PSN) >> 16;
788 *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
789
790 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
791
792 DBG_LEAVE_ROUTINE
793 return 0;
794 }
795
796 static void hpc_release_ctlr(struct controller *ctrl)
797 {
798 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
799 struct php_ctlr_state_s *p, *p_prev;
800 int i;
801 u32 slot_reg, serr_int;
802
803 DBG_ENTER_ROUTINE
804
805 if (!ctrl->hpc_ctlr_handle) {
806 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
807 return ;
808 }
809
810 /*
811 * Mask event interrupts and SERRs of all slots
812 */
813 for (i = 0; i < ctrl->num_slots; i++) {
814 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
815 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
816 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
817 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
818 CON_PFAULT_SERR_MASK);
819 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
820 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
821 }
822
823 cleanup_slots(ctrl);
824
825 /*
826 * Mask SERR and System Interrut generation
827 */
828 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
829 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
830 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
831 serr_int &= ~SERR_INTR_RSVDZ_MASK;
832 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
833
834 if (shpchp_poll_mode) {
835 del_timer(&php_ctlr->int_poll_timer);
836 } else {
837 if (php_ctlr->irq) {
838 free_irq(php_ctlr->irq, ctrl);
839 php_ctlr->irq = 0;
840 pci_disable_msi(php_ctlr->pci_dev);
841 }
842 }
843
844 if (php_ctlr->pci_dev) {
845 iounmap(php_ctlr->creg);
846 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
847 php_ctlr->pci_dev = NULL;
848 }
849
850 spin_lock(&list_lock);
851 p = php_ctlr_list_head;
852 p_prev = NULL;
853 while (p) {
854 if (p == php_ctlr) {
855 if (p_prev)
856 p_prev->pnext = p->pnext;
857 else
858 php_ctlr_list_head = p->pnext;
859 break;
860 } else {
861 p_prev = p;
862 p = p->pnext;
863 }
864 }
865 spin_unlock(&list_lock);
866
867 kfree(php_ctlr);
868
869 DBG_LEAVE_ROUTINE
870
871 }
872
873 static int hpc_power_on_slot(struct slot * slot)
874 {
875 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
876 u8 slot_cmd;
877 int retval = 0;
878
879 DBG_ENTER_ROUTINE
880
881 if (!slot->ctrl->hpc_ctlr_handle) {
882 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
883 return -1;
884 }
885
886 if (slot->hp_slot >= php_ctlr->num_slots) {
887 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
888 return -1;
889 }
890 slot_cmd = 0x01;
891
892 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
893
894 if (retval) {
895 err("%s: Write command failed!\n", __FUNCTION__);
896 return -1;
897 }
898
899 DBG_LEAVE_ROUTINE
900
901 return retval;
902 }
903
904 static int hpc_slot_enable(struct slot * slot)
905 {
906 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
907 u8 slot_cmd;
908 int retval = 0;
909
910 DBG_ENTER_ROUTINE
911
912 if (!slot->ctrl->hpc_ctlr_handle) {
913 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
914 return -1;
915 }
916
917 if (slot->hp_slot >= php_ctlr->num_slots) {
918 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
919 return -1;
920 }
921 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
922 slot_cmd = 0x3A;
923
924 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
925
926 if (retval) {
927 err("%s: Write command failed!\n", __FUNCTION__);
928 return -1;
929 }
930
931 DBG_LEAVE_ROUTINE
932 return retval;
933 }
934
935 static int hpc_slot_disable(struct slot * slot)
936 {
937 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
938 u8 slot_cmd;
939 int retval = 0;
940
941 DBG_ENTER_ROUTINE
942
943 if (!slot->ctrl->hpc_ctlr_handle) {
944 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
945 return -1;
946 }
947
948 if (slot->hp_slot >= php_ctlr->num_slots) {
949 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
950 return -1;
951 }
952
953 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
954 slot_cmd = 0x1F;
955
956 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
957
958 if (retval) {
959 err("%s: Write command failed!\n", __FUNCTION__);
960 return -1;
961 }
962
963 DBG_LEAVE_ROUTINE
964 return retval;
965 }
966
967 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
968 {
969 int retval;
970 struct controller *ctrl = slot->ctrl;
971 u8 pi, cmd;
972
973 DBG_ENTER_ROUTINE
974
975 pi = shpc_readb(ctrl, PROG_INTERFACE);
976 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
977 return -EINVAL;
978
979 switch (value) {
980 case PCI_SPEED_33MHz:
981 cmd = SETA_PCI_33MHZ;
982 break;
983 case PCI_SPEED_66MHz:
984 cmd = SETA_PCI_66MHZ;
985 break;
986 case PCI_SPEED_66MHz_PCIX:
987 cmd = SETA_PCIX_66MHZ;
988 break;
989 case PCI_SPEED_100MHz_PCIX:
990 cmd = SETA_PCIX_100MHZ;
991 break;
992 case PCI_SPEED_133MHz_PCIX:
993 cmd = SETA_PCIX_133MHZ;
994 break;
995 case PCI_SPEED_66MHz_PCIX_ECC:
996 cmd = SETB_PCIX_66MHZ_EM;
997 break;
998 case PCI_SPEED_100MHz_PCIX_ECC:
999 cmd = SETB_PCIX_100MHZ_EM;
1000 break;
1001 case PCI_SPEED_133MHz_PCIX_ECC:
1002 cmd = SETB_PCIX_133MHZ_EM;
1003 break;
1004 case PCI_SPEED_66MHz_PCIX_266:
1005 cmd = SETB_PCIX_66MHZ_266;
1006 break;
1007 case PCI_SPEED_100MHz_PCIX_266:
1008 cmd = SETB_PCIX_100MHZ_266;
1009 break;
1010 case PCI_SPEED_133MHz_PCIX_266:
1011 cmd = SETB_PCIX_133MHZ_266;
1012 break;
1013 case PCI_SPEED_66MHz_PCIX_533:
1014 cmd = SETB_PCIX_66MHZ_533;
1015 break;
1016 case PCI_SPEED_100MHz_PCIX_533:
1017 cmd = SETB_PCIX_100MHZ_533;
1018 break;
1019 case PCI_SPEED_133MHz_PCIX_533:
1020 cmd = SETB_PCIX_133MHZ_533;
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 retval = shpc_write_cmd(slot, 0, cmd);
1027 if (retval)
1028 err("%s: Write command failed!\n", __FUNCTION__);
1029
1030 DBG_LEAVE_ROUTINE
1031 return retval;
1032 }
1033
1034 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1035 {
1036 struct controller *ctrl = NULL;
1037 struct php_ctlr_state_s *php_ctlr;
1038 u8 schedule_flag = 0;
1039 u32 temp_dword, intr_loc, intr_loc2;
1040 int hp_slot;
1041
1042 if (!dev_id)
1043 return IRQ_NONE;
1044
1045 if (!shpchp_poll_mode) {
1046 ctrl = (struct controller *)dev_id;
1047 php_ctlr = ctrl->hpc_ctlr_handle;
1048 } else {
1049 php_ctlr = (struct php_ctlr_state_s *) dev_id;
1050 ctrl = (struct controller *)php_ctlr->callback_instance_id;
1051 }
1052
1053 if (!ctrl)
1054 return IRQ_NONE;
1055
1056 if (!php_ctlr || !php_ctlr->creg)
1057 return IRQ_NONE;
1058
1059 /* Check to see if it was our interrupt */
1060 intr_loc = shpc_readl(ctrl, INTR_LOC);
1061
1062 if (!intr_loc)
1063 return IRQ_NONE;
1064 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
1065
1066 if(!shpchp_poll_mode) {
1067 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1068 /* of SHPC spec rev 1.0*/
1069 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1070 temp_dword |= GLOBAL_INTR_MASK;
1071 temp_dword &= ~SERR_INTR_RSVDZ_MASK;
1072 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
1073
1074 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
1075 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1076 }
1077
1078 if (intr_loc & 0x0001) {
1079 /*
1080 * Command Complete Interrupt Pending
1081 * RO only - clear by writing 1 to the Command Completion
1082 * Detect bit in Controller SERR-INT register
1083 */
1084 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1085 temp_dword &= ~SERR_INTR_RSVDZ_MASK;
1086 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
1087 ctrl->cmd_busy = 0;
1088 wake_up_interruptible(&ctrl->queue);
1089 }
1090
1091 if ((intr_loc = (intr_loc >> 1)) == 0)
1092 goto out;
1093
1094 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1095 /* To find out which slot has interrupt pending */
1096 if ((intr_loc >> hp_slot) & 0x01) {
1097 temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot));
1098 dbg("%s: Slot %x with intr, slot register = %x\n",
1099 __FUNCTION__, hp_slot, temp_dword);
1100 if ((php_ctlr->switch_change_callback) &&
1101 (temp_dword & MRL_CHANGE_DETECTED))
1102 schedule_flag += php_ctlr->switch_change_callback(
1103 hp_slot, php_ctlr->callback_instance_id);
1104 if ((php_ctlr->attention_button_callback) &&
1105 (temp_dword & BUTTON_PRESS_DETECTED))
1106 schedule_flag += php_ctlr->attention_button_callback(
1107 hp_slot, php_ctlr->callback_instance_id);
1108 if ((php_ctlr->presence_change_callback) &&
1109 (temp_dword & PRSNT_CHANGE_DETECTED))
1110 schedule_flag += php_ctlr->presence_change_callback(
1111 hp_slot , php_ctlr->callback_instance_id);
1112 if ((php_ctlr->power_fault_callback) &&
1113 (temp_dword & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)))
1114 schedule_flag += php_ctlr->power_fault_callback(
1115 hp_slot, php_ctlr->callback_instance_id);
1116
1117 /* Clear all slot events */
1118 temp_dword &= ~SLOT_REG_RSVDZ_MASK;
1119 shpc_writel(ctrl, SLOT_REG(hp_slot), temp_dword);
1120
1121 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
1122 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1123 }
1124 }
1125 out:
1126 if (!shpchp_poll_mode) {
1127 /* Unmask Global Interrupt Mask */
1128 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1129 temp_dword &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
1130 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
1131 }
1132
1133 return IRQ_HANDLED;
1134 }
1135
1136 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1137 {
1138 int retval = 0;
1139 struct controller *ctrl = slot->ctrl;
1140 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1141 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1142 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
1143 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
1144
1145 DBG_ENTER_ROUTINE
1146
1147 if (pi == 2) {
1148 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
1149 bus_speed = PCI_SPEED_133MHz_PCIX_533;
1150 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
1151 bus_speed = PCI_SPEED_100MHz_PCIX_533;
1152 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
1153 bus_speed = PCI_SPEED_66MHz_PCIX_533;
1154 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
1155 bus_speed = PCI_SPEED_133MHz_PCIX_266;
1156 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
1157 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1158 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1159 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1160 }
1161
1162 if (bus_speed == PCI_SPEED_UNKNOWN) {
1163 if (slot_avail1 & SLOT_133MHZ_PCIX)
1164 bus_speed = PCI_SPEED_133MHz_PCIX;
1165 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1166 bus_speed = PCI_SPEED_100MHz_PCIX;
1167 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1168 bus_speed = PCI_SPEED_66MHz_PCIX;
1169 else if (slot_avail2 & SLOT_66MHZ)
1170 bus_speed = PCI_SPEED_66MHz;
1171 else if (slot_avail1 & SLOT_33MHZ)
1172 bus_speed = PCI_SPEED_33MHz;
1173 else
1174 retval = -ENODEV;
1175 }
1176
1177 *value = bus_speed;
1178 dbg("Max bus speed = %d\n", bus_speed);
1179 DBG_LEAVE_ROUTINE
1180 return retval;
1181 }
1182
1183 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1184 {
1185 int retval = 0;
1186 struct controller *ctrl = slot->ctrl;
1187 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1188 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
1189 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1190 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
1191
1192 DBG_ENTER_ROUTINE
1193
1194 if ((pi == 1) && (speed_mode > 4)) {
1195 *value = PCI_SPEED_UNKNOWN;
1196 return -ENODEV;
1197 }
1198
1199 switch (speed_mode) {
1200 case 0x0:
1201 *value = PCI_SPEED_33MHz;
1202 break;
1203 case 0x1:
1204 *value = PCI_SPEED_66MHz;
1205 break;
1206 case 0x2:
1207 *value = PCI_SPEED_66MHz_PCIX;
1208 break;
1209 case 0x3:
1210 *value = PCI_SPEED_100MHz_PCIX;
1211 break;
1212 case 0x4:
1213 *value = PCI_SPEED_133MHz_PCIX;
1214 break;
1215 case 0x5:
1216 *value = PCI_SPEED_66MHz_PCIX_ECC;
1217 break;
1218 case 0x6:
1219 *value = PCI_SPEED_100MHz_PCIX_ECC;
1220 break;
1221 case 0x7:
1222 *value = PCI_SPEED_133MHz_PCIX_ECC;
1223 break;
1224 case 0x8:
1225 *value = PCI_SPEED_66MHz_PCIX_266;
1226 break;
1227 case 0x9:
1228 *value = PCI_SPEED_100MHz_PCIX_266;
1229 break;
1230 case 0xa:
1231 *value = PCI_SPEED_133MHz_PCIX_266;
1232 break;
1233 case 0xb:
1234 *value = PCI_SPEED_66MHz_PCIX_533;
1235 break;
1236 case 0xc:
1237 *value = PCI_SPEED_100MHz_PCIX_533;
1238 break;
1239 case 0xd:
1240 *value = PCI_SPEED_133MHz_PCIX_533;
1241 break;
1242 default:
1243 *value = PCI_SPEED_UNKNOWN;
1244 retval = -ENODEV;
1245 break;
1246 }
1247
1248 dbg("Current bus speed = %d\n", bus_speed);
1249 DBG_LEAVE_ROUTINE
1250 return retval;
1251 }
1252
1253 static struct hpc_ops shpchp_hpc_ops = {
1254 .power_on_slot = hpc_power_on_slot,
1255 .slot_enable = hpc_slot_enable,
1256 .slot_disable = hpc_slot_disable,
1257 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1258 .set_attention_status = hpc_set_attention_status,
1259 .get_power_status = hpc_get_power_status,
1260 .get_attention_status = hpc_get_attention_status,
1261 .get_latch_status = hpc_get_latch_status,
1262 .get_adapter_status = hpc_get_adapter_status,
1263
1264 .get_max_bus_speed = hpc_get_max_bus_speed,
1265 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1266 .get_adapter_speed = hpc_get_adapter_speed,
1267 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1268 .get_prog_int = hpc_get_prog_int,
1269
1270 .query_power_fault = hpc_query_power_fault,
1271 .green_led_on = hpc_set_green_led_on,
1272 .green_led_off = hpc_set_green_led_off,
1273 .green_led_blink = hpc_set_green_led_blink,
1274
1275 .release_ctlr = hpc_release_ctlr,
1276 };
1277
1278 int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1279 {
1280 struct php_ctlr_state_s *php_ctlr, *p;
1281 void *instance_id = ctrl;
1282 int rc, num_slots = 0;
1283 u8 hp_slot;
1284 static int first = 1;
1285 u32 shpc_base_offset;
1286 u32 tempdword, slot_reg, slot_config;
1287 u8 i;
1288
1289 DBG_ENTER_ROUTINE
1290
1291 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1292
1293 spin_lock_init(&list_lock);
1294 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);
1295
1296 if (!php_ctlr) { /* allocate controller state data */
1297 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1298 goto abort;
1299 }
1300
1301 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1302
1303 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1304 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1305 /* amd shpc driver doesn't use Base Offset; assume 0 */
1306 ctrl->mmio_base = pci_resource_start(pdev, 0);
1307 ctrl->mmio_size = pci_resource_len(pdev, 0);
1308 } else {
1309 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1310 if (!ctrl->cap_offset) {
1311 err("%s : cap_offset == 0\n", __FUNCTION__);
1312 goto abort_free_ctlr;
1313 }
1314 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1315
1316 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
1317 if (rc) {
1318 err("%s: cannot read base_offset\n", __FUNCTION__);
1319 goto abort_free_ctlr;
1320 }
1321
1322 rc = shpc_indirect_read(ctrl, 3, &tempdword);
1323 if (rc) {
1324 err("%s: cannot read slot config\n", __FUNCTION__);
1325 goto abort_free_ctlr;
1326 }
1327 num_slots = tempdword & SLOT_NUM;
1328 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1329
1330 for (i = 0; i < 9 + num_slots; i++) {
1331 rc = shpc_indirect_read(ctrl, i, &tempdword);
1332 if (rc) {
1333 err("%s: cannot read creg (index = %d)\n",
1334 __FUNCTION__, i);
1335 goto abort_free_ctlr;
1336 }
1337 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1338 tempdword);
1339 }
1340
1341 ctrl->mmio_base =
1342 pci_resource_start(pdev, 0) + shpc_base_offset;
1343 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1344 }
1345
1346 if (first) {
1347 spin_lock_init(&hpc_event_lock);
1348 first = 0;
1349 }
1350
1351 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1352 pdev->subsystem_device);
1353
1354 if (pci_enable_device(pdev))
1355 goto abort_free_ctlr;
1356
1357 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1358 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1359 goto abort_free_ctlr;
1360 }
1361
1362 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1363 if (!php_ctlr->creg) {
1364 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1365 ctrl->mmio_size, ctrl->mmio_base);
1366 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1367 goto abort_free_ctlr;
1368 }
1369 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1370
1371 mutex_init(&ctrl->crit_sect);
1372 mutex_init(&ctrl->cmd_lock);
1373
1374 /* Setup wait queue */
1375 init_waitqueue_head(&ctrl->queue);
1376
1377 /* Find the IRQ */
1378 php_ctlr->irq = pdev->irq;
1379 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1380 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1381 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1382 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1383 php_ctlr->callback_instance_id = instance_id;
1384
1385 ctrl->hpc_ctlr_handle = php_ctlr;
1386 ctrl->hpc_ops = &shpchp_hpc_ops;
1387
1388 /* Return PCI Controller Info */
1389 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1390 php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1391 php_ctlr->num_slots = slot_config & SLOT_NUM;
1392 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1393 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1394
1395 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1396 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1397 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1398 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1399 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1400 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1401 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1402 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1403 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1404
1405 /* Mask the MRL sensor SERR Mask of individual slot in
1406 * Slot SERR-INT Mask & clear all the existing event if any
1407 */
1408 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1409 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1410 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1411 hp_slot, slot_reg);
1412 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1413 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1414 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1415 CON_PFAULT_SERR_MASK);
1416 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1417 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1418 }
1419
1420 if (shpchp_poll_mode) {/* Install interrupt polling code */
1421 /* Install and start the interrupt polling timer */
1422 init_timer(&php_ctlr->int_poll_timer);
1423 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1424 } else {
1425 /* Installs the interrupt handler */
1426 rc = pci_enable_msi(pdev);
1427 if (rc) {
1428 info("Can't get msi for the hotplug controller\n");
1429 info("Use INTx for the hotplug controller\n");
1430 } else
1431 php_ctlr->irq = pdev->irq;
1432
1433 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1434 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1435 if (rc) {
1436 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1437 goto abort_free_ctlr;
1438 }
1439 }
1440 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1441 pdev->bus->number, PCI_SLOT(pdev->devfn),
1442 PCI_FUNC(pdev->devfn), pdev->irq);
1443 get_hp_hw_control_from_firmware(pdev);
1444
1445 /* Add this HPC instance into the HPC list */
1446 spin_lock(&list_lock);
1447 if (php_ctlr_list_head == 0) {
1448 php_ctlr_list_head = php_ctlr;
1449 p = php_ctlr_list_head;
1450 p->pnext = NULL;
1451 } else {
1452 p = php_ctlr_list_head;
1453
1454 while (p->pnext)
1455 p = p->pnext;
1456
1457 p->pnext = php_ctlr;
1458 }
1459 spin_unlock(&list_lock);
1460
1461 ctlr_seq_num++;
1462
1463 /*
1464 * Unmask all event interrupts of all slots
1465 */
1466 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1467 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1468 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1469 hp_slot, slot_reg);
1470 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1471 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1472 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1473 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1474 }
1475 if (!shpchp_poll_mode) {
1476 /* Unmask all general input interrupts and SERR */
1477 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1478 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1479 SERR_INTR_RSVDZ_MASK);
1480 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1481 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1482 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1483 }
1484
1485 DBG_LEAVE_ROUTINE
1486 return 0;
1487
1488 /* We end up here for the many possible ways to fail this API. */
1489 abort_free_ctlr:
1490 kfree(php_ctlr);
1491 abort:
1492 DBG_LEAVE_ROUTINE
1493 return -1;
1494 }
x86 "subsystem" repository