arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm1_44xx.h"
  31 #include "cm2_44xx.h"
  32 #include "prm44xx.h"
  33 #include "prm-regbits-44xx.h"
  34 #include "wd_timer.h"
  35
  36 /* Base offset for all OMAP4 interrupts external to MPUSS */
  37 #define OMAP44XX_IRQ_GIC_START  32
  38
  39 /* Base offset for all OMAP4 dma requests */
  40 #define OMAP44XX_DMA_REQ_START  1
  41
  42 /* Backward references (IPs with Bus Master capability) */
  43 static struct omap_hwmod omap44xx_dma_system_hwmod;
  44 static struct omap_hwmod omap44xx_dmm_hwmod;
  45 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  46 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  47 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  48 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  49 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  50 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  51 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  52 static struct omap_hwmod omap44xx_l4_per_hwmod;
  53 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  54 static struct omap_hwmod omap44xx_mpu_hwmod;
  55 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  56
  57 /*
  58  * Interconnects omap_hwmod structures
  59  * hwmods that compose the global OMAP interconnect
  60  */
  61
  62 /*
  63  * 'dmm' class
  64  * instance(s): dmm
  65  */
  66 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  67         .name = "dmm",
  68 };
  69
  70 /* dmm interface data */
  71 /* l3_main_1 -> dmm */
  72 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  73         .master         = &omap44xx_l3_main_1_hwmod,
  74         .slave          = &omap44xx_dmm_hwmod,
  75         .clk            = "l3_div_ck",
  76         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  77 };
  78
  79 /* mpu -> dmm */
  80 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  81         .master         = &omap44xx_mpu_hwmod,
  82         .slave          = &omap44xx_dmm_hwmod,
  83         .clk            = "l3_div_ck",
  84         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  85 };
  86
  87 /* dmm slave ports */
  88 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
  89         &omap44xx_l3_main_1__dmm,
  90         &omap44xx_mpu__dmm,
  91 };
  92
  93 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  94         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  95 };
  96
  97 static struct omap_hwmod omap44xx_dmm_hwmod = {
  98         .name           = "dmm",
  99         .class          = &omap44xx_dmm_hwmod_class,
 100         .slaves         = omap44xx_dmm_slaves,
 101         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 102         .mpu_irqs       = omap44xx_dmm_irqs,
 103         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 104         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 105 };
 106
 107 /*
 108  * 'emif_fw' class
 109  * instance(s): emif_fw
 110  */
 111 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 112         .name = "emif_fw",
 113 };
 114
 115 /* emif_fw interface data */
 116 /* dmm -> emif_fw */
 117 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 118         .master         = &omap44xx_dmm_hwmod,
 119         .slave          = &omap44xx_emif_fw_hwmod,
 120         .clk            = "l3_div_ck",
 121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 122 };
 123
 124 /* l4_cfg -> emif_fw */
 125 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 126         .master         = &omap44xx_l4_cfg_hwmod,
 127         .slave          = &omap44xx_emif_fw_hwmod,
 128         .clk            = "l4_div_ck",
 129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 130 };
 131
 132 /* emif_fw slave ports */
 133 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 134         &omap44xx_dmm__emif_fw,
 135         &omap44xx_l4_cfg__emif_fw,
 136 };
 137
 138 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 139         .name           = "emif_fw",
 140         .class          = &omap44xx_emif_fw_hwmod_class,
 141         .slaves         = omap44xx_emif_fw_slaves,
 142         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 143         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 144 };
 145
 146 /*
 147  * 'l3' class
 148  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 149  */
 150 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 151         .name = "l3",
 152 };
 153
 154 /* l3_instr interface data */
 155 /* l3_main_3 -> l3_instr */
 156 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 157         .master         = &omap44xx_l3_main_3_hwmod,
 158         .slave          = &omap44xx_l3_instr_hwmod,
 159         .clk            = "l3_div_ck",
 160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 161 };
 162
 163 /* l3_instr slave ports */
 164 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 165         &omap44xx_l3_main_3__l3_instr,
 166 };
 167
 168 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 169         .name           = "l3_instr",
 170         .class          = &omap44xx_l3_hwmod_class,
 171         .slaves         = omap44xx_l3_instr_slaves,
 172         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 173         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 174 };
 175
 176 /* l3_main_2 -> l3_main_1 */
 177 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 178         .master         = &omap44xx_l3_main_2_hwmod,
 179         .slave          = &omap44xx_l3_main_1_hwmod,
 180         .clk            = "l3_div_ck",
 181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 182 };
 183
 184 /* l4_cfg -> l3_main_1 */
 185 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 186         .master         = &omap44xx_l4_cfg_hwmod,
 187         .slave          = &omap44xx_l3_main_1_hwmod,
 188         .clk            = "l4_div_ck",
 189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* mpu -> l3_main_1 */
 193 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 194         .master         = &omap44xx_mpu_hwmod,
 195         .slave          = &omap44xx_l3_main_1_hwmod,
 196         .clk            = "l3_div_ck",
 197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 198 };
 199
 200 /* l3_main_1 slave ports */
 201 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 202         &omap44xx_l3_main_2__l3_main_1,
 203         &omap44xx_l4_cfg__l3_main_1,
 204         &omap44xx_mpu__l3_main_1,
 205 };
 206
 207 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 208         .name           = "l3_main_1",
 209         .class          = &omap44xx_l3_hwmod_class,
 210         .slaves         = omap44xx_l3_main_1_slaves,
 211         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 212         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 213 };
 214
 215 /* l3_main_2 interface data */
 216 /* l3_main_1 -> l3_main_2 */
 217 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 218         .master         = &omap44xx_l3_main_1_hwmod,
 219         .slave          = &omap44xx_l3_main_2_hwmod,
 220         .clk            = "l3_div_ck",
 221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 222 };
 223
 224 /* dma_system -> l3_main_2 */
 225 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 226         .master         = &omap44xx_dma_system_hwmod,
 227         .slave          = &omap44xx_l3_main_2_hwmod,
 228         .clk            = "l3_div_ck",
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* l4_cfg -> l3_main_2 */
 233 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 234         .master         = &omap44xx_l4_cfg_hwmod,
 235         .slave          = &omap44xx_l3_main_2_hwmod,
 236         .clk            = "l4_div_ck",
 237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 238 };
 239
 240 /* l3_main_2 slave ports */
 241 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 242         &omap44xx_dma_system__l3_main_2,
 243         &omap44xx_l3_main_1__l3_main_2,
 244         &omap44xx_l4_cfg__l3_main_2,
 245 };
 246
 247 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 248         .name           = "l3_main_2",
 249         .class          = &omap44xx_l3_hwmod_class,
 250         .slaves         = omap44xx_l3_main_2_slaves,
 251         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 252         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 253 };
 254
 255 /* l3_main_3 interface data */
 256 /* l3_main_1 -> l3_main_3 */
 257 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 258         .master         = &omap44xx_l3_main_1_hwmod,
 259         .slave          = &omap44xx_l3_main_3_hwmod,
 260         .clk            = "l3_div_ck",
 261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 262 };
 263
 264 /* l3_main_2 -> l3_main_3 */
 265 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 266         .master         = &omap44xx_l3_main_2_hwmod,
 267         .slave          = &omap44xx_l3_main_3_hwmod,
 268         .clk            = "l3_div_ck",
 269         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 270 };
 271
 272 /* l4_cfg -> l3_main_3 */
 273 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 274         .master         = &omap44xx_l4_cfg_hwmod,
 275         .slave          = &omap44xx_l3_main_3_hwmod,
 276         .clk            = "l4_div_ck",
 277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 278 };
 279
 280 /* l3_main_3 slave ports */
 281 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 282         &omap44xx_l3_main_1__l3_main_3,
 283         &omap44xx_l3_main_2__l3_main_3,
 284         &omap44xx_l4_cfg__l3_main_3,
 285 };
 286
 287 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 288         .name           = "l3_main_3",
 289         .class          = &omap44xx_l3_hwmod_class,
 290         .slaves         = omap44xx_l3_main_3_slaves,
 291         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 292         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 293 };
 294
 295 /*
 296  * 'l4' class
 297  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 298  */
 299 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 300         .name = "l4",
 301 };
 302
 303 /* l4_abe interface data */
 304 /* l3_main_1 -> l4_abe */
 305 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 306         .master         = &omap44xx_l3_main_1_hwmod,
 307         .slave          = &omap44xx_l4_abe_hwmod,
 308         .clk            = "l3_div_ck",
 309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 310 };
 311
 312 /* mpu -> l4_abe */
 313 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 314         .master         = &omap44xx_mpu_hwmod,
 315         .slave          = &omap44xx_l4_abe_hwmod,
 316         .clk            = "ocp_abe_iclk",
 317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 318 };
 319
 320 /* l4_abe slave ports */
 321 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 322         &omap44xx_l3_main_1__l4_abe,
 323         &omap44xx_mpu__l4_abe,
 324 };
 325
 326 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 327         .name           = "l4_abe",
 328         .class          = &omap44xx_l4_hwmod_class,
 329         .slaves         = omap44xx_l4_abe_slaves,
 330         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 331         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 332 };
 333
 334 /* l4_cfg interface data */
 335 /* l3_main_1 -> l4_cfg */
 336 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 337         .master         = &omap44xx_l3_main_1_hwmod,
 338         .slave          = &omap44xx_l4_cfg_hwmod,
 339         .clk            = "l3_div_ck",
 340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 341 };
 342
 343 /* l4_cfg slave ports */
 344 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 345         &omap44xx_l3_main_1__l4_cfg,
 346 };
 347
 348 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 349         .name           = "l4_cfg",
 350         .class          = &omap44xx_l4_hwmod_class,
 351         .slaves         = omap44xx_l4_cfg_slaves,
 352         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 353         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 354 };
 355
 356 /* l4_per interface data */
 357 /* l3_main_2 -> l4_per */
 358 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 359         .master         = &omap44xx_l3_main_2_hwmod,
 360         .slave          = &omap44xx_l4_per_hwmod,
 361         .clk            = "l3_div_ck",
 362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 363 };
 364
 365 /* l4_per slave ports */
 366 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 367         &omap44xx_l3_main_2__l4_per,
 368 };
 369
 370 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 371         .name           = "l4_per",
 372         .class          = &omap44xx_l4_hwmod_class,
 373         .slaves         = omap44xx_l4_per_slaves,
 374         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 375         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 376 };
 377
 378 /* l4_wkup interface data */
 379 /* l4_cfg -> l4_wkup */
 380 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 381         .master         = &omap44xx_l4_cfg_hwmod,
 382         .slave          = &omap44xx_l4_wkup_hwmod,
 383         .clk            = "l4_div_ck",
 384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 385 };
 386
 387 /* l4_wkup slave ports */
 388 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 389         &omap44xx_l4_cfg__l4_wkup,
 390 };
 391
 392 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 393         .name           = "l4_wkup",
 394         .class          = &omap44xx_l4_hwmod_class,
 395         .slaves         = omap44xx_l4_wkup_slaves,
 396         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 397         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 398 };
 399
 400 /*
 401  * 'i2c' class
 402  * multimaster high-speed i2c controller
 403  */
 404
 405 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
 406         .sysc_offs      = 0x0010,
 407         .syss_offs      = 0x0090,
 408         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 409                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
 410                            SYSC_HAS_AUTOIDLE),
 411         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 412         .sysc_fields    = &omap_hwmod_sysc_type1,
 413 };
 414
 415 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
 416         .name = "i2c",
 417         .sysc = &omap44xx_i2c_sysc,
 418 };
 419
 420 /* i2c1 */
 421 static struct omap_hwmod omap44xx_i2c1_hwmod;
 422 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
 423         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
 424 };
 425
 426 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
 427         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
 428         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
 429 };
 430
 431 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
 432         {
 433                 .pa_start       = 0x48070000,
 434                 .pa_end         = 0x480700ff,
 435                 .flags          = ADDR_TYPE_RT
 436         },
 437 };
 438
 439 /* l4_per -> i2c1 */
 440 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
 441         .master         = &omap44xx_l4_per_hwmod,
 442         .slave          = &omap44xx_i2c1_hwmod,
 443         .clk            = "l4_div_ck",
 444         .addr           = omap44xx_i2c1_addrs,
 445         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
 446         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 447 };
 448
 449 /* i2c1 slave ports */
 450 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
 451         &omap44xx_l4_per__i2c1,
 452 };
 453
 454 static struct omap_hwmod omap44xx_i2c1_hwmod = {
 455         .name           = "i2c1",
 456         .class          = &omap44xx_i2c_hwmod_class,
 457         .flags          = HWMOD_INIT_NO_RESET,
 458         .mpu_irqs       = omap44xx_i2c1_irqs,
 459         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
 460         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
 461         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
 462         .main_clk       = "i2c1_fck",
 463         .prcm = {
 464                 .omap4 = {
 465                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
 466                 },
 467         },
 468         .slaves         = omap44xx_i2c1_slaves,
 469         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
 470         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 471 };
 472
 473 /* i2c2 */
 474 static struct omap_hwmod omap44xx_i2c2_hwmod;
 475 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
 476         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
 477 };
 478
 479 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
 480         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
 481         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
 482 };
 483
 484 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
 485         {
 486                 .pa_start       = 0x48072000,
 487                 .pa_end         = 0x480720ff,
 488                 .flags          = ADDR_TYPE_RT
 489         },
 490 };
 491
 492 /* l4_per -> i2c2 */
 493 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
 494         .master         = &omap44xx_l4_per_hwmod,
 495         .slave          = &omap44xx_i2c2_hwmod,
 496         .clk            = "l4_div_ck",
 497         .addr           = omap44xx_i2c2_addrs,
 498         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
 499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 500 };
 501
 502 /* i2c2 slave ports */
 503 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
 504         &omap44xx_l4_per__i2c2,
 505 };
 506
 507 static struct omap_hwmod omap44xx_i2c2_hwmod = {
 508         .name           = "i2c2",
 509         .class          = &omap44xx_i2c_hwmod_class,
 510         .flags          = HWMOD_INIT_NO_RESET,
 511         .mpu_irqs       = omap44xx_i2c2_irqs,
 512         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
 513         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
 514         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
 515         .main_clk       = "i2c2_fck",
 516         .prcm = {
 517                 .omap4 = {
 518                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
 519                 },
 520         },
 521         .slaves         = omap44xx_i2c2_slaves,
 522         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
 523         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 524 };
 525
 526 /* i2c3 */
 527 static struct omap_hwmod omap44xx_i2c3_hwmod;
 528 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
 529         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
 530 };
 531
 532 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
 533         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
 534         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
 535 };
 536
 537 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
 538         {
 539                 .pa_start       = 0x48060000,
 540                 .pa_end         = 0x480600ff,
 541                 .flags          = ADDR_TYPE_RT
 542         },
 543 };
 544
 545 /* l4_per -> i2c3 */
 546 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
 547         .master         = &omap44xx_l4_per_hwmod,
 548         .slave          = &omap44xx_i2c3_hwmod,
 549         .clk            = "l4_div_ck",
 550         .addr           = omap44xx_i2c3_addrs,
 551         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
 552         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 553 };
 554
 555 /* i2c3 slave ports */
 556 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
 557         &omap44xx_l4_per__i2c3,
 558 };
 559
 560 static struct omap_hwmod omap44xx_i2c3_hwmod = {
 561         .name           = "i2c3",
 562         .class          = &omap44xx_i2c_hwmod_class,
 563         .flags          = HWMOD_INIT_NO_RESET,
 564         .mpu_irqs       = omap44xx_i2c3_irqs,
 565         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
 566         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
 567         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
 568         .main_clk       = "i2c3_fck",
 569         .prcm = {
 570                 .omap4 = {
 571                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
 572                 },
 573         },
 574         .slaves         = omap44xx_i2c3_slaves,
 575         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
 576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 577 };
 578
 579 /* i2c4 */
 580 static struct omap_hwmod omap44xx_i2c4_hwmod;
 581 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
 582         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
 583 };
 584
 585 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
 586         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
 587         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
 588 };
 589
 590 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
 591         {
 592                 .pa_start       = 0x48350000,
 593                 .pa_end         = 0x483500ff,
 594                 .flags          = ADDR_TYPE_RT
 595         },
 596 };
 597
 598 /* l4_per -> i2c4 */
 599 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
 600         .master         = &omap44xx_l4_per_hwmod,
 601         .slave          = &omap44xx_i2c4_hwmod,
 602         .clk            = "l4_div_ck",
 603         .addr           = omap44xx_i2c4_addrs,
 604         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
 605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 606 };
 607
 608 /* i2c4 slave ports */
 609 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
 610         &omap44xx_l4_per__i2c4,
 611 };
 612
 613 static struct omap_hwmod omap44xx_i2c4_hwmod = {
 614         .name           = "i2c4",
 615         .class          = &omap44xx_i2c_hwmod_class,
 616         .flags          = HWMOD_INIT_NO_RESET,
 617         .mpu_irqs       = omap44xx_i2c4_irqs,
 618         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
 619         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
 620         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
 621         .main_clk       = "i2c4_fck",
 622         .prcm = {
 623                 .omap4 = {
 624                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
 625                 },
 626         },
 627         .slaves         = omap44xx_i2c4_slaves,
 628         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
 629         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 630 };
 631
 632 /*
 633  * 'mpu_bus' class
 634  * instance(s): mpu_private
 635  */
 636 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 637         .name = "mpu_bus",
 638 };
 639
 640 /* mpu_private interface data */
 641 /* mpu -> mpu_private */
 642 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 643         .master         = &omap44xx_mpu_hwmod,
 644         .slave          = &omap44xx_mpu_private_hwmod,
 645         .clk            = "l3_div_ck",
 646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 647 };
 648
 649 /* mpu_private slave ports */
 650 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 651         &omap44xx_mpu__mpu_private,
 652 };
 653
 654 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 655         .name           = "mpu_private",
 656         .class          = &omap44xx_mpu_bus_hwmod_class,
 657         .slaves         = omap44xx_mpu_private_slaves,
 658         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 660 };
 661
 662 /*
 663  * 'mpu' class
 664  * mpu sub-system
 665  */
 666
 667 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 668         .name = "mpu",
 669 };
 670
 671 /* mpu */
 672 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
 673         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
 674         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
 675         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
 676 };
 677
 678 /* mpu master ports */
 679 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
 680         &omap44xx_mpu__l3_main_1,
 681         &omap44xx_mpu__l4_abe,
 682         &omap44xx_mpu__dmm,
 683 };
 684
 685 static struct omap_hwmod omap44xx_mpu_hwmod = {
 686         .name           = "mpu",
 687         .class          = &omap44xx_mpu_hwmod_class,
 688         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 689         .mpu_irqs       = omap44xx_mpu_irqs,
 690         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
 691         .main_clk       = "dpll_mpu_m2_ck",
 692         .prcm = {
 693                 .omap4 = {
 694                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
 695                 },
 696         },
 697         .masters        = omap44xx_mpu_masters,
 698         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
 699         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 700 };
 701
 702 /*
 703  * 'wd_timer' class
 704  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 705  * overflow condition
 706  */
 707
 708 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
 709         .rev_offs       = 0x0000,
 710         .sysc_offs      = 0x0010,
 711         .syss_offs      = 0x0014,
 712         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 713                            SYSC_HAS_SOFTRESET),
 714         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 715         .sysc_fields    = &omap_hwmod_sysc_type1,
 716 };
 717
 718 /*
 719  * 'uart' class
 720  * universal asynchronous receiver/transmitter (uart)
 721  */
 722
 723 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
 724         .rev_offs       = 0x0050,
 725         .sysc_offs      = 0x0054,
 726         .syss_offs      = 0x0058,
 727         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 728                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 729         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 730         .sysc_fields    = &omap_hwmod_sysc_type1,
 731 };
 732
 733 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 734         .name           = "wd_timer",
 735         .sysc           = &omap44xx_wd_timer_sysc,
 736         .pre_shutdown   = &omap2_wd_timer_disable
 737 };
 738
 739 /* wd_timer2 */
 740 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
 741 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
 742         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
 743 };
 744
 745 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
 746         {
 747                 .pa_start       = 0x4a314000,
 748                 .pa_end         = 0x4a31407f,
 749                 .flags          = ADDR_TYPE_RT
 750         },
 751 };
 752
 753 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 754         .name = "uart",
 755         .sysc = &omap44xx_uart_sysc,
 756 };
 757
 758 /* uart1 */
 759 static struct omap_hwmod omap44xx_uart1_hwmod;
 760 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
 761         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
 762 };
 763
 764 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
 765         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
 766         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
 767 };
 768
 769 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
 770         {
 771                 .pa_start       = 0x4806a000,
 772                 .pa_end         = 0x4806a0ff,
 773                 .flags          = ADDR_TYPE_RT
 774         },
 775 };
 776
 777 /* l4_per -> uart1 */
 778 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
 779         .master         = &omap44xx_l4_per_hwmod,
 780         .slave          = &omap44xx_uart1_hwmod,
 781         .clk            = "l4_div_ck",
 782         .addr           = omap44xx_uart1_addrs,
 783         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
 784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 785 };
 786
 787 /* uart1 slave ports */
 788 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
 789         &omap44xx_l4_per__uart1,
 790 };
 791
 792 static struct omap_hwmod omap44xx_uart1_hwmod = {
 793         .name           = "uart1",
 794         .class          = &omap44xx_uart_hwmod_class,
 795         .mpu_irqs       = omap44xx_uart1_irqs,
 796         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
 797         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
 798         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
 799         .main_clk       = "uart1_fck",
 800         .prcm = {
 801                 .omap4 = {
 802                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
 803                 },
 804         },
 805         .slaves         = omap44xx_uart1_slaves,
 806         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
 807         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 808 };
 809
 810 /* uart2 */
 811 static struct omap_hwmod omap44xx_uart2_hwmod;
 812 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
 813         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
 814 };
 815
 816 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
 817         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
 818         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
 819 };
 820
 821 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
 822         {
 823                 .pa_start       = 0x4806c000,
 824                 .pa_end         = 0x4806c0ff,
 825                 .flags          = ADDR_TYPE_RT
 826         },
 827 };
 828
 829 /* l4_wkup -> wd_timer2 */
 830 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
 831         .master         = &omap44xx_l4_wkup_hwmod,
 832         .slave          = &omap44xx_wd_timer2_hwmod,
 833         .clk            = "l4_wkup_clk_mux_ck",
 834         .addr           = omap44xx_wd_timer2_addrs,
 835         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
 836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 837 };
 838
 839 /* wd_timer2 slave ports */
 840 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
 841         &omap44xx_l4_wkup__wd_timer2,
 842 };
 843
 844 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 845         .name           = "wd_timer2",
 846         .class          = &omap44xx_wd_timer_hwmod_class,
 847         .mpu_irqs       = omap44xx_wd_timer2_irqs,
 848         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
 849         .main_clk       = "wd_timer2_fck",
 850         .prcm = {
 851                 .omap4 = {
 852                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
 853                 },
 854         },
 855         .slaves         = omap44xx_wd_timer2_slaves,
 856         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
 857         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 858 };
 859
 860 /* wd_timer3 */
 861 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
 862 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
 863         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
 864 };
 865
 866 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
 867         {
 868                 .pa_start       = 0x40130000,
 869                 .pa_end         = 0x4013007f,
 870                 .flags          = ADDR_TYPE_RT
 871         },
 872 };
 873
 874 /* l4_per -> uart2 */
 875 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
 876         .master         = &omap44xx_l4_per_hwmod,
 877         .slave          = &omap44xx_uart2_hwmod,
 878         .clk            = "l4_div_ck",
 879         .addr           = omap44xx_uart2_addrs,
 880         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
 881         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 882 };
 883
 884 /* uart2 slave ports */
 885 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
 886         &omap44xx_l4_per__uart2,
 887 };
 888
 889 static struct omap_hwmod omap44xx_uart2_hwmod = {
 890         .name           = "uart2",
 891         .class          = &omap44xx_uart_hwmod_class,
 892         .mpu_irqs       = omap44xx_uart2_irqs,
 893         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
 894         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
 895         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
 896         .main_clk       = "uart2_fck",
 897         .prcm = {
 898                 .omap4 = {
 899                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
 900                 },
 901         },
 902         .slaves         = omap44xx_uart2_slaves,
 903         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
 904         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 905 };
 906
 907 /* uart3 */
 908 static struct omap_hwmod omap44xx_uart3_hwmod;
 909 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
 910         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
 911 };
 912
 913 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
 914         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
 915         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
 916 };
 917
 918 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
 919         {
 920                 .pa_start       = 0x48020000,
 921                 .pa_end         = 0x480200ff,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924 };
 925
 926 /* l4_abe -> wd_timer3 */
 927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
 928         .master         = &omap44xx_l4_abe_hwmod,
 929         .slave          = &omap44xx_wd_timer3_hwmod,
 930         .clk            = "ocp_abe_iclk",
 931         .addr           = omap44xx_wd_timer3_addrs,
 932         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
 933         .user           = OCP_USER_MPU,
 934 };
 935
 936 /* l4_abe -> wd_timer3 (dma) */
 937 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
 938         {
 939                 .pa_start       = 0x49030000,
 940                 .pa_end         = 0x4903007f,
 941                 .flags          = ADDR_TYPE_RT
 942         },
 943 };
 944
 945 /* l4_per -> uart3 */
 946 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
 947         .master         = &omap44xx_l4_per_hwmod,
 948         .slave          = &omap44xx_uart3_hwmod,
 949         .clk            = "l4_div_ck",
 950         .addr           = omap44xx_uart3_addrs,
 951         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
 952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 953 };
 954
 955 /* uart3 slave ports */
 956 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
 957         &omap44xx_l4_per__uart3,
 958 };
 959
 960 static struct omap_hwmod omap44xx_uart3_hwmod = {
 961         .name           = "uart3",
 962         .class          = &omap44xx_uart_hwmod_class,
 963         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 964         .mpu_irqs       = omap44xx_uart3_irqs,
 965         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
 966         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
 967         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
 968         .main_clk       = "uart3_fck",
 969         .prcm = {
 970                 .omap4 = {
 971                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
 972                 },
 973         },
 974         .slaves         = omap44xx_uart3_slaves,
 975         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
 976         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 977 };
 978
 979 /* uart4 */
 980 static struct omap_hwmod omap44xx_uart4_hwmod;
 981 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
 982         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
 983 };
 984
 985 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
 986         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
 987         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
 988 };
 989
 990 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
 991         {
 992                 .pa_start       = 0x4806e000,
 993                 .pa_end         = 0x4806e0ff,
 994                 .flags          = ADDR_TYPE_RT
 995         },
 996 };
 997
 998 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
 999         .master         = &omap44xx_l4_abe_hwmod,
1000         .slave          = &omap44xx_wd_timer3_hwmod,
1001         .clk            = "ocp_abe_iclk",
1002         .addr           = omap44xx_wd_timer3_dma_addrs,
1003         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1004         .user           = OCP_USER_SDMA,
1005 };
1006
1007 /* wd_timer3 slave ports */
1008 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1009         &omap44xx_l4_abe__wd_timer3,
1010         &omap44xx_l4_abe__wd_timer3_dma,
1011 };
1012
1013 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1014         .name           = "wd_timer3",
1015         .class          = &omap44xx_wd_timer_hwmod_class,
1016         .mpu_irqs       = omap44xx_wd_timer3_irqs,
1017         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1018         .main_clk       = "wd_timer3_fck",
1019         .prcm = {
1020                 .omap4 = {
1021                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1022                 },
1023         },
1024         .slaves         = omap44xx_wd_timer3_slaves,
1025         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1026         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1027 };
1028
1029 /* l4_per -> uart4 */
1030 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1031         .master         = &omap44xx_l4_per_hwmod,
1032         .slave          = &omap44xx_uart4_hwmod,
1033         .clk            = "l4_div_ck",
1034         .addr           = omap44xx_uart4_addrs,
1035         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
1036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1037 };
1038
1039 /* uart4 slave ports */
1040 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1041         &omap44xx_l4_per__uart4,
1042 };
1043
1044 static struct omap_hwmod omap44xx_uart4_hwmod = {
1045         .name           = "uart4",
1046         .class          = &omap44xx_uart_hwmod_class,
1047         .mpu_irqs       = omap44xx_uart4_irqs,
1048         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
1049         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
1050         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1051         .main_clk       = "uart4_fck",
1052         .prcm = {
1053                 .omap4 = {
1054                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1055                 },
1056         },
1057         .slaves         = omap44xx_uart4_slaves,
1058         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
1059         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1060 };
1061
1062 /*
1063  * 'gpio' class
1064  * general purpose io module
1065  */
1066
1067 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1068         .rev_offs       = 0x0000,
1069         .sysc_offs      = 0x0010,
1070         .syss_offs      = 0x0114,
1071         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1072                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1073         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1074         .sysc_fields    = &omap_hwmod_sysc_type1,
1075 };
1076
1077 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1078         .name = "gpio",
1079         .sysc = &omap44xx_gpio_sysc,
1080         .rev = 2,
1081 };
1082
1083 /* gpio dev_attr */
1084 static struct omap_gpio_dev_attr gpio_dev_attr = {
1085         .bank_width = 32,
1086         .dbck_flag = true,
1087 };
1088
1089 /* gpio1 */
1090 static struct omap_hwmod omap44xx_gpio1_hwmod;
1091 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1092         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1093 };
1094
1095 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1096         {
1097                 .pa_start       = 0x4a310000,
1098                 .pa_end         = 0x4a3101ff,
1099                 .flags          = ADDR_TYPE_RT
1100         },
1101 };
1102
1103 /* l4_wkup -> gpio1 */
1104 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1105         .master         = &omap44xx_l4_wkup_hwmod,
1106         .slave          = &omap44xx_gpio1_hwmod,
1107         .addr           = omap44xx_gpio1_addrs,
1108         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1110 };
1111
1112 /* gpio1 slave ports */
1113 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1114         &omap44xx_l4_wkup__gpio1,
1115 };
1116
1117 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1118         { .role = "dbclk", .clk = "sys_32k_ck" },
1119 };
1120
1121 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1122         .name           = "gpio1",
1123         .class          = &omap44xx_gpio_hwmod_class,
1124         .mpu_irqs       = omap44xx_gpio1_irqs,
1125         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1126         .main_clk       = "gpio1_ick",
1127         .prcm = {
1128                 .omap4 = {
1129                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1130                 },
1131         },
1132         .opt_clks       = gpio1_opt_clks,
1133         .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1134         .dev_attr       = &gpio_dev_attr,
1135         .slaves         = omap44xx_gpio1_slaves,
1136         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1137         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1138 };
1139
1140 /* gpio2 */
1141 static struct omap_hwmod omap44xx_gpio2_hwmod;
1142 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1143         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1144 };
1145
1146 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1147         {
1148                 .pa_start       = 0x48055000,
1149                 .pa_end         = 0x480551ff,
1150                 .flags          = ADDR_TYPE_RT
1151         },
1152 };
1153
1154 /* l4_per -> gpio2 */
1155 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1156         .master         = &omap44xx_l4_per_hwmod,
1157         .slave          = &omap44xx_gpio2_hwmod,
1158         .addr           = omap44xx_gpio2_addrs,
1159         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1161 };
1162
1163 /* gpio2 slave ports */
1164 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1165         &omap44xx_l4_per__gpio2,
1166 };
1167
1168 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1169         { .role = "dbclk", .clk = "sys_32k_ck" },
1170 };
1171
1172 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1173         .name           = "gpio2",
1174         .class          = &omap44xx_gpio_hwmod_class,
1175         .mpu_irqs       = omap44xx_gpio2_irqs,
1176         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1177         .main_clk       = "gpio2_ick",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1181                 },
1182         },
1183         .opt_clks       = gpio2_opt_clks,
1184         .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1185         .dev_attr       = &gpio_dev_attr,
1186         .slaves         = omap44xx_gpio2_slaves,
1187         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1188         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1189 };
1190
1191 /* gpio3 */
1192 static struct omap_hwmod omap44xx_gpio3_hwmod;
1193 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1194         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1195 };
1196
1197 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1198         {
1199                 .pa_start       = 0x48057000,
1200                 .pa_end         = 0x480571ff,
1201                 .flags          = ADDR_TYPE_RT
1202         },
1203 };
1204
1205 /* l4_per -> gpio3 */
1206 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1207         .master         = &omap44xx_l4_per_hwmod,
1208         .slave          = &omap44xx_gpio3_hwmod,
1209         .addr           = omap44xx_gpio3_addrs,
1210         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1212 };
1213
1214 /* gpio3 slave ports */
1215 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1216         &omap44xx_l4_per__gpio3,
1217 };
1218
1219 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1220         { .role = "dbclk", .clk = "sys_32k_ck" },
1221 };
1222
1223 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1224         .name           = "gpio3",
1225         .class          = &omap44xx_gpio_hwmod_class,
1226         .mpu_irqs       = omap44xx_gpio3_irqs,
1227         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1228         .main_clk       = "gpio3_ick",
1229         .prcm = {
1230                 .omap4 = {
1231                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1232                 },
1233         },
1234         .opt_clks       = gpio3_opt_clks,
1235         .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1236         .dev_attr       = &gpio_dev_attr,
1237         .slaves         = omap44xx_gpio3_slaves,
1238         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1239         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1240 };
1241
1242 /* gpio4 */
1243 static struct omap_hwmod omap44xx_gpio4_hwmod;
1244 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1245         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1246 };
1247
1248 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1249         {
1250                 .pa_start       = 0x48059000,
1251                 .pa_end         = 0x480591ff,
1252                 .flags          = ADDR_TYPE_RT
1253         },
1254 };
1255
1256 /* l4_per -> gpio4 */
1257 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1258         .master         = &omap44xx_l4_per_hwmod,
1259         .slave          = &omap44xx_gpio4_hwmod,
1260         .addr           = omap44xx_gpio4_addrs,
1261         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1263 };
1264
1265 /* gpio4 slave ports */
1266 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1267         &omap44xx_l4_per__gpio4,
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1271         { .role = "dbclk", .clk = "sys_32k_ck" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1275         .name           = "gpio4",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .mpu_irqs       = omap44xx_gpio4_irqs,
1278         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1279         .main_clk       = "gpio4_ick",
1280         .prcm = {
1281                 .omap4 = {
1282                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1283                 },
1284         },
1285         .opt_clks       = gpio4_opt_clks,
1286         .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1287         .dev_attr       = &gpio_dev_attr,
1288         .slaves         = omap44xx_gpio4_slaves,
1289         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1290         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1291 };
1292
1293 /* gpio5 */
1294 static struct omap_hwmod omap44xx_gpio5_hwmod;
1295 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1296         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1297 };
1298
1299 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1300         {
1301                 .pa_start       = 0x4805b000,
1302                 .pa_end         = 0x4805b1ff,
1303                 .flags          = ADDR_TYPE_RT
1304         },
1305 };
1306
1307 /* l4_per -> gpio5 */
1308 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1309         .master         = &omap44xx_l4_per_hwmod,
1310         .slave          = &omap44xx_gpio5_hwmod,
1311         .addr           = omap44xx_gpio5_addrs,
1312         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1314 };
1315
1316 /* gpio5 slave ports */
1317 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1318         &omap44xx_l4_per__gpio5,
1319 };
1320
1321 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1322         { .role = "dbclk", .clk = "sys_32k_ck" },
1323 };
1324
1325 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1326         .name           = "gpio5",
1327         .class          = &omap44xx_gpio_hwmod_class,
1328         .mpu_irqs       = omap44xx_gpio5_irqs,
1329         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1330         .main_clk       = "gpio5_ick",
1331         .prcm = {
1332                 .omap4 = {
1333                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1334                 },
1335         },
1336         .opt_clks       = gpio5_opt_clks,
1337         .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1338         .dev_attr       = &gpio_dev_attr,
1339         .slaves         = omap44xx_gpio5_slaves,
1340         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1341         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1342 };
1343
1344 /* gpio6 */
1345 static struct omap_hwmod omap44xx_gpio6_hwmod;
1346 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1347         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1348 };
1349
1350 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1351         {
1352                 .pa_start       = 0x4805d000,
1353                 .pa_end         = 0x4805d1ff,
1354                 .flags          = ADDR_TYPE_RT
1355         },
1356 };
1357
1358 /* l4_per -> gpio6 */
1359 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1360         .master         = &omap44xx_l4_per_hwmod,
1361         .slave          = &omap44xx_gpio6_hwmod,
1362         .addr           = omap44xx_gpio6_addrs,
1363         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1365 };
1366
1367 /* gpio6 slave ports */
1368 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1369         &omap44xx_l4_per__gpio6,
1370 };
1371
1372 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1373         { .role = "dbclk", .clk = "sys_32k_ck" },
1374 };
1375
1376 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1377         .name           = "gpio6",
1378         .class          = &omap44xx_gpio_hwmod_class,
1379         .mpu_irqs       = omap44xx_gpio6_irqs,
1380         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1381         .main_clk       = "gpio6_ick",
1382         .prcm = {
1383                 .omap4 = {
1384                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1385                 },
1386         },
1387         .opt_clks       = gpio6_opt_clks,
1388         .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1389         .dev_attr       = &gpio_dev_attr,
1390         .slaves         = omap44xx_gpio6_slaves,
1391         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1392         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1393 };
1394
1395 /*
1396  * 'dma' class
1397  * dma controller for data exchange between memory to memory (i.e. internal or
1398  * external memory) and gp peripherals to memory or memory to gp peripherals
1399  */
1400
1401 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
1402         .rev_offs       = 0x0000,
1403         .sysc_offs      = 0x002c,
1404         .syss_offs      = 0x0028,
1405         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1406                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1407                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1408                            SYSS_HAS_RESET_STATUS),
1409         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1410                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1411         .sysc_fields    = &omap_hwmod_sysc_type1,
1412 };
1413
1414 /* dma attributes */
1415 static struct omap_dma_dev_attr dma_dev_attr = {
1416         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1417                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1418         .lch_count = 32,
1419 };
1420
1421 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
1422         .name   = "dma",
1423         .sysc   = &omap44xx_dma_sysc,
1424 };
1425
1426 /* dma_system */
1427 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
1428         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
1429         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
1430         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
1431         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
1432 };
1433
1434 /* dma_system master ports */
1435 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
1436         &omap44xx_dma_system__l3_main_2,
1437 };
1438
1439 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
1440         {
1441                 .pa_start       = 0x4a056000,
1442                 .pa_end         = 0x4a0560ff,
1443                 .flags          = ADDR_TYPE_RT
1444         },
1445 };
1446
1447 /* l4_cfg -> dma_system */
1448 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
1449         .master         = &omap44xx_l4_cfg_hwmod,
1450         .slave          = &omap44xx_dma_system_hwmod,
1451         .clk            = "l4_div_ck",
1452         .addr           = omap44xx_dma_system_addrs,
1453         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
1454         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1455 };
1456
1457 /* dma_system slave ports */
1458 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
1459         &omap44xx_l4_cfg__dma_system,
1460 };
1461
1462 static struct omap_hwmod omap44xx_dma_system_hwmod = {
1463         .name           = "dma_system",
1464         .class          = &omap44xx_dma_hwmod_class,
1465         .mpu_irqs       = omap44xx_dma_system_irqs,
1466         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
1467         .main_clk       = "l3_div_ck",
1468         .prcm = {
1469                 .omap4 = {
1470                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
1471                 },
1472         },
1473         .slaves         = omap44xx_dma_system_slaves,
1474         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
1475         .masters        = omap44xx_dma_system_masters,
1476         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
1477         .dev_attr       = &dma_dev_attr,
1478         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1479 };
1480
1481 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1482         /* dmm class */
1483         &omap44xx_dmm_hwmod,
1484         /* emif_fw class */
1485         &omap44xx_emif_fw_hwmod,
1486         /* l3 class */
1487         &omap44xx_l3_instr_hwmod,
1488         &omap44xx_l3_main_1_hwmod,
1489         &omap44xx_l3_main_2_hwmod,
1490         &omap44xx_l3_main_3_hwmod,
1491         /* l4 class */
1492         &omap44xx_l4_abe_hwmod,
1493         &omap44xx_l4_cfg_hwmod,
1494         &omap44xx_l4_per_hwmod,
1495         &omap44xx_l4_wkup_hwmod,
1496
1497         /* dma class */
1498         &omap44xx_dma_system_hwmod,
1499
1500         /* i2c class */
1501         &omap44xx_i2c1_hwmod,
1502         &omap44xx_i2c2_hwmod,
1503         &omap44xx_i2c3_hwmod,
1504         &omap44xx_i2c4_hwmod,
1505         /* mpu_bus class */
1506         &omap44xx_mpu_private_hwmod,
1507
1508         /* gpio class */
1509         &omap44xx_gpio1_hwmod,
1510         &omap44xx_gpio2_hwmod,
1511         &omap44xx_gpio3_hwmod,
1512         &omap44xx_gpio4_hwmod,
1513         &omap44xx_gpio5_hwmod,
1514         &omap44xx_gpio6_hwmod,
1515
1516         /* mpu class */
1517         &omap44xx_mpu_hwmod,
1518         /* wd_timer class */
1519         &omap44xx_wd_timer2_hwmod,
1520         &omap44xx_wd_timer3_hwmod,
1521
1522         /* uart class */
1523         &omap44xx_uart1_hwmod,
1524         &omap44xx_uart2_hwmod,
1525         &omap44xx_uart3_hwmod,
1526         &omap44xx_uart4_hwmod,
1527         NULL,
1528 };
1529
1530 int __init omap44xx_hwmod_init(void)
1531 {
1532         return omap_hwmod_init(omap44xx_hwmods);
1533 }
1534