arch/arm/mach-omap2/clockdomains44xx_data.c

   1 /*
   2  * OMAP4 Clock domains framework
   3  *
   4  * Copyright (C) 2009 Texas Instruments, Inc.
   5  * Copyright (C) 2009 Nokia Corporation
   6  *
   7  * Abhijit Pagare (abhijitpagare@ti.com)
   8  * Benoit Cousson (b-cousson@ti.com)
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 /*
  22  * To-Do List
  23  * -> Populate the Sleep/Wakeup dependencies for the domains
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/io.h>
  28
  29 #include <plat/clockdomain.h>
  30
  31 #include "cm1_44xx.h"
  32 #include "cm2_44xx.h"
  33 #include "cm-regbits-44xx.h"
  34 #include "prm44xx.h"
  35 #include "prcm_mpu44xx.h"
  36
  37
  38 static struct clockdomain l4_cefuse_44xx_clkdm = {
  39         .name             = "l4_cefuse_clkdm",
  40         .pwrdm            = { .name = "cefuse_pwrdm" },
  41         .clkstctrl_reg    = OMAP4430_CM_CEFUSE_CLKSTCTRL,
  42         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
  43         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
  44         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  45 };
  46
  47 static struct clockdomain l4_cfg_44xx_clkdm = {
  48         .name             = "l4_cfg_clkdm",
  49         .pwrdm            = { .name = "core_pwrdm" },
  50         .clkstctrl_reg    = OMAP4430_CM_L4CFG_CLKSTCTRL,
  51         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
  52         .flags            = CLKDM_CAN_HWSUP,
  53         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  54 };
  55
  56 static struct clockdomain tesla_44xx_clkdm = {
  57         .name             = "tesla_clkdm",
  58         .pwrdm            = { .name = "tesla_pwrdm" },
  59         .clkstctrl_reg    = OMAP4430_CM_TESLA_CLKSTCTRL,
  60         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
  61         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  62         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  63 };
  64
  65 static struct clockdomain l3_gfx_44xx_clkdm = {
  66         .name             = "l3_gfx_clkdm",
  67         .pwrdm            = { .name = "gfx_pwrdm" },
  68         .clkstctrl_reg    = OMAP4430_CM_GFX_CLKSTCTRL,
  69         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
  70         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  71         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  72 };
  73
  74 static struct clockdomain ivahd_44xx_clkdm = {
  75         .name             = "ivahd_clkdm",
  76         .pwrdm            = { .name = "ivahd_pwrdm" },
  77         .clkstctrl_reg    = OMAP4430_CM_IVAHD_CLKSTCTRL,
  78         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
  79         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  80         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  81 };
  82
  83 static struct clockdomain l4_secure_44xx_clkdm = {
  84         .name             = "l4_secure_clkdm",
  85         .pwrdm            = { .name = "l4per_pwrdm" },
  86         .clkstctrl_reg    = OMAP4430_CM_L4SEC_CLKSTCTRL,
  87         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
  88         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  89         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  90 };
  91
  92 static struct clockdomain l4_per_44xx_clkdm = {
  93         .name             = "l4_per_clkdm",
  94         .pwrdm            = { .name = "l4per_pwrdm" },
  95         .clkstctrl_reg    = OMAP4430_CM_L4PER_CLKSTCTRL,
  96         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
  97         .flags            = CLKDM_CAN_HWSUP_SWSUP,
  98         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  99 };
 100
 101 static struct clockdomain abe_44xx_clkdm = {
 102         .name             = "abe_clkdm",
 103         .pwrdm            = { .name = "abe_pwrdm" },
 104         .clkstctrl_reg    = OMAP4430_CM1_ABE_CLKSTCTRL,
 105         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 106         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 107         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 108 };
 109
 110 static struct clockdomain l3_instr_44xx_clkdm = {
 111         .name             = "l3_instr_clkdm",
 112         .pwrdm            = { .name = "core_pwrdm" },
 113         .clkstctrl_reg    = OMAP4430_CM_L3INSTR_CLKSTCTRL,
 114         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 115         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 116 };
 117
 118 static struct clockdomain l3_init_44xx_clkdm = {
 119         .name             = "l3_init_clkdm",
 120         .pwrdm            = { .name = "l3init_pwrdm" },
 121         .clkstctrl_reg    = OMAP4430_CM_L3INIT_CLKSTCTRL,
 122         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 123         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 124         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 125 };
 126
 127 static struct clockdomain mpuss_44xx_clkdm = {
 128         .name             = "mpuss_clkdm",
 129         .pwrdm            = { .name = "mpu_pwrdm" },
 130         .clkstctrl_reg    = OMAP4430_CM_MPU_CLKSTCTRL,
 131         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 132         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 133         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 134 };
 135
 136 static struct clockdomain mpu0_44xx_clkdm = {
 137         .name             = "mpu0_clkdm",
 138         .pwrdm            = { .name = "cpu0_pwrdm" },
 139         .clkstctrl_reg    = OMAP4430_CM_CPU0_CLKSTCTRL,
 140         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 141         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 142         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 143 };
 144
 145 static struct clockdomain mpu1_44xx_clkdm = {
 146         .name             = "mpu1_clkdm",
 147         .pwrdm            = { .name = "cpu1_pwrdm" },
 148         .clkstctrl_reg    = OMAP4430_CM_CPU1_CLKSTCTRL,
 149         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 150         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 151         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 152 };
 153
 154 static struct clockdomain l3_emif_44xx_clkdm = {
 155         .name             = "l3_emif_clkdm",
 156         .pwrdm            = { .name = "core_pwrdm" },
 157         .clkstctrl_reg    = OMAP4430_CM_MEMIF_CLKSTCTRL,
 158         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 159         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 160         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 161 };
 162
 163 static struct clockdomain l4_ao_44xx_clkdm = {
 164         .name             = "l4_ao_clkdm",
 165         .pwrdm            = { .name = "always_on_core_pwrdm" },
 166         .clkstctrl_reg    = OMAP4430_CM_ALWON_CLKSTCTRL,
 167         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 168         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 169         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 170 };
 171
 172 static struct clockdomain ducati_44xx_clkdm = {
 173         .name             = "ducati_clkdm",
 174         .pwrdm            = { .name = "core_pwrdm" },
 175         .clkstctrl_reg    = OMAP4430_CM_DUCATI_CLKSTCTRL,
 176         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 177         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 178         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 179 };
 180
 181 static struct clockdomain l3_2_44xx_clkdm = {
 182         .name             = "l3_2_clkdm",
 183         .pwrdm            = { .name = "core_pwrdm" },
 184         .clkstctrl_reg    = OMAP4430_CM_L3_2_CLKSTCTRL,
 185         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 186         .flags            = CLKDM_CAN_HWSUP,
 187         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 188 };
 189
 190 static struct clockdomain l3_1_44xx_clkdm = {
 191         .name             = "l3_1_clkdm",
 192         .pwrdm            = { .name = "core_pwrdm" },
 193         .clkstctrl_reg    = OMAP4430_CM_L3_1_CLKSTCTRL,
 194         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 195         .flags            = CLKDM_CAN_HWSUP,
 196         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 197 };
 198
 199 static struct clockdomain l3_d2d_44xx_clkdm = {
 200         .name             = "l3_d2d_clkdm",
 201         .pwrdm            = { .name = "core_pwrdm" },
 202         .clkstctrl_reg    = OMAP4430_CM_D2D_CLKSTCTRL,
 203         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 204         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 205         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 206 };
 207
 208 static struct clockdomain iss_44xx_clkdm = {
 209         .name             = "iss_clkdm",
 210         .pwrdm            = { .name = "cam_pwrdm" },
 211         .clkstctrl_reg    = OMAP4430_CM_CAM_CLKSTCTRL,
 212         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 213         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 214         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 215 };
 216
 217 static struct clockdomain l3_dss_44xx_clkdm = {
 218         .name             = "l3_dss_clkdm",
 219         .pwrdm            = { .name = "dss_pwrdm" },
 220         .clkstctrl_reg    = OMAP4430_CM_DSS_CLKSTCTRL,
 221         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 222         .flags            = CLKDM_CAN_HWSUP_SWSUP,
 223         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 224 };
 225
 226 static struct clockdomain l4_wkup_44xx_clkdm = {
 227         .name             = "l4_wkup_clkdm",
 228         .pwrdm            = { .name = "wkup_pwrdm" },
 229         .clkstctrl_reg    = OMAP4430_CM_WKUP_CLKSTCTRL,
 230         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 231         .flags            = CLKDM_CAN_HWSUP,
 232         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 233 };
 234
 235 static struct clockdomain emu_sys_44xx_clkdm = {
 236         .name             = "emu_sys_clkdm",
 237         .pwrdm            = { .name = "emu_pwrdm" },
 238         .clkstctrl_reg    = OMAP4430_CM_EMU_CLKSTCTRL,
 239         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 240         .flags            = CLKDM_CAN_HWSUP,
 241         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 242 };
 243
 244 static struct clockdomain l3_dma_44xx_clkdm = {
 245         .name             = "l3_dma_clkdm",
 246         .pwrdm            = { .name = "core_pwrdm" },
 247         .clkstctrl_reg    = OMAP4430_CM_SDMA_CLKSTCTRL,
 248         .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
 249         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
 250         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 251 };
 252
 253 static struct clockdomain *clockdomains_omap44xx[] __initdata = {
 254         &l4_cefuse_44xx_clkdm,
 255         &l4_cfg_44xx_clkdm,
 256         &tesla_44xx_clkdm,
 257         &l3_gfx_44xx_clkdm,
 258         &ivahd_44xx_clkdm,
 259         &l4_secure_44xx_clkdm,
 260         &l4_per_44xx_clkdm,
 261         &abe_44xx_clkdm,
 262         &l3_instr_44xx_clkdm,
 263         &l3_init_44xx_clkdm,
 264         &mpuss_44xx_clkdm,
 265         &mpu0_44xx_clkdm,
 266         &mpu1_44xx_clkdm,
 267         &l3_emif_44xx_clkdm,
 268         &l4_ao_44xx_clkdm,
 269         &ducati_44xx_clkdm,
 270         &l3_2_44xx_clkdm,
 271         &l3_1_44xx_clkdm,
 272         &l3_d2d_44xx_clkdm,
 273         &iss_44xx_clkdm,
 274         &l3_dss_44xx_clkdm,
 275         &l4_wkup_44xx_clkdm,
 276         &emu_sys_44xx_clkdm,
 277         &l3_dma_44xx_clkdm,
 278         NULL,
 279 };
 280
 281 void __init omap44xx_clockdomains_init(void)
 282 {
 283         clkdm_init(clockdomains_omap44xx, NULL);
 284 }