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[PATCH] Input: convert hdaps to dynamic input_dev allocation.
[linux-2.6/x86.git] / drivers / net / skge.c
blob596c93b12daad126b18e9ae305bd2c1c8f695687
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/mii.h>
41 #include <asm/irq.h>
42
43 #include "skge.h"
44
45 #define DRV_NAME "skge"
46 #define DRV_VERSION "1.2"
47 #define PFX DRV_NAME " "
48
49 #define DEFAULT_TX_RING_SIZE 128
50 #define DEFAULT_RX_RING_SIZE 512
51 #define MAX_TX_RING_SIZE 1024
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
59 #define BLINK_MS 250
60
61 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
62 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
63 MODULE_LICENSE("GPL");
64 MODULE_VERSION(DRV_VERSION);
65
66 static const u32 default_msg
67 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
68 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
69
70 static int debug = -1; /* defaults above */
71 module_param(debug, int, 0);
72 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73
74 static const struct pci_device_id skge_id_table[] = {
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
82 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
84 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
85 { 0 }
86 };
87 MODULE_DEVICE_TABLE(pci, skge_id_table);
88
89 static int skge_up(struct net_device *dev);
90 static int skge_down(struct net_device *dev);
91 static void skge_tx_clean(struct skge_port *skge);
92 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
94 static void genesis_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_get_stats(struct skge_port *skge, u64 *data);
96 static void yukon_init(struct skge_hw *hw, int port);
97 static void yukon_reset(struct skge_hw *hw, int port);
98 static void genesis_mac_init(struct skge_hw *hw, int port);
99 static void genesis_reset(struct skge_hw *hw, int port);
100 static void genesis_link_up(struct skge_port *skge);
101
102 /* Avoid conditionals by using array */
103 static const int txqaddr[] = { Q_XA1, Q_XA2 };
104 static const int rxqaddr[] = { Q_R1, Q_R2 };
105 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
106 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
107 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
108
109 static int skge_get_regs_len(struct net_device *dev)
110 {
111 return 0x4000;
112 }
113
114 /*
115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
117 * cause bus hangs!
118 */
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121 {
122 const struct skge_port *skge = netdev_priv(dev);
123 const void __iomem *io = skge->hw->regs;
124
125 regs->version = 1;
126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
128
129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
131 }
132
133 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
134 static int wol_supported(const struct skge_hw *hw)
135 {
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
138 }
139
140 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 {
142 struct skge_port *skge = netdev_priv(dev);
143
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
146 }
147
148 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 {
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
152
153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
154 return -EOPNOTSUPP;
155
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
157 return -EOPNOTSUPP;
158
159 skge->wol = wol->wolopts == WAKE_MAGIC;
160
161 if (skge->wol) {
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 } else
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
169
170 return 0;
171 }
172
173 /* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 */
176 static u32 skge_supported_modes(const struct skge_hw *hw)
177 {
178 u32 supported;
179
180 if (hw->copper) {
181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
188
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
194
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
197 } else
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
199 | SUPPORTED_Autoneg;
200
201 return supported;
202 }
203
204 static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
206 {
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
209
210 ecmd->transceiver = XCVR_INTERNAL;
211 ecmd->supported = skge_supported_modes(hw);
212
213 if (hw->copper) {
214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
216 } else
217 ecmd->port = PORT_FIBRE;
218
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
223 return 0;
224 }
225
226 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 {
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
230 u32 supported = skge_supported_modes(hw);
231
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
233 ecmd->advertising = supported;
234 skge->duplex = -1;
235 skge->speed = -1;
236 } else {
237 u32 setting;
238
239 switch (ecmd->speed) {
240 case SPEED_1000:
241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
245 else
246 return -EINVAL;
247 break;
248 case SPEED_100:
249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
253 else
254 return -EINVAL;
255 break;
256
257 case SPEED_10:
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
262 else
263 return -EINVAL;
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 if ((setting & supported) == 0)
270 return -EINVAL;
271
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
274 }
275
276 skge->autoneg = ecmd->autoneg;
277 skge->advertising = ecmd->advertising;
278
279 if (netif_running(dev)) {
280 skge_down(dev);
281 skge_up(dev);
282 }
283 return (0);
284 }
285
286 static void skge_get_drvinfo(struct net_device *dev,
287 struct ethtool_drvinfo *info)
288 {
289 struct skge_port *skge = netdev_priv(dev);
290
291 strcpy(info->driver, DRV_NAME);
292 strcpy(info->version, DRV_VERSION);
293 strcpy(info->fw_version, "N/A");
294 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295 }
296
297 static const struct skge_stat {
298 char name[ETH_GSTRING_LEN];
299 u16 xmac_offset;
300 u16 gma_offset;
301 } skge_stats[] = {
302 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
303 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
304
305 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
306 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
307 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
308 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
309 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
310 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
311 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
312 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
313
314 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
315 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
316 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
317 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
318 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
319 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
320
321 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
322 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
323 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
324 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
325 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326 };
327
328 static int skge_get_stats_count(struct net_device *dev)
329 {
330 return ARRAY_SIZE(skge_stats);
331 }
332
333 static void skge_get_ethtool_stats(struct net_device *dev,
334 struct ethtool_stats *stats, u64 *data)
335 {
336 struct skge_port *skge = netdev_priv(dev);
337
338 if (skge->hw->chip_id == CHIP_ID_GENESIS)
339 genesis_get_stats(skge, data);
340 else
341 yukon_get_stats(skge, data);
342 }
343
344 /* Use hardware MIB variables for critical path statistics and
345 * transmit feedback not reported at interrupt.
346 * Other errors are accounted for in interrupt handler.
347 */
348 static struct net_device_stats *skge_get_stats(struct net_device *dev)
349 {
350 struct skge_port *skge = netdev_priv(dev);
351 u64 data[ARRAY_SIZE(skge_stats)];
352
353 if (skge->hw->chip_id == CHIP_ID_GENESIS)
354 genesis_get_stats(skge, data);
355 else
356 yukon_get_stats(skge, data);
357
358 skge->net_stats.tx_bytes = data[0];
359 skge->net_stats.rx_bytes = data[1];
360 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
361 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
362 skge->net_stats.multicast = data[5] + data[7];
363 skge->net_stats.collisions = data[10];
364 skge->net_stats.tx_aborted_errors = data[12];
365
366 return &skge->net_stats;
367 }
368
369 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
370 {
371 int i;
372
373 switch (stringset) {
374 case ETH_SS_STATS:
375 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
376 memcpy(data + i * ETH_GSTRING_LEN,
377 skge_stats[i].name, ETH_GSTRING_LEN);
378 break;
379 }
380 }
381
382 static void skge_get_ring_param(struct net_device *dev,
383 struct ethtool_ringparam *p)
384 {
385 struct skge_port *skge = netdev_priv(dev);
386
387 p->rx_max_pending = MAX_RX_RING_SIZE;
388 p->tx_max_pending = MAX_TX_RING_SIZE;
389 p->rx_mini_max_pending = 0;
390 p->rx_jumbo_max_pending = 0;
391
392 p->rx_pending = skge->rx_ring.count;
393 p->tx_pending = skge->tx_ring.count;
394 p->rx_mini_pending = 0;
395 p->rx_jumbo_pending = 0;
396 }
397
398 static int skge_set_ring_param(struct net_device *dev,
399 struct ethtool_ringparam *p)
400 {
401 struct skge_port *skge = netdev_priv(dev);
402
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
405 return -EINVAL;
406
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
409
410 if (netif_running(dev)) {
411 skge_down(dev);
412 skge_up(dev);
413 }
414
415 return 0;
416 }
417
418 static u32 skge_get_msglevel(struct net_device *netdev)
419 {
420 struct skge_port *skge = netdev_priv(netdev);
421 return skge->msg_enable;
422 }
423
424 static void skge_set_msglevel(struct net_device *netdev, u32 value)
425 {
426 struct skge_port *skge = netdev_priv(netdev);
427 skge->msg_enable = value;
428 }
429
430 static int skge_nway_reset(struct net_device *dev)
431 {
432 struct skge_port *skge = netdev_priv(dev);
433 struct skge_hw *hw = skge->hw;
434 int port = skge->port;
435
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
437 return -EINVAL;
438
439 spin_lock_bh(&hw->phy_lock);
440 if (hw->chip_id == CHIP_ID_GENESIS) {
441 genesis_reset(hw, port);
442 genesis_mac_init(hw, port);
443 } else {
444 yukon_reset(hw, port);
445 yukon_init(hw, port);
446 }
447 spin_unlock_bh(&hw->phy_lock);
448 return 0;
449 }
450
451 static int skge_set_sg(struct net_device *dev, u32 data)
452 {
453 struct skge_port *skge = netdev_priv(dev);
454 struct skge_hw *hw = skge->hw;
455
456 if (hw->chip_id == CHIP_ID_GENESIS && data)
457 return -EOPNOTSUPP;
458 return ethtool_op_set_sg(dev, data);
459 }
460
461 static int skge_set_tx_csum(struct net_device *dev, u32 data)
462 {
463 struct skge_port *skge = netdev_priv(dev);
464 struct skge_hw *hw = skge->hw;
465
466 if (hw->chip_id == CHIP_ID_GENESIS && data)
467 return -EOPNOTSUPP;
468
469 return ethtool_op_set_tx_csum(dev, data);
470 }
471
472 static u32 skge_get_rx_csum(struct net_device *dev)
473 {
474 struct skge_port *skge = netdev_priv(dev);
475
476 return skge->rx_csum;
477 }
478
479 /* Only Yukon supports checksum offload. */
480 static int skge_set_rx_csum(struct net_device *dev, u32 data)
481 {
482 struct skge_port *skge = netdev_priv(dev);
483
484 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
485 return -EOPNOTSUPP;
486
487 skge->rx_csum = data;
488 return 0;
489 }
490
491 static void skge_get_pauseparam(struct net_device *dev,
492 struct ethtool_pauseparam *ecmd)
493 {
494 struct skge_port *skge = netdev_priv(dev);
495
496 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
497 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
498 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
499 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
500
501 ecmd->autoneg = skge->autoneg;
502 }
503
504 static int skge_set_pauseparam(struct net_device *dev,
505 struct ethtool_pauseparam *ecmd)
506 {
507 struct skge_port *skge = netdev_priv(dev);
508
509 skge->autoneg = ecmd->autoneg;
510 if (ecmd->rx_pause && ecmd->tx_pause)
511 skge->flow_control = FLOW_MODE_SYMMETRIC;
512 else if (ecmd->rx_pause && !ecmd->tx_pause)
513 skge->flow_control = FLOW_MODE_REM_SEND;
514 else if (!ecmd->rx_pause && ecmd->tx_pause)
515 skge->flow_control = FLOW_MODE_LOC_SEND;
516 else
517 skge->flow_control = FLOW_MODE_NONE;
518
519 if (netif_running(dev)) {
520 skge_down(dev);
521 skge_up(dev);
522 }
523 return 0;
524 }
525
526 /* Chip internal frequency for clock calculations */
527 static inline u32 hwkhz(const struct skge_hw *hw)
528 {
529 if (hw->chip_id == CHIP_ID_GENESIS)
530 return 53215; /* or: 53.125 MHz */
531 else
532 return 78215; /* or: 78.125 MHz */
533 }
534
535 /* Chip HZ to microseconds */
536 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
537 {
538 return (ticks * 1000) / hwkhz(hw);
539 }
540
541 /* Microseconds to chip HZ */
542 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
543 {
544 return hwkhz(hw) * usec / 1000;
545 }
546
547 static int skge_get_coalesce(struct net_device *dev,
548 struct ethtool_coalesce *ecmd)
549 {
550 struct skge_port *skge = netdev_priv(dev);
551 struct skge_hw *hw = skge->hw;
552 int port = skge->port;
553
554 ecmd->rx_coalesce_usecs = 0;
555 ecmd->tx_coalesce_usecs = 0;
556
557 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
558 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
559 u32 msk = skge_read32(hw, B2_IRQM_MSK);
560
561 if (msk & rxirqmask[port])
562 ecmd->rx_coalesce_usecs = delay;
563 if (msk & txirqmask[port])
564 ecmd->tx_coalesce_usecs = delay;
565 }
566
567 return 0;
568 }
569
570 /* Note: interrupt timer is per board, but can turn on/off per port */
571 static int skge_set_coalesce(struct net_device *dev,
572 struct ethtool_coalesce *ecmd)
573 {
574 struct skge_port *skge = netdev_priv(dev);
575 struct skge_hw *hw = skge->hw;
576 int port = skge->port;
577 u32 msk = skge_read32(hw, B2_IRQM_MSK);
578 u32 delay = 25;
579
580 if (ecmd->rx_coalesce_usecs == 0)
581 msk &= ~rxirqmask[port];
582 else if (ecmd->rx_coalesce_usecs < 25 ||
583 ecmd->rx_coalesce_usecs > 33333)
584 return -EINVAL;
585 else {
586 msk |= rxirqmask[port];
587 delay = ecmd->rx_coalesce_usecs;
588 }
589
590 if (ecmd->tx_coalesce_usecs == 0)
591 msk &= ~txirqmask[port];
592 else if (ecmd->tx_coalesce_usecs < 25 ||
593 ecmd->tx_coalesce_usecs > 33333)
594 return -EINVAL;
595 else {
596 msk |= txirqmask[port];
597 delay = min(delay, ecmd->rx_coalesce_usecs);
598 }
599
600 skge_write32(hw, B2_IRQM_MSK, msk);
601 if (msk == 0)
602 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
603 else {
604 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
605 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
606 }
607 return 0;
608 }
609
610 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
611 static void skge_led(struct skge_port *skge, enum led_mode mode)
612 {
613 struct skge_hw *hw = skge->hw;
614 int port = skge->port;
615
616 spin_lock_bh(&hw->phy_lock);
617 if (hw->chip_id == CHIP_ID_GENESIS) {
618 switch (mode) {
619 case LED_MODE_OFF:
620 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
621 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
622 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
623 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
624 break;
625
626 case LED_MODE_ON:
627 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
628 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
629
630 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
631 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
632
633 break;
634
635 case LED_MODE_TST:
636 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
637 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
638 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
639
640 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
641 break;
642 }
643 } else {
644 switch (mode) {
645 case LED_MODE_OFF:
646 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
647 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
648 PHY_M_LED_MO_DUP(MO_LED_OFF) |
649 PHY_M_LED_MO_10(MO_LED_OFF) |
650 PHY_M_LED_MO_100(MO_LED_OFF) |
651 PHY_M_LED_MO_1000(MO_LED_OFF) |
652 PHY_M_LED_MO_RX(MO_LED_OFF));
653 break;
654 case LED_MODE_ON:
655 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
656 PHY_M_LED_PULS_DUR(PULS_170MS) |
657 PHY_M_LED_BLINK_RT(BLINK_84MS) |
658 PHY_M_LEDC_TX_CTRL |
659 PHY_M_LEDC_DP_CTRL);
660
661 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
662 PHY_M_LED_MO_RX(MO_LED_OFF) |
663 (skge->speed == SPEED_100 ?
664 PHY_M_LED_MO_100(MO_LED_ON) : 0));
665 break;
666 case LED_MODE_TST:
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
668 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
669 PHY_M_LED_MO_DUP(MO_LED_ON) |
670 PHY_M_LED_MO_10(MO_LED_ON) |
671 PHY_M_LED_MO_100(MO_LED_ON) |
672 PHY_M_LED_MO_1000(MO_LED_ON) |
673 PHY_M_LED_MO_RX(MO_LED_ON));
674 }
675 }
676 spin_unlock_bh(&hw->phy_lock);
677 }
678
679 /* blink LED's for finding board */
680 static int skge_phys_id(struct net_device *dev, u32 data)
681 {
682 struct skge_port *skge = netdev_priv(dev);
683 unsigned long ms;
684 enum led_mode mode = LED_MODE_TST;
685
686 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
687 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
688 else
689 ms = data * 1000;
690
691 while (ms > 0) {
692 skge_led(skge, mode);
693 mode ^= LED_MODE_TST;
694
695 if (msleep_interruptible(BLINK_MS))
696 break;
697 ms -= BLINK_MS;
698 }
699
700 /* back to regular LED state */
701 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
702
703 return 0;
704 }
705
706 static struct ethtool_ops skge_ethtool_ops = {
707 .get_settings = skge_get_settings,
708 .set_settings = skge_set_settings,
709 .get_drvinfo = skge_get_drvinfo,
710 .get_regs_len = skge_get_regs_len,
711 .get_regs = skge_get_regs,
712 .get_wol = skge_get_wol,
713 .set_wol = skge_set_wol,
714 .get_msglevel = skge_get_msglevel,
715 .set_msglevel = skge_set_msglevel,
716 .nway_reset = skge_nway_reset,
717 .get_link = ethtool_op_get_link,
718 .get_ringparam = skge_get_ring_param,
719 .set_ringparam = skge_set_ring_param,
720 .get_pauseparam = skge_get_pauseparam,
721 .set_pauseparam = skge_set_pauseparam,
722 .get_coalesce = skge_get_coalesce,
723 .set_coalesce = skge_set_coalesce,
724 .get_sg = ethtool_op_get_sg,
725 .set_sg = skge_set_sg,
726 .get_tx_csum = ethtool_op_get_tx_csum,
727 .set_tx_csum = skge_set_tx_csum,
728 .get_rx_csum = skge_get_rx_csum,
729 .set_rx_csum = skge_set_rx_csum,
730 .get_strings = skge_get_strings,
731 .phys_id = skge_phys_id,
732 .get_stats_count = skge_get_stats_count,
733 .get_ethtool_stats = skge_get_ethtool_stats,
734 .get_perm_addr = ethtool_op_get_perm_addr,
735 };
736
737 /*
738 * Allocate ring elements and chain them together
739 * One-to-one association of board descriptors with ring elements
740 */
741 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
742 {
743 struct skge_tx_desc *d;
744 struct skge_element *e;
745 int i;
746
747 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
748 if (!ring->start)
749 return -ENOMEM;
750
751 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
752 e->desc = d;
753 e->skb = NULL;
754 if (i == ring->count - 1) {
755 e->next = ring->start;
756 d->next_offset = base;
757 } else {
758 e->next = e + 1;
759 d->next_offset = base + (i+1) * sizeof(*d);
760 }
761 }
762 ring->to_use = ring->to_clean = ring->start;
763
764 return 0;
765 }
766
767 /* Allocate and setup a new buffer for receiving */
768 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
769 struct sk_buff *skb, unsigned int bufsize)
770 {
771 struct skge_rx_desc *rd = e->desc;
772 u64 map;
773
774 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
775 PCI_DMA_FROMDEVICE);
776
777 rd->dma_lo = map;
778 rd->dma_hi = map >> 32;
779 e->skb = skb;
780 rd->csum1_start = ETH_HLEN;
781 rd->csum2_start = ETH_HLEN;
782 rd->csum1 = 0;
783 rd->csum2 = 0;
784
785 wmb();
786
787 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
788 pci_unmap_addr_set(e, mapaddr, map);
789 pci_unmap_len_set(e, maplen, bufsize);
790 }
791
792 /* Resume receiving using existing skb,
793 * Note: DMA address is not changed by chip.
794 * MTU not changed while receiver active.
795 */
796 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
797 {
798 struct skge_rx_desc *rd = e->desc;
799
800 rd->csum2 = 0;
801 rd->csum2_start = ETH_HLEN;
802
803 wmb();
804
805 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
806 }
807
808
809 /* Free all buffers in receive ring, assumes receiver stopped */
810 static void skge_rx_clean(struct skge_port *skge)
811 {
812 struct skge_hw *hw = skge->hw;
813 struct skge_ring *ring = &skge->rx_ring;
814 struct skge_element *e;
815
816 e = ring->start;
817 do {
818 struct skge_rx_desc *rd = e->desc;
819 rd->control = 0;
820 if (e->skb) {
821 pci_unmap_single(hw->pdev,
822 pci_unmap_addr(e, mapaddr),
823 pci_unmap_len(e, maplen),
824 PCI_DMA_FROMDEVICE);
825 dev_kfree_skb(e->skb);
826 e->skb = NULL;
827 }
828 } while ((e = e->next) != ring->start);
829 }
830
831
832 /* Allocate buffers for receive ring
833 * For receive: to_clean is next received frame.
834 */
835 static int skge_rx_fill(struct skge_port *skge)
836 {
837 struct skge_ring *ring = &skge->rx_ring;
838 struct skge_element *e;
839
840 e = ring->start;
841 do {
842 struct sk_buff *skb;
843
844 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
845 if (!skb)
846 return -ENOMEM;
847
848 skb_reserve(skb, NET_IP_ALIGN);
849 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
850 } while ( (e = e->next) != ring->start);
851
852 ring->to_clean = ring->start;
853 return 0;
854 }
855
856 static void skge_link_up(struct skge_port *skge)
857 {
858 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
859 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
860
861 netif_carrier_on(skge->netdev);
862 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
863 netif_wake_queue(skge->netdev);
864
865 if (netif_msg_link(skge))
866 printk(KERN_INFO PFX
867 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
868 skge->netdev->name, skge->speed,
869 skge->duplex == DUPLEX_FULL ? "full" : "half",
870 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
871 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
872 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
873 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
874 "unknown");
875 }
876
877 static void skge_link_down(struct skge_port *skge)
878 {
879 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
880 netif_carrier_off(skge->netdev);
881 netif_stop_queue(skge->netdev);
882
883 if (netif_msg_link(skge))
884 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
885 }
886
887 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
888 {
889 int i;
890
891 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
892 xm_read16(hw, port, XM_PHY_DATA);
893
894 /* Need to wait for external PHY */
895 for (i = 0; i < PHY_RETRIES; i++) {
896 udelay(1);
897 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
898 goto ready;
899 }
900
901 return -ETIMEDOUT;
902 ready:
903 *val = xm_read16(hw, port, XM_PHY_DATA);
904
905 return 0;
906 }
907
908 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
909 {
910 u16 v = 0;
911 if (__xm_phy_read(hw, port, reg, &v))
912 printk(KERN_WARNING PFX "%s: phy read timed out\n",
913 hw->dev[port]->name);
914 return v;
915 }
916
917 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
918 {
919 int i;
920
921 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
922 for (i = 0; i < PHY_RETRIES; i++) {
923 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
924 goto ready;
925 udelay(1);
926 }
927 return -EIO;
928
929 ready:
930 xm_write16(hw, port, XM_PHY_DATA, val);
931 return 0;
932 }
933
934 static void genesis_init(struct skge_hw *hw)
935 {
936 /* set blink source counter */
937 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
938 skge_write8(hw, B2_BSC_CTRL, BSC_START);
939
940 /* configure mac arbiter */
941 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
942
943 /* configure mac arbiter timeout values */
944 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
945 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
946 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
947 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
948
949 skge_write8(hw, B3_MA_RCINI_RX1, 0);
950 skge_write8(hw, B3_MA_RCINI_RX2, 0);
951 skge_write8(hw, B3_MA_RCINI_TX1, 0);
952 skge_write8(hw, B3_MA_RCINI_TX2, 0);
953
954 /* configure packet arbiter timeout */
955 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
956 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
957 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
958 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
959 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
960 }
961
962 static void genesis_reset(struct skge_hw *hw, int port)
963 {
964 const u8 zero[8] = { 0 };
965
966 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
967
968 /* reset the statistics module */
969 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
970 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
971 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
972 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
973 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
974
975 /* disable Broadcom PHY IRQ */
976 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
977
978 xm_outhash(hw, port, XM_HSM, zero);
979 }
980
981
982 /* Convert mode to MII values */
983 static const u16 phy_pause_map[] = {
984 [FLOW_MODE_NONE] = 0,
985 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
986 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
987 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
988 };
989
990
991 /* Check status of Broadcom phy link */
992 static void bcom_check_link(struct skge_hw *hw, int port)
993 {
994 struct net_device *dev = hw->dev[port];
995 struct skge_port *skge = netdev_priv(dev);
996 u16 status;
997
998 /* read twice because of latch */
999 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1000 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1001
1002 if ((status & PHY_ST_LSYNC) == 0) {
1003 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1004 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1005 xm_write16(hw, port, XM_MMU_CMD, cmd);
1006 /* dummy read to ensure writing */
1007 (void) xm_read16(hw, port, XM_MMU_CMD);
1008
1009 if (netif_carrier_ok(dev))
1010 skge_link_down(skge);
1011 } else {
1012 if (skge->autoneg == AUTONEG_ENABLE &&
1013 (status & PHY_ST_AN_OVER)) {
1014 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1015 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1016
1017 if (lpa & PHY_B_AN_RF) {
1018 printk(KERN_NOTICE PFX "%s: remote fault\n",
1019 dev->name);
1020 return;
1021 }
1022
1023 /* Check Duplex mismatch */
1024 switch (aux & PHY_B_AS_AN_RES_MSK) {
1025 case PHY_B_RES_1000FD:
1026 skge->duplex = DUPLEX_FULL;
1027 break;
1028 case PHY_B_RES_1000HD:
1029 skge->duplex = DUPLEX_HALF;
1030 break;
1031 default:
1032 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1033 dev->name);
1034 return;
1035 }
1036
1037
1038 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1039 switch (aux & PHY_B_AS_PAUSE_MSK) {
1040 case PHY_B_AS_PAUSE_MSK:
1041 skge->flow_control = FLOW_MODE_SYMMETRIC;
1042 break;
1043 case PHY_B_AS_PRR:
1044 skge->flow_control = FLOW_MODE_REM_SEND;
1045 break;
1046 case PHY_B_AS_PRT:
1047 skge->flow_control = FLOW_MODE_LOC_SEND;
1048 break;
1049 default:
1050 skge->flow_control = FLOW_MODE_NONE;
1051 }
1052
1053 skge->speed = SPEED_1000;
1054 }
1055
1056 if (!netif_carrier_ok(dev))
1057 genesis_link_up(skge);
1058 }
1059 }
1060
1061 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1062 * Phy on for 100 or 10Mbit operation
1063 */
1064 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1065 {
1066 struct skge_hw *hw = skge->hw;
1067 int port = skge->port;
1068 int i;
1069 u16 id1, r, ext, ctl;
1070
1071 /* magic workaround patterns for Broadcom */
1072 static const struct {
1073 u16 reg;
1074 u16 val;
1075 } A1hack[] = {
1076 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1077 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1078 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1079 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1080 }, C0hack[] = {
1081 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1082 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1083 };
1084
1085 /* read Id from external PHY (all have the same address) */
1086 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1087
1088 /* Optimize MDIO transfer by suppressing preamble. */
1089 r = xm_read16(hw, port, XM_MMU_CMD);
1090 r |= XM_MMU_NO_PRE;
1091 xm_write16(hw, port, XM_MMU_CMD,r);
1092
1093 switch (id1) {
1094 case PHY_BCOM_ID1_C0:
1095 /*
1096 * Workaround BCOM Errata for the C0 type.
1097 * Write magic patterns to reserved registers.
1098 */
1099 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1100 xm_phy_write(hw, port,
1101 C0hack[i].reg, C0hack[i].val);
1102
1103 break;
1104 case PHY_BCOM_ID1_A1:
1105 /*
1106 * Workaround BCOM Errata for the A1 type.
1107 * Write magic patterns to reserved registers.
1108 */
1109 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1110 xm_phy_write(hw, port,
1111 A1hack[i].reg, A1hack[i].val);
1112 break;
1113 }
1114
1115 /*
1116 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1117 * Disable Power Management after reset.
1118 */
1119 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1120 r |= PHY_B_AC_DIS_PM;
1121 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1122
1123 /* Dummy read */
1124 xm_read16(hw, port, XM_ISRC);
1125
1126 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1127 ctl = PHY_CT_SP1000; /* always 1000mbit */
1128
1129 if (skge->autoneg == AUTONEG_ENABLE) {
1130 /*
1131 * Workaround BCOM Errata #1 for the C5 type.
1132 * 1000Base-T Link Acquisition Failure in Slave Mode
1133 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1134 */
1135 u16 adv = PHY_B_1000C_RD;
1136 if (skge->advertising & ADVERTISED_1000baseT_Half)
1137 adv |= PHY_B_1000C_AHD;
1138 if (skge->advertising & ADVERTISED_1000baseT_Full)
1139 adv |= PHY_B_1000C_AFD;
1140 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1141
1142 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1143 } else {
1144 if (skge->duplex == DUPLEX_FULL)
1145 ctl |= PHY_CT_DUP_MD;
1146 /* Force to slave */
1147 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1148 }
1149
1150 /* Set autonegotiation pause parameters */
1151 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1152 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1153
1154 /* Handle Jumbo frames */
1155 if (jumbo) {
1156 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1157 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1158
1159 ext |= PHY_B_PEC_HIGH_LA;
1160
1161 }
1162
1163 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1164 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1165
1166 /* Use link status change interrupt */
1167 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1168
1169 bcom_check_link(hw, port);
1170 }
1171
1172 static void genesis_mac_init(struct skge_hw *hw, int port)
1173 {
1174 struct net_device *dev = hw->dev[port];
1175 struct skge_port *skge = netdev_priv(dev);
1176 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1177 int i;
1178 u32 r;
1179 const u8 zero[6] = { 0 };
1180
1181 /* Clear MIB counters */
1182 xm_write16(hw, port, XM_STAT_CMD,
1183 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1184 /* Clear two times according to Errata #3 */
1185 xm_write16(hw, port, XM_STAT_CMD,
1186 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1187
1188 /* Unreset the XMAC. */
1189 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1190
1191 /*
1192 * Perform additional initialization for external PHYs,
1193 * namely for the 1000baseTX cards that use the XMAC's
1194 * GMII mode.
1195 */
1196 /* Take external Phy out of reset */
1197 r = skge_read32(hw, B2_GP_IO);
1198 if (port == 0)
1199 r |= GP_DIR_0|GP_IO_0;
1200 else
1201 r |= GP_DIR_2|GP_IO_2;
1202
1203 skge_write32(hw, B2_GP_IO, r);
1204 skge_read32(hw, B2_GP_IO);
1205
1206 /* Enable GMII interface */
1207 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1208
1209 bcom_phy_init(skge, jumbo);
1210
1211 /* Set Station Address */
1212 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1213
1214 /* We don't use match addresses so clear */
1215 for (i = 1; i < 16; i++)
1216 xm_outaddr(hw, port, XM_EXM(i), zero);
1217
1218 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1219 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1220
1221 /* We don't need the FCS appended to the packet. */
1222 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1223 if (jumbo)
1224 r |= XM_RX_BIG_PK_OK;
1225
1226 if (skge->duplex == DUPLEX_HALF) {
1227 /*
1228 * If in manual half duplex mode the other side might be in
1229 * full duplex mode, so ignore if a carrier extension is not seen
1230 * on frames received
1231 */
1232 r |= XM_RX_DIS_CEXT;
1233 }
1234 xm_write16(hw, port, XM_RX_CMD, r);
1235
1236
1237 /* We want short frames padded to 60 bytes. */
1238 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1239
1240 /*
1241 * Bump up the transmit threshold. This helps hold off transmit
1242 * underruns when we're blasting traffic from both ports at once.
1243 */
1244 xm_write16(hw, port, XM_TX_THR, 512);
1245
1246 /*
1247 * Enable the reception of all error frames. This is is
1248 * a necessary evil due to the design of the XMAC. The
1249 * XMAC's receive FIFO is only 8K in size, however jumbo
1250 * frames can be up to 9000 bytes in length. When bad
1251 * frame filtering is enabled, the XMAC's RX FIFO operates
1252 * in 'store and forward' mode. For this to work, the
1253 * entire frame has to fit into the FIFO, but that means
1254 * that jumbo frames larger than 8192 bytes will be
1255 * truncated. Disabling all bad frame filtering causes
1256 * the RX FIFO to operate in streaming mode, in which
1257 * case the XMAC will start transferring frames out of the
1258 * RX FIFO as soon as the FIFO threshold is reached.
1259 */
1260 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1261
1262
1263 /*
1264 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1265 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1266 * and 'Octets Rx OK Hi Cnt Ov'.
1267 */
1268 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1269
1270 /*
1271 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1272 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1273 * and 'Octets Tx OK Hi Cnt Ov'.
1274 */
1275 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1276
1277 /* Configure MAC arbiter */
1278 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1279
1280 /* configure timeout values */
1281 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1282 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1283 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1284 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1285
1286 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1287 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1288 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1289 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1290
1291 /* Configure Rx MAC FIFO */
1292 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1293 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1294 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1295
1296 /* Configure Tx MAC FIFO */
1297 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1298 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1299 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1300
1301 if (jumbo) {
1302 /* Enable frame flushing if jumbo frames used */
1303 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1304 } else {
1305 /* enable timeout timers if normal frames */
1306 skge_write16(hw, B3_PA_CTRL,
1307 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1308 }
1309 }
1310
1311 static void genesis_stop(struct skge_port *skge)
1312 {
1313 struct skge_hw *hw = skge->hw;
1314 int port = skge->port;
1315 u32 reg;
1316
1317 genesis_reset(hw, port);
1318
1319 /* Clear Tx packet arbiter timeout IRQ */
1320 skge_write16(hw, B3_PA_CTRL,
1321 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1322
1323 /*
1324 * If the transfer sticks at the MAC the STOP command will not
1325 * terminate if we don't flush the XMAC's transmit FIFO !
1326 */
1327 xm_write32(hw, port, XM_MODE,
1328 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1329
1330
1331 /* Reset the MAC */
1332 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1333
1334 /* For external PHYs there must be special handling */
1335 reg = skge_read32(hw, B2_GP_IO);
1336 if (port == 0) {
1337 reg |= GP_DIR_0;
1338 reg &= ~GP_IO_0;
1339 } else {
1340 reg |= GP_DIR_2;
1341 reg &= ~GP_IO_2;
1342 }
1343 skge_write32(hw, B2_GP_IO, reg);
1344 skge_read32(hw, B2_GP_IO);
1345
1346 xm_write16(hw, port, XM_MMU_CMD,
1347 xm_read16(hw, port, XM_MMU_CMD)
1348 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1349
1350 xm_read16(hw, port, XM_MMU_CMD);
1351 }
1352
1353
1354 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1355 {
1356 struct skge_hw *hw = skge->hw;
1357 int port = skge->port;
1358 int i;
1359 unsigned long timeout = jiffies + HZ;
1360
1361 xm_write16(hw, port,
1362 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1363
1364 /* wait for update to complete */
1365 while (xm_read16(hw, port, XM_STAT_CMD)
1366 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1367 if (time_after(jiffies, timeout))
1368 break;
1369 udelay(10);
1370 }
1371
1372 /* special case for 64 bit octet counter */
1373 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1374 | xm_read32(hw, port, XM_TXO_OK_LO);
1375 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1376 | xm_read32(hw, port, XM_RXO_OK_LO);
1377
1378 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1379 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1380 }
1381
1382 static void genesis_mac_intr(struct skge_hw *hw, int port)
1383 {
1384 struct skge_port *skge = netdev_priv(hw->dev[port]);
1385 u16 status = xm_read16(hw, port, XM_ISRC);
1386
1387 if (netif_msg_intr(skge))
1388 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1389 skge->netdev->name, status);
1390
1391 if (status & XM_IS_TXF_UR) {
1392 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1393 ++skge->net_stats.tx_fifo_errors;
1394 }
1395 if (status & XM_IS_RXF_OV) {
1396 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1397 ++skge->net_stats.rx_fifo_errors;
1398 }
1399 }
1400
1401 static void genesis_link_up(struct skge_port *skge)
1402 {
1403 struct skge_hw *hw = skge->hw;
1404 int port = skge->port;
1405 u16 cmd;
1406 u32 mode, msk;
1407
1408 cmd = xm_read16(hw, port, XM_MMU_CMD);
1409
1410 /*
1411 * enabling pause frame reception is required for 1000BT
1412 * because the XMAC is not reset if the link is going down
1413 */
1414 if (skge->flow_control == FLOW_MODE_NONE ||
1415 skge->flow_control == FLOW_MODE_LOC_SEND)
1416 /* Disable Pause Frame Reception */
1417 cmd |= XM_MMU_IGN_PF;
1418 else
1419 /* Enable Pause Frame Reception */
1420 cmd &= ~XM_MMU_IGN_PF;
1421
1422 xm_write16(hw, port, XM_MMU_CMD, cmd);
1423
1424 mode = xm_read32(hw, port, XM_MODE);
1425 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1426 skge->flow_control == FLOW_MODE_LOC_SEND) {
1427 /*
1428 * Configure Pause Frame Generation
1429 * Use internal and external Pause Frame Generation.
1430 * Sending pause frames is edge triggered.
1431 * Send a Pause frame with the maximum pause time if
1432 * internal oder external FIFO full condition occurs.
1433 * Send a zero pause time frame to re-start transmission.
1434 */
1435 /* XM_PAUSE_DA = '010000C28001' (default) */
1436 /* XM_MAC_PTIME = 0xffff (maximum) */
1437 /* remember this value is defined in big endian (!) */
1438 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1439
1440 mode |= XM_PAUSE_MODE;
1441 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1442 } else {
1443 /*
1444 * disable pause frame generation is required for 1000BT
1445 * because the XMAC is not reset if the link is going down
1446 */
1447 /* Disable Pause Mode in Mode Register */
1448 mode &= ~XM_PAUSE_MODE;
1449
1450 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1451 }
1452
1453 xm_write32(hw, port, XM_MODE, mode);
1454
1455 msk = XM_DEF_MSK;
1456 /* disable GP0 interrupt bit for external Phy */
1457 msk |= XM_IS_INP_ASS;
1458
1459 xm_write16(hw, port, XM_IMSK, msk);
1460 xm_read16(hw, port, XM_ISRC);
1461
1462 /* get MMU Command Reg. */
1463 cmd = xm_read16(hw, port, XM_MMU_CMD);
1464 if (skge->duplex == DUPLEX_FULL)
1465 cmd |= XM_MMU_GMII_FD;
1466
1467 /*
1468 * Workaround BCOM Errata (#10523) for all BCom Phys
1469 * Enable Power Management after link up
1470 */
1471 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1472 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1473 & ~PHY_B_AC_DIS_PM);
1474 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1475
1476 /* enable Rx/Tx */
1477 xm_write16(hw, port, XM_MMU_CMD,
1478 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1479 skge_link_up(skge);
1480 }
1481
1482
1483 static inline void bcom_phy_intr(struct skge_port *skge)
1484 {
1485 struct skge_hw *hw = skge->hw;
1486 int port = skge->port;
1487 u16 isrc;
1488
1489 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1490 if (netif_msg_intr(skge))
1491 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1492 skge->netdev->name, isrc);
1493
1494 if (isrc & PHY_B_IS_PSE)
1495 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1496 hw->dev[port]->name);
1497
1498 /* Workaround BCom Errata:
1499 * enable and disable loopback mode if "NO HCD" occurs.
1500 */
1501 if (isrc & PHY_B_IS_NO_HDCL) {
1502 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1503 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1504 ctrl | PHY_CT_LOOP);
1505 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1506 ctrl & ~PHY_CT_LOOP);
1507 }
1508
1509 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1510 bcom_check_link(hw, port);
1511
1512 }
1513
1514 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1515 {
1516 int i;
1517
1518 gma_write16(hw, port, GM_SMI_DATA, val);
1519 gma_write16(hw, port, GM_SMI_CTRL,
1520 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1521 for (i = 0; i < PHY_RETRIES; i++) {
1522 udelay(1);
1523
1524 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1525 return 0;
1526 }
1527
1528 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1529 hw->dev[port]->name);
1530 return -EIO;
1531 }
1532
1533 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1534 {
1535 int i;
1536
1537 gma_write16(hw, port, GM_SMI_CTRL,
1538 GM_SMI_CT_PHY_AD(hw->phy_addr)
1539 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1540
1541 for (i = 0; i < PHY_RETRIES; i++) {
1542 udelay(1);
1543 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1544 goto ready;
1545 }
1546
1547 return -ETIMEDOUT;
1548 ready:
1549 *val = gma_read16(hw, port, GM_SMI_DATA);
1550 return 0;
1551 }
1552
1553 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1554 {
1555 u16 v = 0;
1556 if (__gm_phy_read(hw, port, reg, &v))
1557 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1558 hw->dev[port]->name);
1559 return v;
1560 }
1561
1562 /* Marvell Phy Initialization */
1563 static void yukon_init(struct skge_hw *hw, int port)
1564 {
1565 struct skge_port *skge = netdev_priv(hw->dev[port]);
1566 u16 ctrl, ct1000, adv;
1567
1568 if (skge->autoneg == AUTONEG_ENABLE) {
1569 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1570
1571 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1572 PHY_M_EC_MAC_S_MSK);
1573 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1574
1575 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1576
1577 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1578 }
1579
1580 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1581 if (skge->autoneg == AUTONEG_DISABLE)
1582 ctrl &= ~PHY_CT_ANE;
1583
1584 ctrl |= PHY_CT_RESET;
1585 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1586
1587 ctrl = 0;
1588 ct1000 = 0;
1589 adv = PHY_AN_CSMA;
1590
1591 if (skge->autoneg == AUTONEG_ENABLE) {
1592 if (hw->copper) {
1593 if (skge->advertising & ADVERTISED_1000baseT_Full)
1594 ct1000 |= PHY_M_1000C_AFD;
1595 if (skge->advertising & ADVERTISED_1000baseT_Half)
1596 ct1000 |= PHY_M_1000C_AHD;
1597 if (skge->advertising & ADVERTISED_100baseT_Full)
1598 adv |= PHY_M_AN_100_FD;
1599 if (skge->advertising & ADVERTISED_100baseT_Half)
1600 adv |= PHY_M_AN_100_HD;
1601 if (skge->advertising & ADVERTISED_10baseT_Full)
1602 adv |= PHY_M_AN_10_FD;
1603 if (skge->advertising & ADVERTISED_10baseT_Half)
1604 adv |= PHY_M_AN_10_HD;
1605 } else /* special defines for FIBER (88E1011S only) */
1606 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1607
1608 /* Set Flow-control capabilities */
1609 adv |= phy_pause_map[skge->flow_control];
1610
1611 /* Restart Auto-negotiation */
1612 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1613 } else {
1614 /* forced speed/duplex settings */
1615 ct1000 = PHY_M_1000C_MSE;
1616
1617 if (skge->duplex == DUPLEX_FULL)
1618 ctrl |= PHY_CT_DUP_MD;
1619
1620 switch (skge->speed) {
1621 case SPEED_1000:
1622 ctrl |= PHY_CT_SP1000;
1623 break;
1624 case SPEED_100:
1625 ctrl |= PHY_CT_SP100;
1626 break;
1627 }
1628
1629 ctrl |= PHY_CT_RESET;
1630 }
1631
1632 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1633
1634 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1635 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1636
1637 /* Enable phy interrupt on autonegotiation complete (or link up) */
1638 if (skge->autoneg == AUTONEG_ENABLE)
1639 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1640 else
1641 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1642 }
1643
1644 static void yukon_reset(struct skge_hw *hw, int port)
1645 {
1646 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1647 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1648 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1649 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1650 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1651
1652 gma_write16(hw, port, GM_RX_CTRL,
1653 gma_read16(hw, port, GM_RX_CTRL)
1654 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1655 }
1656
1657 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1658 static int is_yukon_lite_a0(struct skge_hw *hw)
1659 {
1660 u32 reg;
1661 int ret;
1662
1663 if (hw->chip_id != CHIP_ID_YUKON)
1664 return 0;
1665
1666 reg = skge_read32(hw, B2_FAR);
1667 skge_write8(hw, B2_FAR + 3, 0xff);
1668 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1669 skge_write32(hw, B2_FAR, reg);
1670 return ret;
1671 }
1672
1673 static void yukon_mac_init(struct skge_hw *hw, int port)
1674 {
1675 struct skge_port *skge = netdev_priv(hw->dev[port]);
1676 int i;
1677 u32 reg;
1678 const u8 *addr = hw->dev[port]->dev_addr;
1679
1680 /* WA code for COMA mode -- set PHY reset */
1681 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1682 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1683 reg = skge_read32(hw, B2_GP_IO);
1684 reg |= GP_DIR_9 | GP_IO_9;
1685 skge_write32(hw, B2_GP_IO, reg);
1686 }
1687
1688 /* hard reset */
1689 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1690 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1691
1692 /* WA code for COMA mode -- clear PHY reset */
1693 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1694 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1695 reg = skge_read32(hw, B2_GP_IO);
1696 reg |= GP_DIR_9;
1697 reg &= ~GP_IO_9;
1698 skge_write32(hw, B2_GP_IO, reg);
1699 }
1700
1701 /* Set hardware config mode */
1702 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1703 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1704 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1705
1706 /* Clear GMC reset */
1707 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1708 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1709 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1710 if (skge->autoneg == AUTONEG_DISABLE) {
1711 reg = GM_GPCR_AU_ALL_DIS;
1712 gma_write16(hw, port, GM_GP_CTRL,
1713 gma_read16(hw, port, GM_GP_CTRL) | reg);
1714
1715 switch (skge->speed) {
1716 case SPEED_1000:
1717 reg |= GM_GPCR_SPEED_1000;
1718 /* fallthru */
1719 case SPEED_100:
1720 reg |= GM_GPCR_SPEED_100;
1721 }
1722
1723 if (skge->duplex == DUPLEX_FULL)
1724 reg |= GM_GPCR_DUP_FULL;
1725 } else
1726 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1727 switch (skge->flow_control) {
1728 case FLOW_MODE_NONE:
1729 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1730 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1731 break;
1732 case FLOW_MODE_LOC_SEND:
1733 /* disable Rx flow-control */
1734 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1735 }
1736
1737 gma_write16(hw, port, GM_GP_CTRL, reg);
1738 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1739
1740 yukon_init(hw, port);
1741
1742 /* MIB clear */
1743 reg = gma_read16(hw, port, GM_PHY_ADDR);
1744 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1745
1746 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1747 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1748 gma_write16(hw, port, GM_PHY_ADDR, reg);
1749
1750 /* transmit control */
1751 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1752
1753 /* receive control reg: unicast + multicast + no FCS */
1754 gma_write16(hw, port, GM_RX_CTRL,
1755 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1756
1757 /* transmit flow control */
1758 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1759
1760 /* transmit parameter */
1761 gma_write16(hw, port, GM_TX_PARAM,
1762 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1763 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1764 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1765
1766 /* serial mode register */
1767 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1768 if (hw->dev[port]->mtu > 1500)
1769 reg |= GM_SMOD_JUMBO_ENA;
1770
1771 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1772
1773 /* physical address: used for pause frames */
1774 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1775 /* virtual address for data */
1776 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1777
1778 /* enable interrupt mask for counter overflows */
1779 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1780 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1781 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1782
1783 /* Initialize Mac Fifo */
1784
1785 /* Configure Rx MAC FIFO */
1786 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1787 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1788
1789 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1790 if (is_yukon_lite_a0(hw))
1791 reg &= ~GMF_RX_F_FL_ON;
1792
1793 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1794 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1795 /*
1796 * because Pause Packet Truncation in GMAC is not working
1797 * we have to increase the Flush Threshold to 64 bytes
1798 * in order to flush pause packets in Rx FIFO on Yukon-1
1799 */
1800 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1801
1802 /* Configure Tx MAC FIFO */
1803 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1804 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1805 }
1806
1807 /* Go into power down mode */
1808 static void yukon_suspend(struct skge_hw *hw, int port)
1809 {
1810 u16 ctrl;
1811
1812 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1813 ctrl |= PHY_M_PC_POL_R_DIS;
1814 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1815
1816 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1817 ctrl |= PHY_CT_RESET;
1818 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1819
1820 /* switch IEEE compatible power down mode on */
1821 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1822 ctrl |= PHY_CT_PDOWN;
1823 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1824 }
1825
1826 static void yukon_stop(struct skge_port *skge)
1827 {
1828 struct skge_hw *hw = skge->hw;
1829 int port = skge->port;
1830
1831 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1832 yukon_reset(hw, port);
1833
1834 gma_write16(hw, port, GM_GP_CTRL,
1835 gma_read16(hw, port, GM_GP_CTRL)
1836 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1837 gma_read16(hw, port, GM_GP_CTRL);
1838
1839 yukon_suspend(hw, port);
1840
1841 /* set GPHY Control reset */
1842 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1843 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1844 }
1845
1846 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1847 {
1848 struct skge_hw *hw = skge->hw;
1849 int port = skge->port;
1850 int i;
1851
1852 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1853 | gma_read32(hw, port, GM_TXO_OK_LO);
1854 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1855 | gma_read32(hw, port, GM_RXO_OK_LO);
1856
1857 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1858 data[i] = gma_read32(hw, port,
1859 skge_stats[i].gma_offset);
1860 }
1861
1862 static void yukon_mac_intr(struct skge_hw *hw, int port)
1863 {
1864 struct net_device *dev = hw->dev[port];
1865 struct skge_port *skge = netdev_priv(dev);
1866 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1867
1868 if (netif_msg_intr(skge))
1869 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1870 dev->name, status);
1871
1872 if (status & GM_IS_RX_FF_OR) {
1873 ++skge->net_stats.rx_fifo_errors;
1874 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1875 }
1876
1877 if (status & GM_IS_TX_FF_UR) {
1878 ++skge->net_stats.tx_fifo_errors;
1879 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1880 }
1881
1882 }
1883
1884 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1885 {
1886 switch (aux & PHY_M_PS_SPEED_MSK) {
1887 case PHY_M_PS_SPEED_1000:
1888 return SPEED_1000;
1889 case PHY_M_PS_SPEED_100:
1890 return SPEED_100;
1891 default:
1892 return SPEED_10;
1893 }
1894 }
1895
1896 static void yukon_link_up(struct skge_port *skge)
1897 {
1898 struct skge_hw *hw = skge->hw;
1899 int port = skge->port;
1900 u16 reg;
1901
1902 /* Enable Transmit FIFO Underrun */
1903 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1904
1905 reg = gma_read16(hw, port, GM_GP_CTRL);
1906 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1907 reg |= GM_GPCR_DUP_FULL;
1908
1909 /* enable Rx/Tx */
1910 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1911 gma_write16(hw, port, GM_GP_CTRL, reg);
1912
1913 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1914 skge_link_up(skge);
1915 }
1916
1917 static void yukon_link_down(struct skge_port *skge)
1918 {
1919 struct skge_hw *hw = skge->hw;
1920 int port = skge->port;
1921 u16 ctrl;
1922
1923 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1924
1925 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1926 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1927 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1928
1929 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1930 /* restore Asymmetric Pause bit */
1931 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1932 gm_phy_read(hw, port,
1933 PHY_MARV_AUNE_ADV)
1934 | PHY_M_AN_ASP);
1935
1936 }
1937
1938 yukon_reset(hw, port);
1939 skge_link_down(skge);
1940
1941 yukon_init(hw, port);
1942 }
1943
1944 static void yukon_phy_intr(struct skge_port *skge)
1945 {
1946 struct skge_hw *hw = skge->hw;
1947 int port = skge->port;
1948 const char *reason = NULL;
1949 u16 istatus, phystat;
1950
1951 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1952 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1953
1954 if (netif_msg_intr(skge))
1955 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1956 skge->netdev->name, istatus, phystat);
1957
1958 if (istatus & PHY_M_IS_AN_COMPL) {
1959 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1960 & PHY_M_AN_RF) {
1961 reason = "remote fault";
1962 goto failed;
1963 }
1964
1965 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1966 reason = "master/slave fault";
1967 goto failed;
1968 }
1969
1970 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1971 reason = "speed/duplex";
1972 goto failed;
1973 }
1974
1975 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1976 ? DUPLEX_FULL : DUPLEX_HALF;
1977 skge->speed = yukon_speed(hw, phystat);
1978
1979 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1980 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1981 case PHY_M_PS_PAUSE_MSK:
1982 skge->flow_control = FLOW_MODE_SYMMETRIC;
1983 break;
1984 case PHY_M_PS_RX_P_EN:
1985 skge->flow_control = FLOW_MODE_REM_SEND;
1986 break;
1987 case PHY_M_PS_TX_P_EN:
1988 skge->flow_control = FLOW_MODE_LOC_SEND;
1989 break;
1990 default:
1991 skge->flow_control = FLOW_MODE_NONE;
1992 }
1993
1994 if (skge->flow_control == FLOW_MODE_NONE ||
1995 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1996 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1997 else
1998 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1999 yukon_link_up(skge);
2000 return;
2001 }
2002
2003 if (istatus & PHY_M_IS_LSP_CHANGE)
2004 skge->speed = yukon_speed(hw, phystat);
2005
2006 if (istatus & PHY_M_IS_DUP_CHANGE)
2007 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2008 if (istatus & PHY_M_IS_LST_CHANGE) {
2009 if (phystat & PHY_M_PS_LINK_UP)
2010 yukon_link_up(skge);
2011 else
2012 yukon_link_down(skge);
2013 }
2014 return;
2015 failed:
2016 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2017 skge->netdev->name, reason);
2018
2019 /* XXX restart autonegotiation? */
2020 }
2021
2022 /* Basic MII support */
2023 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2024 {
2025 struct mii_ioctl_data *data = if_mii(ifr);
2026 struct skge_port *skge = netdev_priv(dev);
2027 struct skge_hw *hw = skge->hw;
2028 int err = -EOPNOTSUPP;
2029
2030 if (!netif_running(dev))
2031 return -ENODEV; /* Phy still in reset */
2032
2033 switch(cmd) {
2034 case SIOCGMIIPHY:
2035 data->phy_id = hw->phy_addr;
2036
2037 /* fallthru */
2038 case SIOCGMIIREG: {
2039 u16 val = 0;
2040 spin_lock_bh(&hw->phy_lock);
2041 if (hw->chip_id == CHIP_ID_GENESIS)
2042 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2043 else
2044 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2045 spin_unlock_bh(&hw->phy_lock);
2046 data->val_out = val;
2047 break;
2048 }
2049
2050 case SIOCSMIIREG:
2051 if (!capable(CAP_NET_ADMIN))
2052 return -EPERM;
2053
2054 spin_lock_bh(&hw->phy_lock);
2055 if (hw->chip_id == CHIP_ID_GENESIS)
2056 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2057 data->val_in);
2058 else
2059 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2060 data->val_in);
2061 spin_unlock_bh(&hw->phy_lock);
2062 break;
2063 }
2064 return err;
2065 }
2066
2067 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2068 {
2069 u32 end;
2070
2071 start /= 8;
2072 len /= 8;
2073 end = start + len - 1;
2074
2075 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2076 skge_write32(hw, RB_ADDR(q, RB_START), start);
2077 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2078 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2079 skge_write32(hw, RB_ADDR(q, RB_END), end);
2080
2081 if (q == Q_R1 || q == Q_R2) {
2082 /* Set thresholds on receive queue's */
2083 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2084 start + (2*len)/3);
2085 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2086 start + (len/3));
2087 } else {
2088 /* Enable store & forward on Tx queue's because
2089 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2090 */
2091 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2092 }
2093
2094 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2095 }
2096
2097 /* Setup Bus Memory Interface */
2098 static void skge_qset(struct skge_port *skge, u16 q,
2099 const struct skge_element *e)
2100 {
2101 struct skge_hw *hw = skge->hw;
2102 u32 watermark = 0x600;
2103 u64 base = skge->dma + (e->desc - skge->mem);
2104
2105 /* optimization to reduce window on 32bit/33mhz */
2106 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2107 watermark /= 2;
2108
2109 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2110 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2111 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2112 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2113 }
2114
2115 static int skge_up(struct net_device *dev)
2116 {
2117 struct skge_port *skge = netdev_priv(dev);
2118 struct skge_hw *hw = skge->hw;
2119 int port = skge->port;
2120 u32 chunk, ram_addr;
2121 size_t rx_size, tx_size;
2122 int err;
2123
2124 if (netif_msg_ifup(skge))
2125 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2126
2127 if (dev->mtu > RX_BUF_SIZE)
2128 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2129 else
2130 skge->rx_buf_size = RX_BUF_SIZE;
2131
2132
2133 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2134 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2135 skge->mem_size = tx_size + rx_size;
2136 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2137 if (!skge->mem)
2138 return -ENOMEM;
2139
2140 memset(skge->mem, 0, skge->mem_size);
2141
2142 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2143 goto free_pci_mem;
2144
2145 err = skge_rx_fill(skge);
2146 if (err)
2147 goto free_rx_ring;
2148
2149 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2150 skge->dma + rx_size)))
2151 goto free_rx_ring;
2152
2153 skge->tx_avail = skge->tx_ring.count - 1;
2154
2155 /* Enable IRQ from port */
2156 hw->intr_mask |= portirqmask[port];
2157 skge_write32(hw, B0_IMSK, hw->intr_mask);
2158
2159 /* Initialize MAC */
2160 spin_lock_bh(&hw->phy_lock);
2161 if (hw->chip_id == CHIP_ID_GENESIS)
2162 genesis_mac_init(hw, port);
2163 else
2164 yukon_mac_init(hw, port);
2165 spin_unlock_bh(&hw->phy_lock);
2166
2167 /* Configure RAMbuffers */
2168 chunk = hw->ram_size / ((hw->ports + 1)*2);
2169 ram_addr = hw->ram_offset + 2 * chunk * port;
2170
2171 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2172 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2173
2174 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2175 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2176 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2177
2178 /* Start receiver BMU */
2179 wmb();
2180 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2181 skge_led(skge, LED_MODE_ON);
2182
2183 return 0;
2184
2185 free_rx_ring:
2186 skge_rx_clean(skge);
2187 kfree(skge->rx_ring.start);
2188 free_pci_mem:
2189 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2190
2191 return err;
2192 }
2193
2194 static int skge_down(struct net_device *dev)
2195 {
2196 struct skge_port *skge = netdev_priv(dev);
2197 struct skge_hw *hw = skge->hw;
2198 int port = skge->port;
2199
2200 if (netif_msg_ifdown(skge))
2201 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2202
2203 netif_stop_queue(dev);
2204
2205 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2206 if (hw->chip_id == CHIP_ID_GENESIS)
2207 genesis_stop(skge);
2208 else
2209 yukon_stop(skge);
2210
2211 hw->intr_mask &= ~portirqmask[skge->port];
2212 skge_write32(hw, B0_IMSK, hw->intr_mask);
2213
2214 /* Stop transmitter */
2215 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2216 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2217 RB_RST_SET|RB_DIS_OP_MD);
2218
2219
2220 /* Disable Force Sync bit and Enable Alloc bit */
2221 skge_write8(hw, SK_REG(port, TXA_CTRL),
2222 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2223
2224 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2225 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2226 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2227
2228 /* Reset PCI FIFO */
2229 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2230 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2231
2232 /* Reset the RAM Buffer async Tx queue */
2233 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2234 /* stop receiver */
2235 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2236 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2237 RB_RST_SET|RB_DIS_OP_MD);
2238 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2239
2240 if (hw->chip_id == CHIP_ID_GENESIS) {
2241 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2242 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2243 } else {
2244 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2245 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2246 }
2247
2248 skge_led(skge, LED_MODE_OFF);
2249
2250 skge_tx_clean(skge);
2251 skge_rx_clean(skge);
2252
2253 kfree(skge->rx_ring.start);
2254 kfree(skge->tx_ring.start);
2255 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2256 return 0;
2257 }
2258
2259 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2260 {
2261 struct skge_port *skge = netdev_priv(dev);
2262 struct skge_hw *hw = skge->hw;
2263 struct skge_ring *ring = &skge->tx_ring;
2264 struct skge_element *e;
2265 struct skge_tx_desc *td;
2266 int i;
2267 u32 control, len;
2268 u64 map;
2269 unsigned long flags;
2270
2271 skb = skb_padto(skb, ETH_ZLEN);
2272 if (!skb)
2273 return NETDEV_TX_OK;
2274
2275 local_irq_save(flags);
2276 if (!spin_trylock(&skge->tx_lock)) {
2277 /* Collision - tell upper layer to requeue */
2278 local_irq_restore(flags);
2279 return NETDEV_TX_LOCKED;
2280 }
2281
2282 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2283 netif_stop_queue(dev);
2284 spin_unlock_irqrestore(&skge->tx_lock, flags);
2285
2286 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2287 dev->name);
2288 return NETDEV_TX_BUSY;
2289 }
2290
2291 e = ring->to_use;
2292 td = e->desc;
2293 e->skb = skb;
2294 len = skb_headlen(skb);
2295 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2296 pci_unmap_addr_set(e, mapaddr, map);
2297 pci_unmap_len_set(e, maplen, len);
2298
2299 td->dma_lo = map;
2300 td->dma_hi = map >> 32;
2301
2302 if (skb->ip_summed == CHECKSUM_HW) {
2303 const struct iphdr *ip
2304 = (const struct iphdr *) (skb->data + ETH_HLEN);
2305 int offset = skb->h.raw - skb->data;
2306
2307 /* This seems backwards, but it is what the sk98lin
2308 * does. Looks like hardware is wrong?
2309 */
2310 if (ip->protocol == IPPROTO_UDP
2311 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2312 control = BMU_TCP_CHECK;
2313 else
2314 control = BMU_UDP_CHECK;
2315
2316 td->csum_offs = 0;
2317 td->csum_start = offset;
2318 td->csum_write = offset + skb->csum;
2319 } else
2320 control = BMU_CHECK;
2321
2322 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2323 control |= BMU_EOF| BMU_IRQ_EOF;
2324 else {
2325 struct skge_tx_desc *tf = td;
2326
2327 control |= BMU_STFWD;
2328 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2329 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2330
2331 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2332 frag->size, PCI_DMA_TODEVICE);
2333
2334 e = e->next;
2335 e->skb = NULL;
2336 tf = e->desc;
2337 tf->dma_lo = map;
2338 tf->dma_hi = (u64) map >> 32;
2339 pci_unmap_addr_set(e, mapaddr, map);
2340 pci_unmap_len_set(e, maplen, frag->size);
2341
2342 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2343 }
2344 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2345 }
2346 /* Make sure all the descriptors written */
2347 wmb();
2348 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2349 wmb();
2350
2351 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2352
2353 if (netif_msg_tx_queued(skge))
2354 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2355 dev->name, e - ring->start, skb->len);
2356
2357 ring->to_use = e->next;
2358 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2359 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2360 pr_debug("%s: transmit queue full\n", dev->name);
2361 netif_stop_queue(dev);
2362 }
2363
2364 dev->trans_start = jiffies;
2365 spin_unlock_irqrestore(&skge->tx_lock, flags);
2366
2367 return NETDEV_TX_OK;
2368 }
2369
2370 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2371 {
2372 /* This ring element can be skb or fragment */
2373 if (e->skb) {
2374 pci_unmap_single(hw->pdev,
2375 pci_unmap_addr(e, mapaddr),
2376 pci_unmap_len(e, maplen),
2377 PCI_DMA_TODEVICE);
2378 dev_kfree_skb_any(e->skb);
2379 e->skb = NULL;
2380 } else {
2381 pci_unmap_page(hw->pdev,
2382 pci_unmap_addr(e, mapaddr),
2383 pci_unmap_len(e, maplen),
2384 PCI_DMA_TODEVICE);
2385 }
2386 }
2387
2388 static void skge_tx_clean(struct skge_port *skge)
2389 {
2390 struct skge_ring *ring = &skge->tx_ring;
2391 struct skge_element *e;
2392 unsigned long flags;
2393
2394 spin_lock_irqsave(&skge->tx_lock, flags);
2395 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2396 ++skge->tx_avail;
2397 skge_tx_free(skge->hw, e);
2398 }
2399 ring->to_clean = e;
2400 spin_unlock_irqrestore(&skge->tx_lock, flags);
2401 }
2402
2403 static void skge_tx_timeout(struct net_device *dev)
2404 {
2405 struct skge_port *skge = netdev_priv(dev);
2406
2407 if (netif_msg_timer(skge))
2408 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2409
2410 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2411 skge_tx_clean(skge);
2412 }
2413
2414 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2415 {
2416 int err = 0;
2417 int running = netif_running(dev);
2418
2419 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2420 return -EINVAL;
2421
2422
2423 if (running)
2424 skge_down(dev);
2425 dev->mtu = new_mtu;
2426 if (running)
2427 skge_up(dev);
2428
2429 return err;
2430 }
2431
2432 static void genesis_set_multicast(struct net_device *dev)
2433 {
2434 struct skge_port *skge = netdev_priv(dev);
2435 struct skge_hw *hw = skge->hw;
2436 int port = skge->port;
2437 int i, count = dev->mc_count;
2438 struct dev_mc_list *list = dev->mc_list;
2439 u32 mode;
2440 u8 filter[8];
2441
2442 mode = xm_read32(hw, port, XM_MODE);
2443 mode |= XM_MD_ENA_HASH;
2444 if (dev->flags & IFF_PROMISC)
2445 mode |= XM_MD_ENA_PROM;
2446 else
2447 mode &= ~XM_MD_ENA_PROM;
2448
2449 if (dev->flags & IFF_ALLMULTI)
2450 memset(filter, 0xff, sizeof(filter));
2451 else {
2452 memset(filter, 0, sizeof(filter));
2453 for (i = 0; list && i < count; i++, list = list->next) {
2454 u32 crc, bit;
2455 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2456 bit = ~crc & 0x3f;
2457 filter[bit/8] |= 1 << (bit%8);
2458 }
2459 }
2460
2461 xm_write32(hw, port, XM_MODE, mode);
2462 xm_outhash(hw, port, XM_HSM, filter);
2463 }
2464
2465 static void yukon_set_multicast(struct net_device *dev)
2466 {
2467 struct skge_port *skge = netdev_priv(dev);
2468 struct skge_hw *hw = skge->hw;
2469 int port = skge->port;
2470 struct dev_mc_list *list = dev->mc_list;
2471 u16 reg;
2472 u8 filter[8];
2473
2474 memset(filter, 0, sizeof(filter));
2475
2476 reg = gma_read16(hw, port, GM_RX_CTRL);
2477 reg |= GM_RXCR_UCF_ENA;
2478
2479 if (dev->flags & IFF_PROMISC) /* promiscuous */
2480 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2481 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2482 memset(filter, 0xff, sizeof(filter));
2483 else if (dev->mc_count == 0) /* no multicast */
2484 reg &= ~GM_RXCR_MCF_ENA;
2485 else {
2486 int i;
2487 reg |= GM_RXCR_MCF_ENA;
2488
2489 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2490 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2491 filter[bit/8] |= 1 << (bit%8);
2492 }
2493 }
2494
2495
2496 gma_write16(hw, port, GM_MC_ADDR_H1,
2497 (u16)filter[0] | ((u16)filter[1] << 8));
2498 gma_write16(hw, port, GM_MC_ADDR_H2,
2499 (u16)filter[2] | ((u16)filter[3] << 8));
2500 gma_write16(hw, port, GM_MC_ADDR_H3,
2501 (u16)filter[4] | ((u16)filter[5] << 8));
2502 gma_write16(hw, port, GM_MC_ADDR_H4,
2503 (u16)filter[6] | ((u16)filter[7] << 8));
2504
2505 gma_write16(hw, port, GM_RX_CTRL, reg);
2506 }
2507
2508 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2509 {
2510 if (hw->chip_id == CHIP_ID_GENESIS)
2511 return status >> XMR_FS_LEN_SHIFT;
2512 else
2513 return status >> GMR_FS_LEN_SHIFT;
2514 }
2515
2516 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2517 {
2518 if (hw->chip_id == CHIP_ID_GENESIS)
2519 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2520 else
2521 return (status & GMR_FS_ANY_ERR) ||
2522 (status & GMR_FS_RX_OK) == 0;
2523 }
2524
2525
2526 /* Get receive buffer from descriptor.
2527 * Handles copy of small buffers and reallocation failures
2528 */
2529 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2530 struct skge_element *e,
2531 u32 control, u32 status, u16 csum)
2532 {
2533 struct sk_buff *skb;
2534 u16 len = control & BMU_BBC;
2535
2536 if (unlikely(netif_msg_rx_status(skge)))
2537 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2538 skge->netdev->name, e - skge->rx_ring.start,
2539 status, len);
2540
2541 if (len > skge->rx_buf_size)
2542 goto error;
2543
2544 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2545 goto error;
2546
2547 if (bad_phy_status(skge->hw, status))
2548 goto error;
2549
2550 if (phy_length(skge->hw, status) != len)
2551 goto error;
2552
2553 if (len < RX_COPY_THRESHOLD) {
2554 skb = dev_alloc_skb(len + 2);
2555 if (!skb)
2556 goto resubmit;
2557
2558 skb_reserve(skb, 2);
2559 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2560 pci_unmap_addr(e, mapaddr),
2561 len, PCI_DMA_FROMDEVICE);
2562 memcpy(skb->data, e->skb->data, len);
2563 pci_dma_sync_single_for_device(skge->hw->pdev,
2564 pci_unmap_addr(e, mapaddr),
2565 len, PCI_DMA_FROMDEVICE);
2566 skge_rx_reuse(e, skge->rx_buf_size);
2567 } else {
2568 struct sk_buff *nskb;
2569 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2570 if (!nskb)
2571 goto resubmit;
2572
2573 pci_unmap_single(skge->hw->pdev,
2574 pci_unmap_addr(e, mapaddr),
2575 pci_unmap_len(e, maplen),
2576 PCI_DMA_FROMDEVICE);
2577 skb = e->skb;
2578 prefetch(skb->data);
2579 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2580 }
2581
2582 skb_put(skb, len);
2583 skb->dev = skge->netdev;
2584 if (skge->rx_csum) {
2585 skb->csum = csum;
2586 skb->ip_summed = CHECKSUM_HW;
2587 }
2588
2589 skb->protocol = eth_type_trans(skb, skge->netdev);
2590
2591 return skb;
2592 error:
2593
2594 if (netif_msg_rx_err(skge))
2595 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2596 skge->netdev->name, e - skge->rx_ring.start,
2597 control, status);
2598
2599 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2600 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2601 skge->net_stats.rx_length_errors++;
2602 if (status & XMR_FS_FRA_ERR)
2603 skge->net_stats.rx_frame_errors++;
2604 if (status & XMR_FS_FCS_ERR)
2605 skge->net_stats.rx_crc_errors++;
2606 } else {
2607 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2608 skge->net_stats.rx_length_errors++;
2609 if (status & GMR_FS_FRAGMENT)
2610 skge->net_stats.rx_frame_errors++;
2611 if (status & GMR_FS_CRC_ERR)
2612 skge->net_stats.rx_crc_errors++;
2613 }
2614
2615 resubmit:
2616 skge_rx_reuse(e, skge->rx_buf_size);
2617 return NULL;
2618 }
2619
2620
2621 static int skge_poll(struct net_device *dev, int *budget)
2622 {
2623 struct skge_port *skge = netdev_priv(dev);
2624 struct skge_hw *hw = skge->hw;
2625 struct skge_ring *ring = &skge->rx_ring;
2626 struct skge_element *e;
2627 unsigned int to_do = min(dev->quota, *budget);
2628 unsigned int work_done = 0;
2629
2630 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2631 struct skge_rx_desc *rd = e->desc;
2632 struct sk_buff *skb;
2633 u32 control;
2634
2635 rmb();
2636 control = rd->control;
2637 if (control & BMU_OWN)
2638 break;
2639
2640 skb = skge_rx_get(skge, e, control, rd->status,
2641 le16_to_cpu(rd->csum2));
2642 if (likely(skb)) {
2643 dev->last_rx = jiffies;
2644 netif_receive_skb(skb);
2645
2646 ++work_done;
2647 } else
2648 skge_rx_reuse(e, skge->rx_buf_size);
2649 }
2650 ring->to_clean = e;
2651
2652 /* restart receiver */
2653 wmb();
2654 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2655 CSR_START | CSR_IRQ_CL_F);
2656
2657 *budget -= work_done;
2658 dev->quota -= work_done;
2659
2660 if (work_done >= to_do)
2661 return 1; /* not done */
2662
2663 netif_rx_complete(dev);
2664 hw->intr_mask |= portirqmask[skge->port];
2665 skge_write32(hw, B0_IMSK, hw->intr_mask);
2666 skge_read32(hw, B0_IMSK);
2667
2668 return 0;
2669 }
2670
2671 static inline void skge_tx_intr(struct net_device *dev)
2672 {
2673 struct skge_port *skge = netdev_priv(dev);
2674 struct skge_hw *hw = skge->hw;
2675 struct skge_ring *ring = &skge->tx_ring;
2676 struct skge_element *e;
2677
2678 spin_lock(&skge->tx_lock);
2679 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2680 struct skge_tx_desc *td = e->desc;
2681 u32 control;
2682
2683 rmb();
2684 control = td->control;
2685 if (control & BMU_OWN)
2686 break;
2687
2688 if (unlikely(netif_msg_tx_done(skge)))
2689 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2690 dev->name, e - ring->start, td->status);
2691
2692 skge_tx_free(hw, e);
2693 e->skb = NULL;
2694 ++skge->tx_avail;
2695 }
2696 ring->to_clean = e;
2697 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2698
2699 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2700 netif_wake_queue(dev);
2701
2702 spin_unlock(&skge->tx_lock);
2703 }
2704
2705 /* Parity errors seem to happen when Genesis is connected to a switch
2706 * with no other ports present. Heartbeat error??
2707 */
2708 static void skge_mac_parity(struct skge_hw *hw, int port)
2709 {
2710 struct net_device *dev = hw->dev[port];
2711
2712 if (dev) {
2713 struct skge_port *skge = netdev_priv(dev);
2714 ++skge->net_stats.tx_heartbeat_errors;
2715 }
2716
2717 if (hw->chip_id == CHIP_ID_GENESIS)
2718 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2719 MFF_CLR_PERR);
2720 else
2721 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2722 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2723 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2724 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2725 }
2726
2727 static void skge_pci_clear(struct skge_hw *hw)
2728 {
2729 u16 status;
2730
2731 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2732 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2733 pci_write_config_word(hw->pdev, PCI_STATUS,
2734 status | PCI_STATUS_ERROR_BITS);
2735 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2736 }
2737
2738 static void skge_mac_intr(struct skge_hw *hw, int port)
2739 {
2740 if (hw->chip_id == CHIP_ID_GENESIS)
2741 genesis_mac_intr(hw, port);
2742 else
2743 yukon_mac_intr(hw, port);
2744 }
2745
2746 /* Handle device specific framing and timeout interrupts */
2747 static void skge_error_irq(struct skge_hw *hw)
2748 {
2749 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2750
2751 if (hw->chip_id == CHIP_ID_GENESIS) {
2752 /* clear xmac errors */
2753 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2754 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2755 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2756 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2757 } else {
2758 /* Timestamp (unused) overflow */
2759 if (hwstatus & IS_IRQ_TIST_OV)
2760 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2761 }
2762
2763 if (hwstatus & IS_RAM_RD_PAR) {
2764 printk(KERN_ERR PFX "Ram read data parity error\n");
2765 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2766 }
2767
2768 if (hwstatus & IS_RAM_WR_PAR) {
2769 printk(KERN_ERR PFX "Ram write data parity error\n");
2770 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2771 }
2772
2773 if (hwstatus & IS_M1_PAR_ERR)
2774 skge_mac_parity(hw, 0);
2775
2776 if (hwstatus & IS_M2_PAR_ERR)
2777 skge_mac_parity(hw, 1);
2778
2779 if (hwstatus & IS_R1_PAR_ERR)
2780 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2781
2782 if (hwstatus & IS_R2_PAR_ERR)
2783 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2784
2785 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2786 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2787 hwstatus);
2788
2789 skge_pci_clear(hw);
2790
2791 /* if error still set then just ignore it */
2792 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2793 if (hwstatus & IS_IRQ_STAT) {
2794 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2795 hwstatus);
2796 hw->intr_mask &= ~IS_HW_ERR;
2797 }
2798 }
2799 }
2800
2801 /*
2802 * Interrupt from PHY are handled in tasklet (soft irq)
2803 * because accessing phy registers requires spin wait which might
2804 * cause excess interrupt latency.
2805 */
2806 static void skge_extirq(unsigned long data)
2807 {
2808 struct skge_hw *hw = (struct skge_hw *) data;
2809 int port;
2810
2811 spin_lock(&hw->phy_lock);
2812 for (port = 0; port < 2; port++) {
2813 struct net_device *dev = hw->dev[port];
2814
2815 if (dev && netif_running(dev)) {
2816 struct skge_port *skge = netdev_priv(dev);
2817
2818 if (hw->chip_id != CHIP_ID_GENESIS)
2819 yukon_phy_intr(skge);
2820 else
2821 bcom_phy_intr(skge);
2822 }
2823 }
2824 spin_unlock(&hw->phy_lock);
2825
2826 local_irq_disable();
2827 hw->intr_mask |= IS_EXT_REG;
2828 skge_write32(hw, B0_IMSK, hw->intr_mask);
2829 local_irq_enable();
2830 }
2831
2832 static inline void skge_wakeup(struct net_device *dev)
2833 {
2834 struct skge_port *skge = netdev_priv(dev);
2835
2836 prefetch(skge->rx_ring.to_clean);
2837 netif_rx_schedule(dev);
2838 }
2839
2840 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2841 {
2842 struct skge_hw *hw = dev_id;
2843 u32 status = skge_read32(hw, B0_SP_ISRC);
2844
2845 if (status == 0 || status == ~0) /* hotplug or shared irq */
2846 return IRQ_NONE;
2847
2848 status &= hw->intr_mask;
2849 if (status & IS_R1_F) {
2850 hw->intr_mask &= ~IS_R1_F;
2851 skge_wakeup(hw->dev[0]);
2852 }
2853
2854 if (status & IS_R2_F) {
2855 hw->intr_mask &= ~IS_R2_F;
2856 skge_wakeup(hw->dev[1]);
2857 }
2858
2859 if (status & IS_XA1_F)
2860 skge_tx_intr(hw->dev[0]);
2861
2862 if (status & IS_XA2_F)
2863 skge_tx_intr(hw->dev[1]);
2864
2865 if (status & IS_PA_TO_RX1) {
2866 struct skge_port *skge = netdev_priv(hw->dev[0]);
2867 ++skge->net_stats.rx_over_errors;
2868 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2869 }
2870
2871 if (status & IS_PA_TO_RX2) {
2872 struct skge_port *skge = netdev_priv(hw->dev[1]);
2873 ++skge->net_stats.rx_over_errors;
2874 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2875 }
2876
2877 if (status & IS_PA_TO_TX1)
2878 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2879
2880 if (status & IS_PA_TO_TX2)
2881 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2882
2883 if (status & IS_MAC1)
2884 skge_mac_intr(hw, 0);
2885
2886 if (status & IS_MAC2)
2887 skge_mac_intr(hw, 1);
2888
2889 if (status & IS_HW_ERR)
2890 skge_error_irq(hw);
2891
2892 if (status & IS_EXT_REG) {
2893 hw->intr_mask &= ~IS_EXT_REG;
2894 tasklet_schedule(&hw->ext_tasklet);
2895 }
2896
2897 skge_write32(hw, B0_IMSK, hw->intr_mask);
2898
2899 return IRQ_HANDLED;
2900 }
2901
2902 #ifdef CONFIG_NET_POLL_CONTROLLER
2903 static void skge_netpoll(struct net_device *dev)
2904 {
2905 struct skge_port *skge = netdev_priv(dev);
2906
2907 disable_irq(dev->irq);
2908 skge_intr(dev->irq, skge->hw, NULL);
2909 enable_irq(dev->irq);
2910 }
2911 #endif
2912
2913 static int skge_set_mac_address(struct net_device *dev, void *p)
2914 {
2915 struct skge_port *skge = netdev_priv(dev);
2916 struct skge_hw *hw = skge->hw;
2917 unsigned port = skge->port;
2918 const struct sockaddr *addr = p;
2919
2920 if (!is_valid_ether_addr(addr->sa_data))
2921 return -EADDRNOTAVAIL;
2922
2923 spin_lock_bh(&hw->phy_lock);
2924 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2925 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2926 dev->dev_addr, ETH_ALEN);
2927 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2928 dev->dev_addr, ETH_ALEN);
2929
2930 if (hw->chip_id == CHIP_ID_GENESIS)
2931 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2932 else {
2933 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2934 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2935 }
2936 spin_unlock_bh(&hw->phy_lock);
2937
2938 return 0;
2939 }
2940
2941 static const struct {
2942 u8 id;
2943 const char *name;
2944 } skge_chips[] = {
2945 { CHIP_ID_GENESIS, "Genesis" },
2946 { CHIP_ID_YUKON, "Yukon" },
2947 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2948 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2949 };
2950
2951 static const char *skge_board_name(const struct skge_hw *hw)
2952 {
2953 int i;
2954 static char buf[16];
2955
2956 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2957 if (skge_chips[i].id == hw->chip_id)
2958 return skge_chips[i].name;
2959
2960 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2961 return buf;
2962 }
2963
2964
2965 /*
2966 * Setup the board data structure, but don't bring up
2967 * the port(s)
2968 */
2969 static int skge_reset(struct skge_hw *hw)
2970 {
2971 u32 reg;
2972 u16 ctst;
2973 u8 t8, mac_cfg, pmd_type, phy_type;
2974 int i;
2975
2976 ctst = skge_read16(hw, B0_CTST);
2977
2978 /* do a SW reset */
2979 skge_write8(hw, B0_CTST, CS_RST_SET);
2980 skge_write8(hw, B0_CTST, CS_RST_CLR);
2981
2982 /* clear PCI errors, if any */
2983 skge_pci_clear(hw);
2984
2985 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2986
2987 /* restore CLK_RUN bits (for Yukon-Lite) */
2988 skge_write16(hw, B0_CTST,
2989 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2990
2991 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2992 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2993 pmd_type = skge_read8(hw, B2_PMD_TYP);
2994 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2995
2996 switch (hw->chip_id) {
2997 case CHIP_ID_GENESIS:
2998 switch (phy_type) {
2999 case SK_PHY_BCOM:
3000 hw->phy_addr = PHY_ADDR_BCOM;
3001 break;
3002 default:
3003 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3004 pci_name(hw->pdev), phy_type);
3005 return -EOPNOTSUPP;
3006 }
3007 break;
3008
3009 case CHIP_ID_YUKON:
3010 case CHIP_ID_YUKON_LITE:
3011 case CHIP_ID_YUKON_LP:
3012 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3013 hw->copper = 1;
3014
3015 hw->phy_addr = PHY_ADDR_MARV;
3016 break;
3017
3018 default:
3019 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3020 pci_name(hw->pdev), hw->chip_id);
3021 return -EOPNOTSUPP;
3022 }
3023
3024 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3025 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3026 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3027
3028 /* read the adapters RAM size */
3029 t8 = skge_read8(hw, B2_E_0);
3030 if (hw->chip_id == CHIP_ID_GENESIS) {
3031 if (t8 == 3) {
3032 /* special case: 4 x 64k x 36, offset = 0x80000 */
3033 hw->ram_size = 0x100000;
3034 hw->ram_offset = 0x80000;
3035 } else
3036 hw->ram_size = t8 * 512;
3037 }
3038 else if (t8 == 0)
3039 hw->ram_size = 0x20000;
3040 else
3041 hw->ram_size = t8 * 4096;
3042
3043 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3044 if (hw->chip_id == CHIP_ID_GENESIS)
3045 genesis_init(hw);
3046 else {
3047 /* switch power to VCC (WA for VAUX problem) */
3048 skge_write8(hw, B0_POWER_CTRL,
3049 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3050
3051 /* avoid boards with stuck Hardware error bits */
3052 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3053 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3054 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3055 hw->intr_mask &= ~IS_HW_ERR;
3056 }
3057
3058 /* Clear PHY COMA */
3059 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3060 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3061 reg &= ~PCI_PHY_COMA;
3062 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3063 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3064
3065
3066 for (i = 0; i < hw->ports; i++) {
3067 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3068 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3069 }
3070 }
3071
3072 /* turn off hardware timer (unused) */
3073 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3074 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3075 skge_write8(hw, B0_LED, LED_STAT_ON);
3076
3077 /* enable the Tx Arbiters */
3078 for (i = 0; i < hw->ports; i++)
3079 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3080
3081 /* Initialize ram interface */
3082 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3083
3084 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3085 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3086 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3087 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3088 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3089 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3090 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3091 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3092 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3093 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3094 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3095 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3096
3097 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3098
3099 /* Set interrupt moderation for Transmit only
3100 * Receive interrupts avoided by NAPI
3101 */
3102 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3103 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3104 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3105
3106 skge_write32(hw, B0_IMSK, hw->intr_mask);
3107
3108 spin_lock_bh(&hw->phy_lock);
3109 for (i = 0; i < hw->ports; i++) {
3110 if (hw->chip_id == CHIP_ID_GENESIS)
3111 genesis_reset(hw, i);
3112 else
3113 yukon_reset(hw, i);
3114 }
3115 spin_unlock_bh(&hw->phy_lock);
3116
3117 return 0;
3118 }
3119
3120 /* Initialize network device */
3121 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3122 int highmem)
3123 {
3124 struct skge_port *skge;
3125 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3126
3127 if (!dev) {
3128 printk(KERN_ERR "skge etherdev alloc failed");
3129 return NULL;
3130 }
3131
3132 SET_MODULE_OWNER(dev);
3133 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3134 dev->open = skge_up;
3135 dev->stop = skge_down;
3136 dev->do_ioctl = skge_ioctl;
3137 dev->hard_start_xmit = skge_xmit_frame;
3138 dev->get_stats = skge_get_stats;
3139 if (hw->chip_id == CHIP_ID_GENESIS)
3140 dev->set_multicast_list = genesis_set_multicast;
3141 else
3142 dev->set_multicast_list = yukon_set_multicast;
3143
3144 dev->set_mac_address = skge_set_mac_address;
3145 dev->change_mtu = skge_change_mtu;
3146 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3147 dev->tx_timeout = skge_tx_timeout;
3148 dev->watchdog_timeo = TX_WATCHDOG;
3149 dev->poll = skge_poll;
3150 dev->weight = NAPI_WEIGHT;
3151 #ifdef CONFIG_NET_POLL_CONTROLLER
3152 dev->poll_controller = skge_netpoll;
3153 #endif
3154 dev->irq = hw->pdev->irq;
3155 dev->features = NETIF_F_LLTX;
3156 if (highmem)
3157 dev->features |= NETIF_F_HIGHDMA;
3158
3159 skge = netdev_priv(dev);
3160 skge->netdev = dev;
3161 skge->hw = hw;
3162 skge->msg_enable = netif_msg_init(debug, default_msg);
3163 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3164 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3165
3166 /* Auto speed and flow control */
3167 skge->autoneg = AUTONEG_ENABLE;
3168 skge->flow_control = FLOW_MODE_SYMMETRIC;
3169 skge->duplex = -1;
3170 skge->speed = -1;
3171 skge->advertising = skge_supported_modes(hw);
3172
3173 hw->dev[port] = dev;
3174
3175 skge->port = port;
3176
3177 spin_lock_init(&skge->tx_lock);
3178
3179 if (hw->chip_id != CHIP_ID_GENESIS) {
3180 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3181 skge->rx_csum = 1;
3182 }
3183
3184 /* read the mac address */
3185 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3186 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3187
3188 /* device is off until link detection */
3189 netif_carrier_off(dev);
3190 netif_stop_queue(dev);
3191
3192 return dev;
3193 }
3194
3195 static void __devinit skge_show_addr(struct net_device *dev)
3196 {
3197 const struct skge_port *skge = netdev_priv(dev);
3198
3199 if (netif_msg_probe(skge))
3200 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3201 dev->name,
3202 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3203 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3204 }
3205
3206 static int __devinit skge_probe(struct pci_dev *pdev,
3207 const struct pci_device_id *ent)
3208 {
3209 struct net_device *dev, *dev1;
3210 struct skge_hw *hw;
3211 int err, using_dac = 0;
3212
3213 if ((err = pci_enable_device(pdev))) {
3214 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3215 pci_name(pdev));
3216 goto err_out;
3217 }
3218
3219 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3220 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3221 pci_name(pdev));
3222 goto err_out_disable_pdev;
3223 }
3224
3225 pci_set_master(pdev);
3226
3227 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3228 using_dac = 1;
3229 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3230 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3231 pci_name(pdev));
3232 goto err_out_free_regions;
3233 }
3234
3235 #ifdef __BIG_ENDIAN
3236 /* byte swap descriptors in hardware */
3237 {
3238 u32 reg;
3239
3240 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3241 reg |= PCI_REV_DESC;
3242 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3243 }
3244 #endif
3245
3246 err = -ENOMEM;
3247 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3248 if (!hw) {
3249 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3250 pci_name(pdev));
3251 goto err_out_free_regions;
3252 }
3253
3254 hw->pdev = pdev;
3255 spin_lock_init(&hw->phy_lock);
3256 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3257
3258 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3259 if (!hw->regs) {
3260 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3261 pci_name(pdev));
3262 goto err_out_free_hw;
3263 }
3264
3265 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3266 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3267 pci_name(pdev), pdev->irq);
3268 goto err_out_iounmap;
3269 }
3270 pci_set_drvdata(pdev, hw);
3271
3272 err = skge_reset(hw);
3273 if (err)
3274 goto err_out_free_irq;
3275
3276 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3277 pci_resource_start(pdev, 0), pdev->irq,
3278 skge_board_name(hw), hw->chip_rev);
3279
3280 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3281 goto err_out_led_off;
3282
3283 if ((err = register_netdev(dev))) {
3284 printk(KERN_ERR PFX "%s: cannot register net device\n",
3285 pci_name(pdev));
3286 goto err_out_free_netdev;
3287 }
3288
3289 skge_show_addr(dev);
3290
3291 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3292 if (register_netdev(dev1) == 0)
3293 skge_show_addr(dev1);
3294 else {
3295 /* Failure to register second port need not be fatal */
3296 printk(KERN_WARNING PFX "register of second port failed\n");
3297 hw->dev[1] = NULL;
3298 free_netdev(dev1);
3299 }
3300 }
3301
3302 return 0;
3303
3304 err_out_free_netdev:
3305 free_netdev(dev);
3306 err_out_led_off:
3307 skge_write16(hw, B0_LED, LED_STAT_OFF);
3308 err_out_free_irq:
3309 free_irq(pdev->irq, hw);
3310 err_out_iounmap:
3311 iounmap(hw->regs);
3312 err_out_free_hw:
3313 kfree(hw);
3314 err_out_free_regions:
3315 pci_release_regions(pdev);
3316 err_out_disable_pdev:
3317 pci_disable_device(pdev);
3318 pci_set_drvdata(pdev, NULL);
3319 err_out:
3320 return err;
3321 }
3322
3323 static void __devexit skge_remove(struct pci_dev *pdev)
3324 {
3325 struct skge_hw *hw = pci_get_drvdata(pdev);
3326 struct net_device *dev0, *dev1;
3327
3328 if (!hw)
3329 return;
3330
3331 if ((dev1 = hw->dev[1]))
3332 unregister_netdev(dev1);
3333 dev0 = hw->dev[0];
3334 unregister_netdev(dev0);
3335
3336 skge_write32(hw, B0_IMSK, 0);
3337 skge_write16(hw, B0_LED, LED_STAT_OFF);
3338 skge_pci_clear(hw);
3339 skge_write8(hw, B0_CTST, CS_RST_SET);
3340
3341 tasklet_kill(&hw->ext_tasklet);
3342
3343 free_irq(pdev->irq, hw);
3344 pci_release_regions(pdev);
3345 pci_disable_device(pdev);
3346 if (dev1)
3347 free_netdev(dev1);
3348 free_netdev(dev0);
3349
3350 iounmap(hw->regs);
3351 kfree(hw);
3352 pci_set_drvdata(pdev, NULL);
3353 }
3354
3355 #ifdef CONFIG_PM
3356 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3357 {
3358 struct skge_hw *hw = pci_get_drvdata(pdev);
3359 int i, wol = 0;
3360
3361 for (i = 0; i < 2; i++) {
3362 struct net_device *dev = hw->dev[i];
3363
3364 if (dev) {
3365 struct skge_port *skge = netdev_priv(dev);
3366 if (netif_running(dev)) {
3367 netif_carrier_off(dev);
3368 if (skge->wol)
3369 netif_stop_queue(dev);
3370 else
3371 skge_down(dev);
3372 }
3373 netif_device_detach(dev);
3374 wol |= skge->wol;
3375 }
3376 }
3377
3378 pci_save_state(pdev);
3379 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3380 pci_disable_device(pdev);
3381 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3382
3383 return 0;
3384 }
3385
3386 static int skge_resume(struct pci_dev *pdev)
3387 {
3388 struct skge_hw *hw = pci_get_drvdata(pdev);
3389 int i;
3390
3391 pci_set_power_state(pdev, PCI_D0);
3392 pci_restore_state(pdev);
3393 pci_enable_wake(pdev, PCI_D0, 0);
3394
3395 skge_reset(hw);
3396
3397 for (i = 0; i < 2; i++) {
3398 struct net_device *dev = hw->dev[i];
3399 if (dev) {
3400 netif_device_attach(dev);
3401 if (netif_running(dev))
3402 skge_up(dev);
3403 }
3404 }
3405 return 0;
3406 }
3407 #endif
3408
3409 static struct pci_driver skge_driver = {
3410 .name = DRV_NAME,
3411 .id_table = skge_id_table,
3412 .probe = skge_probe,
3413 .remove = __devexit_p(skge_remove),
3414 #ifdef CONFIG_PM
3415 .suspend = skge_suspend,
3416 .resume = skge_resume,
3417 #endif
3418 };
3419
3420 static int __init skge_init_module(void)
3421 {
3422 return pci_module_init(&skge_driver);
3423 }
3424
3425 static void __exit skge_cleanup_module(void)
3426 {
3427 pci_unregister_driver(&skge_driver);
3428 }
3429
3430 module_init(skge_init_module);
3431 module_exit(skge_cleanup_module);
x86 "subsystem" repository